1 /******************************************************************************
3 * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
28 *****************************************************************************/
30 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
32 #include <linux/kernel.h>
33 #include <linux/module.h>
34 #include <linux/init.h>
35 #include <linux/pci.h>
36 #include <linux/pci-aspm.h>
37 #include <linux/slab.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/delay.h>
40 #include <linux/sched.h>
41 #include <linux/skbuff.h>
42 #include <linux/netdevice.h>
43 #include <linux/wireless.h>
44 #include <linux/firmware.h>
45 #include <linux/etherdevice.h>
46 #include <linux/if_arp.h>
48 #include <net/mac80211.h>
50 #include <asm/div64.h>
52 #define DRV_NAME "iwlagn"
54 #include "iwl-eeprom.h"
58 #include "iwl-helpers.h"
60 #include "iwl-agn-calib.h"
62 #include "iwl-agn-led.h"
65 /******************************************************************************
69 ******************************************************************************/
72 * module name, copyright, version, etc.
74 #define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux"
76 #ifdef CONFIG_IWLWIFI_DEBUG
82 #define DRV_VERSION IWLWIFI_VERSION VD
85 MODULE_DESCRIPTION(DRV_DESCRIPTION
);
86 MODULE_VERSION(DRV_VERSION
);
87 MODULE_AUTHOR(DRV_COPYRIGHT
" " DRV_AUTHOR
);
88 MODULE_LICENSE("GPL");
90 static int iwlagn_ant_coupling
;
91 static bool iwlagn_bt_ch_announce
= 1;
93 void iwl_update_chain_flags(struct iwl_priv
*priv
)
95 struct iwl_rxon_context
*ctx
;
97 if (priv
->cfg
->ops
->hcmd
->set_rxon_chain
) {
98 for_each_context(priv
, ctx
) {
99 priv
->cfg
->ops
->hcmd
->set_rxon_chain(priv
, ctx
);
100 if (ctx
->active
.rx_chain
!= ctx
->staging
.rx_chain
)
101 iwlcore_commit_rxon(priv
, ctx
);
106 static void iwl_clear_free_frames(struct iwl_priv
*priv
)
108 struct list_head
*element
;
110 IWL_DEBUG_INFO(priv
, "%d frames on pre-allocated heap on clear.\n",
113 while (!list_empty(&priv
->free_frames
)) {
114 element
= priv
->free_frames
.next
;
116 kfree(list_entry(element
, struct iwl_frame
, list
));
117 priv
->frames_count
--;
120 if (priv
->frames_count
) {
121 IWL_WARN(priv
, "%d frames still in use. Did we lose one?\n",
123 priv
->frames_count
= 0;
127 static struct iwl_frame
*iwl_get_free_frame(struct iwl_priv
*priv
)
129 struct iwl_frame
*frame
;
130 struct list_head
*element
;
131 if (list_empty(&priv
->free_frames
)) {
132 frame
= kzalloc(sizeof(*frame
), GFP_KERNEL
);
134 IWL_ERR(priv
, "Could not allocate frame!\n");
138 priv
->frames_count
++;
142 element
= priv
->free_frames
.next
;
144 return list_entry(element
, struct iwl_frame
, list
);
147 static void iwl_free_frame(struct iwl_priv
*priv
, struct iwl_frame
*frame
)
149 memset(frame
, 0, sizeof(*frame
));
150 list_add(&frame
->list
, &priv
->free_frames
);
153 static u32
iwl_fill_beacon_frame(struct iwl_priv
*priv
,
154 struct ieee80211_hdr
*hdr
,
157 lockdep_assert_held(&priv
->mutex
);
159 if (!priv
->beacon_skb
)
162 if (priv
->beacon_skb
->len
> left
)
165 memcpy(hdr
, priv
->beacon_skb
->data
, priv
->beacon_skb
->len
);
167 return priv
->beacon_skb
->len
;
170 /* Parse the beacon frame to find the TIM element and set tim_idx & tim_size */
171 static void iwl_set_beacon_tim(struct iwl_priv
*priv
,
172 struct iwl_tx_beacon_cmd
*tx_beacon_cmd
,
173 u8
*beacon
, u32 frame_size
)
176 struct ieee80211_mgmt
*mgmt
= (struct ieee80211_mgmt
*)beacon
;
179 * The index is relative to frame start but we start looking at the
180 * variable-length part of the beacon.
182 tim_idx
= mgmt
->u
.beacon
.variable
- beacon
;
184 /* Parse variable-length elements of beacon to find WLAN_EID_TIM */
185 while ((tim_idx
< (frame_size
- 2)) &&
186 (beacon
[tim_idx
] != WLAN_EID_TIM
))
187 tim_idx
+= beacon
[tim_idx
+1] + 2;
189 /* If TIM field was found, set variables */
190 if ((tim_idx
< (frame_size
- 1)) && (beacon
[tim_idx
] == WLAN_EID_TIM
)) {
191 tx_beacon_cmd
->tim_idx
= cpu_to_le16(tim_idx
);
192 tx_beacon_cmd
->tim_size
= beacon
[tim_idx
+1];
194 IWL_WARN(priv
, "Unable to find TIM Element in beacon\n");
197 static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv
*priv
,
198 struct iwl_frame
*frame
)
200 struct iwl_tx_beacon_cmd
*tx_beacon_cmd
;
205 * We have to set up the TX command, the TX Beacon command, and the
209 lockdep_assert_held(&priv
->mutex
);
211 if (!priv
->beacon_ctx
) {
212 IWL_ERR(priv
, "trying to build beacon w/o beacon context!\n");
216 /* Initialize memory */
217 tx_beacon_cmd
= &frame
->u
.beacon
;
218 memset(tx_beacon_cmd
, 0, sizeof(*tx_beacon_cmd
));
220 /* Set up TX beacon contents */
221 frame_size
= iwl_fill_beacon_frame(priv
, tx_beacon_cmd
->frame
,
222 sizeof(frame
->u
) - sizeof(*tx_beacon_cmd
));
223 if (WARN_ON_ONCE(frame_size
> MAX_MPDU_SIZE
))
228 /* Set up TX command fields */
229 tx_beacon_cmd
->tx
.len
= cpu_to_le16((u16
)frame_size
);
230 tx_beacon_cmd
->tx
.sta_id
= priv
->beacon_ctx
->bcast_sta_id
;
231 tx_beacon_cmd
->tx
.stop_time
.life_time
= TX_CMD_LIFE_TIME_INFINITE
;
232 tx_beacon_cmd
->tx
.tx_flags
= TX_CMD_FLG_SEQ_CTL_MSK
|
233 TX_CMD_FLG_TSF_MSK
| TX_CMD_FLG_STA_RATE_MSK
;
235 /* Set up TX beacon command fields */
236 iwl_set_beacon_tim(priv
, tx_beacon_cmd
, (u8
*)tx_beacon_cmd
->frame
,
239 /* Set up packet rate and flags */
240 rate
= iwl_rate_get_lowest_plcp(priv
, priv
->beacon_ctx
);
241 priv
->mgmt_tx_ant
= iwl_toggle_tx_ant(priv
, priv
->mgmt_tx_ant
,
242 priv
->hw_params
.valid_tx_ant
);
243 rate_flags
= iwl_ant_idx_to_flags(priv
->mgmt_tx_ant
);
244 if ((rate
>= IWL_FIRST_CCK_RATE
) && (rate
<= IWL_LAST_CCK_RATE
))
245 rate_flags
|= RATE_MCS_CCK_MSK
;
246 tx_beacon_cmd
->tx
.rate_n_flags
= iwl_hw_set_rate_n_flags(rate
,
249 return sizeof(*tx_beacon_cmd
) + frame_size
;
252 int iwlagn_send_beacon_cmd(struct iwl_priv
*priv
)
254 struct iwl_frame
*frame
;
255 unsigned int frame_size
;
258 frame
= iwl_get_free_frame(priv
);
260 IWL_ERR(priv
, "Could not obtain free frame buffer for beacon "
265 frame_size
= iwl_hw_get_beacon_cmd(priv
, frame
);
267 IWL_ERR(priv
, "Error configuring the beacon command\n");
268 iwl_free_frame(priv
, frame
);
272 rc
= iwl_send_cmd_pdu(priv
, REPLY_TX_BEACON
, frame_size
,
275 iwl_free_frame(priv
, frame
);
280 static inline dma_addr_t
iwl_tfd_tb_get_addr(struct iwl_tfd
*tfd
, u8 idx
)
282 struct iwl_tfd_tb
*tb
= &tfd
->tbs
[idx
];
284 dma_addr_t addr
= get_unaligned_le32(&tb
->lo
);
285 if (sizeof(dma_addr_t
) > sizeof(u32
))
287 ((dma_addr_t
)(le16_to_cpu(tb
->hi_n_len
) & 0xF) << 16) << 16;
292 static inline u16
iwl_tfd_tb_get_len(struct iwl_tfd
*tfd
, u8 idx
)
294 struct iwl_tfd_tb
*tb
= &tfd
->tbs
[idx
];
296 return le16_to_cpu(tb
->hi_n_len
) >> 4;
299 static inline void iwl_tfd_set_tb(struct iwl_tfd
*tfd
, u8 idx
,
300 dma_addr_t addr
, u16 len
)
302 struct iwl_tfd_tb
*tb
= &tfd
->tbs
[idx
];
303 u16 hi_n_len
= len
<< 4;
305 put_unaligned_le32(addr
, &tb
->lo
);
306 if (sizeof(dma_addr_t
) > sizeof(u32
))
307 hi_n_len
|= ((addr
>> 16) >> 16) & 0xF;
309 tb
->hi_n_len
= cpu_to_le16(hi_n_len
);
311 tfd
->num_tbs
= idx
+ 1;
314 static inline u8
iwl_tfd_get_num_tbs(struct iwl_tfd
*tfd
)
316 return tfd
->num_tbs
& 0x1f;
320 * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
321 * @priv - driver private data
324 * Does NOT advance any TFD circular buffer read/write indexes
325 * Does NOT free the TFD itself (which is within circular buffer)
327 void iwl_hw_txq_free_tfd(struct iwl_priv
*priv
, struct iwl_tx_queue
*txq
)
329 struct iwl_tfd
*tfd_tmp
= (struct iwl_tfd
*)txq
->tfds
;
331 struct pci_dev
*dev
= priv
->pci_dev
;
332 int index
= txq
->q
.read_ptr
;
336 tfd
= &tfd_tmp
[index
];
338 /* Sanity check on number of chunks */
339 num_tbs
= iwl_tfd_get_num_tbs(tfd
);
341 if (num_tbs
>= IWL_NUM_OF_TBS
) {
342 IWL_ERR(priv
, "Too many chunks: %i\n", num_tbs
);
343 /* @todo issue fatal error, it is quite serious situation */
349 pci_unmap_single(dev
,
350 dma_unmap_addr(&txq
->meta
[index
], mapping
),
351 dma_unmap_len(&txq
->meta
[index
], len
),
352 PCI_DMA_BIDIRECTIONAL
);
354 /* Unmap chunks, if any. */
355 for (i
= 1; i
< num_tbs
; i
++)
356 pci_unmap_single(dev
, iwl_tfd_tb_get_addr(tfd
, i
),
357 iwl_tfd_tb_get_len(tfd
, i
), PCI_DMA_TODEVICE
);
363 skb
= txq
->txb
[txq
->q
.read_ptr
].skb
;
365 /* can be called from irqs-disabled context */
367 dev_kfree_skb_any(skb
);
368 txq
->txb
[txq
->q
.read_ptr
].skb
= NULL
;
373 int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv
*priv
,
374 struct iwl_tx_queue
*txq
,
375 dma_addr_t addr
, u16 len
,
379 struct iwl_tfd
*tfd
, *tfd_tmp
;
383 tfd_tmp
= (struct iwl_tfd
*)txq
->tfds
;
384 tfd
= &tfd_tmp
[q
->write_ptr
];
387 memset(tfd
, 0, sizeof(*tfd
));
389 num_tbs
= iwl_tfd_get_num_tbs(tfd
);
391 /* Each TFD can point to a maximum 20 Tx buffers */
392 if (num_tbs
>= IWL_NUM_OF_TBS
) {
393 IWL_ERR(priv
, "Error can not send more than %d chunks\n",
398 BUG_ON(addr
& ~DMA_BIT_MASK(36));
399 if (unlikely(addr
& ~IWL_TX_DMA_MASK
))
400 IWL_ERR(priv
, "Unaligned address = %llx\n",
401 (unsigned long long)addr
);
403 iwl_tfd_set_tb(tfd
, num_tbs
, addr
, len
);
409 * Tell nic where to find circular buffer of Tx Frame Descriptors for
410 * given Tx queue, and enable the DMA channel used for that queue.
412 * supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
413 * channels supported in hardware.
415 int iwl_hw_tx_queue_init(struct iwl_priv
*priv
,
416 struct iwl_tx_queue
*txq
)
418 int txq_id
= txq
->q
.id
;
420 /* Circular buffer (TFD queue in DRAM) physical base address */
421 iwl_write_direct32(priv
, FH_MEM_CBBC_QUEUE(txq_id
),
422 txq
->q
.dma_addr
>> 8);
427 static void iwl_bg_beacon_update(struct work_struct
*work
)
429 struct iwl_priv
*priv
=
430 container_of(work
, struct iwl_priv
, beacon_update
);
431 struct sk_buff
*beacon
;
433 mutex_lock(&priv
->mutex
);
434 if (!priv
->beacon_ctx
) {
435 IWL_ERR(priv
, "updating beacon w/o beacon context!\n");
439 if (priv
->beacon_ctx
->vif
->type
!= NL80211_IFTYPE_AP
) {
441 * The ucode will send beacon notifications even in
442 * IBSS mode, but we don't want to process them. But
443 * we need to defer the type check to here due to
444 * requiring locking around the beacon_ctx access.
449 /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
450 beacon
= ieee80211_beacon_get(priv
->hw
, priv
->beacon_ctx
->vif
);
452 IWL_ERR(priv
, "update beacon failed -- keeping old\n");
456 /* new beacon skb is allocated every time; dispose previous.*/
457 dev_kfree_skb(priv
->beacon_skb
);
459 priv
->beacon_skb
= beacon
;
461 iwlagn_send_beacon_cmd(priv
);
463 mutex_unlock(&priv
->mutex
);
466 static void iwl_bg_bt_runtime_config(struct work_struct
*work
)
468 struct iwl_priv
*priv
=
469 container_of(work
, struct iwl_priv
, bt_runtime_config
);
471 if (test_bit(STATUS_EXIT_PENDING
, &priv
->status
))
474 /* dont send host command if rf-kill is on */
475 if (!iwl_is_ready_rf(priv
))
477 priv
->cfg
->ops
->hcmd
->send_bt_config(priv
);
480 static void iwl_bg_bt_full_concurrency(struct work_struct
*work
)
482 struct iwl_priv
*priv
=
483 container_of(work
, struct iwl_priv
, bt_full_concurrency
);
484 struct iwl_rxon_context
*ctx
;
486 mutex_lock(&priv
->mutex
);
488 if (test_bit(STATUS_EXIT_PENDING
, &priv
->status
))
491 /* dont send host command if rf-kill is on */
492 if (!iwl_is_ready_rf(priv
))
495 IWL_DEBUG_INFO(priv
, "BT coex in %s mode\n",
496 priv
->bt_full_concurrent
?
497 "full concurrency" : "3-wire");
500 * LQ & RXON updated cmds must be sent before BT Config cmd
501 * to avoid 3-wire collisions
503 for_each_context(priv
, ctx
) {
504 if (priv
->cfg
->ops
->hcmd
->set_rxon_chain
)
505 priv
->cfg
->ops
->hcmd
->set_rxon_chain(priv
, ctx
);
506 iwlcore_commit_rxon(priv
, ctx
);
509 priv
->cfg
->ops
->hcmd
->send_bt_config(priv
);
511 mutex_unlock(&priv
->mutex
);
515 * iwl_bg_statistics_periodic - Timer callback to queue statistics
517 * This callback is provided in order to send a statistics request.
519 * This timer function is continually reset to execute within
520 * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
521 * was received. We need to ensure we receive the statistics in order
522 * to update the temperature used for calibrating the TXPOWER.
524 static void iwl_bg_statistics_periodic(unsigned long data
)
526 struct iwl_priv
*priv
= (struct iwl_priv
*)data
;
528 if (test_bit(STATUS_EXIT_PENDING
, &priv
->status
))
531 /* dont send host command if rf-kill is on */
532 if (!iwl_is_ready_rf(priv
))
535 iwl_send_statistics_request(priv
, CMD_ASYNC
, false);
539 static void iwl_print_cont_event_trace(struct iwl_priv
*priv
, u32 base
,
540 u32 start_idx
, u32 num_events
,
544 u32 ptr
; /* SRAM byte address of log data */
545 u32 ev
, time
, data
; /* event log data */
546 unsigned long reg_flags
;
549 ptr
= base
+ (4 * sizeof(u32
)) + (start_idx
* 2 * sizeof(u32
));
551 ptr
= base
+ (4 * sizeof(u32
)) + (start_idx
* 3 * sizeof(u32
));
553 /* Make sure device is powered up for SRAM reads */
554 spin_lock_irqsave(&priv
->reg_lock
, reg_flags
);
555 if (iwl_grab_nic_access(priv
)) {
556 spin_unlock_irqrestore(&priv
->reg_lock
, reg_flags
);
560 /* Set starting address; reads will auto-increment */
561 _iwl_write_direct32(priv
, HBUS_TARG_MEM_RADDR
, ptr
);
565 * "time" is actually "data" for mode 0 (no timestamp).
566 * place event id # at far right for easier visual parsing.
568 for (i
= 0; i
< num_events
; i
++) {
569 ev
= _iwl_read_direct32(priv
, HBUS_TARG_MEM_RDAT
);
570 time
= _iwl_read_direct32(priv
, HBUS_TARG_MEM_RDAT
);
572 trace_iwlwifi_dev_ucode_cont_event(priv
,
575 data
= _iwl_read_direct32(priv
, HBUS_TARG_MEM_RDAT
);
576 trace_iwlwifi_dev_ucode_cont_event(priv
,
580 /* Allow device to power down */
581 iwl_release_nic_access(priv
);
582 spin_unlock_irqrestore(&priv
->reg_lock
, reg_flags
);
585 static void iwl_continuous_event_trace(struct iwl_priv
*priv
)
587 u32 capacity
; /* event log capacity in # entries */
588 u32 base
; /* SRAM byte address of event log header */
589 u32 mode
; /* 0 - no timestamp, 1 - timestamp recorded */
590 u32 num_wraps
; /* # times uCode wrapped to top of log */
591 u32 next_entry
; /* index of next entry to be written by uCode */
593 if (priv
->ucode_type
== UCODE_INIT
)
594 base
= le32_to_cpu(priv
->card_alive_init
.error_event_table_ptr
);
596 base
= le32_to_cpu(priv
->card_alive
.log_event_table_ptr
);
597 if (priv
->cfg
->ops
->lib
->is_valid_rtc_data_addr(base
)) {
598 capacity
= iwl_read_targ_mem(priv
, base
);
599 num_wraps
= iwl_read_targ_mem(priv
, base
+ (2 * sizeof(u32
)));
600 mode
= iwl_read_targ_mem(priv
, base
+ (1 * sizeof(u32
)));
601 next_entry
= iwl_read_targ_mem(priv
, base
+ (3 * sizeof(u32
)));
605 if (num_wraps
== priv
->event_log
.num_wraps
) {
606 iwl_print_cont_event_trace(priv
,
607 base
, priv
->event_log
.next_entry
,
608 next_entry
- priv
->event_log
.next_entry
,
610 priv
->event_log
.non_wraps_count
++;
612 if ((num_wraps
- priv
->event_log
.num_wraps
) > 1)
613 priv
->event_log
.wraps_more_count
++;
615 priv
->event_log
.wraps_once_count
++;
616 trace_iwlwifi_dev_ucode_wrap_event(priv
,
617 num_wraps
- priv
->event_log
.num_wraps
,
618 next_entry
, priv
->event_log
.next_entry
);
619 if (next_entry
< priv
->event_log
.next_entry
) {
620 iwl_print_cont_event_trace(priv
, base
,
621 priv
->event_log
.next_entry
,
622 capacity
- priv
->event_log
.next_entry
,
625 iwl_print_cont_event_trace(priv
, base
, 0,
628 iwl_print_cont_event_trace(priv
, base
,
629 next_entry
, capacity
- next_entry
,
632 iwl_print_cont_event_trace(priv
, base
, 0,
636 priv
->event_log
.num_wraps
= num_wraps
;
637 priv
->event_log
.next_entry
= next_entry
;
641 * iwl_bg_ucode_trace - Timer callback to log ucode event
643 * The timer is continually set to execute every
644 * UCODE_TRACE_PERIOD milliseconds after the last timer expired
645 * this function is to perform continuous uCode event logging operation
648 static void iwl_bg_ucode_trace(unsigned long data
)
650 struct iwl_priv
*priv
= (struct iwl_priv
*)data
;
652 if (test_bit(STATUS_EXIT_PENDING
, &priv
->status
))
655 if (priv
->event_log
.ucode_trace
) {
656 iwl_continuous_event_trace(priv
);
657 /* Reschedule the timer to occur in UCODE_TRACE_PERIOD */
658 mod_timer(&priv
->ucode_trace
,
659 jiffies
+ msecs_to_jiffies(UCODE_TRACE_PERIOD
));
663 static void iwl_bg_tx_flush(struct work_struct
*work
)
665 struct iwl_priv
*priv
=
666 container_of(work
, struct iwl_priv
, tx_flush
);
668 if (test_bit(STATUS_EXIT_PENDING
, &priv
->status
))
671 /* do nothing if rf-kill is on */
672 if (!iwl_is_ready_rf(priv
))
675 if (priv
->cfg
->ops
->lib
->txfifo_flush
) {
676 IWL_DEBUG_INFO(priv
, "device request: flush all tx frames\n");
677 iwlagn_dev_txfifo_flush(priv
, IWL_DROP_ALL
);
682 * iwl_rx_handle - Main entry function for receiving responses from uCode
684 * Uses the priv->rx_handlers callback function array to invoke
685 * the appropriate handlers, including command responses,
686 * frame-received notifications, and other notifications.
688 static void iwl_rx_handle(struct iwl_priv
*priv
)
690 struct iwl_rx_mem_buffer
*rxb
;
691 struct iwl_rx_packet
*pkt
;
692 struct iwl_rx_queue
*rxq
= &priv
->rxq
;
700 /* uCode's read index (stored in shared DRAM) indicates the last Rx
701 * buffer that the driver may process (last buffer filled by ucode). */
702 r
= le16_to_cpu(rxq
->rb_stts
->closed_rb_num
) & 0x0FFF;
705 /* Rx interrupt, but nothing sent from uCode */
707 IWL_DEBUG_RX(priv
, "r = %d, i = %d\n", r
, i
);
709 /* calculate total frames need to be restock after handling RX */
710 total_empty
= r
- rxq
->write_actual
;
712 total_empty
+= RX_QUEUE_SIZE
;
714 if (total_empty
> (RX_QUEUE_SIZE
/ 2))
722 /* If an RXB doesn't have a Rx queue slot associated with it,
723 * then a bug has been introduced in the queue refilling
724 * routines -- catch it here */
727 rxq
->queue
[i
] = NULL
;
729 pci_unmap_page(priv
->pci_dev
, rxb
->page_dma
,
730 PAGE_SIZE
<< priv
->hw_params
.rx_page_order
,
734 len
= le32_to_cpu(pkt
->len_n_flags
) & FH_RSCSR_FRAME_SIZE_MSK
;
735 len
+= sizeof(u32
); /* account for status word */
736 trace_iwlwifi_dev_rx(priv
, pkt
, len
);
738 /* Reclaim a command buffer only if this packet is a response
739 * to a (driver-originated) command.
740 * If the packet (e.g. Rx frame) originated from uCode,
741 * there is no command buffer to reclaim.
742 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
743 * but apparently a few don't get set; catch them here. */
744 reclaim
= !(pkt
->hdr
.sequence
& SEQ_RX_FRAME
) &&
745 (pkt
->hdr
.cmd
!= REPLY_RX_PHY_CMD
) &&
746 (pkt
->hdr
.cmd
!= REPLY_RX
) &&
747 (pkt
->hdr
.cmd
!= REPLY_RX_MPDU_CMD
) &&
748 (pkt
->hdr
.cmd
!= REPLY_COMPRESSED_BA
) &&
749 (pkt
->hdr
.cmd
!= STATISTICS_NOTIFICATION
) &&
750 (pkt
->hdr
.cmd
!= REPLY_TX
);
753 * Do the notification wait before RX handlers so
754 * even if the RX handler consumes the RXB we have
755 * access to it in the notification wait entry.
757 if (!list_empty(&priv
->_agn
.notif_waits
)) {
758 struct iwl_notification_wait
*w
;
760 spin_lock(&priv
->_agn
.notif_wait_lock
);
761 list_for_each_entry(w
, &priv
->_agn
.notif_waits
, list
) {
762 if (w
->cmd
== pkt
->hdr
.cmd
) {
768 spin_unlock(&priv
->_agn
.notif_wait_lock
);
770 wake_up_all(&priv
->_agn
.notif_waitq
);
773 /* Based on type of command response or notification,
774 * handle those that need handling via function in
775 * rx_handlers table. See iwl_setup_rx_handlers() */
776 if (priv
->rx_handlers
[pkt
->hdr
.cmd
]) {
777 IWL_DEBUG_RX(priv
, "r = %d, i = %d, %s, 0x%02x\n", r
,
778 i
, get_cmd_string(pkt
->hdr
.cmd
), pkt
->hdr
.cmd
);
779 priv
->isr_stats
.rx_handlers
[pkt
->hdr
.cmd
]++;
780 priv
->rx_handlers
[pkt
->hdr
.cmd
] (priv
, rxb
);
782 /* No handling needed */
784 "r %d i %d No handler needed for %s, 0x%02x\n",
785 r
, i
, get_cmd_string(pkt
->hdr
.cmd
),
790 * XXX: After here, we should always check rxb->page
791 * against NULL before touching it or its virtual
792 * memory (pkt). Because some rx_handler might have
793 * already taken or freed the pages.
797 /* Invoke any callbacks, transfer the buffer to caller,
798 * and fire off the (possibly) blocking iwl_send_cmd()
799 * as we reclaim the driver command queue */
801 iwl_tx_cmd_complete(priv
, rxb
);
803 IWL_WARN(priv
, "Claim null rxb?\n");
806 /* Reuse the page if possible. For notification packets and
807 * SKBs that fail to Rx correctly, add them back into the
808 * rx_free list for reuse later. */
809 spin_lock_irqsave(&rxq
->lock
, flags
);
810 if (rxb
->page
!= NULL
) {
811 rxb
->page_dma
= pci_map_page(priv
->pci_dev
, rxb
->page
,
812 0, PAGE_SIZE
<< priv
->hw_params
.rx_page_order
,
814 list_add_tail(&rxb
->list
, &rxq
->rx_free
);
817 list_add_tail(&rxb
->list
, &rxq
->rx_used
);
819 spin_unlock_irqrestore(&rxq
->lock
, flags
);
821 i
= (i
+ 1) & RX_QUEUE_MASK
;
822 /* If there are a lot of unused frames,
823 * restock the Rx queue so ucode wont assert. */
828 iwlagn_rx_replenish_now(priv
);
834 /* Backtrack one entry */
837 iwlagn_rx_replenish_now(priv
);
839 iwlagn_rx_queue_restock(priv
);
842 /* call this function to flush any scheduled tasklet */
843 static inline void iwl_synchronize_irq(struct iwl_priv
*priv
)
845 /* wait to make sure we flush pending tasklet*/
846 synchronize_irq(priv
->pci_dev
->irq
);
847 tasklet_kill(&priv
->irq_tasklet
);
850 /* tasklet for iwlagn interrupt */
851 static void iwl_irq_tasklet(struct iwl_priv
*priv
)
857 #ifdef CONFIG_IWLWIFI_DEBUG
861 spin_lock_irqsave(&priv
->lock
, flags
);
863 /* Ack/clear/reset pending uCode interrupts.
864 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
866 /* There is a hardware bug in the interrupt mask function that some
867 * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
868 * they are disabled in the CSR_INT_MASK register. Furthermore the
869 * ICT interrupt handling mechanism has another bug that might cause
870 * these unmasked interrupts fail to be detected. We workaround the
871 * hardware bugs here by ACKing all the possible interrupts so that
872 * interrupt coalescing can still be achieved.
874 iwl_write32(priv
, CSR_INT
, priv
->_agn
.inta
| ~priv
->inta_mask
);
876 inta
= priv
->_agn
.inta
;
878 #ifdef CONFIG_IWLWIFI_DEBUG
879 if (iwl_get_debug_level(priv
) & IWL_DL_ISR
) {
881 inta_mask
= iwl_read32(priv
, CSR_INT_MASK
);
882 IWL_DEBUG_ISR(priv
, "inta 0x%08x, enabled 0x%08x\n ",
887 spin_unlock_irqrestore(&priv
->lock
, flags
);
889 /* saved interrupt in inta variable now we can reset priv->_agn.inta */
892 /* Now service all interrupt bits discovered above. */
893 if (inta
& CSR_INT_BIT_HW_ERR
) {
894 IWL_ERR(priv
, "Hardware error detected. Restarting.\n");
896 /* Tell the device to stop sending interrupts */
897 iwl_disable_interrupts(priv
);
899 priv
->isr_stats
.hw
++;
900 iwl_irq_handle_error(priv
);
902 handled
|= CSR_INT_BIT_HW_ERR
;
907 #ifdef CONFIG_IWLWIFI_DEBUG
908 if (iwl_get_debug_level(priv
) & (IWL_DL_ISR
)) {
909 /* NIC fires this, but we don't use it, redundant with WAKEUP */
910 if (inta
& CSR_INT_BIT_SCD
) {
911 IWL_DEBUG_ISR(priv
, "Scheduler finished to transmit "
912 "the frame/frames.\n");
913 priv
->isr_stats
.sch
++;
916 /* Alive notification via Rx interrupt will do the real work */
917 if (inta
& CSR_INT_BIT_ALIVE
) {
918 IWL_DEBUG_ISR(priv
, "Alive interrupt\n");
919 priv
->isr_stats
.alive
++;
923 /* Safely ignore these bits for debug checks below */
924 inta
&= ~(CSR_INT_BIT_SCD
| CSR_INT_BIT_ALIVE
);
926 /* HW RF KILL switch toggled */
927 if (inta
& CSR_INT_BIT_RF_KILL
) {
929 if (!(iwl_read32(priv
, CSR_GP_CNTRL
) &
930 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW
))
933 IWL_WARN(priv
, "RF_KILL bit toggled to %s.\n",
934 hw_rf_kill
? "disable radio" : "enable radio");
936 priv
->isr_stats
.rfkill
++;
938 /* driver only loads ucode once setting the interface up.
939 * the driver allows loading the ucode even if the radio
940 * is killed. Hence update the killswitch state here. The
941 * rfkill handler will care about restarting if needed.
943 if (!test_bit(STATUS_ALIVE
, &priv
->status
)) {
945 set_bit(STATUS_RF_KILL_HW
, &priv
->status
);
947 clear_bit(STATUS_RF_KILL_HW
, &priv
->status
);
948 wiphy_rfkill_set_hw_state(priv
->hw
->wiphy
, hw_rf_kill
);
951 handled
|= CSR_INT_BIT_RF_KILL
;
954 /* Chip got too hot and stopped itself */
955 if (inta
& CSR_INT_BIT_CT_KILL
) {
956 IWL_ERR(priv
, "Microcode CT kill error detected.\n");
957 priv
->isr_stats
.ctkill
++;
958 handled
|= CSR_INT_BIT_CT_KILL
;
961 /* Error detected by uCode */
962 if (inta
& CSR_INT_BIT_SW_ERR
) {
963 IWL_ERR(priv
, "Microcode SW error detected. "
964 " Restarting 0x%X.\n", inta
);
965 priv
->isr_stats
.sw
++;
966 iwl_irq_handle_error(priv
);
967 handled
|= CSR_INT_BIT_SW_ERR
;
970 /* uCode wakes up after power-down sleep */
971 if (inta
& CSR_INT_BIT_WAKEUP
) {
972 IWL_DEBUG_ISR(priv
, "Wakeup interrupt\n");
973 iwl_rx_queue_update_write_ptr(priv
, &priv
->rxq
);
974 for (i
= 0; i
< priv
->hw_params
.max_txq_num
; i
++)
975 iwl_txq_update_write_ptr(priv
, &priv
->txq
[i
]);
977 priv
->isr_stats
.wakeup
++;
979 handled
|= CSR_INT_BIT_WAKEUP
;
982 /* All uCode command responses, including Tx command responses,
983 * Rx "responses" (frame-received notification), and other
984 * notifications from uCode come through here*/
985 if (inta
& (CSR_INT_BIT_FH_RX
| CSR_INT_BIT_SW_RX
|
986 CSR_INT_BIT_RX_PERIODIC
)) {
987 IWL_DEBUG_ISR(priv
, "Rx interrupt\n");
988 if (inta
& (CSR_INT_BIT_FH_RX
| CSR_INT_BIT_SW_RX
)) {
989 handled
|= (CSR_INT_BIT_FH_RX
| CSR_INT_BIT_SW_RX
);
990 iwl_write32(priv
, CSR_FH_INT_STATUS
,
993 if (inta
& CSR_INT_BIT_RX_PERIODIC
) {
994 handled
|= CSR_INT_BIT_RX_PERIODIC
;
995 iwl_write32(priv
, CSR_INT
, CSR_INT_BIT_RX_PERIODIC
);
997 /* Sending RX interrupt require many steps to be done in the
999 * 1- write interrupt to current index in ICT table.
1001 * 3- update RX shared data to indicate last write index.
1002 * 4- send interrupt.
1003 * This could lead to RX race, driver could receive RX interrupt
1004 * but the shared data changes does not reflect this;
1005 * periodic interrupt will detect any dangling Rx activity.
1008 /* Disable periodic interrupt; we use it as just a one-shot. */
1009 iwl_write8(priv
, CSR_INT_PERIODIC_REG
,
1010 CSR_INT_PERIODIC_DIS
);
1011 iwl_rx_handle(priv
);
1014 * Enable periodic interrupt in 8 msec only if we received
1015 * real RX interrupt (instead of just periodic int), to catch
1016 * any dangling Rx interrupt. If it was just the periodic
1017 * interrupt, there was no dangling Rx activity, and no need
1018 * to extend the periodic interrupt; one-shot is enough.
1020 if (inta
& (CSR_INT_BIT_FH_RX
| CSR_INT_BIT_SW_RX
))
1021 iwl_write8(priv
, CSR_INT_PERIODIC_REG
,
1022 CSR_INT_PERIODIC_ENA
);
1024 priv
->isr_stats
.rx
++;
1027 /* This "Tx" DMA channel is used only for loading uCode */
1028 if (inta
& CSR_INT_BIT_FH_TX
) {
1029 iwl_write32(priv
, CSR_FH_INT_STATUS
, CSR_FH_INT_TX_MASK
);
1030 IWL_DEBUG_ISR(priv
, "uCode load interrupt\n");
1031 priv
->isr_stats
.tx
++;
1032 handled
|= CSR_INT_BIT_FH_TX
;
1033 /* Wake up uCode load routine, now that load is complete */
1034 priv
->ucode_write_complete
= 1;
1035 wake_up_interruptible(&priv
->wait_command_queue
);
1038 if (inta
& ~handled
) {
1039 IWL_ERR(priv
, "Unhandled INTA bits 0x%08x\n", inta
& ~handled
);
1040 priv
->isr_stats
.unhandled
++;
1043 if (inta
& ~(priv
->inta_mask
)) {
1044 IWL_WARN(priv
, "Disabled INTA bits 0x%08x were pending\n",
1045 inta
& ~priv
->inta_mask
);
1048 /* Re-enable all interrupts */
1049 /* only Re-enable if disabled by irq */
1050 if (test_bit(STATUS_INT_ENABLED
, &priv
->status
))
1051 iwl_enable_interrupts(priv
);
1052 /* Re-enable RF_KILL if it occurred */
1053 else if (handled
& CSR_INT_BIT_RF_KILL
)
1054 iwl_enable_rfkill_int(priv
);
1057 /*****************************************************************************
1061 *****************************************************************************/
1063 #ifdef CONFIG_IWLWIFI_DEBUG
1066 * The following adds a new attribute to the sysfs representation
1067 * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
1068 * used for controlling the debug level.
1070 * See the level definitions in iwl for details.
1072 * The debug_level being managed using sysfs below is a per device debug
1073 * level that is used instead of the global debug level if it (the per
1074 * device debug level) is set.
1076 static ssize_t
show_debug_level(struct device
*d
,
1077 struct device_attribute
*attr
, char *buf
)
1079 struct iwl_priv
*priv
= dev_get_drvdata(d
);
1080 return sprintf(buf
, "0x%08X\n", iwl_get_debug_level(priv
));
1082 static ssize_t
store_debug_level(struct device
*d
,
1083 struct device_attribute
*attr
,
1084 const char *buf
, size_t count
)
1086 struct iwl_priv
*priv
= dev_get_drvdata(d
);
1090 ret
= strict_strtoul(buf
, 0, &val
);
1092 IWL_ERR(priv
, "%s is not in hex or decimal form.\n", buf
);
1094 priv
->debug_level
= val
;
1095 if (iwl_alloc_traffic_mem(priv
))
1097 "Not enough memory to generate traffic log\n");
1099 return strnlen(buf
, count
);
1102 static DEVICE_ATTR(debug_level
, S_IWUSR
| S_IRUGO
,
1103 show_debug_level
, store_debug_level
);
1106 #endif /* CONFIG_IWLWIFI_DEBUG */
1109 static ssize_t
show_temperature(struct device
*d
,
1110 struct device_attribute
*attr
, char *buf
)
1112 struct iwl_priv
*priv
= dev_get_drvdata(d
);
1114 if (!iwl_is_alive(priv
))
1117 return sprintf(buf
, "%d\n", priv
->temperature
);
1120 static DEVICE_ATTR(temperature
, S_IRUGO
, show_temperature
, NULL
);
1122 static ssize_t
show_tx_power(struct device
*d
,
1123 struct device_attribute
*attr
, char *buf
)
1125 struct iwl_priv
*priv
= dev_get_drvdata(d
);
1127 if (!iwl_is_ready_rf(priv
))
1128 return sprintf(buf
, "off\n");
1130 return sprintf(buf
, "%d\n", priv
->tx_power_user_lmt
);
1133 static ssize_t
store_tx_power(struct device
*d
,
1134 struct device_attribute
*attr
,
1135 const char *buf
, size_t count
)
1137 struct iwl_priv
*priv
= dev_get_drvdata(d
);
1141 ret
= strict_strtoul(buf
, 10, &val
);
1143 IWL_INFO(priv
, "%s is not in decimal form.\n", buf
);
1145 ret
= iwl_set_tx_power(priv
, val
, false);
1147 IWL_ERR(priv
, "failed setting tx power (0x%d).\n",
1155 static DEVICE_ATTR(tx_power
, S_IWUSR
| S_IRUGO
, show_tx_power
, store_tx_power
);
1157 static struct attribute
*iwl_sysfs_entries
[] = {
1158 &dev_attr_temperature
.attr
,
1159 &dev_attr_tx_power
.attr
,
1160 #ifdef CONFIG_IWLWIFI_DEBUG
1161 &dev_attr_debug_level
.attr
,
1166 static struct attribute_group iwl_attribute_group
= {
1167 .name
= NULL
, /* put in device directory */
1168 .attrs
= iwl_sysfs_entries
,
1171 /******************************************************************************
1173 * uCode download functions
1175 ******************************************************************************/
1177 static void iwl_dealloc_ucode_pci(struct iwl_priv
*priv
)
1179 iwl_free_fw_desc(priv
->pci_dev
, &priv
->ucode_code
);
1180 iwl_free_fw_desc(priv
->pci_dev
, &priv
->ucode_data
);
1181 iwl_free_fw_desc(priv
->pci_dev
, &priv
->ucode_data_backup
);
1182 iwl_free_fw_desc(priv
->pci_dev
, &priv
->ucode_init
);
1183 iwl_free_fw_desc(priv
->pci_dev
, &priv
->ucode_init_data
);
1184 iwl_free_fw_desc(priv
->pci_dev
, &priv
->ucode_boot
);
1187 static void iwl_nic_start(struct iwl_priv
*priv
)
1189 /* Remove all resets to allow NIC to operate */
1190 iwl_write32(priv
, CSR_RESET
, 0);
1193 struct iwlagn_ucode_capabilities
{
1194 u32 max_probe_length
;
1195 u32 standard_phy_calibration_size
;
1199 static void iwl_ucode_callback(const struct firmware
*ucode_raw
, void *context
);
1200 static int iwl_mac_setup_register(struct iwl_priv
*priv
,
1201 struct iwlagn_ucode_capabilities
*capa
);
1203 #define UCODE_EXPERIMENTAL_INDEX 100
1204 #define UCODE_EXPERIMENTAL_TAG "exp"
1206 static int __must_check
iwl_request_firmware(struct iwl_priv
*priv
, bool first
)
1208 const char *name_pre
= priv
->cfg
->fw_name_pre
;
1212 #ifdef CONFIG_IWLWIFI_DEBUG_EXPERIMENTAL_UCODE
1213 priv
->fw_index
= UCODE_EXPERIMENTAL_INDEX
;
1214 strcpy(tag
, UCODE_EXPERIMENTAL_TAG
);
1215 } else if (priv
->fw_index
== UCODE_EXPERIMENTAL_INDEX
) {
1217 priv
->fw_index
= priv
->cfg
->ucode_api_max
;
1218 sprintf(tag
, "%d", priv
->fw_index
);
1221 sprintf(tag
, "%d", priv
->fw_index
);
1224 if (priv
->fw_index
< priv
->cfg
->ucode_api_min
) {
1225 IWL_ERR(priv
, "no suitable firmware found!\n");
1229 sprintf(priv
->firmware_name
, "%s%s%s", name_pre
, tag
, ".ucode");
1231 IWL_DEBUG_INFO(priv
, "attempting to load firmware %s'%s'\n",
1232 (priv
->fw_index
== UCODE_EXPERIMENTAL_INDEX
)
1233 ? "EXPERIMENTAL " : "",
1234 priv
->firmware_name
);
1236 return request_firmware_nowait(THIS_MODULE
, 1, priv
->firmware_name
,
1237 &priv
->pci_dev
->dev
, GFP_KERNEL
, priv
,
1238 iwl_ucode_callback
);
1241 struct iwlagn_firmware_pieces
{
1242 const void *inst
, *data
, *init
, *init_data
, *boot
;
1243 size_t inst_size
, data_size
, init_size
, init_data_size
, boot_size
;
1247 u32 init_evtlog_ptr
, init_evtlog_size
, init_errlog_ptr
;
1248 u32 inst_evtlog_ptr
, inst_evtlog_size
, inst_errlog_ptr
;
1251 static int iwlagn_load_legacy_firmware(struct iwl_priv
*priv
,
1252 const struct firmware
*ucode_raw
,
1253 struct iwlagn_firmware_pieces
*pieces
)
1255 struct iwl_ucode_header
*ucode
= (void *)ucode_raw
->data
;
1256 u32 api_ver
, hdr_size
;
1259 priv
->ucode_ver
= le32_to_cpu(ucode
->ver
);
1260 api_ver
= IWL_UCODE_API(priv
->ucode_ver
);
1265 if (ucode_raw
->size
< hdr_size
) {
1266 IWL_ERR(priv
, "File size too small!\n");
1269 pieces
->build
= le32_to_cpu(ucode
->u
.v2
.build
);
1270 pieces
->inst_size
= le32_to_cpu(ucode
->u
.v2
.inst_size
);
1271 pieces
->data_size
= le32_to_cpu(ucode
->u
.v2
.data_size
);
1272 pieces
->init_size
= le32_to_cpu(ucode
->u
.v2
.init_size
);
1273 pieces
->init_data_size
= le32_to_cpu(ucode
->u
.v2
.init_data_size
);
1274 pieces
->boot_size
= le32_to_cpu(ucode
->u
.v2
.boot_size
);
1275 src
= ucode
->u
.v2
.data
;
1281 if (ucode_raw
->size
< hdr_size
) {
1282 IWL_ERR(priv
, "File size too small!\n");
1286 pieces
->inst_size
= le32_to_cpu(ucode
->u
.v1
.inst_size
);
1287 pieces
->data_size
= le32_to_cpu(ucode
->u
.v1
.data_size
);
1288 pieces
->init_size
= le32_to_cpu(ucode
->u
.v1
.init_size
);
1289 pieces
->init_data_size
= le32_to_cpu(ucode
->u
.v1
.init_data_size
);
1290 pieces
->boot_size
= le32_to_cpu(ucode
->u
.v1
.boot_size
);
1291 src
= ucode
->u
.v1
.data
;
1295 /* Verify size of file vs. image size info in file's header */
1296 if (ucode_raw
->size
!= hdr_size
+ pieces
->inst_size
+
1297 pieces
->data_size
+ pieces
->init_size
+
1298 pieces
->init_data_size
+ pieces
->boot_size
) {
1301 "uCode file size %d does not match expected size\n",
1302 (int)ucode_raw
->size
);
1307 src
+= pieces
->inst_size
;
1309 src
+= pieces
->data_size
;
1311 src
+= pieces
->init_size
;
1312 pieces
->init_data
= src
;
1313 src
+= pieces
->init_data_size
;
1315 src
+= pieces
->boot_size
;
1320 static int iwlagn_wanted_ucode_alternative
= 1;
1322 static int iwlagn_load_firmware(struct iwl_priv
*priv
,
1323 const struct firmware
*ucode_raw
,
1324 struct iwlagn_firmware_pieces
*pieces
,
1325 struct iwlagn_ucode_capabilities
*capa
)
1327 struct iwl_tlv_ucode_header
*ucode
= (void *)ucode_raw
->data
;
1328 struct iwl_ucode_tlv
*tlv
;
1329 size_t len
= ucode_raw
->size
;
1331 int wanted_alternative
= iwlagn_wanted_ucode_alternative
, tmp
;
1334 enum iwl_ucode_tlv_type tlv_type
;
1337 if (len
< sizeof(*ucode
)) {
1338 IWL_ERR(priv
, "uCode has invalid length: %zd\n", len
);
1342 if (ucode
->magic
!= cpu_to_le32(IWL_TLV_UCODE_MAGIC
)) {
1343 IWL_ERR(priv
, "invalid uCode magic: 0X%x\n",
1344 le32_to_cpu(ucode
->magic
));
1349 * Check which alternatives are present, and "downgrade"
1350 * when the chosen alternative is not present, warning
1351 * the user when that happens. Some files may not have
1352 * any alternatives, so don't warn in that case.
1354 alternatives
= le64_to_cpu(ucode
->alternatives
);
1355 tmp
= wanted_alternative
;
1356 if (wanted_alternative
> 63)
1357 wanted_alternative
= 63;
1358 while (wanted_alternative
&& !(alternatives
& BIT(wanted_alternative
)))
1359 wanted_alternative
--;
1360 if (wanted_alternative
&& wanted_alternative
!= tmp
)
1362 "uCode alternative %d not available, choosing %d\n",
1363 tmp
, wanted_alternative
);
1365 priv
->ucode_ver
= le32_to_cpu(ucode
->ver
);
1366 pieces
->build
= le32_to_cpu(ucode
->build
);
1369 len
-= sizeof(*ucode
);
1371 while (len
>= sizeof(*tlv
)) {
1374 len
-= sizeof(*tlv
);
1377 tlv_len
= le32_to_cpu(tlv
->length
);
1378 tlv_type
= le16_to_cpu(tlv
->type
);
1379 tlv_alt
= le16_to_cpu(tlv
->alternative
);
1380 tlv_data
= tlv
->data
;
1382 if (len
< tlv_len
) {
1383 IWL_ERR(priv
, "invalid TLV len: %zd/%u\n",
1387 len
-= ALIGN(tlv_len
, 4);
1388 data
+= sizeof(*tlv
) + ALIGN(tlv_len
, 4);
1391 * Alternative 0 is always valid.
1393 * Skip alternative TLVs that are not selected.
1395 if (tlv_alt
!= 0 && tlv_alt
!= wanted_alternative
)
1399 case IWL_UCODE_TLV_INST
:
1400 pieces
->inst
= tlv_data
;
1401 pieces
->inst_size
= tlv_len
;
1403 case IWL_UCODE_TLV_DATA
:
1404 pieces
->data
= tlv_data
;
1405 pieces
->data_size
= tlv_len
;
1407 case IWL_UCODE_TLV_INIT
:
1408 pieces
->init
= tlv_data
;
1409 pieces
->init_size
= tlv_len
;
1411 case IWL_UCODE_TLV_INIT_DATA
:
1412 pieces
->init_data
= tlv_data
;
1413 pieces
->init_data_size
= tlv_len
;
1415 case IWL_UCODE_TLV_BOOT
:
1416 pieces
->boot
= tlv_data
;
1417 pieces
->boot_size
= tlv_len
;
1419 case IWL_UCODE_TLV_PROBE_MAX_LEN
:
1420 if (tlv_len
!= sizeof(u32
))
1421 goto invalid_tlv_len
;
1422 capa
->max_probe_length
=
1423 le32_to_cpup((__le32
*)tlv_data
);
1425 case IWL_UCODE_TLV_PAN
:
1427 goto invalid_tlv_len
;
1430 case IWL_UCODE_TLV_INIT_EVTLOG_PTR
:
1431 if (tlv_len
!= sizeof(u32
))
1432 goto invalid_tlv_len
;
1433 pieces
->init_evtlog_ptr
=
1434 le32_to_cpup((__le32
*)tlv_data
);
1436 case IWL_UCODE_TLV_INIT_EVTLOG_SIZE
:
1437 if (tlv_len
!= sizeof(u32
))
1438 goto invalid_tlv_len
;
1439 pieces
->init_evtlog_size
=
1440 le32_to_cpup((__le32
*)tlv_data
);
1442 case IWL_UCODE_TLV_INIT_ERRLOG_PTR
:
1443 if (tlv_len
!= sizeof(u32
))
1444 goto invalid_tlv_len
;
1445 pieces
->init_errlog_ptr
=
1446 le32_to_cpup((__le32
*)tlv_data
);
1448 case IWL_UCODE_TLV_RUNT_EVTLOG_PTR
:
1449 if (tlv_len
!= sizeof(u32
))
1450 goto invalid_tlv_len
;
1451 pieces
->inst_evtlog_ptr
=
1452 le32_to_cpup((__le32
*)tlv_data
);
1454 case IWL_UCODE_TLV_RUNT_EVTLOG_SIZE
:
1455 if (tlv_len
!= sizeof(u32
))
1456 goto invalid_tlv_len
;
1457 pieces
->inst_evtlog_size
=
1458 le32_to_cpup((__le32
*)tlv_data
);
1460 case IWL_UCODE_TLV_RUNT_ERRLOG_PTR
:
1461 if (tlv_len
!= sizeof(u32
))
1462 goto invalid_tlv_len
;
1463 pieces
->inst_errlog_ptr
=
1464 le32_to_cpup((__le32
*)tlv_data
);
1466 case IWL_UCODE_TLV_ENHANCE_SENS_TBL
:
1468 goto invalid_tlv_len
;
1469 priv
->enhance_sensitivity_table
= true;
1471 case IWL_UCODE_TLV_PHY_CALIBRATION_SIZE
:
1472 if (tlv_len
!= sizeof(u32
))
1473 goto invalid_tlv_len
;
1474 capa
->standard_phy_calibration_size
=
1475 le32_to_cpup((__le32
*)tlv_data
);
1478 IWL_WARN(priv
, "unknown TLV: %d\n", tlv_type
);
1484 IWL_ERR(priv
, "invalid TLV after parsing: %zd\n", len
);
1485 iwl_print_hex_dump(priv
, IWL_DL_FW
, (u8
*)data
, len
);
1492 IWL_ERR(priv
, "TLV %d has invalid size: %u\n", tlv_type
, tlv_len
);
1493 iwl_print_hex_dump(priv
, IWL_DL_FW
, tlv_data
, tlv_len
);
1499 * iwl_ucode_callback - callback when firmware was loaded
1501 * If loaded successfully, copies the firmware into buffers
1502 * for the card to fetch (via DMA).
1504 static void iwl_ucode_callback(const struct firmware
*ucode_raw
, void *context
)
1506 struct iwl_priv
*priv
= context
;
1507 struct iwl_ucode_header
*ucode
;
1509 struct iwlagn_firmware_pieces pieces
;
1510 const unsigned int api_max
= priv
->cfg
->ucode_api_max
;
1511 const unsigned int api_min
= priv
->cfg
->ucode_api_min
;
1515 struct iwlagn_ucode_capabilities ucode_capa
= {
1516 .max_probe_length
= 200,
1517 .standard_phy_calibration_size
=
1518 IWL_DEFAULT_STANDARD_PHY_CALIBRATE_TBL_SIZE
,
1521 memset(&pieces
, 0, sizeof(pieces
));
1524 if (priv
->fw_index
<= priv
->cfg
->ucode_api_max
)
1526 "request for firmware file '%s' failed.\n",
1527 priv
->firmware_name
);
1531 IWL_DEBUG_INFO(priv
, "Loaded firmware file '%s' (%zd bytes).\n",
1532 priv
->firmware_name
, ucode_raw
->size
);
1534 /* Make sure that we got at least the API version number */
1535 if (ucode_raw
->size
< 4) {
1536 IWL_ERR(priv
, "File size way too small!\n");
1540 /* Data from ucode file: header followed by uCode images */
1541 ucode
= (struct iwl_ucode_header
*)ucode_raw
->data
;
1544 err
= iwlagn_load_legacy_firmware(priv
, ucode_raw
, &pieces
);
1546 err
= iwlagn_load_firmware(priv
, ucode_raw
, &pieces
,
1552 api_ver
= IWL_UCODE_API(priv
->ucode_ver
);
1553 build
= pieces
.build
;
1556 * api_ver should match the api version forming part of the
1557 * firmware filename ... but we don't check for that and only rely
1558 * on the API version read from firmware header from here on forward
1560 /* no api version check required for experimental uCode */
1561 if (priv
->fw_index
!= UCODE_EXPERIMENTAL_INDEX
) {
1562 if (api_ver
< api_min
|| api_ver
> api_max
) {
1564 "Driver unable to support your firmware API. "
1565 "Driver supports v%u, firmware is v%u.\n",
1570 if (api_ver
!= api_max
)
1572 "Firmware has old API version. Expected v%u, "
1573 "got v%u. New firmware can be obtained "
1574 "from http://www.intellinuxwireless.org.\n",
1579 sprintf(buildstr
, " build %u%s", build
,
1580 (priv
->fw_index
== UCODE_EXPERIMENTAL_INDEX
)
1585 IWL_INFO(priv
, "loaded firmware version %u.%u.%u.%u%s\n",
1586 IWL_UCODE_MAJOR(priv
->ucode_ver
),
1587 IWL_UCODE_MINOR(priv
->ucode_ver
),
1588 IWL_UCODE_API(priv
->ucode_ver
),
1589 IWL_UCODE_SERIAL(priv
->ucode_ver
),
1592 snprintf(priv
->hw
->wiphy
->fw_version
,
1593 sizeof(priv
->hw
->wiphy
->fw_version
),
1595 IWL_UCODE_MAJOR(priv
->ucode_ver
),
1596 IWL_UCODE_MINOR(priv
->ucode_ver
),
1597 IWL_UCODE_API(priv
->ucode_ver
),
1598 IWL_UCODE_SERIAL(priv
->ucode_ver
),
1602 * For any of the failures below (before allocating pci memory)
1603 * we will try to load a version with a smaller API -- maybe the
1604 * user just got a corrupted version of the latest API.
1607 IWL_DEBUG_INFO(priv
, "f/w package hdr ucode version raw = 0x%x\n",
1609 IWL_DEBUG_INFO(priv
, "f/w package hdr runtime inst size = %Zd\n",
1611 IWL_DEBUG_INFO(priv
, "f/w package hdr runtime data size = %Zd\n",
1613 IWL_DEBUG_INFO(priv
, "f/w package hdr init inst size = %Zd\n",
1615 IWL_DEBUG_INFO(priv
, "f/w package hdr init data size = %Zd\n",
1616 pieces
.init_data_size
);
1617 IWL_DEBUG_INFO(priv
, "f/w package hdr boot inst size = %Zd\n",
1620 /* Verify that uCode images will fit in card's SRAM */
1621 if (pieces
.inst_size
> priv
->hw_params
.max_inst_size
) {
1622 IWL_ERR(priv
, "uCode instr len %Zd too large to fit in\n",
1627 if (pieces
.data_size
> priv
->hw_params
.max_data_size
) {
1628 IWL_ERR(priv
, "uCode data len %Zd too large to fit in\n",
1633 if (pieces
.init_size
> priv
->hw_params
.max_inst_size
) {
1634 IWL_ERR(priv
, "uCode init instr len %Zd too large to fit in\n",
1639 if (pieces
.init_data_size
> priv
->hw_params
.max_data_size
) {
1640 IWL_ERR(priv
, "uCode init data len %Zd too large to fit in\n",
1641 pieces
.init_data_size
);
1645 if (pieces
.boot_size
> priv
->hw_params
.max_bsm_size
) {
1646 IWL_ERR(priv
, "uCode boot instr len %Zd too large to fit in\n",
1651 /* Allocate ucode buffers for card's bus-master loading ... */
1653 /* Runtime instructions and 2 copies of data:
1654 * 1) unmodified from disk
1655 * 2) backup cache for save/restore during power-downs */
1656 priv
->ucode_code
.len
= pieces
.inst_size
;
1657 iwl_alloc_fw_desc(priv
->pci_dev
, &priv
->ucode_code
);
1659 priv
->ucode_data
.len
= pieces
.data_size
;
1660 iwl_alloc_fw_desc(priv
->pci_dev
, &priv
->ucode_data
);
1662 priv
->ucode_data_backup
.len
= pieces
.data_size
;
1663 iwl_alloc_fw_desc(priv
->pci_dev
, &priv
->ucode_data_backup
);
1665 if (!priv
->ucode_code
.v_addr
|| !priv
->ucode_data
.v_addr
||
1666 !priv
->ucode_data_backup
.v_addr
)
1669 /* Initialization instructions and data */
1670 if (pieces
.init_size
&& pieces
.init_data_size
) {
1671 priv
->ucode_init
.len
= pieces
.init_size
;
1672 iwl_alloc_fw_desc(priv
->pci_dev
, &priv
->ucode_init
);
1674 priv
->ucode_init_data
.len
= pieces
.init_data_size
;
1675 iwl_alloc_fw_desc(priv
->pci_dev
, &priv
->ucode_init_data
);
1677 if (!priv
->ucode_init
.v_addr
|| !priv
->ucode_init_data
.v_addr
)
1681 /* Bootstrap (instructions only, no data) */
1682 if (pieces
.boot_size
) {
1683 priv
->ucode_boot
.len
= pieces
.boot_size
;
1684 iwl_alloc_fw_desc(priv
->pci_dev
, &priv
->ucode_boot
);
1686 if (!priv
->ucode_boot
.v_addr
)
1690 /* Now that we can no longer fail, copy information */
1693 * The (size - 16) / 12 formula is based on the information recorded
1694 * for each event, which is of mode 1 (including timestamp) for all
1695 * new microcodes that include this information.
1697 priv
->_agn
.init_evtlog_ptr
= pieces
.init_evtlog_ptr
;
1698 if (pieces
.init_evtlog_size
)
1699 priv
->_agn
.init_evtlog_size
= (pieces
.init_evtlog_size
- 16)/12;
1701 priv
->_agn
.init_evtlog_size
=
1702 priv
->cfg
->base_params
->max_event_log_size
;
1703 priv
->_agn
.init_errlog_ptr
= pieces
.init_errlog_ptr
;
1704 priv
->_agn
.inst_evtlog_ptr
= pieces
.inst_evtlog_ptr
;
1705 if (pieces
.inst_evtlog_size
)
1706 priv
->_agn
.inst_evtlog_size
= (pieces
.inst_evtlog_size
- 16)/12;
1708 priv
->_agn
.inst_evtlog_size
=
1709 priv
->cfg
->base_params
->max_event_log_size
;
1710 priv
->_agn
.inst_errlog_ptr
= pieces
.inst_errlog_ptr
;
1712 if (ucode_capa
.pan
) {
1713 priv
->valid_contexts
|= BIT(IWL_RXON_CTX_PAN
);
1714 priv
->sta_key_max_num
= STA_KEY_MAX_NUM_PAN
;
1716 priv
->sta_key_max_num
= STA_KEY_MAX_NUM
;
1718 /* Copy images into buffers for card's bus-master reads ... */
1720 /* Runtime instructions (first block of data in file) */
1721 IWL_DEBUG_INFO(priv
, "Copying (but not loading) uCode instr len %Zd\n",
1723 memcpy(priv
->ucode_code
.v_addr
, pieces
.inst
, pieces
.inst_size
);
1725 IWL_DEBUG_INFO(priv
, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
1726 priv
->ucode_code
.v_addr
, (u32
)priv
->ucode_code
.p_addr
);
1730 * NOTE: Copy into backup buffer will be done in iwl_up()
1732 IWL_DEBUG_INFO(priv
, "Copying (but not loading) uCode data len %Zd\n",
1734 memcpy(priv
->ucode_data
.v_addr
, pieces
.data
, pieces
.data_size
);
1735 memcpy(priv
->ucode_data_backup
.v_addr
, pieces
.data
, pieces
.data_size
);
1737 /* Initialization instructions */
1738 if (pieces
.init_size
) {
1739 IWL_DEBUG_INFO(priv
, "Copying (but not loading) init instr len %Zd\n",
1741 memcpy(priv
->ucode_init
.v_addr
, pieces
.init
, pieces
.init_size
);
1744 /* Initialization data */
1745 if (pieces
.init_data_size
) {
1746 IWL_DEBUG_INFO(priv
, "Copying (but not loading) init data len %Zd\n",
1747 pieces
.init_data_size
);
1748 memcpy(priv
->ucode_init_data
.v_addr
, pieces
.init_data
,
1749 pieces
.init_data_size
);
1752 /* Bootstrap instructions */
1753 IWL_DEBUG_INFO(priv
, "Copying (but not loading) boot instr len %Zd\n",
1755 memcpy(priv
->ucode_boot
.v_addr
, pieces
.boot
, pieces
.boot_size
);
1758 * figure out the offset of chain noise reset and gain commands
1759 * base on the size of standard phy calibration commands table size
1761 if (ucode_capa
.standard_phy_calibration_size
>
1762 IWL_MAX_PHY_CALIBRATE_TBL_SIZE
)
1763 ucode_capa
.standard_phy_calibration_size
=
1764 IWL_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE
;
1766 priv
->_agn
.phy_calib_chain_noise_reset_cmd
=
1767 ucode_capa
.standard_phy_calibration_size
;
1768 priv
->_agn
.phy_calib_chain_noise_gain_cmd
=
1769 ucode_capa
.standard_phy_calibration_size
+ 1;
1771 /**************************************************
1772 * This is still part of probe() in a sense...
1774 * 9. Setup and register with mac80211 and debugfs
1775 **************************************************/
1776 err
= iwl_mac_setup_register(priv
, &ucode_capa
);
1780 err
= iwl_dbgfs_register(priv
, DRV_NAME
);
1782 IWL_ERR(priv
, "failed to create debugfs files. Ignoring error: %d\n", err
);
1784 err
= sysfs_create_group(&priv
->pci_dev
->dev
.kobj
,
1785 &iwl_attribute_group
);
1787 IWL_ERR(priv
, "failed to create sysfs device attributes\n");
1791 /* We have our copies now, allow OS release its copies */
1792 release_firmware(ucode_raw
);
1793 complete(&priv
->_agn
.firmware_loading_complete
);
1797 /* try next, if any */
1798 if (iwl_request_firmware(priv
, false))
1800 release_firmware(ucode_raw
);
1804 IWL_ERR(priv
, "failed to allocate pci memory\n");
1805 iwl_dealloc_ucode_pci(priv
);
1807 complete(&priv
->_agn
.firmware_loading_complete
);
1808 device_release_driver(&priv
->pci_dev
->dev
);
1809 release_firmware(ucode_raw
);
1812 static const char *desc_lookup_text
[] = {
1817 "NMI_INTERRUPT_WDG",
1821 "HW_ERROR_TUNE_LOCK",
1822 "HW_ERROR_TEMPERATURE",
1823 "ILLEGAL_CHAN_FREQ",
1826 "NMI_INTERRUPT_HOST",
1827 "NMI_INTERRUPT_ACTION_PT",
1828 "NMI_INTERRUPT_UNKNOWN",
1829 "UCODE_VERSION_MISMATCH",
1830 "HW_ERROR_ABS_LOCK",
1831 "HW_ERROR_CAL_LOCK_FAIL",
1832 "NMI_INTERRUPT_INST_ACTION_PT",
1833 "NMI_INTERRUPT_DATA_ACTION_PT",
1835 "NMI_INTERRUPT_TRM",
1836 "NMI_INTERRUPT_BREAK_POINT"
1843 static struct { char *name
; u8 num
; } advanced_lookup
[] = {
1844 { "NMI_INTERRUPT_WDG", 0x34 },
1845 { "SYSASSERT", 0x35 },
1846 { "UCODE_VERSION_MISMATCH", 0x37 },
1847 { "BAD_COMMAND", 0x38 },
1848 { "NMI_INTERRUPT_DATA_ACTION_PT", 0x3C },
1849 { "FATAL_ERROR", 0x3D },
1850 { "NMI_TRM_HW_ERR", 0x46 },
1851 { "NMI_INTERRUPT_TRM", 0x4C },
1852 { "NMI_INTERRUPT_BREAK_POINT", 0x54 },
1853 { "NMI_INTERRUPT_WDG_RXF_FULL", 0x5C },
1854 { "NMI_INTERRUPT_WDG_NO_RBD_RXF_FULL", 0x64 },
1855 { "NMI_INTERRUPT_HOST", 0x66 },
1856 { "NMI_INTERRUPT_ACTION_PT", 0x7C },
1857 { "NMI_INTERRUPT_UNKNOWN", 0x84 },
1858 { "NMI_INTERRUPT_INST_ACTION_PT", 0x86 },
1859 { "ADVANCED_SYSASSERT", 0 },
1862 static const char *desc_lookup(u32 num
)
1865 int max
= ARRAY_SIZE(desc_lookup_text
);
1868 return desc_lookup_text
[num
];
1870 max
= ARRAY_SIZE(advanced_lookup
) - 1;
1871 for (i
= 0; i
< max
; i
++) {
1872 if (advanced_lookup
[i
].num
== num
)
1875 return advanced_lookup
[i
].name
;
1878 #define ERROR_START_OFFSET (1 * sizeof(u32))
1879 #define ERROR_ELEM_SIZE (7 * sizeof(u32))
1881 void iwl_dump_nic_error_log(struct iwl_priv
*priv
)
1884 u32 desc
, time
, count
, base
, data1
;
1885 u32 blink1
, blink2
, ilink1
, ilink2
;
1888 if (priv
->ucode_type
== UCODE_INIT
) {
1889 base
= le32_to_cpu(priv
->card_alive_init
.error_event_table_ptr
);
1891 base
= priv
->_agn
.init_errlog_ptr
;
1893 base
= le32_to_cpu(priv
->card_alive
.error_event_table_ptr
);
1895 base
= priv
->_agn
.inst_errlog_ptr
;
1898 if (!priv
->cfg
->ops
->lib
->is_valid_rtc_data_addr(base
)) {
1900 "Not valid error log pointer 0x%08X for %s uCode\n",
1901 base
, (priv
->ucode_type
== UCODE_INIT
) ? "Init" : "RT");
1905 count
= iwl_read_targ_mem(priv
, base
);
1907 if (ERROR_START_OFFSET
<= count
* ERROR_ELEM_SIZE
) {
1908 IWL_ERR(priv
, "Start IWL Error Log Dump:\n");
1909 IWL_ERR(priv
, "Status: 0x%08lX, count: %d\n",
1910 priv
->status
, count
);
1913 desc
= iwl_read_targ_mem(priv
, base
+ 1 * sizeof(u32
));
1914 priv
->isr_stats
.err_code
= desc
;
1915 pc
= iwl_read_targ_mem(priv
, base
+ 2 * sizeof(u32
));
1916 blink1
= iwl_read_targ_mem(priv
, base
+ 3 * sizeof(u32
));
1917 blink2
= iwl_read_targ_mem(priv
, base
+ 4 * sizeof(u32
));
1918 ilink1
= iwl_read_targ_mem(priv
, base
+ 5 * sizeof(u32
));
1919 ilink2
= iwl_read_targ_mem(priv
, base
+ 6 * sizeof(u32
));
1920 data1
= iwl_read_targ_mem(priv
, base
+ 7 * sizeof(u32
));
1921 data2
= iwl_read_targ_mem(priv
, base
+ 8 * sizeof(u32
));
1922 line
= iwl_read_targ_mem(priv
, base
+ 9 * sizeof(u32
));
1923 time
= iwl_read_targ_mem(priv
, base
+ 11 * sizeof(u32
));
1924 hcmd
= iwl_read_targ_mem(priv
, base
+ 22 * sizeof(u32
));
1926 trace_iwlwifi_dev_ucode_error(priv
, desc
, time
, data1
, data2
, line
,
1927 blink1
, blink2
, ilink1
, ilink2
);
1929 IWL_ERR(priv
, "Desc Time "
1930 "data1 data2 line\n");
1931 IWL_ERR(priv
, "%-28s (0x%04X) %010u 0x%08X 0x%08X %u\n",
1932 desc_lookup(desc
), desc
, time
, data1
, data2
, line
);
1933 IWL_ERR(priv
, "pc blink1 blink2 ilink1 ilink2 hcmd\n");
1934 IWL_ERR(priv
, "0x%05X 0x%05X 0x%05X 0x%05X 0x%05X 0x%05X\n",
1935 pc
, blink1
, blink2
, ilink1
, ilink2
, hcmd
);
1938 #define EVENT_START_OFFSET (4 * sizeof(u32))
1941 * iwl_print_event_log - Dump error event log to syslog
1944 static int iwl_print_event_log(struct iwl_priv
*priv
, u32 start_idx
,
1945 u32 num_events
, u32 mode
,
1946 int pos
, char **buf
, size_t bufsz
)
1949 u32 base
; /* SRAM byte address of event log header */
1950 u32 event_size
; /* 2 u32s, or 3 u32s if timestamp recorded */
1951 u32 ptr
; /* SRAM byte address of log data */
1952 u32 ev
, time
, data
; /* event log data */
1953 unsigned long reg_flags
;
1955 if (num_events
== 0)
1958 if (priv
->ucode_type
== UCODE_INIT
) {
1959 base
= le32_to_cpu(priv
->card_alive_init
.log_event_table_ptr
);
1961 base
= priv
->_agn
.init_evtlog_ptr
;
1963 base
= le32_to_cpu(priv
->card_alive
.log_event_table_ptr
);
1965 base
= priv
->_agn
.inst_evtlog_ptr
;
1969 event_size
= 2 * sizeof(u32
);
1971 event_size
= 3 * sizeof(u32
);
1973 ptr
= base
+ EVENT_START_OFFSET
+ (start_idx
* event_size
);
1975 /* Make sure device is powered up for SRAM reads */
1976 spin_lock_irqsave(&priv
->reg_lock
, reg_flags
);
1977 iwl_grab_nic_access(priv
);
1979 /* Set starting address; reads will auto-increment */
1980 _iwl_write_direct32(priv
, HBUS_TARG_MEM_RADDR
, ptr
);
1983 /* "time" is actually "data" for mode 0 (no timestamp).
1984 * place event id # at far right for easier visual parsing. */
1985 for (i
= 0; i
< num_events
; i
++) {
1986 ev
= _iwl_read_direct32(priv
, HBUS_TARG_MEM_RDAT
);
1987 time
= _iwl_read_direct32(priv
, HBUS_TARG_MEM_RDAT
);
1991 pos
+= scnprintf(*buf
+ pos
, bufsz
- pos
,
1992 "EVT_LOG:0x%08x:%04u\n",
1995 trace_iwlwifi_dev_ucode_event(priv
, 0,
1997 IWL_ERR(priv
, "EVT_LOG:0x%08x:%04u\n",
2001 data
= _iwl_read_direct32(priv
, HBUS_TARG_MEM_RDAT
);
2003 pos
+= scnprintf(*buf
+ pos
, bufsz
- pos
,
2004 "EVT_LOGT:%010u:0x%08x:%04u\n",
2007 IWL_ERR(priv
, "EVT_LOGT:%010u:0x%08x:%04u\n",
2009 trace_iwlwifi_dev_ucode_event(priv
, time
,
2015 /* Allow device to power down */
2016 iwl_release_nic_access(priv
);
2017 spin_unlock_irqrestore(&priv
->reg_lock
, reg_flags
);
2022 * iwl_print_last_event_logs - Dump the newest # of event log to syslog
2024 static int iwl_print_last_event_logs(struct iwl_priv
*priv
, u32 capacity
,
2025 u32 num_wraps
, u32 next_entry
,
2027 int pos
, char **buf
, size_t bufsz
)
2030 * display the newest DEFAULT_LOG_ENTRIES entries
2031 * i.e the entries just before the next ont that uCode would fill.
2034 if (next_entry
< size
) {
2035 pos
= iwl_print_event_log(priv
,
2036 capacity
- (size
- next_entry
),
2037 size
- next_entry
, mode
,
2039 pos
= iwl_print_event_log(priv
, 0,
2043 pos
= iwl_print_event_log(priv
, next_entry
- size
,
2044 size
, mode
, pos
, buf
, bufsz
);
2046 if (next_entry
< size
) {
2047 pos
= iwl_print_event_log(priv
, 0, next_entry
,
2048 mode
, pos
, buf
, bufsz
);
2050 pos
= iwl_print_event_log(priv
, next_entry
- size
,
2051 size
, mode
, pos
, buf
, bufsz
);
2057 #define DEFAULT_DUMP_EVENT_LOG_ENTRIES (20)
2059 int iwl_dump_nic_event_log(struct iwl_priv
*priv
, bool full_log
,
2060 char **buf
, bool display
)
2062 u32 base
; /* SRAM byte address of event log header */
2063 u32 capacity
; /* event log capacity in # entries */
2064 u32 mode
; /* 0 - no timestamp, 1 - timestamp recorded */
2065 u32 num_wraps
; /* # times uCode wrapped to top of log */
2066 u32 next_entry
; /* index of next entry to be written by uCode */
2067 u32 size
; /* # entries that we'll print */
2072 if (priv
->ucode_type
== UCODE_INIT
) {
2073 base
= le32_to_cpu(priv
->card_alive_init
.log_event_table_ptr
);
2074 logsize
= priv
->_agn
.init_evtlog_size
;
2076 base
= priv
->_agn
.init_evtlog_ptr
;
2078 base
= le32_to_cpu(priv
->card_alive
.log_event_table_ptr
);
2079 logsize
= priv
->_agn
.inst_evtlog_size
;
2081 base
= priv
->_agn
.inst_evtlog_ptr
;
2084 if (!priv
->cfg
->ops
->lib
->is_valid_rtc_data_addr(base
)) {
2086 "Invalid event log pointer 0x%08X for %s uCode\n",
2087 base
, (priv
->ucode_type
== UCODE_INIT
) ? "Init" : "RT");
2091 /* event log header */
2092 capacity
= iwl_read_targ_mem(priv
, base
);
2093 mode
= iwl_read_targ_mem(priv
, base
+ (1 * sizeof(u32
)));
2094 num_wraps
= iwl_read_targ_mem(priv
, base
+ (2 * sizeof(u32
)));
2095 next_entry
= iwl_read_targ_mem(priv
, base
+ (3 * sizeof(u32
)));
2097 if (capacity
> logsize
) {
2098 IWL_ERR(priv
, "Log capacity %d is bogus, limit to %d entries\n",
2103 if (next_entry
> logsize
) {
2104 IWL_ERR(priv
, "Log write index %d is bogus, limit to %d\n",
2105 next_entry
, logsize
);
2106 next_entry
= logsize
;
2109 size
= num_wraps
? capacity
: next_entry
;
2111 /* bail out if nothing in log */
2113 IWL_ERR(priv
, "Start IWL Event Log Dump: nothing in log\n");
2117 /* enable/disable bt channel inhibition */
2118 priv
->bt_ch_announce
= iwlagn_bt_ch_announce
;
2120 #ifdef CONFIG_IWLWIFI_DEBUG
2121 if (!(iwl_get_debug_level(priv
) & IWL_DL_FW_ERRORS
) && !full_log
)
2122 size
= (size
> DEFAULT_DUMP_EVENT_LOG_ENTRIES
)
2123 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES
: size
;
2125 size
= (size
> DEFAULT_DUMP_EVENT_LOG_ENTRIES
)
2126 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES
: size
;
2128 IWL_ERR(priv
, "Start IWL Event Log Dump: display last %u entries\n",
2131 #ifdef CONFIG_IWLWIFI_DEBUG
2134 bufsz
= capacity
* 48;
2137 *buf
= kmalloc(bufsz
, GFP_KERNEL
);
2141 if ((iwl_get_debug_level(priv
) & IWL_DL_FW_ERRORS
) || full_log
) {
2143 * if uCode has wrapped back to top of log,
2144 * start at the oldest entry,
2145 * i.e the next one that uCode would fill.
2148 pos
= iwl_print_event_log(priv
, next_entry
,
2149 capacity
- next_entry
, mode
,
2151 /* (then/else) start at top of log */
2152 pos
= iwl_print_event_log(priv
, 0,
2153 next_entry
, mode
, pos
, buf
, bufsz
);
2155 pos
= iwl_print_last_event_logs(priv
, capacity
, num_wraps
,
2156 next_entry
, size
, mode
,
2159 pos
= iwl_print_last_event_logs(priv
, capacity
, num_wraps
,
2160 next_entry
, size
, mode
,
2166 static void iwl_rf_kill_ct_config(struct iwl_priv
*priv
)
2168 struct iwl_ct_kill_config cmd
;
2169 struct iwl_ct_kill_throttling_config adv_cmd
;
2170 unsigned long flags
;
2173 spin_lock_irqsave(&priv
->lock
, flags
);
2174 iwl_write32(priv
, CSR_UCODE_DRV_GP1_CLR
,
2175 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT
);
2176 spin_unlock_irqrestore(&priv
->lock
, flags
);
2177 priv
->thermal_throttle
.ct_kill_toggle
= false;
2179 if (priv
->cfg
->base_params
->support_ct_kill_exit
) {
2180 adv_cmd
.critical_temperature_enter
=
2181 cpu_to_le32(priv
->hw_params
.ct_kill_threshold
);
2182 adv_cmd
.critical_temperature_exit
=
2183 cpu_to_le32(priv
->hw_params
.ct_kill_exit_threshold
);
2185 ret
= iwl_send_cmd_pdu(priv
, REPLY_CT_KILL_CONFIG_CMD
,
2186 sizeof(adv_cmd
), &adv_cmd
);
2188 IWL_ERR(priv
, "REPLY_CT_KILL_CONFIG_CMD failed\n");
2190 IWL_DEBUG_INFO(priv
, "REPLY_CT_KILL_CONFIG_CMD "
2192 "critical temperature enter is %d,"
2194 priv
->hw_params
.ct_kill_threshold
,
2195 priv
->hw_params
.ct_kill_exit_threshold
);
2197 cmd
.critical_temperature_R
=
2198 cpu_to_le32(priv
->hw_params
.ct_kill_threshold
);
2200 ret
= iwl_send_cmd_pdu(priv
, REPLY_CT_KILL_CONFIG_CMD
,
2203 IWL_ERR(priv
, "REPLY_CT_KILL_CONFIG_CMD failed\n");
2205 IWL_DEBUG_INFO(priv
, "REPLY_CT_KILL_CONFIG_CMD "
2207 "critical temperature is %d\n",
2208 priv
->hw_params
.ct_kill_threshold
);
2212 static int iwlagn_send_calib_cfg_rt(struct iwl_priv
*priv
, u32 cfg
)
2214 struct iwl_calib_cfg_cmd calib_cfg_cmd
;
2215 struct iwl_host_cmd cmd
= {
2216 .id
= CALIBRATION_CFG_CMD
,
2217 .len
= sizeof(struct iwl_calib_cfg_cmd
),
2218 .data
= &calib_cfg_cmd
,
2221 memset(&calib_cfg_cmd
, 0, sizeof(calib_cfg_cmd
));
2222 calib_cfg_cmd
.ucd_calib_cfg
.once
.is_enable
= IWL_CALIB_INIT_CFG_ALL
;
2223 calib_cfg_cmd
.ucd_calib_cfg
.once
.start
= cpu_to_le32(cfg
);
2225 return iwl_send_cmd(priv
, &cmd
);
2230 * iwl_alive_start - called after REPLY_ALIVE notification received
2231 * from protocol/runtime uCode (initialization uCode's
2232 * Alive gets handled by iwl_init_alive_start()).
2234 static void iwl_alive_start(struct iwl_priv
*priv
)
2237 struct iwl_rxon_context
*ctx
= &priv
->contexts
[IWL_RXON_CTX_BSS
];
2239 IWL_DEBUG_INFO(priv
, "Runtime Alive received.\n");
2241 /* Initialize uCode has loaded Runtime uCode ... verify inst image.
2242 * This is a paranoid check, because we would not have gotten the
2243 * "runtime" alive if code weren't properly loaded. */
2244 if (iwl_verify_ucode(priv
)) {
2245 /* Runtime instruction load was bad;
2246 * take it all the way back down so we can try again */
2247 IWL_DEBUG_INFO(priv
, "Bad runtime uCode load.\n");
2251 ret
= priv
->cfg
->ops
->lib
->alive_notify(priv
);
2254 "Could not complete ALIVE transition [ntf]: %d\n", ret
);
2259 /* After the ALIVE response, we can send host commands to the uCode */
2260 set_bit(STATUS_ALIVE
, &priv
->status
);
2262 /* Enable watchdog to monitor the driver tx queues */
2263 iwl_setup_watchdog(priv
);
2265 if (iwl_is_rfkill(priv
))
2268 /* download priority table before any calibration request */
2269 if (priv
->cfg
->bt_params
&&
2270 priv
->cfg
->bt_params
->advanced_bt_coexist
) {
2271 /* Configure Bluetooth device coexistence support */
2272 priv
->bt_valid
= IWLAGN_BT_ALL_VALID_MSK
;
2273 priv
->kill_ack_mask
= IWLAGN_BT_KILL_ACK_MASK_DEFAULT
;
2274 priv
->kill_cts_mask
= IWLAGN_BT_KILL_CTS_MASK_DEFAULT
;
2275 priv
->cfg
->ops
->hcmd
->send_bt_config(priv
);
2276 priv
->bt_valid
= IWLAGN_BT_VALID_ENABLE_FLAGS
;
2277 iwlagn_send_prio_tbl(priv
);
2279 /* FIXME: w/a to force change uCode BT state machine */
2280 iwlagn_send_bt_env(priv
, IWL_BT_COEX_ENV_OPEN
,
2281 BT_COEX_PRIO_TBL_EVT_INIT_CALIB2
);
2282 iwlagn_send_bt_env(priv
, IWL_BT_COEX_ENV_CLOSE
,
2283 BT_COEX_PRIO_TBL_EVT_INIT_CALIB2
);
2285 if (priv
->hw_params
.calib_rt_cfg
)
2286 iwlagn_send_calib_cfg_rt(priv
, priv
->hw_params
.calib_rt_cfg
);
2288 ieee80211_wake_queues(priv
->hw
);
2290 priv
->active_rate
= IWL_RATES_MASK
;
2292 /* Configure Tx antenna selection based on H/W config */
2293 if (priv
->cfg
->ops
->hcmd
->set_tx_ant
)
2294 priv
->cfg
->ops
->hcmd
->set_tx_ant(priv
, priv
->cfg
->valid_tx_ant
);
2296 if (iwl_is_associated_ctx(ctx
)) {
2297 struct iwl_rxon_cmd
*active_rxon
=
2298 (struct iwl_rxon_cmd
*)&ctx
->active
;
2299 /* apply any changes in staging */
2300 ctx
->staging
.filter_flags
|= RXON_FILTER_ASSOC_MSK
;
2301 active_rxon
->filter_flags
&= ~RXON_FILTER_ASSOC_MSK
;
2303 struct iwl_rxon_context
*tmp
;
2304 /* Initialize our rx_config data */
2305 for_each_context(priv
, tmp
)
2306 iwl_connection_init_rx_config(priv
, tmp
);
2308 if (priv
->cfg
->ops
->hcmd
->set_rxon_chain
)
2309 priv
->cfg
->ops
->hcmd
->set_rxon_chain(priv
, ctx
);
2312 if (!priv
->cfg
->bt_params
|| (priv
->cfg
->bt_params
&&
2313 !priv
->cfg
->bt_params
->advanced_bt_coexist
)) {
2315 * default is 2-wire BT coexexistence support
2317 priv
->cfg
->ops
->hcmd
->send_bt_config(priv
);
2320 iwl_reset_run_time_calib(priv
);
2322 set_bit(STATUS_READY
, &priv
->status
);
2324 /* Configure the adapter for unassociated operation */
2325 iwlcore_commit_rxon(priv
, ctx
);
2327 /* At this point, the NIC is initialized and operational */
2328 iwl_rf_kill_ct_config(priv
);
2330 IWL_DEBUG_INFO(priv
, "ALIVE processing complete.\n");
2331 wake_up_interruptible(&priv
->wait_command_queue
);
2333 iwl_power_update_mode(priv
, true);
2334 IWL_DEBUG_INFO(priv
, "Updated power mode\n");
2340 queue_work(priv
->workqueue
, &priv
->restart
);
2343 static void iwl_cancel_deferred_work(struct iwl_priv
*priv
);
2345 static void __iwl_down(struct iwl_priv
*priv
)
2347 unsigned long flags
;
2350 IWL_DEBUG_INFO(priv
, DRV_NAME
" is going down\n");
2352 iwl_scan_cancel_timeout(priv
, 200);
2354 exit_pending
= test_and_set_bit(STATUS_EXIT_PENDING
, &priv
->status
);
2356 /* Stop TX queues watchdog. We need to have STATUS_EXIT_PENDING bit set
2357 * to prevent rearm timer */
2358 del_timer_sync(&priv
->watchdog
);
2360 iwl_clear_ucode_stations(priv
, NULL
);
2361 iwl_dealloc_bcast_stations(priv
);
2362 iwl_clear_driver_stations(priv
);
2364 /* reset BT coex data */
2365 priv
->bt_status
= 0;
2366 if (priv
->cfg
->bt_params
)
2367 priv
->bt_traffic_load
=
2368 priv
->cfg
->bt_params
->bt_init_traffic_load
;
2370 priv
->bt_traffic_load
= 0;
2371 priv
->bt_full_concurrent
= false;
2372 priv
->bt_ci_compliance
= 0;
2374 /* Wipe out the EXIT_PENDING status bit if we are not actually
2375 * exiting the module */
2377 clear_bit(STATUS_EXIT_PENDING
, &priv
->status
);
2379 /* stop and reset the on-board processor */
2380 iwl_write32(priv
, CSR_RESET
, CSR_RESET_REG_FLAG_NEVO_RESET
);
2382 /* tell the device to stop sending interrupts */
2383 spin_lock_irqsave(&priv
->lock
, flags
);
2384 iwl_disable_interrupts(priv
);
2385 spin_unlock_irqrestore(&priv
->lock
, flags
);
2386 iwl_synchronize_irq(priv
);
2388 if (priv
->mac80211_registered
)
2389 ieee80211_stop_queues(priv
->hw
);
2391 /* If we have not previously called iwl_init() then
2392 * clear all bits but the RF Kill bit and return */
2393 if (!iwl_is_init(priv
)) {
2394 priv
->status
= test_bit(STATUS_RF_KILL_HW
, &priv
->status
) <<
2396 test_bit(STATUS_GEO_CONFIGURED
, &priv
->status
) <<
2397 STATUS_GEO_CONFIGURED
|
2398 test_bit(STATUS_EXIT_PENDING
, &priv
->status
) <<
2399 STATUS_EXIT_PENDING
;
2403 /* ...otherwise clear out all the status bits but the RF Kill
2404 * bit and continue taking the NIC down. */
2405 priv
->status
&= test_bit(STATUS_RF_KILL_HW
, &priv
->status
) <<
2407 test_bit(STATUS_GEO_CONFIGURED
, &priv
->status
) <<
2408 STATUS_GEO_CONFIGURED
|
2409 test_bit(STATUS_FW_ERROR
, &priv
->status
) <<
2411 test_bit(STATUS_EXIT_PENDING
, &priv
->status
) <<
2412 STATUS_EXIT_PENDING
;
2414 /* device going down, Stop using ICT table */
2415 if (priv
->cfg
->ops
->lib
->isr_ops
.disable
)
2416 priv
->cfg
->ops
->lib
->isr_ops
.disable(priv
);
2418 iwlagn_txq_ctx_stop(priv
);
2419 iwlagn_rxq_stop(priv
);
2421 /* Power-down device's busmaster DMA clocks */
2422 iwl_write_prph(priv
, APMG_CLK_DIS_REG
, APMG_CLK_VAL_DMA_CLK_RQT
);
2425 /* Make sure (redundant) we've released our request to stay awake */
2426 iwl_clear_bit(priv
, CSR_GP_CNTRL
, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
);
2428 /* Stop the device, and put it in low power state */
2432 memset(&priv
->card_alive
, 0, sizeof(struct iwl_alive_resp
));
2434 dev_kfree_skb(priv
->beacon_skb
);
2435 priv
->beacon_skb
= NULL
;
2437 /* clear out any free frames */
2438 iwl_clear_free_frames(priv
);
2441 static void iwl_down(struct iwl_priv
*priv
)
2443 mutex_lock(&priv
->mutex
);
2445 mutex_unlock(&priv
->mutex
);
2447 iwl_cancel_deferred_work(priv
);
2450 #define HW_READY_TIMEOUT (50)
2452 static int iwl_set_hw_ready(struct iwl_priv
*priv
)
2456 iwl_set_bit(priv
, CSR_HW_IF_CONFIG_REG
,
2457 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY
);
2459 /* See if we got it */
2460 ret
= iwl_poll_bit(priv
, CSR_HW_IF_CONFIG_REG
,
2461 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY
,
2462 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY
,
2464 if (ret
!= -ETIMEDOUT
)
2465 priv
->hw_ready
= true;
2467 priv
->hw_ready
= false;
2469 IWL_DEBUG_INFO(priv
, "hardware %s\n",
2470 (priv
->hw_ready
== 1) ? "ready" : "not ready");
2474 static int iwl_prepare_card_hw(struct iwl_priv
*priv
)
2478 IWL_DEBUG_INFO(priv
, "iwl_prepare_card_hw enter\n");
2480 ret
= iwl_set_hw_ready(priv
);
2484 /* If HW is not ready, prepare the conditions to check again */
2485 iwl_set_bit(priv
, CSR_HW_IF_CONFIG_REG
,
2486 CSR_HW_IF_CONFIG_REG_PREPARE
);
2488 ret
= iwl_poll_bit(priv
, CSR_HW_IF_CONFIG_REG
,
2489 ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE
,
2490 CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE
, 150000);
2492 /* HW should be ready by now, check again. */
2493 if (ret
!= -ETIMEDOUT
)
2494 iwl_set_hw_ready(priv
);
2499 #define MAX_HW_RESTARTS 5
2501 static int __iwl_up(struct iwl_priv
*priv
)
2503 struct iwl_rxon_context
*ctx
;
2507 if (test_bit(STATUS_EXIT_PENDING
, &priv
->status
)) {
2508 IWL_WARN(priv
, "Exit pending; will not bring the NIC up\n");
2512 if (!priv
->ucode_data_backup
.v_addr
|| !priv
->ucode_data
.v_addr
) {
2513 IWL_ERR(priv
, "ucode not available for device bringup\n");
2517 for_each_context(priv
, ctx
) {
2518 ret
= iwlagn_alloc_bcast_station(priv
, ctx
);
2520 iwl_dealloc_bcast_stations(priv
);
2525 iwl_prepare_card_hw(priv
);
2527 if (!priv
->hw_ready
) {
2528 IWL_WARN(priv
, "Exit HW not ready\n");
2532 /* If platform's RF_KILL switch is NOT set to KILL */
2533 if (iwl_read32(priv
, CSR_GP_CNTRL
) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW
)
2534 clear_bit(STATUS_RF_KILL_HW
, &priv
->status
);
2536 set_bit(STATUS_RF_KILL_HW
, &priv
->status
);
2538 if (iwl_is_rfkill(priv
)) {
2539 wiphy_rfkill_set_hw_state(priv
->hw
->wiphy
, true);
2541 iwl_enable_interrupts(priv
);
2542 IWL_WARN(priv
, "Radio disabled by HW RF Kill switch\n");
2546 iwl_write32(priv
, CSR_INT
, 0xFFFFFFFF);
2548 /* must be initialised before iwl_hw_nic_init */
2549 if (priv
->valid_contexts
!= BIT(IWL_RXON_CTX_BSS
))
2550 priv
->cmd_queue
= IWL_IPAN_CMD_QUEUE_NUM
;
2552 priv
->cmd_queue
= IWL_DEFAULT_CMD_QUEUE_NUM
;
2554 ret
= iwlagn_hw_nic_init(priv
);
2556 IWL_ERR(priv
, "Unable to init nic\n");
2560 /* make sure rfkill handshake bits are cleared */
2561 iwl_write32(priv
, CSR_UCODE_DRV_GP1_CLR
, CSR_UCODE_SW_BIT_RFKILL
);
2562 iwl_write32(priv
, CSR_UCODE_DRV_GP1_CLR
,
2563 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED
);
2565 /* clear (again), then enable host interrupts */
2566 iwl_write32(priv
, CSR_INT
, 0xFFFFFFFF);
2567 iwl_enable_interrupts(priv
);
2569 /* really make sure rfkill handshake bits are cleared */
2570 iwl_write32(priv
, CSR_UCODE_DRV_GP1_CLR
, CSR_UCODE_SW_BIT_RFKILL
);
2571 iwl_write32(priv
, CSR_UCODE_DRV_GP1_CLR
, CSR_UCODE_SW_BIT_RFKILL
);
2573 /* Copy original ucode data image from disk into backup cache.
2574 * This will be used to initialize the on-board processor's
2575 * data SRAM for a clean start when the runtime program first loads. */
2576 memcpy(priv
->ucode_data_backup
.v_addr
, priv
->ucode_data
.v_addr
,
2577 priv
->ucode_data
.len
);
2579 for (i
= 0; i
< MAX_HW_RESTARTS
; i
++) {
2581 /* load bootstrap state machine,
2582 * load bootstrap program into processor's memory,
2583 * prepare to load the "initialize" uCode */
2584 ret
= priv
->cfg
->ops
->lib
->load_ucode(priv
);
2587 IWL_ERR(priv
, "Unable to set up bootstrap uCode: %d\n",
2592 /* start card; "initialize" will load runtime ucode */
2593 iwl_nic_start(priv
);
2595 IWL_DEBUG_INFO(priv
, DRV_NAME
" is coming up\n");
2600 set_bit(STATUS_EXIT_PENDING
, &priv
->status
);
2602 clear_bit(STATUS_EXIT_PENDING
, &priv
->status
);
2604 /* tried to restart and config the device for as long as our
2605 * patience could withstand */
2606 IWL_ERR(priv
, "Unable to initialize device after %d attempts.\n", i
);
2611 /*****************************************************************************
2613 * Workqueue callbacks
2615 *****************************************************************************/
2617 static void iwl_bg_init_alive_start(struct work_struct
*data
)
2619 struct iwl_priv
*priv
=
2620 container_of(data
, struct iwl_priv
, init_alive_start
.work
);
2622 mutex_lock(&priv
->mutex
);
2624 if (test_bit(STATUS_EXIT_PENDING
, &priv
->status
)) {
2625 mutex_unlock(&priv
->mutex
);
2629 priv
->cfg
->ops
->lib
->init_alive_start(priv
);
2630 mutex_unlock(&priv
->mutex
);
2633 static void iwl_bg_alive_start(struct work_struct
*data
)
2635 struct iwl_priv
*priv
=
2636 container_of(data
, struct iwl_priv
, alive_start
.work
);
2638 mutex_lock(&priv
->mutex
);
2639 if (test_bit(STATUS_EXIT_PENDING
, &priv
->status
))
2642 /* enable dram interrupt */
2643 if (priv
->cfg
->ops
->lib
->isr_ops
.reset
)
2644 priv
->cfg
->ops
->lib
->isr_ops
.reset(priv
);
2646 iwl_alive_start(priv
);
2648 mutex_unlock(&priv
->mutex
);
2651 static void iwl_bg_run_time_calib_work(struct work_struct
*work
)
2653 struct iwl_priv
*priv
= container_of(work
, struct iwl_priv
,
2654 run_time_calib_work
);
2656 mutex_lock(&priv
->mutex
);
2658 if (test_bit(STATUS_EXIT_PENDING
, &priv
->status
) ||
2659 test_bit(STATUS_SCANNING
, &priv
->status
)) {
2660 mutex_unlock(&priv
->mutex
);
2664 if (priv
->start_calib
) {
2665 if (iwl_bt_statistics(priv
)) {
2666 iwl_chain_noise_calibration(priv
,
2667 (void *)&priv
->_agn
.statistics_bt
);
2668 iwl_sensitivity_calibration(priv
,
2669 (void *)&priv
->_agn
.statistics_bt
);
2671 iwl_chain_noise_calibration(priv
,
2672 (void *)&priv
->_agn
.statistics
);
2673 iwl_sensitivity_calibration(priv
,
2674 (void *)&priv
->_agn
.statistics
);
2678 mutex_unlock(&priv
->mutex
);
2681 static void iwl_bg_restart(struct work_struct
*data
)
2683 struct iwl_priv
*priv
= container_of(data
, struct iwl_priv
, restart
);
2685 if (test_bit(STATUS_EXIT_PENDING
, &priv
->status
))
2688 if (test_and_clear_bit(STATUS_FW_ERROR
, &priv
->status
)) {
2689 struct iwl_rxon_context
*ctx
;
2690 bool bt_full_concurrent
;
2691 u8 bt_ci_compliance
;
2695 mutex_lock(&priv
->mutex
);
2696 for_each_context(priv
, ctx
)
2701 * __iwl_down() will clear the BT status variables,
2702 * which is correct, but when we restart we really
2703 * want to keep them so restore them afterwards.
2705 * The restart process will later pick them up and
2706 * re-configure the hw when we reconfigure the BT
2709 bt_full_concurrent
= priv
->bt_full_concurrent
;
2710 bt_ci_compliance
= priv
->bt_ci_compliance
;
2711 bt_load
= priv
->bt_traffic_load
;
2712 bt_status
= priv
->bt_status
;
2716 priv
->bt_full_concurrent
= bt_full_concurrent
;
2717 priv
->bt_ci_compliance
= bt_ci_compliance
;
2718 priv
->bt_traffic_load
= bt_load
;
2719 priv
->bt_status
= bt_status
;
2721 mutex_unlock(&priv
->mutex
);
2722 iwl_cancel_deferred_work(priv
);
2723 ieee80211_restart_hw(priv
->hw
);
2727 if (test_bit(STATUS_EXIT_PENDING
, &priv
->status
))
2730 mutex_lock(&priv
->mutex
);
2732 mutex_unlock(&priv
->mutex
);
2736 static void iwl_bg_rx_replenish(struct work_struct
*data
)
2738 struct iwl_priv
*priv
=
2739 container_of(data
, struct iwl_priv
, rx_replenish
);
2741 if (test_bit(STATUS_EXIT_PENDING
, &priv
->status
))
2744 mutex_lock(&priv
->mutex
);
2745 iwlagn_rx_replenish(priv
);
2746 mutex_unlock(&priv
->mutex
);
2749 static int iwl_mac_offchannel_tx(struct ieee80211_hw
*hw
, struct sk_buff
*skb
,
2750 struct ieee80211_channel
*chan
,
2751 enum nl80211_channel_type channel_type
,
2754 struct iwl_priv
*priv
= hw
->priv
;
2757 /* Not supported if we don't have PAN */
2758 if (!(priv
->valid_contexts
& BIT(IWL_RXON_CTX_PAN
))) {
2763 /* Not supported on pre-P2P firmware */
2764 if (!(priv
->contexts
[IWL_RXON_CTX_PAN
].interface_modes
&
2765 BIT(NL80211_IFTYPE_P2P_CLIENT
))) {
2770 mutex_lock(&priv
->mutex
);
2772 if (!priv
->contexts
[IWL_RXON_CTX_PAN
].is_active
) {
2774 * If the PAN context is free, use the normal
2775 * way of doing remain-on-channel offload + TX.
2781 /* TODO: queue up if scanning? */
2782 if (test_bit(STATUS_SCANNING
, &priv
->status
) ||
2783 priv
->_agn
.offchan_tx_skb
) {
2789 * max_scan_ie_len doesn't include the blank SSID or the header,
2790 * so need to add that again here.
2792 if (skb
->len
> hw
->wiphy
->max_scan_ie_len
+ 24 + 2) {
2797 priv
->_agn
.offchan_tx_skb
= skb
;
2798 priv
->_agn
.offchan_tx_timeout
= wait
;
2799 priv
->_agn
.offchan_tx_chan
= chan
;
2801 ret
= iwl_scan_initiate(priv
, priv
->contexts
[IWL_RXON_CTX_PAN
].vif
,
2802 IWL_SCAN_OFFCH_TX
, chan
->band
);
2804 priv
->_agn
.offchan_tx_skb
= NULL
;
2806 mutex_unlock(&priv
->mutex
);
2814 static int iwl_mac_offchannel_tx_cancel_wait(struct ieee80211_hw
*hw
)
2816 struct iwl_priv
*priv
= hw
->priv
;
2819 mutex_lock(&priv
->mutex
);
2821 if (!priv
->_agn
.offchan_tx_skb
) {
2826 priv
->_agn
.offchan_tx_skb
= NULL
;
2828 ret
= iwl_scan_cancel_timeout(priv
, 200);
2832 mutex_unlock(&priv
->mutex
);
2837 /*****************************************************************************
2839 * mac80211 entry point functions
2841 *****************************************************************************/
2843 #define UCODE_READY_TIMEOUT (4 * HZ)
2846 * Not a mac80211 entry point function, but it fits in with all the
2847 * other mac80211 functions grouped here.
2849 static int iwl_mac_setup_register(struct iwl_priv
*priv
,
2850 struct iwlagn_ucode_capabilities
*capa
)
2853 struct ieee80211_hw
*hw
= priv
->hw
;
2854 struct iwl_rxon_context
*ctx
;
2856 hw
->rate_control_algorithm
= "iwl-agn-rs";
2858 /* Tell mac80211 our characteristics */
2859 hw
->flags
= IEEE80211_HW_SIGNAL_DBM
|
2860 IEEE80211_HW_AMPDU_AGGREGATION
|
2861 IEEE80211_HW_NEED_DTIM_PERIOD
|
2862 IEEE80211_HW_SPECTRUM_MGMT
|
2863 IEEE80211_HW_REPORTS_TX_ACK_STATUS
;
2865 hw
->max_tx_aggregation_subframes
= LINK_QUAL_AGG_FRAME_LIMIT_DEF
;
2867 if (!priv
->cfg
->base_params
->broken_powersave
)
2868 hw
->flags
|= IEEE80211_HW_SUPPORTS_PS
|
2869 IEEE80211_HW_SUPPORTS_DYNAMIC_PS
;
2871 if (priv
->cfg
->sku
& IWL_SKU_N
)
2872 hw
->flags
|= IEEE80211_HW_SUPPORTS_DYNAMIC_SMPS
|
2873 IEEE80211_HW_SUPPORTS_STATIC_SMPS
;
2875 hw
->sta_data_size
= sizeof(struct iwl_station_priv
);
2876 hw
->vif_data_size
= sizeof(struct iwl_vif_priv
);
2878 for_each_context(priv
, ctx
) {
2879 hw
->wiphy
->interface_modes
|= ctx
->interface_modes
;
2880 hw
->wiphy
->interface_modes
|= ctx
->exclusive_interface_modes
;
2883 hw
->wiphy
->max_remain_on_channel_duration
= 1000;
2885 hw
->wiphy
->flags
|= WIPHY_FLAG_CUSTOM_REGULATORY
|
2886 WIPHY_FLAG_DISABLE_BEACON_HINTS
|
2887 WIPHY_FLAG_IBSS_RSN
;
2890 * For now, disable PS by default because it affects
2891 * RX performance significantly.
2893 hw
->wiphy
->flags
&= ~WIPHY_FLAG_PS_ON_BY_DEFAULT
;
2895 hw
->wiphy
->max_scan_ssids
= PROBE_OPTION_MAX
;
2896 /* we create the 802.11 header and a zero-length SSID element */
2897 hw
->wiphy
->max_scan_ie_len
= capa
->max_probe_length
- 24 - 2;
2899 /* Default value; 4 EDCA QOS priorities */
2902 hw
->max_listen_interval
= IWL_CONN_MAX_LISTEN_INTERVAL
;
2904 if (priv
->bands
[IEEE80211_BAND_2GHZ
].n_channels
)
2905 priv
->hw
->wiphy
->bands
[IEEE80211_BAND_2GHZ
] =
2906 &priv
->bands
[IEEE80211_BAND_2GHZ
];
2907 if (priv
->bands
[IEEE80211_BAND_5GHZ
].n_channels
)
2908 priv
->hw
->wiphy
->bands
[IEEE80211_BAND_5GHZ
] =
2909 &priv
->bands
[IEEE80211_BAND_5GHZ
];
2911 iwl_leds_init(priv
);
2913 ret
= ieee80211_register_hw(priv
->hw
);
2915 IWL_ERR(priv
, "Failed to register hw (error %d)\n", ret
);
2918 priv
->mac80211_registered
= 1;
2924 int iwlagn_mac_start(struct ieee80211_hw
*hw
)
2926 struct iwl_priv
*priv
= hw
->priv
;
2929 IWL_DEBUG_MAC80211(priv
, "enter\n");
2931 /* we should be verifying the device is ready to be opened */
2932 mutex_lock(&priv
->mutex
);
2933 ret
= __iwl_up(priv
);
2934 mutex_unlock(&priv
->mutex
);
2939 if (iwl_is_rfkill(priv
))
2942 IWL_DEBUG_INFO(priv
, "Start UP work done.\n");
2944 /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
2945 * mac80211 will not be run successfully. */
2946 ret
= wait_event_interruptible_timeout(priv
->wait_command_queue
,
2947 test_bit(STATUS_READY
, &priv
->status
),
2948 UCODE_READY_TIMEOUT
);
2950 if (!test_bit(STATUS_READY
, &priv
->status
)) {
2951 IWL_ERR(priv
, "START_ALIVE timeout after %dms.\n",
2952 jiffies_to_msecs(UCODE_READY_TIMEOUT
));
2957 iwlagn_led_enable(priv
);
2961 IWL_DEBUG_MAC80211(priv
, "leave\n");
2965 void iwlagn_mac_stop(struct ieee80211_hw
*hw
)
2967 struct iwl_priv
*priv
= hw
->priv
;
2969 IWL_DEBUG_MAC80211(priv
, "enter\n");
2978 flush_workqueue(priv
->workqueue
);
2980 /* User space software may expect getting rfkill changes
2981 * even if interface is down */
2982 iwl_write32(priv
, CSR_INT
, 0xFFFFFFFF);
2983 iwl_enable_rfkill_int(priv
);
2985 IWL_DEBUG_MAC80211(priv
, "leave\n");
2988 void iwlagn_mac_tx(struct ieee80211_hw
*hw
, struct sk_buff
*skb
)
2990 struct iwl_priv
*priv
= hw
->priv
;
2992 IWL_DEBUG_MACDUMP(priv
, "enter\n");
2994 IWL_DEBUG_TX(priv
, "dev->xmit(%d bytes) at rate 0x%02x\n", skb
->len
,
2995 ieee80211_get_tx_rate(hw
, IEEE80211_SKB_CB(skb
))->bitrate
);
2997 if (iwlagn_tx_skb(priv
, skb
))
2998 dev_kfree_skb_any(skb
);
3000 IWL_DEBUG_MACDUMP(priv
, "leave\n");
3003 void iwlagn_mac_update_tkip_key(struct ieee80211_hw
*hw
,
3004 struct ieee80211_vif
*vif
,
3005 struct ieee80211_key_conf
*keyconf
,
3006 struct ieee80211_sta
*sta
,
3007 u32 iv32
, u16
*phase1key
)
3009 struct iwl_priv
*priv
= hw
->priv
;
3010 struct iwl_vif_priv
*vif_priv
= (void *)vif
->drv_priv
;
3012 IWL_DEBUG_MAC80211(priv
, "enter\n");
3014 iwl_update_tkip_key(priv
, vif_priv
->ctx
, keyconf
, sta
,
3017 IWL_DEBUG_MAC80211(priv
, "leave\n");
3020 int iwlagn_mac_set_key(struct ieee80211_hw
*hw
, enum set_key_cmd cmd
,
3021 struct ieee80211_vif
*vif
, struct ieee80211_sta
*sta
,
3022 struct ieee80211_key_conf
*key
)
3024 struct iwl_priv
*priv
= hw
->priv
;
3025 struct iwl_vif_priv
*vif_priv
= (void *)vif
->drv_priv
;
3026 struct iwl_rxon_context
*ctx
= vif_priv
->ctx
;
3029 bool is_default_wep_key
= false;
3031 IWL_DEBUG_MAC80211(priv
, "enter\n");
3033 if (priv
->cfg
->mod_params
->sw_crypto
) {
3034 IWL_DEBUG_MAC80211(priv
, "leave - hwcrypto disabled\n");
3039 * To support IBSS RSN, don't program group keys in IBSS, the
3040 * hardware will then not attempt to decrypt the frames.
3042 if (vif
->type
== NL80211_IFTYPE_ADHOC
&&
3043 !(key
->flags
& IEEE80211_KEY_FLAG_PAIRWISE
))
3046 sta_id
= iwl_sta_id_or_broadcast(priv
, vif_priv
->ctx
, sta
);
3047 if (sta_id
== IWL_INVALID_STATION
)
3050 mutex_lock(&priv
->mutex
);
3051 iwl_scan_cancel_timeout(priv
, 100);
3054 * If we are getting WEP group key and we didn't receive any key mapping
3055 * so far, we are in legacy wep mode (group key only), otherwise we are
3057 * In legacy wep mode, we use another host command to the uCode.
3059 if ((key
->cipher
== WLAN_CIPHER_SUITE_WEP40
||
3060 key
->cipher
== WLAN_CIPHER_SUITE_WEP104
) &&
3063 is_default_wep_key
= !ctx
->key_mapping_keys
;
3065 is_default_wep_key
=
3066 (key
->hw_key_idx
== HW_KEY_DEFAULT
);
3071 if (is_default_wep_key
)
3072 ret
= iwl_set_default_wep_key(priv
, vif_priv
->ctx
, key
);
3074 ret
= iwl_set_dynamic_key(priv
, vif_priv
->ctx
,
3077 IWL_DEBUG_MAC80211(priv
, "enable hwcrypto key\n");
3080 if (is_default_wep_key
)
3081 ret
= iwl_remove_default_wep_key(priv
, ctx
, key
);
3083 ret
= iwl_remove_dynamic_key(priv
, ctx
, key
, sta_id
);
3085 IWL_DEBUG_MAC80211(priv
, "disable hwcrypto key\n");
3091 mutex_unlock(&priv
->mutex
);
3092 IWL_DEBUG_MAC80211(priv
, "leave\n");
3097 int iwlagn_mac_ampdu_action(struct ieee80211_hw
*hw
,
3098 struct ieee80211_vif
*vif
,
3099 enum ieee80211_ampdu_mlme_action action
,
3100 struct ieee80211_sta
*sta
, u16 tid
, u16
*ssn
,
3103 struct iwl_priv
*priv
= hw
->priv
;
3105 struct iwl_station_priv
*sta_priv
= (void *) sta
->drv_priv
;
3107 IWL_DEBUG_HT(priv
, "A-MPDU action on addr %pM tid %d\n",
3110 if (!(priv
->cfg
->sku
& IWL_SKU_N
))
3113 mutex_lock(&priv
->mutex
);
3116 case IEEE80211_AMPDU_RX_START
:
3117 IWL_DEBUG_HT(priv
, "start Rx\n");
3118 ret
= iwl_sta_rx_agg_start(priv
, sta
, tid
, *ssn
);
3120 case IEEE80211_AMPDU_RX_STOP
:
3121 IWL_DEBUG_HT(priv
, "stop Rx\n");
3122 ret
= iwl_sta_rx_agg_stop(priv
, sta
, tid
);
3123 if (test_bit(STATUS_EXIT_PENDING
, &priv
->status
))
3126 case IEEE80211_AMPDU_TX_START
:
3127 IWL_DEBUG_HT(priv
, "start Tx\n");
3128 ret
= iwlagn_tx_agg_start(priv
, vif
, sta
, tid
, ssn
);
3130 priv
->_agn
.agg_tids_count
++;
3131 IWL_DEBUG_HT(priv
, "priv->_agn.agg_tids_count = %u\n",
3132 priv
->_agn
.agg_tids_count
);
3135 case IEEE80211_AMPDU_TX_STOP
:
3136 IWL_DEBUG_HT(priv
, "stop Tx\n");
3137 ret
= iwlagn_tx_agg_stop(priv
, vif
, sta
, tid
);
3138 if ((ret
== 0) && (priv
->_agn
.agg_tids_count
> 0)) {
3139 priv
->_agn
.agg_tids_count
--;
3140 IWL_DEBUG_HT(priv
, "priv->_agn.agg_tids_count = %u\n",
3141 priv
->_agn
.agg_tids_count
);
3143 if (test_bit(STATUS_EXIT_PENDING
, &priv
->status
))
3145 if (priv
->cfg
->ht_params
&&
3146 priv
->cfg
->ht_params
->use_rts_for_aggregation
) {
3147 struct iwl_station_priv
*sta_priv
=
3148 (void *) sta
->drv_priv
;
3150 * switch off RTS/CTS if it was previously enabled
3153 sta_priv
->lq_sta
.lq
.general_params
.flags
&=
3154 ~LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK
;
3155 iwl_send_lq_cmd(priv
, iwl_rxon_ctx_from_vif(vif
),
3156 &sta_priv
->lq_sta
.lq
, CMD_ASYNC
, false);
3159 case IEEE80211_AMPDU_TX_OPERATIONAL
:
3160 buf_size
= min_t(int, buf_size
, LINK_QUAL_AGG_FRAME_LIMIT_DEF
);
3162 iwlagn_txq_agg_queue_setup(priv
, sta
, tid
, buf_size
);
3165 * If the limit is 0, then it wasn't initialised yet,
3166 * use the default. We can do that since we take the
3167 * minimum below, and we don't want to go above our
3168 * default due to hardware restrictions.
3170 if (sta_priv
->max_agg_bufsize
== 0)
3171 sta_priv
->max_agg_bufsize
=
3172 LINK_QUAL_AGG_FRAME_LIMIT_DEF
;
3175 * Even though in theory the peer could have different
3176 * aggregation reorder buffer sizes for different sessions,
3177 * our ucode doesn't allow for that and has a global limit
3178 * for each station. Therefore, use the minimum of all the
3179 * aggregation sessions and our default value.
3181 sta_priv
->max_agg_bufsize
=
3182 min(sta_priv
->max_agg_bufsize
, buf_size
);
3184 if (priv
->cfg
->ht_params
&&
3185 priv
->cfg
->ht_params
->use_rts_for_aggregation
) {
3187 * switch to RTS/CTS if it is the prefer protection
3188 * method for HT traffic
3191 sta_priv
->lq_sta
.lq
.general_params
.flags
|=
3192 LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK
;
3195 sta_priv
->lq_sta
.lq
.agg_params
.agg_frame_cnt_limit
=
3196 sta_priv
->max_agg_bufsize
;
3198 iwl_send_lq_cmd(priv
, iwl_rxon_ctx_from_vif(vif
),
3199 &sta_priv
->lq_sta
.lq
, CMD_ASYNC
, false);
3203 mutex_unlock(&priv
->mutex
);
3208 int iwlagn_mac_sta_add(struct ieee80211_hw
*hw
,
3209 struct ieee80211_vif
*vif
,
3210 struct ieee80211_sta
*sta
)
3212 struct iwl_priv
*priv
= hw
->priv
;
3213 struct iwl_station_priv
*sta_priv
= (void *)sta
->drv_priv
;
3214 struct iwl_vif_priv
*vif_priv
= (void *)vif
->drv_priv
;
3215 bool is_ap
= vif
->type
== NL80211_IFTYPE_STATION
;
3219 IWL_DEBUG_INFO(priv
, "received request to add station %pM\n",
3221 mutex_lock(&priv
->mutex
);
3222 IWL_DEBUG_INFO(priv
, "proceeding to add station %pM\n",
3224 sta_priv
->common
.sta_id
= IWL_INVALID_STATION
;
3226 atomic_set(&sta_priv
->pending_frames
, 0);
3227 if (vif
->type
== NL80211_IFTYPE_AP
)
3228 sta_priv
->client
= true;
3230 ret
= iwl_add_station_common(priv
, vif_priv
->ctx
, sta
->addr
,
3231 is_ap
, sta
, &sta_id
);
3233 IWL_ERR(priv
, "Unable to add station %pM (%d)\n",
3235 /* Should we return success if return code is EEXIST ? */
3236 mutex_unlock(&priv
->mutex
);
3240 sta_priv
->common
.sta_id
= sta_id
;
3242 /* Initialize rate scaling */
3243 IWL_DEBUG_INFO(priv
, "Initializing rate scaling for station %pM\n",
3245 iwl_rs_rate_init(priv
, sta
, sta_id
);
3246 mutex_unlock(&priv
->mutex
);
3251 void iwlagn_mac_channel_switch(struct ieee80211_hw
*hw
,
3252 struct ieee80211_channel_switch
*ch_switch
)
3254 struct iwl_priv
*priv
= hw
->priv
;
3255 const struct iwl_channel_info
*ch_info
;
3256 struct ieee80211_conf
*conf
= &hw
->conf
;
3257 struct ieee80211_channel
*channel
= ch_switch
->channel
;
3258 struct iwl_ht_config
*ht_conf
= &priv
->current_ht_config
;
3261 * When we add support for multiple interfaces, we need to
3262 * revisit this. The channel switch command in the device
3263 * only affects the BSS context, but what does that really
3264 * mean? And what if we get a CSA on the second interface?
3265 * This needs a lot of work.
3267 struct iwl_rxon_context
*ctx
= &priv
->contexts
[IWL_RXON_CTX_BSS
];
3269 unsigned long flags
= 0;
3271 IWL_DEBUG_MAC80211(priv
, "enter\n");
3273 mutex_lock(&priv
->mutex
);
3275 if (iwl_is_rfkill(priv
))
3278 if (test_bit(STATUS_EXIT_PENDING
, &priv
->status
) ||
3279 test_bit(STATUS_SCANNING
, &priv
->status
))
3282 if (!iwl_is_associated_ctx(ctx
))
3285 /* channel switch in progress */
3286 if (priv
->switch_rxon
.switch_in_progress
== true)
3289 if (priv
->cfg
->ops
->lib
->set_channel_switch
) {
3291 ch
= channel
->hw_value
;
3292 if (le16_to_cpu(ctx
->active
.channel
) != ch
) {
3293 ch_info
= iwl_get_channel_info(priv
,
3296 if (!is_channel_valid(ch_info
)) {
3297 IWL_DEBUG_MAC80211(priv
, "invalid channel\n");
3300 spin_lock_irqsave(&priv
->lock
, flags
);
3302 priv
->current_ht_config
.smps
= conf
->smps_mode
;
3304 /* Configure HT40 channels */
3305 ctx
->ht
.enabled
= conf_is_ht(conf
);
3306 if (ctx
->ht
.enabled
) {
3307 if (conf_is_ht40_minus(conf
)) {
3308 ctx
->ht
.extension_chan_offset
=
3309 IEEE80211_HT_PARAM_CHA_SEC_BELOW
;
3310 ctx
->ht
.is_40mhz
= true;
3311 } else if (conf_is_ht40_plus(conf
)) {
3312 ctx
->ht
.extension_chan_offset
=
3313 IEEE80211_HT_PARAM_CHA_SEC_ABOVE
;
3314 ctx
->ht
.is_40mhz
= true;
3316 ctx
->ht
.extension_chan_offset
=
3317 IEEE80211_HT_PARAM_CHA_SEC_NONE
;
3318 ctx
->ht
.is_40mhz
= false;
3321 ctx
->ht
.is_40mhz
= false;
3323 if ((le16_to_cpu(ctx
->staging
.channel
) != ch
))
3324 ctx
->staging
.flags
= 0;
3326 iwl_set_rxon_channel(priv
, channel
, ctx
);
3327 iwl_set_rxon_ht(priv
, ht_conf
);
3328 iwl_set_flags_for_band(priv
, ctx
, channel
->band
,
3330 spin_unlock_irqrestore(&priv
->lock
, flags
);
3334 * at this point, staging_rxon has the
3335 * configuration for channel switch
3337 if (priv
->cfg
->ops
->lib
->set_channel_switch(priv
,
3339 priv
->switch_rxon
.switch_in_progress
= false;
3343 mutex_unlock(&priv
->mutex
);
3344 if (!priv
->switch_rxon
.switch_in_progress
)
3345 ieee80211_chswitch_done(ctx
->vif
, false);
3346 IWL_DEBUG_MAC80211(priv
, "leave\n");
3349 void iwlagn_configure_filter(struct ieee80211_hw
*hw
,
3350 unsigned int changed_flags
,
3351 unsigned int *total_flags
,
3354 struct iwl_priv
*priv
= hw
->priv
;
3355 __le32 filter_or
= 0, filter_nand
= 0;
3356 struct iwl_rxon_context
*ctx
;
3358 #define CHK(test, flag) do { \
3359 if (*total_flags & (test)) \
3360 filter_or |= (flag); \
3362 filter_nand |= (flag); \
3365 IWL_DEBUG_MAC80211(priv
, "Enter: changed: 0x%x, total: 0x%x\n",
3366 changed_flags
, *total_flags
);
3368 CHK(FIF_OTHER_BSS
| FIF_PROMISC_IN_BSS
, RXON_FILTER_PROMISC_MSK
);
3369 /* Setting _just_ RXON_FILTER_CTL2HOST_MSK causes FH errors */
3370 CHK(FIF_CONTROL
, RXON_FILTER_CTL2HOST_MSK
| RXON_FILTER_PROMISC_MSK
);
3371 CHK(FIF_BCN_PRBRESP_PROMISC
, RXON_FILTER_BCON_AWARE_MSK
);
3375 mutex_lock(&priv
->mutex
);
3377 for_each_context(priv
, ctx
) {
3378 ctx
->staging
.filter_flags
&= ~filter_nand
;
3379 ctx
->staging
.filter_flags
|= filter_or
;
3382 * Not committing directly because hardware can perform a scan,
3383 * but we'll eventually commit the filter flags change anyway.
3387 mutex_unlock(&priv
->mutex
);
3390 * Receiving all multicast frames is always enabled by the
3391 * default flags setup in iwl_connection_init_rx_config()
3392 * since we currently do not support programming multicast
3393 * filters into the device.
3395 *total_flags
&= FIF_OTHER_BSS
| FIF_ALLMULTI
| FIF_PROMISC_IN_BSS
|
3396 FIF_BCN_PRBRESP_PROMISC
| FIF_CONTROL
;
3399 void iwlagn_mac_flush(struct ieee80211_hw
*hw
, bool drop
)
3401 struct iwl_priv
*priv
= hw
->priv
;
3403 mutex_lock(&priv
->mutex
);
3404 IWL_DEBUG_MAC80211(priv
, "enter\n");
3406 /* do not support "flush" */
3407 if (!priv
->cfg
->ops
->lib
->txfifo_flush
)
3410 if (test_bit(STATUS_EXIT_PENDING
, &priv
->status
)) {
3411 IWL_DEBUG_TX(priv
, "Aborting flush due to device shutdown\n");
3414 if (iwl_is_rfkill(priv
)) {
3415 IWL_DEBUG_TX(priv
, "Aborting flush due to RF Kill\n");
3420 * mac80211 will not push any more frames for transmit
3421 * until the flush is completed
3424 IWL_DEBUG_MAC80211(priv
, "send flush command\n");
3425 if (priv
->cfg
->ops
->lib
->txfifo_flush(priv
, IWL_DROP_ALL
)) {
3426 IWL_ERR(priv
, "flush request fail\n");
3430 IWL_DEBUG_MAC80211(priv
, "wait transmit/flush all frames\n");
3431 iwlagn_wait_tx_queue_empty(priv
);
3433 mutex_unlock(&priv
->mutex
);
3434 IWL_DEBUG_MAC80211(priv
, "leave\n");
3437 static void iwlagn_disable_roc(struct iwl_priv
*priv
)
3439 struct iwl_rxon_context
*ctx
= &priv
->contexts
[IWL_RXON_CTX_PAN
];
3440 struct ieee80211_channel
*chan
= ACCESS_ONCE(priv
->hw
->conf
.channel
);
3442 lockdep_assert_held(&priv
->mutex
);
3444 if (!ctx
->is_active
)
3447 ctx
->staging
.dev_type
= RXON_DEV_TYPE_2STA
;
3448 ctx
->staging
.filter_flags
&= ~RXON_FILTER_ASSOC_MSK
;
3449 iwl_set_rxon_channel(priv
, chan
, ctx
);
3450 iwl_set_flags_for_band(priv
, ctx
, chan
->band
, NULL
);
3452 priv
->_agn
.hw_roc_channel
= NULL
;
3454 iwlcore_commit_rxon(priv
, ctx
);
3456 ctx
->is_active
= false;
3459 static void iwlagn_bg_roc_done(struct work_struct
*work
)
3461 struct iwl_priv
*priv
= container_of(work
, struct iwl_priv
,
3462 _agn
.hw_roc_work
.work
);
3464 mutex_lock(&priv
->mutex
);
3465 ieee80211_remain_on_channel_expired(priv
->hw
);
3466 iwlagn_disable_roc(priv
);
3467 mutex_unlock(&priv
->mutex
);
3470 static int iwl_mac_remain_on_channel(struct ieee80211_hw
*hw
,
3471 struct ieee80211_channel
*channel
,
3472 enum nl80211_channel_type channel_type
,
3475 struct iwl_priv
*priv
= hw
->priv
;
3478 if (!(priv
->valid_contexts
& BIT(IWL_RXON_CTX_PAN
)))
3481 if (!(priv
->contexts
[IWL_RXON_CTX_PAN
].interface_modes
&
3482 BIT(NL80211_IFTYPE_P2P_CLIENT
)))
3485 mutex_lock(&priv
->mutex
);
3487 if (priv
->contexts
[IWL_RXON_CTX_PAN
].is_active
||
3488 test_bit(STATUS_SCAN_HW
, &priv
->status
)) {
3493 priv
->contexts
[IWL_RXON_CTX_PAN
].is_active
= true;
3494 priv
->_agn
.hw_roc_channel
= channel
;
3495 priv
->_agn
.hw_roc_chantype
= channel_type
;
3496 priv
->_agn
.hw_roc_duration
= DIV_ROUND_UP(duration
* 1000, 1024);
3497 iwlcore_commit_rxon(priv
, &priv
->contexts
[IWL_RXON_CTX_PAN
]);
3498 queue_delayed_work(priv
->workqueue
, &priv
->_agn
.hw_roc_work
,
3499 msecs_to_jiffies(duration
+ 20));
3501 msleep(IWL_MIN_SLOT_TIME
); /* TU is almost ms */
3502 ieee80211_ready_on_channel(priv
->hw
);
3505 mutex_unlock(&priv
->mutex
);
3510 static int iwl_mac_cancel_remain_on_channel(struct ieee80211_hw
*hw
)
3512 struct iwl_priv
*priv
= hw
->priv
;
3514 if (!(priv
->valid_contexts
& BIT(IWL_RXON_CTX_PAN
)))
3517 cancel_delayed_work_sync(&priv
->_agn
.hw_roc_work
);
3519 mutex_lock(&priv
->mutex
);
3520 iwlagn_disable_roc(priv
);
3521 mutex_unlock(&priv
->mutex
);
3526 /*****************************************************************************
3528 * driver setup and teardown
3530 *****************************************************************************/
3532 static void iwl_setup_deferred_work(struct iwl_priv
*priv
)
3534 priv
->workqueue
= create_singlethread_workqueue(DRV_NAME
);
3536 init_waitqueue_head(&priv
->wait_command_queue
);
3538 INIT_WORK(&priv
->restart
, iwl_bg_restart
);
3539 INIT_WORK(&priv
->rx_replenish
, iwl_bg_rx_replenish
);
3540 INIT_WORK(&priv
->beacon_update
, iwl_bg_beacon_update
);
3541 INIT_WORK(&priv
->run_time_calib_work
, iwl_bg_run_time_calib_work
);
3542 INIT_WORK(&priv
->tx_flush
, iwl_bg_tx_flush
);
3543 INIT_WORK(&priv
->bt_full_concurrency
, iwl_bg_bt_full_concurrency
);
3544 INIT_WORK(&priv
->bt_runtime_config
, iwl_bg_bt_runtime_config
);
3545 INIT_DELAYED_WORK(&priv
->init_alive_start
, iwl_bg_init_alive_start
);
3546 INIT_DELAYED_WORK(&priv
->alive_start
, iwl_bg_alive_start
);
3547 INIT_DELAYED_WORK(&priv
->_agn
.hw_roc_work
, iwlagn_bg_roc_done
);
3549 iwl_setup_scan_deferred_work(priv
);
3551 if (priv
->cfg
->ops
->lib
->setup_deferred_work
)
3552 priv
->cfg
->ops
->lib
->setup_deferred_work(priv
);
3554 init_timer(&priv
->statistics_periodic
);
3555 priv
->statistics_periodic
.data
= (unsigned long)priv
;
3556 priv
->statistics_periodic
.function
= iwl_bg_statistics_periodic
;
3558 init_timer(&priv
->ucode_trace
);
3559 priv
->ucode_trace
.data
= (unsigned long)priv
;
3560 priv
->ucode_trace
.function
= iwl_bg_ucode_trace
;
3562 init_timer(&priv
->watchdog
);
3563 priv
->watchdog
.data
= (unsigned long)priv
;
3564 priv
->watchdog
.function
= iwl_bg_watchdog
;
3566 tasklet_init(&priv
->irq_tasklet
, (void (*)(unsigned long))
3567 iwl_irq_tasklet
, (unsigned long)priv
);
3570 static void iwl_cancel_deferred_work(struct iwl_priv
*priv
)
3572 if (priv
->cfg
->ops
->lib
->cancel_deferred_work
)
3573 priv
->cfg
->ops
->lib
->cancel_deferred_work(priv
);
3575 cancel_delayed_work_sync(&priv
->init_alive_start
);
3576 cancel_delayed_work(&priv
->alive_start
);
3577 cancel_work_sync(&priv
->run_time_calib_work
);
3578 cancel_work_sync(&priv
->beacon_update
);
3580 iwl_cancel_scan_deferred_work(priv
);
3582 cancel_work_sync(&priv
->bt_full_concurrency
);
3583 cancel_work_sync(&priv
->bt_runtime_config
);
3585 del_timer_sync(&priv
->statistics_periodic
);
3586 del_timer_sync(&priv
->ucode_trace
);
3589 static void iwl_init_hw_rates(struct iwl_priv
*priv
,
3590 struct ieee80211_rate
*rates
)
3594 for (i
= 0; i
< IWL_RATE_COUNT_LEGACY
; i
++) {
3595 rates
[i
].bitrate
= iwl_rates
[i
].ieee
* 5;
3596 rates
[i
].hw_value
= i
; /* Rate scaling will work on indexes */
3597 rates
[i
].hw_value_short
= i
;
3599 if ((i
>= IWL_FIRST_CCK_RATE
) && (i
<= IWL_LAST_CCK_RATE
)) {
3601 * If CCK != 1M then set short preamble rate flag.
3604 (iwl_rates
[i
].plcp
== IWL_RATE_1M_PLCP
) ?
3605 0 : IEEE80211_RATE_SHORT_PREAMBLE
;
3610 static int iwl_init_drv(struct iwl_priv
*priv
)
3614 spin_lock_init(&priv
->sta_lock
);
3615 spin_lock_init(&priv
->hcmd_lock
);
3617 INIT_LIST_HEAD(&priv
->free_frames
);
3619 mutex_init(&priv
->mutex
);
3621 priv
->ieee_channels
= NULL
;
3622 priv
->ieee_rates
= NULL
;
3623 priv
->band
= IEEE80211_BAND_2GHZ
;
3625 priv
->iw_mode
= NL80211_IFTYPE_STATION
;
3626 priv
->current_ht_config
.smps
= IEEE80211_SMPS_STATIC
;
3627 priv
->missed_beacon_threshold
= IWL_MISSED_BEACON_THRESHOLD_DEF
;
3628 priv
->_agn
.agg_tids_count
= 0;
3630 /* initialize force reset */
3631 priv
->force_reset
[IWL_RF_RESET
].reset_duration
=
3632 IWL_DELAY_NEXT_FORCE_RF_RESET
;
3633 priv
->force_reset
[IWL_FW_RESET
].reset_duration
=
3634 IWL_DELAY_NEXT_FORCE_FW_RELOAD
;
3636 priv
->rx_statistics_jiffies
= jiffies
;
3638 /* Choose which receivers/antennas to use */
3639 if (priv
->cfg
->ops
->hcmd
->set_rxon_chain
)
3640 priv
->cfg
->ops
->hcmd
->set_rxon_chain(priv
,
3641 &priv
->contexts
[IWL_RXON_CTX_BSS
]);
3643 iwl_init_scan_params(priv
);
3646 if (priv
->cfg
->bt_params
&&
3647 priv
->cfg
->bt_params
->advanced_bt_coexist
) {
3648 priv
->kill_ack_mask
= IWLAGN_BT_KILL_ACK_MASK_DEFAULT
;
3649 priv
->kill_cts_mask
= IWLAGN_BT_KILL_CTS_MASK_DEFAULT
;
3650 priv
->bt_valid
= IWLAGN_BT_ALL_VALID_MSK
;
3651 priv
->bt_on_thresh
= BT_ON_THRESHOLD_DEF
;
3652 priv
->bt_duration
= BT_DURATION_LIMIT_DEF
;
3653 priv
->dynamic_frag_thresh
= BT_FRAG_THRESHOLD_DEF
;
3656 /* Set the tx_power_user_lmt to the lowest power level
3657 * this value will get overwritten by channel max power avg
3659 priv
->tx_power_user_lmt
= IWLAGN_TX_POWER_TARGET_POWER_MIN
;
3660 priv
->tx_power_next
= IWLAGN_TX_POWER_TARGET_POWER_MIN
;
3662 ret
= iwl_init_channel_map(priv
);
3664 IWL_ERR(priv
, "initializing regulatory failed: %d\n", ret
);
3668 ret
= iwlcore_init_geos(priv
);
3670 IWL_ERR(priv
, "initializing geos failed: %d\n", ret
);
3671 goto err_free_channel_map
;
3673 iwl_init_hw_rates(priv
, priv
->ieee_rates
);
3677 err_free_channel_map
:
3678 iwl_free_channel_map(priv
);
3683 static void iwl_uninit_drv(struct iwl_priv
*priv
)
3685 iwl_calib_free_results(priv
);
3686 iwlcore_free_geos(priv
);
3687 iwl_free_channel_map(priv
);
3688 kfree(priv
->scan_cmd
);
3691 struct ieee80211_ops iwlagn_hw_ops
= {
3692 .tx
= iwlagn_mac_tx
,
3693 .start
= iwlagn_mac_start
,
3694 .stop
= iwlagn_mac_stop
,
3695 .add_interface
= iwl_mac_add_interface
,
3696 .remove_interface
= iwl_mac_remove_interface
,
3697 .change_interface
= iwl_mac_change_interface
,
3698 .config
= iwlagn_mac_config
,
3699 .configure_filter
= iwlagn_configure_filter
,
3700 .set_key
= iwlagn_mac_set_key
,
3701 .update_tkip_key
= iwlagn_mac_update_tkip_key
,
3702 .conf_tx
= iwl_mac_conf_tx
,
3703 .bss_info_changed
= iwlagn_bss_info_changed
,
3704 .ampdu_action
= iwlagn_mac_ampdu_action
,
3705 .hw_scan
= iwl_mac_hw_scan
,
3706 .sta_notify
= iwlagn_mac_sta_notify
,
3707 .sta_add
= iwlagn_mac_sta_add
,
3708 .sta_remove
= iwl_mac_sta_remove
,
3709 .channel_switch
= iwlagn_mac_channel_switch
,
3710 .flush
= iwlagn_mac_flush
,
3711 .tx_last_beacon
= iwl_mac_tx_last_beacon
,
3712 .remain_on_channel
= iwl_mac_remain_on_channel
,
3713 .cancel_remain_on_channel
= iwl_mac_cancel_remain_on_channel
,
3714 .offchannel_tx
= iwl_mac_offchannel_tx
,
3715 .offchannel_tx_cancel_wait
= iwl_mac_offchannel_tx_cancel_wait
,
3718 static void iwl_hw_detect(struct iwl_priv
*priv
)
3720 priv
->hw_rev
= _iwl_read32(priv
, CSR_HW_REV
);
3721 priv
->hw_wa_rev
= _iwl_read32(priv
, CSR_HW_REV_WA_REG
);
3722 priv
->rev_id
= priv
->pci_dev
->revision
;
3723 IWL_DEBUG_INFO(priv
, "HW Revision ID = 0x%X\n", priv
->rev_id
);
3726 static int iwl_set_hw_params(struct iwl_priv
*priv
)
3728 priv
->hw_params
.max_rxq_size
= RX_QUEUE_SIZE
;
3729 priv
->hw_params
.max_rxq_log
= RX_QUEUE_SIZE_LOG
;
3730 if (priv
->cfg
->mod_params
->amsdu_size_8K
)
3731 priv
->hw_params
.rx_page_order
= get_order(IWL_RX_BUF_SIZE_8K
);
3733 priv
->hw_params
.rx_page_order
= get_order(IWL_RX_BUF_SIZE_4K
);
3735 priv
->hw_params
.max_beacon_itrvl
= IWL_MAX_UCODE_BEACON_INTERVAL
;
3737 if (priv
->cfg
->mod_params
->disable_11n
)
3738 priv
->cfg
->sku
&= ~IWL_SKU_N
;
3740 /* Device-specific setup */
3741 return priv
->cfg
->ops
->lib
->set_hw_params(priv
);
3744 static const u8 iwlagn_bss_ac_to_fifo
[] = {
3751 static const u8 iwlagn_bss_ac_to_queue
[] = {
3755 static const u8 iwlagn_pan_ac_to_fifo
[] = {
3756 IWL_TX_FIFO_VO_IPAN
,
3757 IWL_TX_FIFO_VI_IPAN
,
3758 IWL_TX_FIFO_BE_IPAN
,
3759 IWL_TX_FIFO_BK_IPAN
,
3762 static const u8 iwlagn_pan_ac_to_queue
[] = {
3766 static int iwl_pci_probe(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
3769 struct iwl_priv
*priv
;
3770 struct ieee80211_hw
*hw
;
3771 struct iwl_cfg
*cfg
= (struct iwl_cfg
*)(ent
->driver_data
);
3772 unsigned long flags
;
3773 u16 pci_cmd
, num_mac
;
3775 /************************
3776 * 1. Allocating HW data
3777 ************************/
3779 hw
= iwl_alloc_all(cfg
);
3785 /* At this point both hw and priv are allocated. */
3788 * The default context is always valid,
3789 * more may be discovered when firmware
3792 priv
->valid_contexts
= BIT(IWL_RXON_CTX_BSS
);
3794 for (i
= 0; i
< NUM_IWL_RXON_CTX
; i
++)
3795 priv
->contexts
[i
].ctxid
= i
;
3797 priv
->contexts
[IWL_RXON_CTX_BSS
].always_active
= true;
3798 priv
->contexts
[IWL_RXON_CTX_BSS
].is_active
= true;
3799 priv
->contexts
[IWL_RXON_CTX_BSS
].rxon_cmd
= REPLY_RXON
;
3800 priv
->contexts
[IWL_RXON_CTX_BSS
].rxon_timing_cmd
= REPLY_RXON_TIMING
;
3801 priv
->contexts
[IWL_RXON_CTX_BSS
].rxon_assoc_cmd
= REPLY_RXON_ASSOC
;
3802 priv
->contexts
[IWL_RXON_CTX_BSS
].qos_cmd
= REPLY_QOS_PARAM
;
3803 priv
->contexts
[IWL_RXON_CTX_BSS
].ap_sta_id
= IWL_AP_ID
;
3804 priv
->contexts
[IWL_RXON_CTX_BSS
].wep_key_cmd
= REPLY_WEPKEY
;
3805 priv
->contexts
[IWL_RXON_CTX_BSS
].ac_to_fifo
= iwlagn_bss_ac_to_fifo
;
3806 priv
->contexts
[IWL_RXON_CTX_BSS
].ac_to_queue
= iwlagn_bss_ac_to_queue
;
3807 priv
->contexts
[IWL_RXON_CTX_BSS
].exclusive_interface_modes
=
3808 BIT(NL80211_IFTYPE_ADHOC
);
3809 priv
->contexts
[IWL_RXON_CTX_BSS
].interface_modes
=
3810 BIT(NL80211_IFTYPE_STATION
);
3811 priv
->contexts
[IWL_RXON_CTX_BSS
].ap_devtype
= RXON_DEV_TYPE_AP
;
3812 priv
->contexts
[IWL_RXON_CTX_BSS
].ibss_devtype
= RXON_DEV_TYPE_IBSS
;
3813 priv
->contexts
[IWL_RXON_CTX_BSS
].station_devtype
= RXON_DEV_TYPE_ESS
;
3814 priv
->contexts
[IWL_RXON_CTX_BSS
].unused_devtype
= RXON_DEV_TYPE_ESS
;
3816 priv
->contexts
[IWL_RXON_CTX_PAN
].rxon_cmd
= REPLY_WIPAN_RXON
;
3817 priv
->contexts
[IWL_RXON_CTX_PAN
].rxon_timing_cmd
= REPLY_WIPAN_RXON_TIMING
;
3818 priv
->contexts
[IWL_RXON_CTX_PAN
].rxon_assoc_cmd
= REPLY_WIPAN_RXON_ASSOC
;
3819 priv
->contexts
[IWL_RXON_CTX_PAN
].qos_cmd
= REPLY_WIPAN_QOS_PARAM
;
3820 priv
->contexts
[IWL_RXON_CTX_PAN
].ap_sta_id
= IWL_AP_ID_PAN
;
3821 priv
->contexts
[IWL_RXON_CTX_PAN
].wep_key_cmd
= REPLY_WIPAN_WEPKEY
;
3822 priv
->contexts
[IWL_RXON_CTX_PAN
].bcast_sta_id
= IWLAGN_PAN_BCAST_ID
;
3823 priv
->contexts
[IWL_RXON_CTX_PAN
].station_flags
= STA_FLG_PAN_STATION
;
3824 priv
->contexts
[IWL_RXON_CTX_PAN
].ac_to_fifo
= iwlagn_pan_ac_to_fifo
;
3825 priv
->contexts
[IWL_RXON_CTX_PAN
].ac_to_queue
= iwlagn_pan_ac_to_queue
;
3826 priv
->contexts
[IWL_RXON_CTX_PAN
].mcast_queue
= IWL_IPAN_MCAST_QUEUE
;
3827 priv
->contexts
[IWL_RXON_CTX_PAN
].interface_modes
=
3828 BIT(NL80211_IFTYPE_STATION
) | BIT(NL80211_IFTYPE_AP
);
3829 #ifdef CONFIG_IWL_P2P
3830 priv
->contexts
[IWL_RXON_CTX_PAN
].interface_modes
|=
3831 BIT(NL80211_IFTYPE_P2P_CLIENT
) | BIT(NL80211_IFTYPE_P2P_GO
);
3833 priv
->contexts
[IWL_RXON_CTX_PAN
].ap_devtype
= RXON_DEV_TYPE_CP
;
3834 priv
->contexts
[IWL_RXON_CTX_PAN
].station_devtype
= RXON_DEV_TYPE_2STA
;
3835 priv
->contexts
[IWL_RXON_CTX_PAN
].unused_devtype
= RXON_DEV_TYPE_P2P
;
3837 BUILD_BUG_ON(NUM_IWL_RXON_CTX
!= 2);
3839 SET_IEEE80211_DEV(hw
, &pdev
->dev
);
3841 IWL_DEBUG_INFO(priv
, "*** LOAD DRIVER ***\n");
3843 priv
->pci_dev
= pdev
;
3844 priv
->inta_mask
= CSR_INI_SET_MASK
;
3846 /* is antenna coupling more than 35dB ? */
3847 priv
->bt_ant_couple_ok
=
3848 (iwlagn_ant_coupling
> IWL_BT_ANTENNA_COUPLING_THRESHOLD
) ?
3851 /* enable/disable bt channel inhibition */
3852 priv
->bt_ch_announce
= iwlagn_bt_ch_announce
;
3853 IWL_DEBUG_INFO(priv
, "BT channel inhibition is %s\n",
3854 (priv
->bt_ch_announce
) ? "On" : "Off");
3856 if (iwl_alloc_traffic_mem(priv
))
3857 IWL_ERR(priv
, "Not enough memory to generate traffic log\n");
3859 /**************************
3860 * 2. Initializing PCI bus
3861 **************************/
3862 pci_disable_link_state(pdev
, PCIE_LINK_STATE_L0S
| PCIE_LINK_STATE_L1
|
3863 PCIE_LINK_STATE_CLKPM
);
3865 if (pci_enable_device(pdev
)) {
3867 goto out_ieee80211_free_hw
;
3870 pci_set_master(pdev
);
3872 err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(36));
3874 err
= pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(36));
3876 err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
3878 err
= pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(32));
3879 /* both attempts failed: */
3881 IWL_WARN(priv
, "No suitable DMA available.\n");
3882 goto out_pci_disable_device
;
3886 err
= pci_request_regions(pdev
, DRV_NAME
);
3888 goto out_pci_disable_device
;
3890 pci_set_drvdata(pdev
, priv
);
3893 /***********************
3894 * 3. Read REV register
3895 ***********************/
3896 priv
->hw_base
= pci_iomap(pdev
, 0, 0);
3897 if (!priv
->hw_base
) {
3899 goto out_pci_release_regions
;
3902 IWL_DEBUG_INFO(priv
, "pci_resource_len = 0x%08llx\n",
3903 (unsigned long long) pci_resource_len(pdev
, 0));
3904 IWL_DEBUG_INFO(priv
, "pci_resource_base = %p\n", priv
->hw_base
);
3906 /* these spin locks will be used in apm_ops.init and EEPROM access
3907 * we should init now
3909 spin_lock_init(&priv
->reg_lock
);
3910 spin_lock_init(&priv
->lock
);
3913 * stop and reset the on-board processor just in case it is in a
3914 * strange state ... like being left stranded by a primary kernel
3915 * and this is now the kdump kernel trying to start up
3917 iwl_write32(priv
, CSR_RESET
, CSR_RESET_REG_FLAG_NEVO_RESET
);
3919 iwl_hw_detect(priv
);
3920 IWL_INFO(priv
, "Detected %s, REV=0x%X\n",
3921 priv
->cfg
->name
, priv
->hw_rev
);
3923 /* We disable the RETRY_TIMEOUT register (0x41) to keep
3924 * PCI Tx retries from interfering with C3 CPU state */
3925 pci_write_config_byte(pdev
, PCI_CFG_RETRY_TIMEOUT
, 0x00);
3927 iwl_prepare_card_hw(priv
);
3928 if (!priv
->hw_ready
) {
3929 IWL_WARN(priv
, "Failed, HW not ready\n");
3936 /* Read the EEPROM */
3937 err
= iwl_eeprom_init(priv
);
3939 IWL_ERR(priv
, "Unable to init EEPROM\n");
3942 err
= iwl_eeprom_check_version(priv
);
3944 goto out_free_eeprom
;
3946 err
= iwl_eeprom_check_sku(priv
);
3948 goto out_free_eeprom
;
3950 /* extract MAC Address */
3951 iwl_eeprom_get_mac(priv
, priv
->addresses
[0].addr
);
3952 IWL_DEBUG_INFO(priv
, "MAC address: %pM\n", priv
->addresses
[0].addr
);
3953 priv
->hw
->wiphy
->addresses
= priv
->addresses
;
3954 priv
->hw
->wiphy
->n_addresses
= 1;
3955 num_mac
= iwl_eeprom_query16(priv
, EEPROM_NUM_MAC_ADDRESS
);
3957 memcpy(priv
->addresses
[1].addr
, priv
->addresses
[0].addr
,
3959 priv
->addresses
[1].addr
[5]++;
3960 priv
->hw
->wiphy
->n_addresses
++;
3963 /************************
3964 * 5. Setup HW constants
3965 ************************/
3966 if (iwl_set_hw_params(priv
)) {
3967 IWL_ERR(priv
, "failed to set hw parameters\n");
3968 goto out_free_eeprom
;
3971 /*******************
3973 *******************/
3975 err
= iwl_init_drv(priv
);
3977 goto out_free_eeprom
;
3978 /* At this point both hw and priv are initialized. */
3980 /********************
3982 ********************/
3983 spin_lock_irqsave(&priv
->lock
, flags
);
3984 iwl_disable_interrupts(priv
);
3985 spin_unlock_irqrestore(&priv
->lock
, flags
);
3987 pci_enable_msi(priv
->pci_dev
);
3989 if (priv
->cfg
->ops
->lib
->isr_ops
.alloc
)
3990 priv
->cfg
->ops
->lib
->isr_ops
.alloc(priv
);
3992 err
= request_irq(priv
->pci_dev
->irq
, priv
->cfg
->ops
->lib
->isr_ops
.isr
,
3993 IRQF_SHARED
, DRV_NAME
, priv
);
3995 IWL_ERR(priv
, "Error allocating IRQ %d\n", priv
->pci_dev
->irq
);
3996 goto out_disable_msi
;
3999 iwl_setup_deferred_work(priv
);
4000 iwl_setup_rx_handlers(priv
);
4002 /*********************************************
4003 * 8. Enable interrupts and read RFKILL state
4004 *********************************************/
4006 /* enable rfkill interrupt: hw bug w/a */
4007 pci_read_config_word(priv
->pci_dev
, PCI_COMMAND
, &pci_cmd
);
4008 if (pci_cmd
& PCI_COMMAND_INTX_DISABLE
) {
4009 pci_cmd
&= ~PCI_COMMAND_INTX_DISABLE
;
4010 pci_write_config_word(priv
->pci_dev
, PCI_COMMAND
, pci_cmd
);
4013 iwl_enable_rfkill_int(priv
);
4015 /* If platform's RF_KILL switch is NOT set to KILL */
4016 if (iwl_read32(priv
, CSR_GP_CNTRL
) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW
)
4017 clear_bit(STATUS_RF_KILL_HW
, &priv
->status
);
4019 set_bit(STATUS_RF_KILL_HW
, &priv
->status
);
4021 wiphy_rfkill_set_hw_state(priv
->hw
->wiphy
,
4022 test_bit(STATUS_RF_KILL_HW
, &priv
->status
));
4024 iwl_power_initialize(priv
);
4025 iwl_tt_initialize(priv
);
4027 init_completion(&priv
->_agn
.firmware_loading_complete
);
4029 err
= iwl_request_firmware(priv
, true);
4031 goto out_destroy_workqueue
;
4035 out_destroy_workqueue
:
4036 destroy_workqueue(priv
->workqueue
);
4037 priv
->workqueue
= NULL
;
4038 free_irq(priv
->pci_dev
->irq
, priv
);
4039 if (priv
->cfg
->ops
->lib
->isr_ops
.free
)
4040 priv
->cfg
->ops
->lib
->isr_ops
.free(priv
);
4042 pci_disable_msi(priv
->pci_dev
);
4043 iwl_uninit_drv(priv
);
4045 iwl_eeprom_free(priv
);
4047 pci_iounmap(pdev
, priv
->hw_base
);
4048 out_pci_release_regions
:
4049 pci_set_drvdata(pdev
, NULL
);
4050 pci_release_regions(pdev
);
4051 out_pci_disable_device
:
4052 pci_disable_device(pdev
);
4053 out_ieee80211_free_hw
:
4054 iwl_free_traffic_mem(priv
);
4055 ieee80211_free_hw(priv
->hw
);
4060 static void __devexit
iwl_pci_remove(struct pci_dev
*pdev
)
4062 struct iwl_priv
*priv
= pci_get_drvdata(pdev
);
4063 unsigned long flags
;
4068 wait_for_completion(&priv
->_agn
.firmware_loading_complete
);
4070 IWL_DEBUG_INFO(priv
, "*** UNLOAD DRIVER ***\n");
4072 iwl_dbgfs_unregister(priv
);
4073 sysfs_remove_group(&pdev
->dev
.kobj
, &iwl_attribute_group
);
4075 /* ieee80211_unregister_hw call wil cause iwl_mac_stop to
4076 * to be called and iwl_down since we are removing the device
4077 * we need to set STATUS_EXIT_PENDING bit.
4079 set_bit(STATUS_EXIT_PENDING
, &priv
->status
);
4081 iwl_leds_exit(priv
);
4083 if (priv
->mac80211_registered
) {
4084 ieee80211_unregister_hw(priv
->hw
);
4085 priv
->mac80211_registered
= 0;
4091 * Make sure device is reset to low power before unloading driver.
4092 * This may be redundant with iwl_down(), but there are paths to
4093 * run iwl_down() without calling apm_ops.stop(), and there are
4094 * paths to avoid running iwl_down() at all before leaving driver.
4095 * This (inexpensive) call *makes sure* device is reset.
4101 /* make sure we flush any pending irq or
4102 * tasklet for the driver
4104 spin_lock_irqsave(&priv
->lock
, flags
);
4105 iwl_disable_interrupts(priv
);
4106 spin_unlock_irqrestore(&priv
->lock
, flags
);
4108 iwl_synchronize_irq(priv
);
4110 iwl_dealloc_ucode_pci(priv
);
4113 iwlagn_rx_queue_free(priv
, &priv
->rxq
);
4114 iwlagn_hw_txq_ctx_free(priv
);
4116 iwl_eeprom_free(priv
);
4119 /*netif_stop_queue(dev); */
4120 flush_workqueue(priv
->workqueue
);
4122 /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes
4123 * priv->workqueue... so we can't take down the workqueue
4125 destroy_workqueue(priv
->workqueue
);
4126 priv
->workqueue
= NULL
;
4127 iwl_free_traffic_mem(priv
);
4129 free_irq(priv
->pci_dev
->irq
, priv
);
4130 pci_disable_msi(priv
->pci_dev
);
4131 pci_iounmap(pdev
, priv
->hw_base
);
4132 pci_release_regions(pdev
);
4133 pci_disable_device(pdev
);
4134 pci_set_drvdata(pdev
, NULL
);
4136 iwl_uninit_drv(priv
);
4138 if (priv
->cfg
->ops
->lib
->isr_ops
.free
)
4139 priv
->cfg
->ops
->lib
->isr_ops
.free(priv
);
4141 dev_kfree_skb(priv
->beacon_skb
);
4143 ieee80211_free_hw(priv
->hw
);
4147 /*****************************************************************************
4149 * driver and module entry point
4151 *****************************************************************************/
4153 /* Hardware specific file defines the PCI IDs table for that hardware module */
4154 static DEFINE_PCI_DEVICE_TABLE(iwl_hw_card_ids
) = {
4155 {IWL_PCI_DEVICE(0x4232, 0x1201, iwl5100_agn_cfg
)}, /* Mini Card */
4156 {IWL_PCI_DEVICE(0x4232, 0x1301, iwl5100_agn_cfg
)}, /* Half Mini Card */
4157 {IWL_PCI_DEVICE(0x4232, 0x1204, iwl5100_agn_cfg
)}, /* Mini Card */
4158 {IWL_PCI_DEVICE(0x4232, 0x1304, iwl5100_agn_cfg
)}, /* Half Mini Card */
4159 {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bgn_cfg
)}, /* Mini Card */
4160 {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bgn_cfg
)}, /* Half Mini Card */
4161 {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg
)}, /* Mini Card */
4162 {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg
)}, /* Half Mini Card */
4163 {IWL_PCI_DEVICE(0x4232, 0x1221, iwl5100_agn_cfg
)}, /* Mini Card */
4164 {IWL_PCI_DEVICE(0x4232, 0x1321, iwl5100_agn_cfg
)}, /* Half Mini Card */
4165 {IWL_PCI_DEVICE(0x4232, 0x1224, iwl5100_agn_cfg
)}, /* Mini Card */
4166 {IWL_PCI_DEVICE(0x4232, 0x1324, iwl5100_agn_cfg
)}, /* Half Mini Card */
4167 {IWL_PCI_DEVICE(0x4232, 0x1225, iwl5100_bgn_cfg
)}, /* Mini Card */
4168 {IWL_PCI_DEVICE(0x4232, 0x1325, iwl5100_bgn_cfg
)}, /* Half Mini Card */
4169 {IWL_PCI_DEVICE(0x4232, 0x1226, iwl5100_abg_cfg
)}, /* Mini Card */
4170 {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg
)}, /* Half Mini Card */
4171 {IWL_PCI_DEVICE(0x4237, 0x1211, iwl5100_agn_cfg
)}, /* Mini Card */
4172 {IWL_PCI_DEVICE(0x4237, 0x1311, iwl5100_agn_cfg
)}, /* Half Mini Card */
4173 {IWL_PCI_DEVICE(0x4237, 0x1214, iwl5100_agn_cfg
)}, /* Mini Card */
4174 {IWL_PCI_DEVICE(0x4237, 0x1314, iwl5100_agn_cfg
)}, /* Half Mini Card */
4175 {IWL_PCI_DEVICE(0x4237, 0x1215, iwl5100_bgn_cfg
)}, /* Mini Card */
4176 {IWL_PCI_DEVICE(0x4237, 0x1315, iwl5100_bgn_cfg
)}, /* Half Mini Card */
4177 {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg
)}, /* Mini Card */
4178 {IWL_PCI_DEVICE(0x4237, 0x1316, iwl5100_abg_cfg
)}, /* Half Mini Card */
4180 /* 5300 Series WiFi */
4181 {IWL_PCI_DEVICE(0x4235, 0x1021, iwl5300_agn_cfg
)}, /* Mini Card */
4182 {IWL_PCI_DEVICE(0x4235, 0x1121, iwl5300_agn_cfg
)}, /* Half Mini Card */
4183 {IWL_PCI_DEVICE(0x4235, 0x1024, iwl5300_agn_cfg
)}, /* Mini Card */
4184 {IWL_PCI_DEVICE(0x4235, 0x1124, iwl5300_agn_cfg
)}, /* Half Mini Card */
4185 {IWL_PCI_DEVICE(0x4235, 0x1001, iwl5300_agn_cfg
)}, /* Mini Card */
4186 {IWL_PCI_DEVICE(0x4235, 0x1101, iwl5300_agn_cfg
)}, /* Half Mini Card */
4187 {IWL_PCI_DEVICE(0x4235, 0x1004, iwl5300_agn_cfg
)}, /* Mini Card */
4188 {IWL_PCI_DEVICE(0x4235, 0x1104, iwl5300_agn_cfg
)}, /* Half Mini Card */
4189 {IWL_PCI_DEVICE(0x4236, 0x1011, iwl5300_agn_cfg
)}, /* Mini Card */
4190 {IWL_PCI_DEVICE(0x4236, 0x1111, iwl5300_agn_cfg
)}, /* Half Mini Card */
4191 {IWL_PCI_DEVICE(0x4236, 0x1014, iwl5300_agn_cfg
)}, /* Mini Card */
4192 {IWL_PCI_DEVICE(0x4236, 0x1114, iwl5300_agn_cfg
)}, /* Half Mini Card */
4194 /* 5350 Series WiFi/WiMax */
4195 {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg
)}, /* Mini Card */
4196 {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg
)}, /* Mini Card */
4197 {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg
)}, /* Mini Card */
4199 /* 5150 Series Wifi/WiMax */
4200 {IWL_PCI_DEVICE(0x423C, 0x1201, iwl5150_agn_cfg
)}, /* Mini Card */
4201 {IWL_PCI_DEVICE(0x423C, 0x1301, iwl5150_agn_cfg
)}, /* Half Mini Card */
4202 {IWL_PCI_DEVICE(0x423C, 0x1206, iwl5150_abg_cfg
)}, /* Mini Card */
4203 {IWL_PCI_DEVICE(0x423C, 0x1306, iwl5150_abg_cfg
)}, /* Half Mini Card */
4204 {IWL_PCI_DEVICE(0x423C, 0x1221, iwl5150_agn_cfg
)}, /* Mini Card */
4205 {IWL_PCI_DEVICE(0x423C, 0x1321, iwl5150_agn_cfg
)}, /* Half Mini Card */
4207 {IWL_PCI_DEVICE(0x423D, 0x1211, iwl5150_agn_cfg
)}, /* Mini Card */
4208 {IWL_PCI_DEVICE(0x423D, 0x1311, iwl5150_agn_cfg
)}, /* Half Mini Card */
4209 {IWL_PCI_DEVICE(0x423D, 0x1216, iwl5150_abg_cfg
)}, /* Mini Card */
4210 {IWL_PCI_DEVICE(0x423D, 0x1316, iwl5150_abg_cfg
)}, /* Half Mini Card */
4213 {IWL_PCI_DEVICE(0x422B, 0x1101, iwl6000_3agn_cfg
)},
4214 {IWL_PCI_DEVICE(0x422B, 0x1121, iwl6000_3agn_cfg
)},
4215 {IWL_PCI_DEVICE(0x422C, 0x1301, iwl6000i_2agn_cfg
)},
4216 {IWL_PCI_DEVICE(0x422C, 0x1306, iwl6000i_2abg_cfg
)},
4217 {IWL_PCI_DEVICE(0x422C, 0x1307, iwl6000i_2bg_cfg
)},
4218 {IWL_PCI_DEVICE(0x422C, 0x1321, iwl6000i_2agn_cfg
)},
4219 {IWL_PCI_DEVICE(0x422C, 0x1326, iwl6000i_2abg_cfg
)},
4220 {IWL_PCI_DEVICE(0x4238, 0x1111, iwl6000_3agn_cfg
)},
4221 {IWL_PCI_DEVICE(0x4239, 0x1311, iwl6000i_2agn_cfg
)},
4222 {IWL_PCI_DEVICE(0x4239, 0x1316, iwl6000i_2abg_cfg
)},
4225 {IWL_PCI_DEVICE(0x0082, 0x1301, iwl6005_2agn_cfg
)},
4226 {IWL_PCI_DEVICE(0x0082, 0x1306, iwl6005_2abg_cfg
)},
4227 {IWL_PCI_DEVICE(0x0082, 0x1307, iwl6005_2bg_cfg
)},
4228 {IWL_PCI_DEVICE(0x0082, 0x1321, iwl6005_2agn_cfg
)},
4229 {IWL_PCI_DEVICE(0x0082, 0x1326, iwl6005_2abg_cfg
)},
4230 {IWL_PCI_DEVICE(0x0085, 0x1311, iwl6005_2agn_cfg
)},
4231 {IWL_PCI_DEVICE(0x0085, 0x1316, iwl6005_2abg_cfg
)},
4234 {IWL_PCI_DEVICE(0x008A, 0x5305, iwl1030_bgn_cfg
)},
4235 {IWL_PCI_DEVICE(0x008A, 0x5307, iwl1030_bg_cfg
)},
4236 {IWL_PCI_DEVICE(0x008A, 0x5325, iwl1030_bgn_cfg
)},
4237 {IWL_PCI_DEVICE(0x008A, 0x5327, iwl1030_bg_cfg
)},
4238 {IWL_PCI_DEVICE(0x008B, 0x5315, iwl1030_bgn_cfg
)},
4239 {IWL_PCI_DEVICE(0x008B, 0x5317, iwl1030_bg_cfg
)},
4240 {IWL_PCI_DEVICE(0x0090, 0x5211, iwl6030_2agn_cfg
)},
4241 {IWL_PCI_DEVICE(0x0090, 0x5215, iwl6030_2bgn_cfg
)},
4242 {IWL_PCI_DEVICE(0x0090, 0x5216, iwl6030_2abg_cfg
)},
4243 {IWL_PCI_DEVICE(0x0091, 0x5201, iwl6030_2agn_cfg
)},
4244 {IWL_PCI_DEVICE(0x0091, 0x5205, iwl6030_2bgn_cfg
)},
4245 {IWL_PCI_DEVICE(0x0091, 0x5206, iwl6030_2abg_cfg
)},
4246 {IWL_PCI_DEVICE(0x0091, 0x5207, iwl6030_2bg_cfg
)},
4247 {IWL_PCI_DEVICE(0x0091, 0x5221, iwl6030_2agn_cfg
)},
4248 {IWL_PCI_DEVICE(0x0091, 0x5225, iwl6030_2bgn_cfg
)},
4249 {IWL_PCI_DEVICE(0x0091, 0x5226, iwl6030_2abg_cfg
)},
4251 /* 6x50 WiFi/WiMax Series */
4252 {IWL_PCI_DEVICE(0x0087, 0x1301, iwl6050_2agn_cfg
)},
4253 {IWL_PCI_DEVICE(0x0087, 0x1306, iwl6050_2abg_cfg
)},
4254 {IWL_PCI_DEVICE(0x0087, 0x1321, iwl6050_2agn_cfg
)},
4255 {IWL_PCI_DEVICE(0x0087, 0x1326, iwl6050_2abg_cfg
)},
4256 {IWL_PCI_DEVICE(0x0089, 0x1311, iwl6050_2agn_cfg
)},
4257 {IWL_PCI_DEVICE(0x0089, 0x1316, iwl6050_2abg_cfg
)},
4259 /* 6150 WiFi/WiMax Series */
4260 {IWL_PCI_DEVICE(0x0885, 0x1305, iwl6150_bgn_cfg
)},
4261 {IWL_PCI_DEVICE(0x0885, 0x1306, iwl6150_bgn_cfg
)},
4262 {IWL_PCI_DEVICE(0x0885, 0x1325, iwl6150_bgn_cfg
)},
4263 {IWL_PCI_DEVICE(0x0885, 0x1326, iwl6150_bgn_cfg
)},
4264 {IWL_PCI_DEVICE(0x0886, 0x1315, iwl6150_bgn_cfg
)},
4265 {IWL_PCI_DEVICE(0x0886, 0x1316, iwl6150_bgn_cfg
)},
4267 /* 1000 Series WiFi */
4268 {IWL_PCI_DEVICE(0x0083, 0x1205, iwl1000_bgn_cfg
)},
4269 {IWL_PCI_DEVICE(0x0083, 0x1305, iwl1000_bgn_cfg
)},
4270 {IWL_PCI_DEVICE(0x0083, 0x1225, iwl1000_bgn_cfg
)},
4271 {IWL_PCI_DEVICE(0x0083, 0x1325, iwl1000_bgn_cfg
)},
4272 {IWL_PCI_DEVICE(0x0084, 0x1215, iwl1000_bgn_cfg
)},
4273 {IWL_PCI_DEVICE(0x0084, 0x1315, iwl1000_bgn_cfg
)},
4274 {IWL_PCI_DEVICE(0x0083, 0x1206, iwl1000_bg_cfg
)},
4275 {IWL_PCI_DEVICE(0x0083, 0x1306, iwl1000_bg_cfg
)},
4276 {IWL_PCI_DEVICE(0x0083, 0x1226, iwl1000_bg_cfg
)},
4277 {IWL_PCI_DEVICE(0x0083, 0x1326, iwl1000_bg_cfg
)},
4278 {IWL_PCI_DEVICE(0x0084, 0x1216, iwl1000_bg_cfg
)},
4279 {IWL_PCI_DEVICE(0x0084, 0x1316, iwl1000_bg_cfg
)},
4281 /* 100 Series WiFi */
4282 {IWL_PCI_DEVICE(0x08AE, 0x1005, iwl100_bgn_cfg
)},
4283 {IWL_PCI_DEVICE(0x08AE, 0x1007, iwl100_bg_cfg
)},
4284 {IWL_PCI_DEVICE(0x08AF, 0x1015, iwl100_bgn_cfg
)},
4285 {IWL_PCI_DEVICE(0x08AF, 0x1017, iwl100_bg_cfg
)},
4286 {IWL_PCI_DEVICE(0x08AE, 0x1025, iwl100_bgn_cfg
)},
4287 {IWL_PCI_DEVICE(0x08AE, 0x1027, iwl100_bg_cfg
)},
4289 /* 130 Series WiFi */
4290 {IWL_PCI_DEVICE(0x0896, 0x5005, iwl130_bgn_cfg
)},
4291 {IWL_PCI_DEVICE(0x0896, 0x5007, iwl130_bg_cfg
)},
4292 {IWL_PCI_DEVICE(0x0897, 0x5015, iwl130_bgn_cfg
)},
4293 {IWL_PCI_DEVICE(0x0897, 0x5017, iwl130_bg_cfg
)},
4294 {IWL_PCI_DEVICE(0x0896, 0x5025, iwl130_bgn_cfg
)},
4295 {IWL_PCI_DEVICE(0x0896, 0x5027, iwl130_bg_cfg
)},
4298 {IWL_PCI_DEVICE(0x0890, 0x4022, iwl2000_2bgn_cfg
)},
4299 {IWL_PCI_DEVICE(0x0891, 0x4222, iwl2000_2bgn_cfg
)},
4300 {IWL_PCI_DEVICE(0x0890, 0x4422, iwl2000_2bgn_cfg
)},
4301 {IWL_PCI_DEVICE(0x0890, 0x4026, iwl2000_2bg_cfg
)},
4302 {IWL_PCI_DEVICE(0x0891, 0x4226, iwl2000_2bg_cfg
)},
4303 {IWL_PCI_DEVICE(0x0890, 0x4426, iwl2000_2bg_cfg
)},
4306 {IWL_PCI_DEVICE(0x0887, 0x4062, iwl2030_2bgn_cfg
)},
4307 {IWL_PCI_DEVICE(0x0888, 0x4262, iwl2030_2bgn_cfg
)},
4308 {IWL_PCI_DEVICE(0x0887, 0x4462, iwl2030_2bgn_cfg
)},
4309 {IWL_PCI_DEVICE(0x0887, 0x4066, iwl2030_2bg_cfg
)},
4310 {IWL_PCI_DEVICE(0x0888, 0x4266, iwl2030_2bg_cfg
)},
4311 {IWL_PCI_DEVICE(0x0887, 0x4466, iwl2030_2bg_cfg
)},
4314 {IWL_PCI_DEVICE(0x088E, 0x4060, iwl6035_2agn_cfg
)},
4315 {IWL_PCI_DEVICE(0x088F, 0x4260, iwl6035_2agn_cfg
)},
4316 {IWL_PCI_DEVICE(0x088E, 0x4460, iwl6035_2agn_cfg
)},
4317 {IWL_PCI_DEVICE(0x088E, 0x4064, iwl6035_2abg_cfg
)},
4318 {IWL_PCI_DEVICE(0x088F, 0x4264, iwl6035_2abg_cfg
)},
4319 {IWL_PCI_DEVICE(0x088E, 0x4464, iwl6035_2abg_cfg
)},
4320 {IWL_PCI_DEVICE(0x088E, 0x4066, iwl6035_2bg_cfg
)},
4321 {IWL_PCI_DEVICE(0x088F, 0x4266, iwl6035_2bg_cfg
)},
4322 {IWL_PCI_DEVICE(0x088E, 0x4466, iwl6035_2bg_cfg
)},
4325 {IWL_PCI_DEVICE(0x0894, 0x0022, iwl200_bgn_cfg
)},
4326 {IWL_PCI_DEVICE(0x0895, 0x0222, iwl200_bgn_cfg
)},
4327 {IWL_PCI_DEVICE(0x0894, 0x0422, iwl200_bgn_cfg
)},
4328 {IWL_PCI_DEVICE(0x0894, 0x0026, iwl200_bg_cfg
)},
4329 {IWL_PCI_DEVICE(0x0895, 0x0226, iwl200_bg_cfg
)},
4330 {IWL_PCI_DEVICE(0x0894, 0x0426, iwl200_bg_cfg
)},
4333 {IWL_PCI_DEVICE(0x0892, 0x0062, iwl230_bgn_cfg
)},
4334 {IWL_PCI_DEVICE(0x0893, 0x0262, iwl230_bgn_cfg
)},
4335 {IWL_PCI_DEVICE(0x0892, 0x0462, iwl230_bgn_cfg
)},
4336 {IWL_PCI_DEVICE(0x0892, 0x0066, iwl230_bg_cfg
)},
4337 {IWL_PCI_DEVICE(0x0893, 0x0266, iwl230_bg_cfg
)},
4338 {IWL_PCI_DEVICE(0x0892, 0x0466, iwl230_bg_cfg
)},
4342 MODULE_DEVICE_TABLE(pci
, iwl_hw_card_ids
);
4344 static struct pci_driver iwl_driver
= {
4346 .id_table
= iwl_hw_card_ids
,
4347 .probe
= iwl_pci_probe
,
4348 .remove
= __devexit_p(iwl_pci_remove
),
4349 .driver
.pm
= IWL_PM_OPS
,
4352 static int __init
iwl_init(void)
4356 pr_info(DRV_DESCRIPTION
", " DRV_VERSION
"\n");
4357 pr_info(DRV_COPYRIGHT
"\n");
4359 ret
= iwlagn_rate_control_register();
4361 pr_err("Unable to register rate control algorithm: %d\n", ret
);
4365 ret
= pci_register_driver(&iwl_driver
);
4367 pr_err("Unable to initialize PCI module\n");
4368 goto error_register
;
4374 iwlagn_rate_control_unregister();
4378 static void __exit
iwl_exit(void)
4380 pci_unregister_driver(&iwl_driver
);
4381 iwlagn_rate_control_unregister();
4384 module_exit(iwl_exit
);
4385 module_init(iwl_init
);
4387 #ifdef CONFIG_IWLWIFI_DEBUG
4388 module_param_named(debug
, iwl_debug_level
, uint
, S_IRUGO
| S_IWUSR
);
4389 MODULE_PARM_DESC(debug
, "debug output mask");
4392 module_param_named(swcrypto
, iwlagn_mod_params
.sw_crypto
, int, S_IRUGO
);
4393 MODULE_PARM_DESC(swcrypto
, "using crypto in software (default 0 [hardware])");
4394 module_param_named(queues_num
, iwlagn_mod_params
.num_of_queues
, int, S_IRUGO
);
4395 MODULE_PARM_DESC(queues_num
, "number of hw queues.");
4396 module_param_named(11n_disable
, iwlagn_mod_params
.disable_11n
, int, S_IRUGO
);
4397 MODULE_PARM_DESC(11n_disable
, "disable 11n functionality");
4398 module_param_named(amsdu_size_8K
, iwlagn_mod_params
.amsdu_size_8K
,
4400 MODULE_PARM_DESC(amsdu_size_8K
, "enable 8K amsdu size");
4401 module_param_named(fw_restart
, iwlagn_mod_params
.restart_fw
, int, S_IRUGO
);
4402 MODULE_PARM_DESC(fw_restart
, "restart firmware in case of error");
4404 module_param_named(ucode_alternative
, iwlagn_wanted_ucode_alternative
, int,
4406 MODULE_PARM_DESC(ucode_alternative
,
4407 "specify ucode alternative to use from ucode file");
4409 module_param_named(antenna_coupling
, iwlagn_ant_coupling
, int, S_IRUGO
);
4410 MODULE_PARM_DESC(antenna_coupling
,
4411 "specify antenna coupling in dB (defualt: 0 dB)");
4413 module_param_named(bt_ch_inhibition
, iwlagn_bt_ch_announce
, bool, S_IRUGO
);
4414 MODULE_PARM_DESC(bt_ch_inhibition
,
4415 "Disable BT channel inhibition (default: enable)");
4417 module_param_named(plcp_check
, iwlagn_mod_params
.plcp_check
, bool, S_IRUGO
);
4418 MODULE_PARM_DESC(plcp_check
, "Check plcp health (default: 1 [enabled])");
4420 module_param_named(ack_check
, iwlagn_mod_params
.ack_check
, bool, S_IRUGO
);
4421 MODULE_PARM_DESC(ack_check
, "Check ack health (default: 0 [disabled])");