arch/x86/kernel/cpu/amd.c

   1 #include <linux/init.h>
   2 #include <linux/bitops.h>
   3 #include <linux/mm.h>
   4
   5 #include <linux/io.h>
   6 #include <asm/processor.h>
   7 #include <asm/apic.h>
   8 #include <asm/cpu.h>
   9 #include <asm/pci-direct.h>
  10
  11 #ifdef CONFIG_X86_64
  12 # include <asm/numa_64.h>
  13 # include <asm/mmconfig.h>
  14 # include <asm/cacheflush.h>
  15 #endif
  16
  17 #include "cpu.h"
  18
  19 #ifdef CONFIG_X86_32
  20 /*
  21  *      B step AMD K6 before B 9730xxxx have hardware bugs that can cause
  22  *      misexecution of code under Linux. Owners of such processors should
  23  *      contact AMD for precise details and a CPU swap.
  24  *
  25  *      See     http://www.multimania.com/poulot/k6bug.html
  26  *              http://www.amd.com/K6/k6docs/revgd.html
  27  *
  28  *      The following test is erm.. interesting. AMD neglected to up
  29  *      the chip setting when fixing the bug but they also tweaked some
  30  *      performance at the same time..
  31  */
  32
  33 extern void vide(void);
  34 __asm__(".align 4\nvide: ret");
  35
  36 static void __cpuinit init_amd_k5(struct cpuinfo_x86 *c)
  37 {
  38 /*
  39  * General Systems BIOSen alias the cpu frequency registers
  40  * of the Elan at 0x000df000. Unfortuantly, one of the Linux
  41  * drivers subsequently pokes it, and changes the CPU speed.
  42  * Workaround : Remove the unneeded alias.
  43  */
  44 #define CBAR            (0xfffc) /* Configuration Base Address  (32-bit) */
  45 #define CBAR_ENB        (0x80000000)
  46 #define CBAR_KEY        (0X000000CB)
  47         if (c->x86_model == 9 || c->x86_model == 10) {
  48                 if (inl(CBAR) & CBAR_ENB)
  49                         outl(0 | CBAR_KEY, CBAR);
  50         }
  51 }
  52
  53
  54 static void __cpuinit init_amd_k6(struct cpuinfo_x86 *c)
  55 {
  56         u32 l, h;
  57         int mbytes = num_physpages >> (20-PAGE_SHIFT);
  58
  59         if (c->x86_model < 6) {
  60                 /* Based on AMD doc 20734R - June 2000 */
  61                 if (c->x86_model == 0) {
  62                         clear_cpu_cap(c, X86_FEATURE_APIC);
  63                         set_cpu_cap(c, X86_FEATURE_PGE);
  64                 }
  65                 return;
  66         }
  67
  68         if (c->x86_model == 6 && c->x86_mask == 1) {
  69                 const int K6_BUG_LOOP = 1000000;
  70                 int n;
  71                 void (*f_vide)(void);
  72                 unsigned long d, d2;
  73
  74                 printk(KERN_INFO "AMD K6 stepping B detected - ");
  75
  76                 /*
  77                  * It looks like AMD fixed the 2.6.2 bug and improved indirect
  78                  * calls at the same time.
  79                  */
  80
  81                 n = K6_BUG_LOOP;
  82                 f_vide = vide;
  83                 rdtscl(d);
  84                 while (n--)
  85                         f_vide();
  86                 rdtscl(d2);
  87                 d = d2-d;
  88
  89                 if (d > 20*K6_BUG_LOOP)
  90                         printk(KERN_CONT
  91                                 "system stability may be impaired when more than 32 MB are used.\n");
  92                 else
  93                         printk(KERN_CONT "probably OK (after B9730xxxx).\n");
  94                 printk(KERN_INFO "Please see http://membres.lycos.fr/poulot/k6bug.html\n");
  95         }
  96
  97         /* K6 with old style WHCR */
  98         if (c->x86_model < 8 ||
  99            (c->x86_model == 8 && c->x86_mask < 8)) {
 100                 /* We can only write allocate on the low 508Mb */
 101                 if (mbytes > 508)
 102                         mbytes = 508;
 103
 104                 rdmsr(MSR_K6_WHCR, l, h);
 105                 if ((l&0x0000FFFF) == 0) {
 106                         unsigned long flags;
 107                         l = (1<<0)|((mbytes/4)<<1);
 108                         local_irq_save(flags);
 109                         wbinvd();
 110                         wrmsr(MSR_K6_WHCR, l, h);
 111                         local_irq_restore(flags);
 112                         printk(KERN_INFO "Enabling old style K6 write allocation for %d Mb\n",
 113                                 mbytes);
 114                 }
 115                 return;
 116         }
 117
 118         if ((c->x86_model == 8 && c->x86_mask > 7) ||
 119              c->x86_model == 9 || c->x86_model == 13) {
 120                 /* The more serious chips .. */
 121
 122                 if (mbytes > 4092)
 123                         mbytes = 4092;
 124
 125                 rdmsr(MSR_K6_WHCR, l, h);
 126                 if ((l&0xFFFF0000) == 0) {
 127                         unsigned long flags;
 128                         l = ((mbytes>>2)<<22)|(1<<16);
 129                         local_irq_save(flags);
 130                         wbinvd();
 131                         wrmsr(MSR_K6_WHCR, l, h);
 132                         local_irq_restore(flags);
 133                         printk(KERN_INFO "Enabling new style K6 write allocation for %d Mb\n",
 134                                 mbytes);
 135                 }
 136
 137                 return;
 138         }
 139
 140         if (c->x86_model == 10) {
 141                 /* AMD Geode LX is model 10 */
 142                 /* placeholder for any needed mods */
 143                 return;
 144         }
 145 }
 146
 147 static void __cpuinit amd_k7_smp_check(struct cpuinfo_x86 *c)
 148 {
 149 #ifdef CONFIG_SMP
 150         /* calling is from identify_secondary_cpu() ? */
 151         if (c->cpu_index == boot_cpu_id)
 152                 return;
 153
 154         /*
 155          * Certain Athlons might work (for various values of 'work') in SMP
 156          * but they are not certified as MP capable.
 157          */
 158         /* Athlon 660/661 is valid. */
 159         if ((c->x86_model == 6) && ((c->x86_mask == 0) ||
 160             (c->x86_mask == 1)))
 161                 goto valid_k7;
 162
 163         /* Duron 670 is valid */
 164         if ((c->x86_model == 7) && (c->x86_mask == 0))
 165                 goto valid_k7;
 166
 167         /*
 168          * Athlon 662, Duron 671, and Athlon >model 7 have capability
 169          * bit. It's worth noting that the A5 stepping (662) of some
 170          * Athlon XP's have the MP bit set.
 171          * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for
 172          * more.
 173          */
 174         if (((c->x86_model == 6) && (c->x86_mask >= 2)) ||
 175             ((c->x86_model == 7) && (c->x86_mask >= 1)) ||
 176              (c->x86_model > 7))
 177                 if (cpu_has_mp)
 178                         goto valid_k7;
 179
 180         /* If we get here, not a certified SMP capable AMD system. */
 181
 182         /*
 183          * Don't taint if we are running SMP kernel on a single non-MP
 184          * approved Athlon
 185          */
 186         WARN_ONCE(1, "WARNING: This combination of AMD"
 187                 " processors is not suitable for SMP.\n");
 188         if (!test_taint(TAINT_UNSAFE_SMP))
 189                 add_taint(TAINT_UNSAFE_SMP);
 190
 191 valid_k7:
 192         ;
 193 #endif
 194 }
 195
 196 static void __cpuinit init_amd_k7(struct cpuinfo_x86 *c)
 197 {
 198         u32 l, h;
 199
 200         /*
 201          * Bit 15 of Athlon specific MSR 15, needs to be 0
 202          * to enable SSE on Palomino/Morgan/Barton CPU's.
 203          * If the BIOS didn't enable it already, enable it here.
 204          */
 205         if (c->x86_model >= 6 && c->x86_model <= 10) {
 206                 if (!cpu_has(c, X86_FEATURE_XMM)) {
 207                         printk(KERN_INFO "Enabling disabled K7/SSE Support.\n");
 208                         rdmsr(MSR_K7_HWCR, l, h);
 209                         l &= ~0x00008000;
 210                         wrmsr(MSR_K7_HWCR, l, h);
 211                         set_cpu_cap(c, X86_FEATURE_XMM);
 212                 }
 213         }
 214
 215         /*
 216          * It's been determined by AMD that Athlons since model 8 stepping 1
 217          * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx
 218          * As per AMD technical note 27212 0.2
 219          */
 220         if ((c->x86_model == 8 && c->x86_mask >= 1) || (c->x86_model > 8)) {
 221                 rdmsr(MSR_K7_CLK_CTL, l, h);
 222                 if ((l & 0xfff00000) != 0x20000000) {
 223                         printk(KERN_INFO
 224                             "CPU: CLK_CTL MSR was %x. Reprogramming to %x\n",
 225                                         l, ((l & 0x000fffff)|0x20000000));
 226                         wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h);
 227                 }
 228         }
 229
 230         set_cpu_cap(c, X86_FEATURE_K7);
 231
 232         amd_k7_smp_check(c);
 233 }
 234 #endif
 235
 236 #if defined(CONFIG_NUMA) && defined(CONFIG_X86_64)
 237 static int __cpuinit nearby_node(int apicid)
 238 {
 239         int i, node;
 240
 241         for (i = apicid - 1; i >= 0; i--) {
 242                 node = apicid_to_node[i];
 243                 if (node != NUMA_NO_NODE && node_online(node))
 244                         return node;
 245         }
 246         for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) {
 247                 node = apicid_to_node[i];
 248                 if (node != NUMA_NO_NODE && node_online(node))
 249                         return node;
 250         }
 251         return first_node(node_online_map); /* Shouldn't happen */
 252 }
 253 #endif
 254
 255 /*
 256  * Fixup core topology information for AMD multi-node processors.
 257  * Assumption: Number of cores in each internal node is the same.
 258  */
 259 #ifdef CONFIG_X86_HT
 260 static void __cpuinit amd_fixup_dcm(struct cpuinfo_x86 *c)
 261 {
 262         unsigned long long value;
 263         u32 nodes, cores_per_node;
 264         int cpu = smp_processor_id();
 265
 266         if (!cpu_has(c, X86_FEATURE_NODEID_MSR))
 267                 return;
 268
 269         /* fixup topology information only once for a core */
 270         if (cpu_has(c, X86_FEATURE_AMD_DCM))
 271                 return;
 272
 273         rdmsrl(MSR_FAM10H_NODE_ID, value);
 274
 275         nodes = ((value >> 3) & 7) + 1;
 276         if (nodes == 1)
 277                 return;
 278
 279         set_cpu_cap(c, X86_FEATURE_AMD_DCM);
 280         cores_per_node = c->x86_max_cores / nodes;
 281
 282         /* store NodeID, use llc_shared_map to store sibling info */
 283         per_cpu(cpu_llc_id, cpu) = value & 7;
 284
 285         /* fixup core id to be in range from 0 to (cores_per_node - 1) */
 286         c->cpu_core_id = c->cpu_core_id % cores_per_node;
 287 }
 288 #endif
 289
 290 /*
 291  * On a AMD dual core setup the lower bits of the APIC id distingush the cores.
 292  * Assumes number of cores is a power of two.
 293  */
 294 static void __cpuinit amd_detect_cmp(struct cpuinfo_x86 *c)
 295 {
 296 #ifdef CONFIG_X86_HT
 297         unsigned bits;
 298         int cpu = smp_processor_id();
 299
 300         bits = c->x86_coreid_bits;
 301         /* Low order bits define the core id (index of core in socket) */
 302         c->cpu_core_id = c->initial_apicid & ((1 << bits)-1);
 303         /* Convert the initial APIC ID into the socket ID */
 304         c->phys_proc_id = c->initial_apicid >> bits;
 305         /* use socket ID also for last level cache */
 306         per_cpu(cpu_llc_id, cpu) = c->phys_proc_id;
 307         /* fixup topology information on multi-node processors */
 308         amd_fixup_dcm(c);
 309 #endif
 310 }
 311
 312 int amd_get_nb_id(int cpu)
 313 {
 314         int id = 0;
 315 #ifdef CONFIG_SMP
 316         id = per_cpu(cpu_llc_id, cpu);
 317 #endif
 318         return id;
 319 }
 320 EXPORT_SYMBOL_GPL(amd_get_nb_id);
 321
 322 static void __cpuinit srat_detect_node(struct cpuinfo_x86 *c)
 323 {
 324 #if defined(CONFIG_NUMA) && defined(CONFIG_X86_64)
 325         int cpu = smp_processor_id();
 326         int node;
 327         unsigned apicid = c->apicid;
 328
 329         node = per_cpu(cpu_llc_id, cpu);
 330
 331         if (apicid_to_node[apicid] != NUMA_NO_NODE)
 332                 node = apicid_to_node[apicid];
 333         if (!node_online(node)) {
 334                 /* Two possibilities here:
 335                    - The CPU is missing memory and no node was created.
 336                    In that case try picking one from a nearby CPU
 337                    - The APIC IDs differ from the HyperTransport node IDs
 338                    which the K8 northbridge parsing fills in.
 339                    Assume they are all increased by a constant offset,
 340                    but in the same order as the HT nodeids.
 341                    If that doesn't result in a usable node fall back to the
 342                    path for the previous case.  */
 343
 344                 int ht_nodeid = c->initial_apicid;
 345
 346                 if (ht_nodeid >= 0 &&
 347                     apicid_to_node[ht_nodeid] != NUMA_NO_NODE)
 348                         node = apicid_to_node[ht_nodeid];
 349                 /* Pick a nearby node */
 350                 if (!node_online(node))
 351                         node = nearby_node(apicid);
 352         }
 353         numa_set_node(cpu, node);
 354 #endif
 355 }
 356
 357 static void __cpuinit early_init_amd_mc(struct cpuinfo_x86 *c)
 358 {
 359 #ifdef CONFIG_X86_HT
 360         unsigned bits, ecx;
 361
 362         /* Multi core CPU? */
 363         if (c->extended_cpuid_level < 0x80000008)
 364                 return;
 365
 366         ecx = cpuid_ecx(0x80000008);
 367
 368         c->x86_max_cores = (ecx & 0xff) + 1;
 369
 370         /* CPU telling us the core id bits shift? */
 371         bits = (ecx >> 12) & 0xF;
 372
 373         /* Otherwise recompute */
 374         if (bits == 0) {
 375                 while ((1 << bits) < c->x86_max_cores)
 376                         bits++;
 377         }
 378
 379         c->x86_coreid_bits = bits;
 380 #endif
 381 }
 382
 383 static void __cpuinit early_init_amd(struct cpuinfo_x86 *c)
 384 {
 385         early_init_amd_mc(c);
 386
 387         /*
 388          * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
 389          * with P/T states and does not stop in deep C-states
 390          */
 391         if (c->x86_power & (1 << 8)) {
 392                 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
 393                 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
 394         }
 395
 396 #ifdef CONFIG_X86_64
 397         set_cpu_cap(c, X86_FEATURE_SYSCALL32);
 398 #else
 399         /*  Set MTRR capability flag if appropriate */
 400         if (c->x86 == 5)
 401                 if (c->x86_model == 13 || c->x86_model == 9 ||
 402                     (c->x86_model == 8 && c->x86_mask >= 8))
 403                         set_cpu_cap(c, X86_FEATURE_K6_MTRR);
 404 #endif
 405 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_PCI)
 406         /* check CPU config space for extended APIC ID */
 407         if (cpu_has_apic && c->x86 >= 0xf) {
 408                 unsigned int val;
 409                 val = read_pci_config(0, 24, 0, 0x68);
 410                 if ((val & ((1 << 17) | (1 << 18))) == ((1 << 17) | (1 << 18)))
 411                         set_cpu_cap(c, X86_FEATURE_EXTD_APICID);
 412         }
 413 #endif
 414 }
 415
 416 static void __cpuinit init_amd(struct cpuinfo_x86 *c)
 417 {
 418 #ifdef CONFIG_SMP
 419         unsigned long long value;
 420
 421         /*
 422          * Disable TLB flush filter by setting HWCR.FFDIS on K8
 423          * bit 6 of msr C001_0015
 424          *
 425          * Errata 63 for SH-B3 steppings
 426          * Errata 122 for all steppings (F+ have it disabled by default)
 427          */
 428         if (c->x86 == 0xf) {
 429                 rdmsrl(MSR_K7_HWCR, value);
 430                 value |= 1 << 6;
 431                 wrmsrl(MSR_K7_HWCR, value);
 432         }
 433 #endif
 434
 435         early_init_amd(c);
 436
 437         /*
 438          * Bit 31 in normal CPUID used for nonstandard 3DNow ID;
 439          * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway
 440          */
 441         clear_cpu_cap(c, 0*32+31);
 442
 443 #ifdef CONFIG_X86_64
 444         /* On C+ stepping K8 rep microcode works well for copy/memset */
 445         if (c->x86 == 0xf) {
 446                 u32 level;
 447
 448                 level = cpuid_eax(1);
 449                 if ((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58)
 450                         set_cpu_cap(c, X86_FEATURE_REP_GOOD);
 451
 452                 /*
 453                  * Some BIOSes incorrectly force this feature, but only K8
 454                  * revision D (model = 0x14) and later actually support it.
 455                  * (AMD Erratum #110, docId: 25759).
 456                  */
 457                 if (c->x86_model < 0x14 && cpu_has(c, X86_FEATURE_LAHF_LM)) {
 458                         u64 val;
 459
 460                         clear_cpu_cap(c, X86_FEATURE_LAHF_LM);
 461                         if (!rdmsrl_amd_safe(0xc001100d, &val)) {
 462                                 val &= ~(1ULL << 32);
 463                                 wrmsrl_amd_safe(0xc001100d, val);
 464                         }
 465                 }
 466
 467         }
 468         if (c->x86 == 0x10 || c->x86 == 0x11)
 469                 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
 470
 471         /* get apicid instead of initial apic id from cpuid */
 472         c->apicid = hard_smp_processor_id();
 473 #else
 474
 475         /*
 476          *      FIXME: We should handle the K5 here. Set up the write
 477          *      range and also turn on MSR 83 bits 4 and 31 (write alloc,
 478          *      no bus pipeline)
 479          */
 480
 481         switch (c->x86) {
 482         case 4:
 483                 init_amd_k5(c);
 484                 break;
 485         case 5:
 486                 init_amd_k6(c);
 487                 break;
 488         case 6: /* An Athlon/Duron */
 489                 init_amd_k7(c);
 490                 break;
 491         }
 492
 493         /* K6s reports MCEs but don't actually have all the MSRs */
 494         if (c->x86 < 6)
 495                 clear_cpu_cap(c, X86_FEATURE_MCE);
 496 #endif
 497
 498         /* Enable workaround for FXSAVE leak */
 499         if (c->x86 >= 6)
 500                 set_cpu_cap(c, X86_FEATURE_FXSAVE_LEAK);
 501
 502         if (!c->x86_model_id[0]) {
 503                 switch (c->x86) {
 504                 case 0xf:
 505                         /* Should distinguish Models here, but this is only
 506                            a fallback anyways. */
 507                         strcpy(c->x86_model_id, "Hammer");
 508                         break;
 509                 }
 510         }
 511
 512         cpu_detect_cache_sizes(c);
 513
 514         /* Multi core CPU? */
 515         if (c->extended_cpuid_level >= 0x80000008) {
 516                 amd_detect_cmp(c);
 517                 srat_detect_node(c);
 518         }
 519
 520 #ifdef CONFIG_X86_32
 521         detect_ht(c);
 522 #endif
 523
 524         if (c->extended_cpuid_level >= 0x80000006) {
 525                 if ((c->x86 >= 0x0f) && (cpuid_edx(0x80000006) & 0xf000))
 526                         num_cache_leaves = 4;
 527                 else
 528                         num_cache_leaves = 3;
 529         }
 530
 531         if (c->x86 >= 0xf && c->x86 <= 0x11)
 532                 set_cpu_cap(c, X86_FEATURE_K8);
 533
 534         if (cpu_has_xmm2) {
 535                 /* MFENCE stops RDTSC speculation */
 536                 set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC);
 537         }
 538
 539 #ifdef CONFIG_X86_64
 540         if (c->x86 == 0x10) {
 541                 /* do this for boot cpu */
 542                 if (c == &boot_cpu_data)
 543                         check_enable_amd_mmconf_dmi();
 544
 545                 fam10h_check_enable_mmcfg();
 546         }
 547
 548         if (c == &boot_cpu_data && c->x86 >= 0xf && c->x86 <= 0x11) {
 549                 unsigned long long tseg;
 550
 551                 /*
 552                  * Split up direct mapping around the TSEG SMM area.
 553                  * Don't do it for gbpages because there seems very little
 554                  * benefit in doing so.
 555                  */
 556                 if (!rdmsrl_safe(MSR_K8_TSEG_ADDR, &tseg)) {
 557                         printk(KERN_DEBUG "tseg: %010llx\n", tseg);
 558                         if ((tseg>>PMD_SHIFT) <
 559                                 (max_low_pfn_mapped>>(PMD_SHIFT-PAGE_SHIFT)) ||
 560                                 ((tseg>>PMD_SHIFT) <
 561                                 (max_pfn_mapped>>(PMD_SHIFT-PAGE_SHIFT)) &&
 562                                 (tseg>>PMD_SHIFT) >= (1ULL<<(32 - PMD_SHIFT))))
 563                                 set_memory_4k((unsigned long)__va(tseg), 1);
 564                 }
 565         }
 566 #endif
 567
 568         /* As a rule processors have APIC timer running in deep C states */
 569         if (c->x86 >= 0xf && !cpu_has_amd_erratum(amd_erratum_400))
 570                 set_cpu_cap(c, X86_FEATURE_ARAT);
 571
 572         /*
 573          * Disable GART TLB Walk Errors on Fam10h. We do this here
 574          * because this is always needed when GART is enabled, even in a
 575          * kernel which has no MCE support built in.
 576          */
 577         if (c->x86 == 0x10) {
 578                 /*
 579                  * BIOS should disable GartTlbWlk Errors themself. If
 580                  * it doesn't do it here as suggested by the BKDG.
 581                  *
 582                  * Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=33012
 583                  */
 584                 u64 mask;
 585
 586                 rdmsrl(MSR_AMD64_MCx_MASK(4), mask);
 587                 mask |= (1 << 10);
 588                 wrmsrl(MSR_AMD64_MCx_MASK(4), mask);
 589         }
 590 }
 591
 592 #ifdef CONFIG_X86_32
 593 static unsigned int __cpuinit amd_size_cache(struct cpuinfo_x86 *c,
 594                                                         unsigned int size)
 595 {
 596         /* AMD errata T13 (order #21922) */
 597         if ((c->x86 == 6)) {
 598                 /* Duron Rev A0 */
 599                 if (c->x86_model == 3 && c->x86_mask == 0)
 600                         size = 64;
 601                 /* Tbird rev A1/A2 */
 602                 if (c->x86_model == 4 &&
 603                         (c->x86_mask == 0 || c->x86_mask == 1))
 604                         size = 256;
 605         }
 606         return size;
 607 }
 608 #endif
 609
 610 static const struct cpu_dev __cpuinitconst amd_cpu_dev = {
 611         .c_vendor       = "AMD",
 612         .c_ident        = { "AuthenticAMD" },
 613 #ifdef CONFIG_X86_32
 614         .c_models = {
 615                 { .vendor = X86_VENDOR_AMD, .family = 4, .model_names =
 616                   {
 617                           [3] = "486 DX/2",
 618                           [7] = "486 DX/2-WB",
 619                           [8] = "486 DX/4",
 620                           [9] = "486 DX/4-WB",
 621                           [14] = "Am5x86-WT",
 622                           [15] = "Am5x86-WB"
 623                   }
 624                 },
 625         },
 626         .c_size_cache   = amd_size_cache,
 627 #endif
 628         .c_early_init   = early_init_amd,
 629         .c_init         = init_amd,
 630         .c_x86_vendor   = X86_VENDOR_AMD,
 631 };
 632
 633 cpu_dev_register(amd_cpu_dev);
 634
 635 /*
 636  * AMD errata checking
 637  *
 638  * Errata are defined as arrays of ints using the AMD_LEGACY_ERRATUM() or
 639  * AMD_OSVW_ERRATUM() macros. The latter is intended for newer errata that
 640  * have an OSVW id assigned, which it takes as first argument. Both take a
 641  * variable number of family-specific model-stepping ranges created by
 642  * AMD_MODEL_RANGE(). Each erratum also has to be declared as extern const
 643  * int[] in arch/x86/include/asm/processor.h.
 644  *
 645  * Example:
 646  *
 647  * const int amd_erratum_319[] =
 648  *      AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0x4, 0x2),
 649  *                         AMD_MODEL_RANGE(0x10, 0x8, 0x0, 0x8, 0x0),
 650  *                         AMD_MODEL_RANGE(0x10, 0x9, 0x0, 0x9, 0x0));
 651  */
 652
 653 const int amd_erratum_400[] =
 654         AMD_OSVW_ERRATUM(1, AMD_MODEL_RANGE(0xf, 0x41, 0x2, 0xff, 0xf),
 655                             AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0xff, 0xf));
 656
 657
 658 bool cpu_has_amd_erratum(const int *erratum)
 659 {
 660         struct cpuinfo_x86 *cpu = &current_cpu_data;
 661         int osvw_id = *erratum++;
 662         u32 range;
 663         u32 ms;
 664
 665         /*
 666          * If called early enough that current_cpu_data hasn't been initialized
 667          * yet, fall back to boot_cpu_data.
 668          */
 669         if (cpu->x86 == 0)
 670                 cpu = &boot_cpu_data;
 671
 672         if (cpu->x86_vendor != X86_VENDOR_AMD)
 673                 return false;
 674
 675         if (osvw_id >= 0 && osvw_id < 65536 &&
 676             cpu_has(cpu, X86_FEATURE_OSVW)) {
 677                 u64 osvw_len;
 678
 679                 rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, osvw_len);
 680                 if (osvw_id < osvw_len) {
 681                         u64 osvw_bits;
 682
 683                         rdmsrl(MSR_AMD64_OSVW_STATUS + (osvw_id >> 6),
 684                             osvw_bits);
 685                         return osvw_bits & (1ULL << (osvw_id & 0x3f));
 686                 }
 687         }
 688
 689         /* OSVW unavailable or ID unknown, match family-model-stepping range */
 690         ms = (cpu->x86_model << 4) | cpu->x86_mask;
 691         while ((range = *erratum++))
 692                 if ((cpu->x86 == AMD_MODEL_RANGE_FAMILY(range)) &&
 693                     (ms >= AMD_MODEL_RANGE_START(range)) &&
 694                     (ms <= AMD_MODEL_RANGE_END(range)))
 695                         return true;
 696
 697         return false;
 698 }