drivers/gpu/drm/radeon/radeon_object.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <glisse@freedesktop.org>
  29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30  *    Dave Airlie
  31  */
  32 #include <linux/list.h>
  33 #include <linux/slab.h>
  34 #include <drm/drmP.h>
  35 #include "radeon_drm.h"
  36 #include "radeon.h"
  37 #include "radeon_trace.h"
  38
  39
  40 int radeon_ttm_init(struct radeon_device *rdev);
  41 void radeon_ttm_fini(struct radeon_device *rdev);
  42 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo);
  43
  44 /*
  45  * To exclude mutual BO access we rely on bo_reserve exclusion, as all
  46  * function are calling it.
  47  */
  48
  49 static void radeon_ttm_bo_destroy(struct ttm_buffer_object *tbo)
  50 {
  51         struct radeon_bo *bo;
  52
  53         bo = container_of(tbo, struct radeon_bo, tbo);
  54         mutex_lock(&bo->rdev->gem.mutex);
  55         list_del_init(&bo->list);
  56         mutex_unlock(&bo->rdev->gem.mutex);
  57         radeon_bo_clear_surface_reg(bo);
  58         drm_gem_object_release(&bo->gem_base);
  59         kfree(bo);
  60 }
  61
  62 bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo)
  63 {
  64         if (bo->destroy == &radeon_ttm_bo_destroy)
  65                 return true;
  66         return false;
  67 }
  68
  69 void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain)
  70 {
  71         u32 c = 0;
  72
  73         rbo->placement.fpfn = 0;
  74         rbo->placement.lpfn = 0;
  75         rbo->placement.placement = rbo->placements;
  76         rbo->placement.busy_placement = rbo->placements;
  77         if (domain & RADEON_GEM_DOMAIN_VRAM)
  78                 rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
  79                                         TTM_PL_FLAG_VRAM;
  80         if (domain & RADEON_GEM_DOMAIN_GTT)
  81                 rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
  82         if (domain & RADEON_GEM_DOMAIN_CPU)
  83                 rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
  84         if (!c)
  85                 rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
  86         rbo->placement.num_placement = c;
  87         rbo->placement.num_busy_placement = c;
  88 }
  89
  90 int radeon_bo_create(struct radeon_device *rdev,
  91                      unsigned long size, int byte_align, bool kernel, u32 domain,
  92                      struct radeon_bo **bo_ptr)
  93 {
  94         struct radeon_bo *bo;
  95         enum ttm_bo_type type;
  96         unsigned long page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT;
  97         unsigned long max_size = 0;
  98         int r;
  99
 100         size = ALIGN(size, PAGE_SIZE);
 101
 102         if (unlikely(rdev->mman.bdev.dev_mapping == NULL)) {
 103                 rdev->mman.bdev.dev_mapping = rdev->ddev->dev_mapping;
 104         }
 105         if (kernel) {
 106                 type = ttm_bo_type_kernel;
 107         } else {
 108                 type = ttm_bo_type_device;
 109         }
 110         *bo_ptr = NULL;
 111
 112         /* maximun bo size is the minimun btw visible vram and gtt size */
 113         max_size = min(rdev->mc.visible_vram_size, rdev->mc.gtt_size);
 114         if ((page_align << PAGE_SHIFT) >= max_size) {
 115                 printk(KERN_WARNING "%s:%d alloc size %ldM bigger than %ldMb limit\n",
 116                         __func__, __LINE__, page_align  >> (20 - PAGE_SHIFT), max_size >> 20);
 117                 return -ENOMEM;
 118         }
 119
 120 retry:
 121         bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL);
 122         if (bo == NULL)
 123                 return -ENOMEM;
 124         r = drm_gem_object_init(rdev->ddev, &bo->gem_base, size);
 125         if (unlikely(r)) {
 126                 kfree(bo);
 127                 return r;
 128         }
 129         bo->rdev = rdev;
 130         bo->gobj = &bo->gem_base;
 131         bo->gem_base.driver_private = NULL;
 132         bo->surface_reg = -1;
 133         INIT_LIST_HEAD(&bo->list);
 134         radeon_ttm_placement_from_domain(bo, domain);
 135         /* Kernel allocation are uninterruptible */
 136         mutex_lock(&rdev->vram_mutex);
 137         r = ttm_bo_init(&rdev->mman.bdev, &bo->tbo, size, type,
 138                         &bo->placement, page_align, 0, !kernel, NULL, size,
 139                         &radeon_ttm_bo_destroy);
 140         mutex_unlock(&rdev->vram_mutex);
 141         if (unlikely(r != 0)) {
 142                 if (r != -ERESTARTSYS) {
 143                         if (domain == RADEON_GEM_DOMAIN_VRAM) {
 144                                 domain |= RADEON_GEM_DOMAIN_GTT;
 145                                 goto retry;
 146                         }
 147                         dev_err(rdev->dev,
 148                                 "object_init failed for (%lu, 0x%08X)\n",
 149                                 size, domain);
 150                 }
 151                 return r;
 152         }
 153         *bo_ptr = bo;
 154
 155         trace_radeon_bo_create(bo);
 156
 157         return 0;
 158 }
 159
 160 int radeon_bo_kmap(struct radeon_bo *bo, void **ptr)
 161 {
 162         bool is_iomem;
 163         int r;
 164
 165         if (bo->kptr) {
 166                 if (ptr) {
 167                         *ptr = bo->kptr;
 168                 }
 169                 return 0;
 170         }
 171         r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap);
 172         if (r) {
 173                 return r;
 174         }
 175         bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
 176         if (ptr) {
 177                 *ptr = bo->kptr;
 178         }
 179         radeon_bo_check_tiling(bo, 0, 0);
 180         return 0;
 181 }
 182
 183 void radeon_bo_kunmap(struct radeon_bo *bo)
 184 {
 185         if (bo->kptr == NULL)
 186                 return;
 187         bo->kptr = NULL;
 188         radeon_bo_check_tiling(bo, 0, 0);
 189         ttm_bo_kunmap(&bo->kmap);
 190 }
 191
 192 void radeon_bo_unref(struct radeon_bo **bo)
 193 {
 194         struct ttm_buffer_object *tbo;
 195         struct radeon_device *rdev;
 196
 197         if ((*bo) == NULL)
 198                 return;
 199         rdev = (*bo)->rdev;
 200         tbo = &((*bo)->tbo);
 201         mutex_lock(&rdev->vram_mutex);
 202         ttm_bo_unref(&tbo);
 203         mutex_unlock(&rdev->vram_mutex);
 204         if (tbo == NULL)
 205                 *bo = NULL;
 206 }
 207
 208 int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr)
 209 {
 210         int r, i;
 211
 212         if (bo->pin_count) {
 213                 bo->pin_count++;
 214                 if (gpu_addr)
 215                         *gpu_addr = radeon_bo_gpu_offset(bo);
 216                 return 0;
 217         }
 218         radeon_ttm_placement_from_domain(bo, domain);
 219         if (domain == RADEON_GEM_DOMAIN_VRAM) {
 220                 /* force to pin into visible video ram */
 221                 bo->placement.lpfn = bo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
 222         }
 223         for (i = 0; i < bo->placement.num_placement; i++)
 224                 bo->placements[i] |= TTM_PL_FLAG_NO_EVICT;
 225         r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false, false);
 226         if (likely(r == 0)) {
 227                 bo->pin_count = 1;
 228                 if (gpu_addr != NULL)
 229                         *gpu_addr = radeon_bo_gpu_offset(bo);
 230         }
 231         if (unlikely(r != 0))
 232                 dev_err(bo->rdev->dev, "%p pin failed\n", bo);
 233         return r;
 234 }
 235
 236 int radeon_bo_unpin(struct radeon_bo *bo)
 237 {
 238         int r, i;
 239
 240         if (!bo->pin_count) {
 241                 dev_warn(bo->rdev->dev, "%p unpin not necessary\n", bo);
 242                 return 0;
 243         }
 244         bo->pin_count--;
 245         if (bo->pin_count)
 246                 return 0;
 247         for (i = 0; i < bo->placement.num_placement; i++)
 248                 bo->placements[i] &= ~TTM_PL_FLAG_NO_EVICT;
 249         r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false, false);
 250         if (unlikely(r != 0))
 251                 dev_err(bo->rdev->dev, "%p validate failed for unpin\n", bo);
 252         return r;
 253 }
 254
 255 int radeon_bo_evict_vram(struct radeon_device *rdev)
 256 {
 257         /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */
 258         if (0 && (rdev->flags & RADEON_IS_IGP)) {
 259                 if (rdev->mc.igp_sideport_enabled == false)
 260                         /* Useless to evict on IGP chips */
 261                         return 0;
 262         }
 263         return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM);
 264 }
 265
 266 void radeon_bo_force_delete(struct radeon_device *rdev)
 267 {
 268         struct radeon_bo *bo, *n;
 269         struct drm_gem_object *gobj;
 270
 271         if (list_empty(&rdev->gem.objects)) {
 272                 return;
 273         }
 274         dev_err(rdev->dev, "Userspace still has active objects !\n");
 275         list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
 276                 mutex_lock(&rdev->ddev->struct_mutex);
 277                 gobj = bo->gobj;
 278                 dev_err(rdev->dev, "%p %p %lu %lu force free\n",
 279                         gobj, bo, (unsigned long)gobj->size,
 280                         *((unsigned long *)&gobj->refcount));
 281                 mutex_lock(&bo->rdev->gem.mutex);
 282                 list_del_init(&bo->list);
 283                 mutex_unlock(&bo->rdev->gem.mutex);
 284                 radeon_bo_unref(&bo);
 285                 drm_gem_object_unreference(gobj);
 286                 mutex_unlock(&rdev->ddev->struct_mutex);
 287         }
 288 }
 289
 290 int radeon_bo_init(struct radeon_device *rdev)
 291 {
 292         /* Add an MTRR for the VRAM */
 293         rdev->mc.vram_mtrr = mtrr_add(rdev->mc.aper_base, rdev->mc.aper_size,
 294                         MTRR_TYPE_WRCOMB, 1);
 295         DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
 296                 rdev->mc.mc_vram_size >> 20,
 297                 (unsigned long long)rdev->mc.aper_size >> 20);
 298         DRM_INFO("RAM width %dbits %cDR\n",
 299                         rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S');
 300         return radeon_ttm_init(rdev);
 301 }
 302
 303 void radeon_bo_fini(struct radeon_device *rdev)
 304 {
 305         radeon_ttm_fini(rdev);
 306 }
 307
 308 void radeon_bo_list_add_object(struct radeon_bo_list *lobj,
 309                                 struct list_head *head)
 310 {
 311         if (lobj->wdomain) {
 312                 list_add(&lobj->tv.head, head);
 313         } else {
 314                 list_add_tail(&lobj->tv.head, head);
 315         }
 316 }
 317
 318 int radeon_bo_list_validate(struct list_head *head)
 319 {
 320         struct radeon_bo_list *lobj;
 321         struct radeon_bo *bo;
 322         u32 domain;
 323         int r;
 324
 325         r = ttm_eu_reserve_buffers(head);
 326         if (unlikely(r != 0)) {
 327                 return r;
 328         }
 329         list_for_each_entry(lobj, head, tv.head) {
 330                 bo = lobj->bo;
 331                 if (!bo->pin_count) {
 332                         domain = lobj->wdomain ? lobj->wdomain : lobj->rdomain;
 333
 334                 retry:
 335                         radeon_ttm_placement_from_domain(bo, domain);
 336                         r = ttm_bo_validate(&bo->tbo, &bo->placement,
 337                                                 true, false, false);
 338                         if (unlikely(r)) {
 339                                 if (r != -ERESTARTSYS && domain == RADEON_GEM_DOMAIN_VRAM) {
 340                                         domain |= RADEON_GEM_DOMAIN_GTT;
 341                                         goto retry;
 342                                 }
 343                                 return r;
 344                         }
 345                 }
 346                 lobj->gpu_offset = radeon_bo_gpu_offset(bo);
 347                 lobj->tiling_flags = bo->tiling_flags;
 348         }
 349         return 0;
 350 }
 351
 352 int radeon_bo_fbdev_mmap(struct radeon_bo *bo,
 353                              struct vm_area_struct *vma)
 354 {
 355         return ttm_fbdev_mmap(vma, &bo->tbo);
 356 }
 357
 358 int radeon_bo_get_surface_reg(struct radeon_bo *bo)
 359 {
 360         struct radeon_device *rdev = bo->rdev;
 361         struct radeon_surface_reg *reg;
 362         struct radeon_bo *old_object;
 363         int steal;
 364         int i;
 365
 366         BUG_ON(!atomic_read(&bo->tbo.reserved));
 367
 368         if (!bo->tiling_flags)
 369                 return 0;
 370
 371         if (bo->surface_reg >= 0) {
 372                 reg = &rdev->surface_regs[bo->surface_reg];
 373                 i = bo->surface_reg;
 374                 goto out;
 375         }
 376
 377         steal = -1;
 378         for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
 379
 380                 reg = &rdev->surface_regs[i];
 381                 if (!reg->bo)
 382                         break;
 383
 384                 old_object = reg->bo;
 385                 if (old_object->pin_count == 0)
 386                         steal = i;
 387         }
 388
 389         /* if we are all out */
 390         if (i == RADEON_GEM_MAX_SURFACES) {
 391                 if (steal == -1)
 392                         return -ENOMEM;
 393                 /* find someone with a surface reg and nuke their BO */
 394                 reg = &rdev->surface_regs[steal];
 395                 old_object = reg->bo;
 396                 /* blow away the mapping */
 397                 DRM_DEBUG("stealing surface reg %d from %p\n", steal, old_object);
 398                 ttm_bo_unmap_virtual(&old_object->tbo);
 399                 old_object->surface_reg = -1;
 400                 i = steal;
 401         }
 402
 403         bo->surface_reg = i;
 404         reg->bo = bo;
 405
 406 out:
 407         radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch,
 408                                bo->tbo.mem.start << PAGE_SHIFT,
 409                                bo->tbo.num_pages << PAGE_SHIFT);
 410         return 0;
 411 }
 412
 413 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo)
 414 {
 415         struct radeon_device *rdev = bo->rdev;
 416         struct radeon_surface_reg *reg;
 417
 418         if (bo->surface_reg == -1)
 419                 return;
 420
 421         reg = &rdev->surface_regs[bo->surface_reg];
 422         radeon_clear_surface_reg(rdev, bo->surface_reg);
 423
 424         reg->bo = NULL;
 425         bo->surface_reg = -1;
 426 }
 427
 428 int radeon_bo_set_tiling_flags(struct radeon_bo *bo,
 429                                 uint32_t tiling_flags, uint32_t pitch)
 430 {
 431         int r;
 432
 433         r = radeon_bo_reserve(bo, false);
 434         if (unlikely(r != 0))
 435                 return r;
 436         bo->tiling_flags = tiling_flags;
 437         bo->pitch = pitch;
 438         radeon_bo_unreserve(bo);
 439         return 0;
 440 }
 441
 442 void radeon_bo_get_tiling_flags(struct radeon_bo *bo,
 443                                 uint32_t *tiling_flags,
 444                                 uint32_t *pitch)
 445 {
 446         BUG_ON(!atomic_read(&bo->tbo.reserved));
 447         if (tiling_flags)
 448                 *tiling_flags = bo->tiling_flags;
 449         if (pitch)
 450                 *pitch = bo->pitch;
 451 }
 452
 453 int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved,
 454                                 bool force_drop)
 455 {
 456         BUG_ON(!atomic_read(&bo->tbo.reserved));
 457
 458         if (!(bo->tiling_flags & RADEON_TILING_SURFACE))
 459                 return 0;
 460
 461         if (force_drop) {
 462                 radeon_bo_clear_surface_reg(bo);
 463                 return 0;
 464         }
 465
 466         if (bo->tbo.mem.mem_type != TTM_PL_VRAM) {
 467                 if (!has_moved)
 468                         return 0;
 469
 470                 if (bo->surface_reg >= 0)
 471                         radeon_bo_clear_surface_reg(bo);
 472                 return 0;
 473         }
 474
 475         if ((bo->surface_reg >= 0) && !has_moved)
 476                 return 0;
 477
 478         return radeon_bo_get_surface_reg(bo);
 479 }
 480
 481 void radeon_bo_move_notify(struct ttm_buffer_object *bo,
 482                            struct ttm_mem_reg *mem)
 483 {
 484         struct radeon_bo *rbo;
 485         if (!radeon_ttm_bo_is_radeon_bo(bo))
 486                 return;
 487         rbo = container_of(bo, struct radeon_bo, tbo);
 488         radeon_bo_check_tiling(rbo, 0, 1);
 489 }
 490
 491 int radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
 492 {
 493         struct radeon_device *rdev;
 494         struct radeon_bo *rbo;
 495         unsigned long offset, size;
 496         int r;
 497
 498         if (!radeon_ttm_bo_is_radeon_bo(bo))
 499                 return 0;
 500         rbo = container_of(bo, struct radeon_bo, tbo);
 501         radeon_bo_check_tiling(rbo, 0, 0);
 502         rdev = rbo->rdev;
 503         if (bo->mem.mem_type == TTM_PL_VRAM) {
 504                 size = bo->mem.num_pages << PAGE_SHIFT;
 505                 offset = bo->mem.start << PAGE_SHIFT;
 506                 if ((offset + size) > rdev->mc.visible_vram_size) {
 507                         /* hurrah the memory is not visible ! */
 508                         radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM);
 509                         rbo->placement.lpfn = rdev->mc.visible_vram_size >> PAGE_SHIFT;
 510                         r = ttm_bo_validate(bo, &rbo->placement, false, true, false);
 511                         if (unlikely(r != 0))
 512                                 return r;
 513                         offset = bo->mem.start << PAGE_SHIFT;
 514                         /* this should not happen */
 515                         if ((offset + size) > rdev->mc.visible_vram_size)
 516                                 return -EINVAL;
 517                 }
 518         }
 519         return 0;
 520 }