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drm/radeon/kms: set HPD polarity in hpd_init()
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / gpu / drm / radeon / r600.c
blob1a4ed433eba3c2d591451ab272fb9bd59cde6f5a
1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #include <linux/slab.h>
29 #include <linux/seq_file.h>
30 #include <linux/firmware.h>
31 #include <linux/platform_device.h>
32 #include "drmP.h"
33 #include "radeon_drm.h"
34 #include "radeon.h"
35 #include "radeon_asic.h"
36 #include "radeon_mode.h"
37 #include "r600d.h"
38 #include "atom.h"
39 #include "avivod.h"
40
41 #define PFP_UCODE_SIZE 576
42 #define PM4_UCODE_SIZE 1792
43 #define RLC_UCODE_SIZE 768
44 #define R700_PFP_UCODE_SIZE 848
45 #define R700_PM4_UCODE_SIZE 1360
46 #define R700_RLC_UCODE_SIZE 1024
47 #define EVERGREEN_PFP_UCODE_SIZE 1120
48 #define EVERGREEN_PM4_UCODE_SIZE 1376
49 #define EVERGREEN_RLC_UCODE_SIZE 768
50 #define CAYMAN_RLC_UCODE_SIZE 1024
51
52 /* Firmware Names */
53 MODULE_FIRMWARE("radeon/R600_pfp.bin");
54 MODULE_FIRMWARE("radeon/R600_me.bin");
55 MODULE_FIRMWARE("radeon/RV610_pfp.bin");
56 MODULE_FIRMWARE("radeon/RV610_me.bin");
57 MODULE_FIRMWARE("radeon/RV630_pfp.bin");
58 MODULE_FIRMWARE("radeon/RV630_me.bin");
59 MODULE_FIRMWARE("radeon/RV620_pfp.bin");
60 MODULE_FIRMWARE("radeon/RV620_me.bin");
61 MODULE_FIRMWARE("radeon/RV635_pfp.bin");
62 MODULE_FIRMWARE("radeon/RV635_me.bin");
63 MODULE_FIRMWARE("radeon/RV670_pfp.bin");
64 MODULE_FIRMWARE("radeon/RV670_me.bin");
65 MODULE_FIRMWARE("radeon/RS780_pfp.bin");
66 MODULE_FIRMWARE("radeon/RS780_me.bin");
67 MODULE_FIRMWARE("radeon/RV770_pfp.bin");
68 MODULE_FIRMWARE("radeon/RV770_me.bin");
69 MODULE_FIRMWARE("radeon/RV730_pfp.bin");
70 MODULE_FIRMWARE("radeon/RV730_me.bin");
71 MODULE_FIRMWARE("radeon/RV710_pfp.bin");
72 MODULE_FIRMWARE("radeon/RV710_me.bin");
73 MODULE_FIRMWARE("radeon/R600_rlc.bin");
74 MODULE_FIRMWARE("radeon/R700_rlc.bin");
75 MODULE_FIRMWARE("radeon/CEDAR_pfp.bin");
76 MODULE_FIRMWARE("radeon/CEDAR_me.bin");
77 MODULE_FIRMWARE("radeon/CEDAR_rlc.bin");
78 MODULE_FIRMWARE("radeon/REDWOOD_pfp.bin");
79 MODULE_FIRMWARE("radeon/REDWOOD_me.bin");
80 MODULE_FIRMWARE("radeon/REDWOOD_rlc.bin");
81 MODULE_FIRMWARE("radeon/JUNIPER_pfp.bin");
82 MODULE_FIRMWARE("radeon/JUNIPER_me.bin");
83 MODULE_FIRMWARE("radeon/JUNIPER_rlc.bin");
84 MODULE_FIRMWARE("radeon/CYPRESS_pfp.bin");
85 MODULE_FIRMWARE("radeon/CYPRESS_me.bin");
86 MODULE_FIRMWARE("radeon/CYPRESS_rlc.bin");
87 MODULE_FIRMWARE("radeon/PALM_pfp.bin");
88 MODULE_FIRMWARE("radeon/PALM_me.bin");
89 MODULE_FIRMWARE("radeon/SUMO_rlc.bin");
90 MODULE_FIRMWARE("radeon/SUMO_pfp.bin");
91 MODULE_FIRMWARE("radeon/SUMO_me.bin");
92 MODULE_FIRMWARE("radeon/SUMO2_pfp.bin");
93 MODULE_FIRMWARE("radeon/SUMO2_me.bin");
94
95 int r600_debugfs_mc_info_init(struct radeon_device *rdev);
96
97 /* r600,rv610,rv630,rv620,rv635,rv670 */
98 int r600_mc_wait_for_idle(struct radeon_device *rdev);
99 void r600_gpu_init(struct radeon_device *rdev);
100 void r600_fini(struct radeon_device *rdev);
101 void r600_irq_disable(struct radeon_device *rdev);
102 static void r600_pcie_gen2_enable(struct radeon_device *rdev);
103
104 /* get temperature in millidegrees */
105 int rv6xx_get_temp(struct radeon_device *rdev)
106 {
107 u32 temp = (RREG32(CG_THERMAL_STATUS) & ASIC_T_MASK) >>
108 ASIC_T_SHIFT;
109 int actual_temp = temp & 0xff;
110
111 if (temp & 0x100)
112 actual_temp -= 256;
113
114 return actual_temp * 1000;
115 }
116
117 void r600_pm_get_dynpm_state(struct radeon_device *rdev)
118 {
119 int i;
120
121 rdev->pm.dynpm_can_upclock = true;
122 rdev->pm.dynpm_can_downclock = true;
123
124 /* power state array is low to high, default is first */
125 if ((rdev->flags & RADEON_IS_IGP) || (rdev->family == CHIP_R600)) {
126 int min_power_state_index = 0;
127
128 if (rdev->pm.num_power_states > 2)
129 min_power_state_index = 1;
130
131 switch (rdev->pm.dynpm_planned_action) {
132 case DYNPM_ACTION_MINIMUM:
133 rdev->pm.requested_power_state_index = min_power_state_index;
134 rdev->pm.requested_clock_mode_index = 0;
135 rdev->pm.dynpm_can_downclock = false;
136 break;
137 case DYNPM_ACTION_DOWNCLOCK:
138 if (rdev->pm.current_power_state_index == min_power_state_index) {
139 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
140 rdev->pm.dynpm_can_downclock = false;
141 } else {
142 if (rdev->pm.active_crtc_count > 1) {
143 for (i = 0; i < rdev->pm.num_power_states; i++) {
144 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
145 continue;
146 else if (i >= rdev->pm.current_power_state_index) {
147 rdev->pm.requested_power_state_index =
148 rdev->pm.current_power_state_index;
149 break;
150 } else {
151 rdev->pm.requested_power_state_index = i;
152 break;
153 }
154 }
155 } else {
156 if (rdev->pm.current_power_state_index == 0)
157 rdev->pm.requested_power_state_index =
158 rdev->pm.num_power_states - 1;
159 else
160 rdev->pm.requested_power_state_index =
161 rdev->pm.current_power_state_index - 1;
162 }
163 }
164 rdev->pm.requested_clock_mode_index = 0;
165 /* don't use the power state if crtcs are active and no display flag is set */
166 if ((rdev->pm.active_crtc_count > 0) &&
167 (rdev->pm.power_state[rdev->pm.requested_power_state_index].
168 clock_info[rdev->pm.requested_clock_mode_index].flags &
169 RADEON_PM_MODE_NO_DISPLAY)) {
170 rdev->pm.requested_power_state_index++;
171 }
172 break;
173 case DYNPM_ACTION_UPCLOCK:
174 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
175 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
176 rdev->pm.dynpm_can_upclock = false;
177 } else {
178 if (rdev->pm.active_crtc_count > 1) {
179 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
180 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
181 continue;
182 else if (i <= rdev->pm.current_power_state_index) {
183 rdev->pm.requested_power_state_index =
184 rdev->pm.current_power_state_index;
185 break;
186 } else {
187 rdev->pm.requested_power_state_index = i;
188 break;
189 }
190 }
191 } else
192 rdev->pm.requested_power_state_index =
193 rdev->pm.current_power_state_index + 1;
194 }
195 rdev->pm.requested_clock_mode_index = 0;
196 break;
197 case DYNPM_ACTION_DEFAULT:
198 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
199 rdev->pm.requested_clock_mode_index = 0;
200 rdev->pm.dynpm_can_upclock = false;
201 break;
202 case DYNPM_ACTION_NONE:
203 default:
204 DRM_ERROR("Requested mode for not defined action\n");
205 return;
206 }
207 } else {
208 /* XXX select a power state based on AC/DC, single/dualhead, etc. */
209 /* for now just select the first power state and switch between clock modes */
210 /* power state array is low to high, default is first (0) */
211 if (rdev->pm.active_crtc_count > 1) {
212 rdev->pm.requested_power_state_index = -1;
213 /* start at 1 as we don't want the default mode */
214 for (i = 1; i < rdev->pm.num_power_states; i++) {
215 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
216 continue;
217 else if ((rdev->pm.power_state[i].type == POWER_STATE_TYPE_PERFORMANCE) ||
218 (rdev->pm.power_state[i].type == POWER_STATE_TYPE_BATTERY)) {
219 rdev->pm.requested_power_state_index = i;
220 break;
221 }
222 }
223 /* if nothing selected, grab the default state. */
224 if (rdev->pm.requested_power_state_index == -1)
225 rdev->pm.requested_power_state_index = 0;
226 } else
227 rdev->pm.requested_power_state_index = 1;
228
229 switch (rdev->pm.dynpm_planned_action) {
230 case DYNPM_ACTION_MINIMUM:
231 rdev->pm.requested_clock_mode_index = 0;
232 rdev->pm.dynpm_can_downclock = false;
233 break;
234 case DYNPM_ACTION_DOWNCLOCK:
235 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
236 if (rdev->pm.current_clock_mode_index == 0) {
237 rdev->pm.requested_clock_mode_index = 0;
238 rdev->pm.dynpm_can_downclock = false;
239 } else
240 rdev->pm.requested_clock_mode_index =
241 rdev->pm.current_clock_mode_index - 1;
242 } else {
243 rdev->pm.requested_clock_mode_index = 0;
244 rdev->pm.dynpm_can_downclock = false;
245 }
246 /* don't use the power state if crtcs are active and no display flag is set */
247 if ((rdev->pm.active_crtc_count > 0) &&
248 (rdev->pm.power_state[rdev->pm.requested_power_state_index].
249 clock_info[rdev->pm.requested_clock_mode_index].flags &
250 RADEON_PM_MODE_NO_DISPLAY)) {
251 rdev->pm.requested_clock_mode_index++;
252 }
253 break;
254 case DYNPM_ACTION_UPCLOCK:
255 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
256 if (rdev->pm.current_clock_mode_index ==
257 (rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1)) {
258 rdev->pm.requested_clock_mode_index = rdev->pm.current_clock_mode_index;
259 rdev->pm.dynpm_can_upclock = false;
260 } else
261 rdev->pm.requested_clock_mode_index =
262 rdev->pm.current_clock_mode_index + 1;
263 } else {
264 rdev->pm.requested_clock_mode_index =
265 rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1;
266 rdev->pm.dynpm_can_upclock = false;
267 }
268 break;
269 case DYNPM_ACTION_DEFAULT:
270 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
271 rdev->pm.requested_clock_mode_index = 0;
272 rdev->pm.dynpm_can_upclock = false;
273 break;
274 case DYNPM_ACTION_NONE:
275 default:
276 DRM_ERROR("Requested mode for not defined action\n");
277 return;
278 }
279 }
280
281 DRM_DEBUG_DRIVER("Requested: e: %d m: %d p: %d\n",
282 rdev->pm.power_state[rdev->pm.requested_power_state_index].
283 clock_info[rdev->pm.requested_clock_mode_index].sclk,
284 rdev->pm.power_state[rdev->pm.requested_power_state_index].
285 clock_info[rdev->pm.requested_clock_mode_index].mclk,
286 rdev->pm.power_state[rdev->pm.requested_power_state_index].
287 pcie_lanes);
288 }
289
290 static int r600_pm_get_type_index(struct radeon_device *rdev,
291 enum radeon_pm_state_type ps_type,
292 int instance)
293 {
294 int i;
295 int found_instance = -1;
296
297 for (i = 0; i < rdev->pm.num_power_states; i++) {
298 if (rdev->pm.power_state[i].type == ps_type) {
299 found_instance++;
300 if (found_instance == instance)
301 return i;
302 }
303 }
304 /* return default if no match */
305 return rdev->pm.default_power_state_index;
306 }
307
308 void rs780_pm_init_profile(struct radeon_device *rdev)
309 {
310 if (rdev->pm.num_power_states == 2) {
311 /* default */
312 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
313 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
314 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
315 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
316 /* low sh */
317 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
318 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
319 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
320 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
321 /* mid sh */
322 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
323 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
324 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
325 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
326 /* high sh */
327 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
328 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
329 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
330 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
331 /* low mh */
332 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
333 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
334 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
335 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
336 /* mid mh */
337 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
338 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
339 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
340 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
341 /* high mh */
342 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
343 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 1;
344 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
345 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
346 } else if (rdev->pm.num_power_states == 3) {
347 /* default */
348 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
349 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
350 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
351 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
352 /* low sh */
353 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
354 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
355 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
356 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
357 /* mid sh */
358 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
359 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
360 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
361 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
362 /* high sh */
363 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
364 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 2;
365 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
366 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
367 /* low mh */
368 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 1;
369 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 1;
370 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
371 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
372 /* mid mh */
373 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 1;
374 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 1;
375 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
376 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
377 /* high mh */
378 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 1;
379 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
380 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
381 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
382 } else {
383 /* default */
384 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
385 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
386 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
387 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
388 /* low sh */
389 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 2;
390 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 2;
391 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
392 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
393 /* mid sh */
394 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 2;
395 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 2;
396 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
397 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
398 /* high sh */
399 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 2;
400 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 3;
401 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
402 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
403 /* low mh */
404 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
405 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
406 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
407 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
408 /* mid mh */
409 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
410 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
411 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
412 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
413 /* high mh */
414 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
415 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 3;
416 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
417 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
418 }
419 }
420
421 void r600_pm_init_profile(struct radeon_device *rdev)
422 {
423 if (rdev->family == CHIP_R600) {
424 /* XXX */
425 /* default */
426 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
427 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
428 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
429 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
430 /* low sh */
431 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
432 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
433 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
434 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
435 /* mid sh */
436 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
437 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
438 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
439 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
440 /* high sh */
441 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
442 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
443 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
444 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
445 /* low mh */
446 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
447 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
448 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
449 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
450 /* mid mh */
451 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
452 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
453 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
454 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
455 /* high mh */
456 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
457 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
458 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
459 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
460 } else {
461 if (rdev->pm.num_power_states < 4) {
462 /* default */
463 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
464 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
465 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
466 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
467 /* low sh */
468 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
469 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
470 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
471 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
472 /* mid sh */
473 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
474 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
475 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
476 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
477 /* high sh */
478 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
479 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
480 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
481 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
482 /* low mh */
483 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
484 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 2;
485 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
486 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
487 /* low mh */
488 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
489 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 2;
490 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
491 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
492 /* high mh */
493 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
494 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
495 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
496 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
497 } else {
498 /* default */
499 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
500 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
501 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
502 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
503 /* low sh */
504 if (rdev->flags & RADEON_IS_MOBILITY) {
505 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx =
506 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
507 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx =
508 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
509 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
510 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
511 } else {
512 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx =
513 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
514 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx =
515 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
516 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
517 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
518 }
519 /* mid sh */
520 if (rdev->flags & RADEON_IS_MOBILITY) {
521 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx =
522 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
523 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx =
524 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
525 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
526 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
527 } else {
528 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx =
529 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
530 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx =
531 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
532 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
533 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
534 }
535 /* high sh */
536 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx =
537 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
538 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx =
539 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
540 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
541 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
542 /* low mh */
543 if (rdev->flags & RADEON_IS_MOBILITY) {
544 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx =
545 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
546 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx =
547 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
548 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
549 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
550 } else {
551 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx =
552 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
553 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx =
554 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
555 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
556 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
557 }
558 /* mid mh */
559 if (rdev->flags & RADEON_IS_MOBILITY) {
560 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx =
561 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
562 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx =
563 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
564 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
565 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
566 } else {
567 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx =
568 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
569 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx =
570 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
571 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
572 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
573 }
574 /* high mh */
575 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx =
576 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
577 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx =
578 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
579 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
580 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
581 }
582 }
583 }
584
585 void r600_pm_misc(struct radeon_device *rdev)
586 {
587 int req_ps_idx = rdev->pm.requested_power_state_index;
588 int req_cm_idx = rdev->pm.requested_clock_mode_index;
589 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
590 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
591
592 if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
593 /* 0xff01 is a flag rather then an actual voltage */
594 if (voltage->voltage == 0xff01)
595 return;
596 if (voltage->voltage != rdev->pm.current_vddc) {
597 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
598 rdev->pm.current_vddc = voltage->voltage;
599 DRM_DEBUG_DRIVER("Setting: v: %d\n", voltage->voltage);
600 }
601 }
602 }
603
604 bool r600_gui_idle(struct radeon_device *rdev)
605 {
606 if (RREG32(GRBM_STATUS) & GUI_ACTIVE)
607 return false;
608 else
609 return true;
610 }
611
612 /* hpd for digital panel detect/disconnect */
613 bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
614 {
615 bool connected = false;
616
617 if (ASIC_IS_DCE3(rdev)) {
618 switch (hpd) {
619 case RADEON_HPD_1:
620 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
621 connected = true;
622 break;
623 case RADEON_HPD_2:
624 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
625 connected = true;
626 break;
627 case RADEON_HPD_3:
628 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
629 connected = true;
630 break;
631 case RADEON_HPD_4:
632 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
633 connected = true;
634 break;
635 /* DCE 3.2 */
636 case RADEON_HPD_5:
637 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
638 connected = true;
639 break;
640 case RADEON_HPD_6:
641 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
642 connected = true;
643 break;
644 default:
645 break;
646 }
647 } else {
648 switch (hpd) {
649 case RADEON_HPD_1:
650 if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
651 connected = true;
652 break;
653 case RADEON_HPD_2:
654 if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
655 connected = true;
656 break;
657 case RADEON_HPD_3:
658 if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
659 connected = true;
660 break;
661 default:
662 break;
663 }
664 }
665 return connected;
666 }
667
668 void r600_hpd_set_polarity(struct radeon_device *rdev,
669 enum radeon_hpd_id hpd)
670 {
671 u32 tmp;
672 bool connected = r600_hpd_sense(rdev, hpd);
673
674 if (ASIC_IS_DCE3(rdev)) {
675 switch (hpd) {
676 case RADEON_HPD_1:
677 tmp = RREG32(DC_HPD1_INT_CONTROL);
678 if (connected)
679 tmp &= ~DC_HPDx_INT_POLARITY;
680 else
681 tmp |= DC_HPDx_INT_POLARITY;
682 WREG32(DC_HPD1_INT_CONTROL, tmp);
683 break;
684 case RADEON_HPD_2:
685 tmp = RREG32(DC_HPD2_INT_CONTROL);
686 if (connected)
687 tmp &= ~DC_HPDx_INT_POLARITY;
688 else
689 tmp |= DC_HPDx_INT_POLARITY;
690 WREG32(DC_HPD2_INT_CONTROL, tmp);
691 break;
692 case RADEON_HPD_3:
693 tmp = RREG32(DC_HPD3_INT_CONTROL);
694 if (connected)
695 tmp &= ~DC_HPDx_INT_POLARITY;
696 else
697 tmp |= DC_HPDx_INT_POLARITY;
698 WREG32(DC_HPD3_INT_CONTROL, tmp);
699 break;
700 case RADEON_HPD_4:
701 tmp = RREG32(DC_HPD4_INT_CONTROL);
702 if (connected)
703 tmp &= ~DC_HPDx_INT_POLARITY;
704 else
705 tmp |= DC_HPDx_INT_POLARITY;
706 WREG32(DC_HPD4_INT_CONTROL, tmp);
707 break;
708 case RADEON_HPD_5:
709 tmp = RREG32(DC_HPD5_INT_CONTROL);
710 if (connected)
711 tmp &= ~DC_HPDx_INT_POLARITY;
712 else
713 tmp |= DC_HPDx_INT_POLARITY;
714 WREG32(DC_HPD5_INT_CONTROL, tmp);
715 break;
716 /* DCE 3.2 */
717 case RADEON_HPD_6:
718 tmp = RREG32(DC_HPD6_INT_CONTROL);
719 if (connected)
720 tmp &= ~DC_HPDx_INT_POLARITY;
721 else
722 tmp |= DC_HPDx_INT_POLARITY;
723 WREG32(DC_HPD6_INT_CONTROL, tmp);
724 break;
725 default:
726 break;
727 }
728 } else {
729 switch (hpd) {
730 case RADEON_HPD_1:
731 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
732 if (connected)
733 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
734 else
735 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
736 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
737 break;
738 case RADEON_HPD_2:
739 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
740 if (connected)
741 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
742 else
743 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
744 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
745 break;
746 case RADEON_HPD_3:
747 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
748 if (connected)
749 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
750 else
751 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
752 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
753 break;
754 default:
755 break;
756 }
757 }
758 }
759
760 void r600_hpd_init(struct radeon_device *rdev)
761 {
762 struct drm_device *dev = rdev->ddev;
763 struct drm_connector *connector;
764
765 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
766 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
767
768 if (ASIC_IS_DCE3(rdev)) {
769 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa);
770 if (ASIC_IS_DCE32(rdev))
771 tmp |= DC_HPDx_EN;
772
773 switch (radeon_connector->hpd.hpd) {
774 case RADEON_HPD_1:
775 WREG32(DC_HPD1_CONTROL, tmp);
776 rdev->irq.hpd[0] = true;
777 break;
778 case RADEON_HPD_2:
779 WREG32(DC_HPD2_CONTROL, tmp);
780 rdev->irq.hpd[1] = true;
781 break;
782 case RADEON_HPD_3:
783 WREG32(DC_HPD3_CONTROL, tmp);
784 rdev->irq.hpd[2] = true;
785 break;
786 case RADEON_HPD_4:
787 WREG32(DC_HPD4_CONTROL, tmp);
788 rdev->irq.hpd[3] = true;
789 break;
790 /* DCE 3.2 */
791 case RADEON_HPD_5:
792 WREG32(DC_HPD5_CONTROL, tmp);
793 rdev->irq.hpd[4] = true;
794 break;
795 case RADEON_HPD_6:
796 WREG32(DC_HPD6_CONTROL, tmp);
797 rdev->irq.hpd[5] = true;
798 break;
799 default:
800 break;
801 }
802 } else {
803 switch (radeon_connector->hpd.hpd) {
804 case RADEON_HPD_1:
805 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN);
806 rdev->irq.hpd[0] = true;
807 break;
808 case RADEON_HPD_2:
809 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN);
810 rdev->irq.hpd[1] = true;
811 break;
812 case RADEON_HPD_3:
813 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN);
814 rdev->irq.hpd[2] = true;
815 break;
816 default:
817 break;
818 }
819 }
820 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
821 }
822 if (rdev->irq.installed)
823 r600_irq_set(rdev);
824 }
825
826 void r600_hpd_fini(struct radeon_device *rdev)
827 {
828 struct drm_device *dev = rdev->ddev;
829 struct drm_connector *connector;
830
831 if (ASIC_IS_DCE3(rdev)) {
832 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
833 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
834 switch (radeon_connector->hpd.hpd) {
835 case RADEON_HPD_1:
836 WREG32(DC_HPD1_CONTROL, 0);
837 rdev->irq.hpd[0] = false;
838 break;
839 case RADEON_HPD_2:
840 WREG32(DC_HPD2_CONTROL, 0);
841 rdev->irq.hpd[1] = false;
842 break;
843 case RADEON_HPD_3:
844 WREG32(DC_HPD3_CONTROL, 0);
845 rdev->irq.hpd[2] = false;
846 break;
847 case RADEON_HPD_4:
848 WREG32(DC_HPD4_CONTROL, 0);
849 rdev->irq.hpd[3] = false;
850 break;
851 /* DCE 3.2 */
852 case RADEON_HPD_5:
853 WREG32(DC_HPD5_CONTROL, 0);
854 rdev->irq.hpd[4] = false;
855 break;
856 case RADEON_HPD_6:
857 WREG32(DC_HPD6_CONTROL, 0);
858 rdev->irq.hpd[5] = false;
859 break;
860 default:
861 break;
862 }
863 }
864 } else {
865 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
866 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
867 switch (radeon_connector->hpd.hpd) {
868 case RADEON_HPD_1:
869 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0);
870 rdev->irq.hpd[0] = false;
871 break;
872 case RADEON_HPD_2:
873 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0);
874 rdev->irq.hpd[1] = false;
875 break;
876 case RADEON_HPD_3:
877 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0);
878 rdev->irq.hpd[2] = false;
879 break;
880 default:
881 break;
882 }
883 }
884 }
885 }
886
887 /*
888 * R600 PCIE GART
889 */
890 void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
891 {
892 unsigned i;
893 u32 tmp;
894
895 /* flush hdp cache so updates hit vram */
896 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) &&
897 !(rdev->flags & RADEON_IS_AGP)) {
898 void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
899 u32 tmp;
900
901 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read
902 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL
903 * This seems to cause problems on some AGP cards. Just use the old
904 * method for them.
905 */
906 WREG32(HDP_DEBUG1, 0);
907 tmp = readl((void __iomem *)ptr);
908 } else
909 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
910
911 WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);
912 WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);
913 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
914 for (i = 0; i < rdev->usec_timeout; i++) {
915 /* read MC_STATUS */
916 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
917 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
918 if (tmp == 2) {
919 printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
920 return;
921 }
922 if (tmp) {
923 return;
924 }
925 udelay(1);
926 }
927 }
928
929 int r600_pcie_gart_init(struct radeon_device *rdev)
930 {
931 int r;
932
933 if (rdev->gart.table.vram.robj) {
934 WARN(1, "R600 PCIE GART already initialized\n");
935 return 0;
936 }
937 /* Initialize common gart structure */
938 r = radeon_gart_init(rdev);
939 if (r)
940 return r;
941 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
942 return radeon_gart_table_vram_alloc(rdev);
943 }
944
945 int r600_pcie_gart_enable(struct radeon_device *rdev)
946 {
947 u32 tmp;
948 int r, i;
949
950 if (rdev->gart.table.vram.robj == NULL) {
951 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
952 return -EINVAL;
953 }
954 r = radeon_gart_table_vram_pin(rdev);
955 if (r)
956 return r;
957 radeon_gart_restore(rdev);
958
959 /* Setup L2 cache */
960 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
961 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
962 EFFECTIVE_L2_QUEUE_SIZE(7));
963 WREG32(VM_L2_CNTL2, 0);
964 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
965 /* Setup TLB control */
966 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
967 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
968 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
969 ENABLE_WAIT_L2_QUERY;
970 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
971 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
972 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
973 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
974 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
975 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
976 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
977 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
978 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
979 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
980 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
981 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
982 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
983 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
984 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
985 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
986 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
987 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
988 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
989 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
990 (u32)(rdev->dummy_page.addr >> 12));
991 for (i = 1; i < 7; i++)
992 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
993
994 r600_pcie_gart_tlb_flush(rdev);
995 rdev->gart.ready = true;
996 return 0;
997 }
998
999 void r600_pcie_gart_disable(struct radeon_device *rdev)
1000 {
1001 u32 tmp;
1002 int i, r;
1003
1004 /* Disable all tables */
1005 for (i = 0; i < 7; i++)
1006 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
1007
1008 /* Disable L2 cache */
1009 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
1010 EFFECTIVE_L2_QUEUE_SIZE(7));
1011 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
1012 /* Setup L1 TLB control */
1013 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
1014 ENABLE_WAIT_L2_QUERY;
1015 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
1016 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
1017 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
1018 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
1019 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
1020 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
1021 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
1022 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
1023 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp);
1024 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp);
1025 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
1026 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
1027 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);
1028 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
1029 if (rdev->gart.table.vram.robj) {
1030 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
1031 if (likely(r == 0)) {
1032 radeon_bo_kunmap(rdev->gart.table.vram.robj);
1033 radeon_bo_unpin(rdev->gart.table.vram.robj);
1034 radeon_bo_unreserve(rdev->gart.table.vram.robj);
1035 }
1036 }
1037 }
1038
1039 void r600_pcie_gart_fini(struct radeon_device *rdev)
1040 {
1041 radeon_gart_fini(rdev);
1042 r600_pcie_gart_disable(rdev);
1043 radeon_gart_table_vram_free(rdev);
1044 }
1045
1046 void r600_agp_enable(struct radeon_device *rdev)
1047 {
1048 u32 tmp;
1049 int i;
1050
1051 /* Setup L2 cache */
1052 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
1053 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1054 EFFECTIVE_L2_QUEUE_SIZE(7));
1055 WREG32(VM_L2_CNTL2, 0);
1056 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
1057 /* Setup TLB control */
1058 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
1059 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1060 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
1061 ENABLE_WAIT_L2_QUERY;
1062 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
1063 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
1064 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
1065 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
1066 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
1067 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
1068 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
1069 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
1070 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
1071 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
1072 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
1073 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
1074 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1075 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1076 for (i = 0; i < 7; i++)
1077 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
1078 }
1079
1080 int r600_mc_wait_for_idle(struct radeon_device *rdev)
1081 {
1082 unsigned i;
1083 u32 tmp;
1084
1085 for (i = 0; i < rdev->usec_timeout; i++) {
1086 /* read MC_STATUS */
1087 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00;
1088 if (!tmp)
1089 return 0;
1090 udelay(1);
1091 }
1092 return -1;
1093 }
1094
1095 static void r600_mc_program(struct radeon_device *rdev)
1096 {
1097 struct rv515_mc_save save;
1098 u32 tmp;
1099 int i, j;
1100
1101 /* Initialize HDP */
1102 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1103 WREG32((0x2c14 + j), 0x00000000);
1104 WREG32((0x2c18 + j), 0x00000000);
1105 WREG32((0x2c1c + j), 0x00000000);
1106 WREG32((0x2c20 + j), 0x00000000);
1107 WREG32((0x2c24 + j), 0x00000000);
1108 }
1109 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
1110
1111 rv515_mc_stop(rdev, &save);
1112 if (r600_mc_wait_for_idle(rdev)) {
1113 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1114 }
1115 /* Lockout access through VGA aperture (doesn't exist before R600) */
1116 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
1117 /* Update configuration */
1118 if (rdev->flags & RADEON_IS_AGP) {
1119 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1120 /* VRAM before AGP */
1121 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1122 rdev->mc.vram_start >> 12);
1123 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1124 rdev->mc.gtt_end >> 12);
1125 } else {
1126 /* VRAM after AGP */
1127 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1128 rdev->mc.gtt_start >> 12);
1129 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1130 rdev->mc.vram_end >> 12);
1131 }
1132 } else {
1133 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
1134 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12);
1135 }
1136 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
1137 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
1138 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1139 WREG32(MC_VM_FB_LOCATION, tmp);
1140 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
1141 WREG32(HDP_NONSURFACE_INFO, (2 << 7));
1142 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
1143 if (rdev->flags & RADEON_IS_AGP) {
1144 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22);
1145 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22);
1146 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1147 } else {
1148 WREG32(MC_VM_AGP_BASE, 0);
1149 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1150 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1151 }
1152 if (r600_mc_wait_for_idle(rdev)) {
1153 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1154 }
1155 rv515_mc_resume(rdev, &save);
1156 /* we need to own VRAM, so turn off the VGA renderer here
1157 * to stop it overwriting our objects */
1158 rv515_vga_render_disable(rdev);
1159 }
1160
1161 /**
1162 * r600_vram_gtt_location - try to find VRAM & GTT location
1163 * @rdev: radeon device structure holding all necessary informations
1164 * @mc: memory controller structure holding memory informations
1165 *
1166 * Function will place try to place VRAM at same place as in CPU (PCI)
1167 * address space as some GPU seems to have issue when we reprogram at
1168 * different address space.
1169 *
1170 * If there is not enough space to fit the unvisible VRAM after the
1171 * aperture then we limit the VRAM size to the aperture.
1172 *
1173 * If we are using AGP then place VRAM adjacent to AGP aperture are we need
1174 * them to be in one from GPU point of view so that we can program GPU to
1175 * catch access outside them (weird GPU policy see ??).
1176 *
1177 * This function will never fails, worst case are limiting VRAM or GTT.
1178 *
1179 * Note: GTT start, end, size should be initialized before calling this
1180 * function on AGP platform.
1181 */
1182 static void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
1183 {
1184 u64 size_bf, size_af;
1185
1186 if (mc->mc_vram_size > 0xE0000000) {
1187 /* leave room for at least 512M GTT */
1188 dev_warn(rdev->dev, "limiting VRAM\n");
1189 mc->real_vram_size = 0xE0000000;
1190 mc->mc_vram_size = 0xE0000000;
1191 }
1192 if (rdev->flags & RADEON_IS_AGP) {
1193 size_bf = mc->gtt_start;
1194 size_af = 0xFFFFFFFF - mc->gtt_end + 1;
1195 if (size_bf > size_af) {
1196 if (mc->mc_vram_size > size_bf) {
1197 dev_warn(rdev->dev, "limiting VRAM\n");
1198 mc->real_vram_size = size_bf;
1199 mc->mc_vram_size = size_bf;
1200 }
1201 mc->vram_start = mc->gtt_start - mc->mc_vram_size;
1202 } else {
1203 if (mc->mc_vram_size > size_af) {
1204 dev_warn(rdev->dev, "limiting VRAM\n");
1205 mc->real_vram_size = size_af;
1206 mc->mc_vram_size = size_af;
1207 }
1208 mc->vram_start = mc->gtt_end;
1209 }
1210 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
1211 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
1212 mc->mc_vram_size >> 20, mc->vram_start,
1213 mc->vram_end, mc->real_vram_size >> 20);
1214 } else {
1215 u64 base = 0;
1216 if (rdev->flags & RADEON_IS_IGP) {
1217 base = RREG32(MC_VM_FB_LOCATION) & 0xFFFF;
1218 base <<= 24;
1219 }
1220 radeon_vram_location(rdev, &rdev->mc, base);
1221 rdev->mc.gtt_base_align = 0;
1222 radeon_gtt_location(rdev, mc);
1223 }
1224 }
1225
1226 int r600_mc_init(struct radeon_device *rdev)
1227 {
1228 u32 tmp;
1229 int chansize, numchan;
1230
1231 /* Get VRAM informations */
1232 rdev->mc.vram_is_ddr = true;
1233 tmp = RREG32(RAMCFG);
1234 if (tmp & CHANSIZE_OVERRIDE) {
1235 chansize = 16;
1236 } else if (tmp & CHANSIZE_MASK) {
1237 chansize = 64;
1238 } else {
1239 chansize = 32;
1240 }
1241 tmp = RREG32(CHMAP);
1242 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1243 case 0:
1244 default:
1245 numchan = 1;
1246 break;
1247 case 1:
1248 numchan = 2;
1249 break;
1250 case 2:
1251 numchan = 4;
1252 break;
1253 case 3:
1254 numchan = 8;
1255 break;
1256 }
1257 rdev->mc.vram_width = numchan * chansize;
1258 /* Could aper size report 0 ? */
1259 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
1260 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
1261 /* Setup GPU memory space */
1262 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
1263 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
1264 rdev->mc.visible_vram_size = rdev->mc.aper_size;
1265 r600_vram_gtt_location(rdev, &rdev->mc);
1266
1267 if (rdev->flags & RADEON_IS_IGP) {
1268 rs690_pm_info(rdev);
1269 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
1270 }
1271 radeon_update_bandwidth_info(rdev);
1272 return 0;
1273 }
1274
1275 /* We doesn't check that the GPU really needs a reset we simply do the
1276 * reset, it's up to the caller to determine if the GPU needs one. We
1277 * might add an helper function to check that.
1278 */
1279 int r600_gpu_soft_reset(struct radeon_device *rdev)
1280 {
1281 struct rv515_mc_save save;
1282 u32 grbm_busy_mask = S_008010_VC_BUSY(1) | S_008010_VGT_BUSY_NO_DMA(1) |
1283 S_008010_VGT_BUSY(1) | S_008010_TA03_BUSY(1) |
1284 S_008010_TC_BUSY(1) | S_008010_SX_BUSY(1) |
1285 S_008010_SH_BUSY(1) | S_008010_SPI03_BUSY(1) |
1286 S_008010_SMX_BUSY(1) | S_008010_SC_BUSY(1) |
1287 S_008010_PA_BUSY(1) | S_008010_DB03_BUSY(1) |
1288 S_008010_CR_BUSY(1) | S_008010_CB03_BUSY(1) |
1289 S_008010_GUI_ACTIVE(1);
1290 u32 grbm2_busy_mask = S_008014_SPI0_BUSY(1) | S_008014_SPI1_BUSY(1) |
1291 S_008014_SPI2_BUSY(1) | S_008014_SPI3_BUSY(1) |
1292 S_008014_TA0_BUSY(1) | S_008014_TA1_BUSY(1) |
1293 S_008014_TA2_BUSY(1) | S_008014_TA3_BUSY(1) |
1294 S_008014_DB0_BUSY(1) | S_008014_DB1_BUSY(1) |
1295 S_008014_DB2_BUSY(1) | S_008014_DB3_BUSY(1) |
1296 S_008014_CB0_BUSY(1) | S_008014_CB1_BUSY(1) |
1297 S_008014_CB2_BUSY(1) | S_008014_CB3_BUSY(1);
1298 u32 tmp;
1299
1300 if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
1301 return 0;
1302
1303 dev_info(rdev->dev, "GPU softreset \n");
1304 dev_info(rdev->dev, " R_008010_GRBM_STATUS=0x%08X\n",
1305 RREG32(R_008010_GRBM_STATUS));
1306 dev_info(rdev->dev, " R_008014_GRBM_STATUS2=0x%08X\n",
1307 RREG32(R_008014_GRBM_STATUS2));
1308 dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n",
1309 RREG32(R_000E50_SRBM_STATUS));
1310 rv515_mc_stop(rdev, &save);
1311 if (r600_mc_wait_for_idle(rdev)) {
1312 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1313 }
1314 /* Disable CP parsing/prefetching */
1315 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1316 /* Check if any of the rendering block is busy and reset it */
1317 if ((RREG32(R_008010_GRBM_STATUS) & grbm_busy_mask) ||
1318 (RREG32(R_008014_GRBM_STATUS2) & grbm2_busy_mask)) {
1319 tmp = S_008020_SOFT_RESET_CR(1) |
1320 S_008020_SOFT_RESET_DB(1) |
1321 S_008020_SOFT_RESET_CB(1) |
1322 S_008020_SOFT_RESET_PA(1) |
1323 S_008020_SOFT_RESET_SC(1) |
1324 S_008020_SOFT_RESET_SMX(1) |
1325 S_008020_SOFT_RESET_SPI(1) |
1326 S_008020_SOFT_RESET_SX(1) |
1327 S_008020_SOFT_RESET_SH(1) |
1328 S_008020_SOFT_RESET_TC(1) |
1329 S_008020_SOFT_RESET_TA(1) |
1330 S_008020_SOFT_RESET_VC(1) |
1331 S_008020_SOFT_RESET_VGT(1);
1332 dev_info(rdev->dev, " R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
1333 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
1334 RREG32(R_008020_GRBM_SOFT_RESET);
1335 mdelay(15);
1336 WREG32(R_008020_GRBM_SOFT_RESET, 0);
1337 }
1338 /* Reset CP (we always reset CP) */
1339 tmp = S_008020_SOFT_RESET_CP(1);
1340 dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
1341 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
1342 RREG32(R_008020_GRBM_SOFT_RESET);
1343 mdelay(15);
1344 WREG32(R_008020_GRBM_SOFT_RESET, 0);
1345 /* Wait a little for things to settle down */
1346 mdelay(1);
1347 dev_info(rdev->dev, " R_008010_GRBM_STATUS=0x%08X\n",
1348 RREG32(R_008010_GRBM_STATUS));
1349 dev_info(rdev->dev, " R_008014_GRBM_STATUS2=0x%08X\n",
1350 RREG32(R_008014_GRBM_STATUS2));
1351 dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n",
1352 RREG32(R_000E50_SRBM_STATUS));
1353 rv515_mc_resume(rdev, &save);
1354 return 0;
1355 }
1356
1357 bool r600_gpu_is_lockup(struct radeon_device *rdev)
1358 {
1359 u32 srbm_status;
1360 u32 grbm_status;
1361 u32 grbm_status2;
1362 struct r100_gpu_lockup *lockup;
1363 int r;
1364
1365 if (rdev->family >= CHIP_RV770)
1366 lockup = &rdev->config.rv770.lockup;
1367 else
1368 lockup = &rdev->config.r600.lockup;
1369
1370 srbm_status = RREG32(R_000E50_SRBM_STATUS);
1371 grbm_status = RREG32(R_008010_GRBM_STATUS);
1372 grbm_status2 = RREG32(R_008014_GRBM_STATUS2);
1373 if (!G_008010_GUI_ACTIVE(grbm_status)) {
1374 r100_gpu_lockup_update(lockup, &rdev->cp);
1375 return false;
1376 }
1377 /* force CP activities */
1378 r = radeon_ring_lock(rdev, 2);
1379 if (!r) {
1380 /* PACKET2 NOP */
1381 radeon_ring_write(rdev, 0x80000000);
1382 radeon_ring_write(rdev, 0x80000000);
1383 radeon_ring_unlock_commit(rdev);
1384 }
1385 rdev->cp.rptr = RREG32(R600_CP_RB_RPTR);
1386 return r100_gpu_cp_is_lockup(rdev, lockup, &rdev->cp);
1387 }
1388
1389 int r600_asic_reset(struct radeon_device *rdev)
1390 {
1391 return r600_gpu_soft_reset(rdev);
1392 }
1393
1394 static u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
1395 u32 num_backends,
1396 u32 backend_disable_mask)
1397 {
1398 u32 backend_map = 0;
1399 u32 enabled_backends_mask;
1400 u32 enabled_backends_count;
1401 u32 cur_pipe;
1402 u32 swizzle_pipe[R6XX_MAX_PIPES];
1403 u32 cur_backend;
1404 u32 i;
1405
1406 if (num_tile_pipes > R6XX_MAX_PIPES)
1407 num_tile_pipes = R6XX_MAX_PIPES;
1408 if (num_tile_pipes < 1)
1409 num_tile_pipes = 1;
1410 if (num_backends > R6XX_MAX_BACKENDS)
1411 num_backends = R6XX_MAX_BACKENDS;
1412 if (num_backends < 1)
1413 num_backends = 1;
1414
1415 enabled_backends_mask = 0;
1416 enabled_backends_count = 0;
1417 for (i = 0; i < R6XX_MAX_BACKENDS; ++i) {
1418 if (((backend_disable_mask >> i) & 1) == 0) {
1419 enabled_backends_mask |= (1 << i);
1420 ++enabled_backends_count;
1421 }
1422 if (enabled_backends_count == num_backends)
1423 break;
1424 }
1425
1426 if (enabled_backends_count == 0) {
1427 enabled_backends_mask = 1;
1428 enabled_backends_count = 1;
1429 }
1430
1431 if (enabled_backends_count != num_backends)
1432 num_backends = enabled_backends_count;
1433
1434 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R6XX_MAX_PIPES);
1435 switch (num_tile_pipes) {
1436 case 1:
1437 swizzle_pipe[0] = 0;
1438 break;
1439 case 2:
1440 swizzle_pipe[0] = 0;
1441 swizzle_pipe[1] = 1;
1442 break;
1443 case 3:
1444 swizzle_pipe[0] = 0;
1445 swizzle_pipe[1] = 1;
1446 swizzle_pipe[2] = 2;
1447 break;
1448 case 4:
1449 swizzle_pipe[0] = 0;
1450 swizzle_pipe[1] = 1;
1451 swizzle_pipe[2] = 2;
1452 swizzle_pipe[3] = 3;
1453 break;
1454 case 5:
1455 swizzle_pipe[0] = 0;
1456 swizzle_pipe[1] = 1;
1457 swizzle_pipe[2] = 2;
1458 swizzle_pipe[3] = 3;
1459 swizzle_pipe[4] = 4;
1460 break;
1461 case 6:
1462 swizzle_pipe[0] = 0;
1463 swizzle_pipe[1] = 2;
1464 swizzle_pipe[2] = 4;
1465 swizzle_pipe[3] = 5;
1466 swizzle_pipe[4] = 1;
1467 swizzle_pipe[5] = 3;
1468 break;
1469 case 7:
1470 swizzle_pipe[0] = 0;
1471 swizzle_pipe[1] = 2;
1472 swizzle_pipe[2] = 4;
1473 swizzle_pipe[3] = 6;
1474 swizzle_pipe[4] = 1;
1475 swizzle_pipe[5] = 3;
1476 swizzle_pipe[6] = 5;
1477 break;
1478 case 8:
1479 swizzle_pipe[0] = 0;
1480 swizzle_pipe[1] = 2;
1481 swizzle_pipe[2] = 4;
1482 swizzle_pipe[3] = 6;
1483 swizzle_pipe[4] = 1;
1484 swizzle_pipe[5] = 3;
1485 swizzle_pipe[6] = 5;
1486 swizzle_pipe[7] = 7;
1487 break;
1488 }
1489
1490 cur_backend = 0;
1491 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
1492 while (((1 << cur_backend) & enabled_backends_mask) == 0)
1493 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
1494
1495 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
1496
1497 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
1498 }
1499
1500 return backend_map;
1501 }
1502
1503 int r600_count_pipe_bits(uint32_t val)
1504 {
1505 int i, ret = 0;
1506
1507 for (i = 0; i < 32; i++) {
1508 ret += val & 1;
1509 val >>= 1;
1510 }
1511 return ret;
1512 }
1513
1514 void r600_gpu_init(struct radeon_device *rdev)
1515 {
1516 u32 tiling_config;
1517 u32 ramcfg;
1518 u32 backend_map;
1519 u32 cc_rb_backend_disable;
1520 u32 cc_gc_shader_pipe_config;
1521 u32 tmp;
1522 int i, j;
1523 u32 sq_config;
1524 u32 sq_gpr_resource_mgmt_1 = 0;
1525 u32 sq_gpr_resource_mgmt_2 = 0;
1526 u32 sq_thread_resource_mgmt = 0;
1527 u32 sq_stack_resource_mgmt_1 = 0;
1528 u32 sq_stack_resource_mgmt_2 = 0;
1529
1530 /* FIXME: implement */
1531 switch (rdev->family) {
1532 case CHIP_R600:
1533 rdev->config.r600.max_pipes = 4;
1534 rdev->config.r600.max_tile_pipes = 8;
1535 rdev->config.r600.max_simds = 4;
1536 rdev->config.r600.max_backends = 4;
1537 rdev->config.r600.max_gprs = 256;
1538 rdev->config.r600.max_threads = 192;
1539 rdev->config.r600.max_stack_entries = 256;
1540 rdev->config.r600.max_hw_contexts = 8;
1541 rdev->config.r600.max_gs_threads = 16;
1542 rdev->config.r600.sx_max_export_size = 128;
1543 rdev->config.r600.sx_max_export_pos_size = 16;
1544 rdev->config.r600.sx_max_export_smx_size = 128;
1545 rdev->config.r600.sq_num_cf_insts = 2;
1546 break;
1547 case CHIP_RV630:
1548 case CHIP_RV635:
1549 rdev->config.r600.max_pipes = 2;
1550 rdev->config.r600.max_tile_pipes = 2;
1551 rdev->config.r600.max_simds = 3;
1552 rdev->config.r600.max_backends = 1;
1553 rdev->config.r600.max_gprs = 128;
1554 rdev->config.r600.max_threads = 192;
1555 rdev->config.r600.max_stack_entries = 128;
1556 rdev->config.r600.max_hw_contexts = 8;
1557 rdev->config.r600.max_gs_threads = 4;
1558 rdev->config.r600.sx_max_export_size = 128;
1559 rdev->config.r600.sx_max_export_pos_size = 16;
1560 rdev->config.r600.sx_max_export_smx_size = 128;
1561 rdev->config.r600.sq_num_cf_insts = 2;
1562 break;
1563 case CHIP_RV610:
1564 case CHIP_RV620:
1565 case CHIP_RS780:
1566 case CHIP_RS880:
1567 rdev->config.r600.max_pipes = 1;
1568 rdev->config.r600.max_tile_pipes = 1;
1569 rdev->config.r600.max_simds = 2;
1570 rdev->config.r600.max_backends = 1;
1571 rdev->config.r600.max_gprs = 128;
1572 rdev->config.r600.max_threads = 192;
1573 rdev->config.r600.max_stack_entries = 128;
1574 rdev->config.r600.max_hw_contexts = 4;
1575 rdev->config.r600.max_gs_threads = 4;
1576 rdev->config.r600.sx_max_export_size = 128;
1577 rdev->config.r600.sx_max_export_pos_size = 16;
1578 rdev->config.r600.sx_max_export_smx_size = 128;
1579 rdev->config.r600.sq_num_cf_insts = 1;
1580 break;
1581 case CHIP_RV670:
1582 rdev->config.r600.max_pipes = 4;
1583 rdev->config.r600.max_tile_pipes = 4;
1584 rdev->config.r600.max_simds = 4;
1585 rdev->config.r600.max_backends = 4;
1586 rdev->config.r600.max_gprs = 192;
1587 rdev->config.r600.max_threads = 192;
1588 rdev->config.r600.max_stack_entries = 256;
1589 rdev->config.r600.max_hw_contexts = 8;
1590 rdev->config.r600.max_gs_threads = 16;
1591 rdev->config.r600.sx_max_export_size = 128;
1592 rdev->config.r600.sx_max_export_pos_size = 16;
1593 rdev->config.r600.sx_max_export_smx_size = 128;
1594 rdev->config.r600.sq_num_cf_insts = 2;
1595 break;
1596 default:
1597 break;
1598 }
1599
1600 /* Initialize HDP */
1601 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1602 WREG32((0x2c14 + j), 0x00000000);
1603 WREG32((0x2c18 + j), 0x00000000);
1604 WREG32((0x2c1c + j), 0x00000000);
1605 WREG32((0x2c20 + j), 0x00000000);
1606 WREG32((0x2c24 + j), 0x00000000);
1607 }
1608
1609 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1610
1611 /* Setup tiling */
1612 tiling_config = 0;
1613 ramcfg = RREG32(RAMCFG);
1614 switch (rdev->config.r600.max_tile_pipes) {
1615 case 1:
1616 tiling_config |= PIPE_TILING(0);
1617 break;
1618 case 2:
1619 tiling_config |= PIPE_TILING(1);
1620 break;
1621 case 4:
1622 tiling_config |= PIPE_TILING(2);
1623 break;
1624 case 8:
1625 tiling_config |= PIPE_TILING(3);
1626 break;
1627 default:
1628 break;
1629 }
1630 rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes;
1631 rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
1632 tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
1633 tiling_config |= GROUP_SIZE((ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
1634 if ((ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT)
1635 rdev->config.r600.tiling_group_size = 512;
1636 else
1637 rdev->config.r600.tiling_group_size = 256;
1638 tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
1639 if (tmp > 3) {
1640 tiling_config |= ROW_TILING(3);
1641 tiling_config |= SAMPLE_SPLIT(3);
1642 } else {
1643 tiling_config |= ROW_TILING(tmp);
1644 tiling_config |= SAMPLE_SPLIT(tmp);
1645 }
1646 tiling_config |= BANK_SWAPS(1);
1647
1648 cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000;
1649 cc_rb_backend_disable |=
1650 BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << rdev->config.r600.max_backends) & R6XX_MAX_BACKENDS_MASK);
1651
1652 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00;
1653 cc_gc_shader_pipe_config |=
1654 INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << rdev->config.r600.max_pipes) & R6XX_MAX_PIPES_MASK);
1655 cc_gc_shader_pipe_config |=
1656 INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << rdev->config.r600.max_simds) & R6XX_MAX_SIMDS_MASK);
1657
1658 backend_map = r600_get_tile_pipe_to_backend_map(rdev->config.r600.max_tile_pipes,
1659 (R6XX_MAX_BACKENDS -
1660 r600_count_pipe_bits((cc_rb_backend_disable &
1661 R6XX_MAX_BACKENDS_MASK) >> 16)),
1662 (cc_rb_backend_disable >> 16));
1663 rdev->config.r600.tile_config = tiling_config;
1664 tiling_config |= BACKEND_MAP(backend_map);
1665 WREG32(GB_TILING_CONFIG, tiling_config);
1666 WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff);
1667 WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff);
1668
1669 /* Setup pipes */
1670 WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
1671 WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
1672 WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
1673
1674 tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
1675 WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK);
1676 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK);
1677
1678 /* Setup some CP states */
1679 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b)));
1680 WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40)));
1681
1682 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT |
1683 SYNC_WALKER | SYNC_ALIGNER));
1684 /* Setup various GPU states */
1685 if (rdev->family == CHIP_RV670)
1686 WREG32(ARB_GDEC_RD_CNTL, 0x00000021);
1687
1688 tmp = RREG32(SX_DEBUG_1);
1689 tmp |= SMX_EVENT_RELEASE;
1690 if ((rdev->family > CHIP_R600))
1691 tmp |= ENABLE_NEW_SMX_ADDRESS;
1692 WREG32(SX_DEBUG_1, tmp);
1693
1694 if (((rdev->family) == CHIP_R600) ||
1695 ((rdev->family) == CHIP_RV630) ||
1696 ((rdev->family) == CHIP_RV610) ||
1697 ((rdev->family) == CHIP_RV620) ||
1698 ((rdev->family) == CHIP_RS780) ||
1699 ((rdev->family) == CHIP_RS880)) {
1700 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE);
1701 } else {
1702 WREG32(DB_DEBUG, 0);
1703 }
1704 WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) |
1705 DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4)));
1706
1707 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1708 WREG32(VGT_NUM_INSTANCES, 0);
1709
1710 WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
1711 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0));
1712
1713 tmp = RREG32(SQ_MS_FIFO_SIZES);
1714 if (((rdev->family) == CHIP_RV610) ||
1715 ((rdev->family) == CHIP_RV620) ||
1716 ((rdev->family) == CHIP_RS780) ||
1717 ((rdev->family) == CHIP_RS880)) {
1718 tmp = (CACHE_FIFO_SIZE(0xa) |
1719 FETCH_FIFO_HIWATER(0xa) |
1720 DONE_FIFO_HIWATER(0xe0) |
1721 ALU_UPDATE_FIFO_HIWATER(0x8));
1722 } else if (((rdev->family) == CHIP_R600) ||
1723 ((rdev->family) == CHIP_RV630)) {
1724 tmp &= ~DONE_FIFO_HIWATER(0xff);
1725 tmp |= DONE_FIFO_HIWATER(0x4);
1726 }
1727 WREG32(SQ_MS_FIFO_SIZES, tmp);
1728
1729 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
1730 * should be adjusted as needed by the 2D/3D drivers. This just sets default values
1731 */
1732 sq_config = RREG32(SQ_CONFIG);
1733 sq_config &= ~(PS_PRIO(3) |
1734 VS_PRIO(3) |
1735 GS_PRIO(3) |
1736 ES_PRIO(3));
1737 sq_config |= (DX9_CONSTS |
1738 VC_ENABLE |
1739 PS_PRIO(0) |
1740 VS_PRIO(1) |
1741 GS_PRIO(2) |
1742 ES_PRIO(3));
1743
1744 if ((rdev->family) == CHIP_R600) {
1745 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) |
1746 NUM_VS_GPRS(124) |
1747 NUM_CLAUSE_TEMP_GPRS(4));
1748 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) |
1749 NUM_ES_GPRS(0));
1750 sq_thread_resource_mgmt = (NUM_PS_THREADS(136) |
1751 NUM_VS_THREADS(48) |
1752 NUM_GS_THREADS(4) |
1753 NUM_ES_THREADS(4));
1754 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) |
1755 NUM_VS_STACK_ENTRIES(128));
1756 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) |
1757 NUM_ES_STACK_ENTRIES(0));
1758 } else if (((rdev->family) == CHIP_RV610) ||
1759 ((rdev->family) == CHIP_RV620) ||
1760 ((rdev->family) == CHIP_RS780) ||
1761 ((rdev->family) == CHIP_RS880)) {
1762 /* no vertex cache */
1763 sq_config &= ~VC_ENABLE;
1764
1765 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1766 NUM_VS_GPRS(44) |
1767 NUM_CLAUSE_TEMP_GPRS(2));
1768 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1769 NUM_ES_GPRS(17));
1770 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1771 NUM_VS_THREADS(78) |
1772 NUM_GS_THREADS(4) |
1773 NUM_ES_THREADS(31));
1774 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1775 NUM_VS_STACK_ENTRIES(40));
1776 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1777 NUM_ES_STACK_ENTRIES(16));
1778 } else if (((rdev->family) == CHIP_RV630) ||
1779 ((rdev->family) == CHIP_RV635)) {
1780 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1781 NUM_VS_GPRS(44) |
1782 NUM_CLAUSE_TEMP_GPRS(2));
1783 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) |
1784 NUM_ES_GPRS(18));
1785 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1786 NUM_VS_THREADS(78) |
1787 NUM_GS_THREADS(4) |
1788 NUM_ES_THREADS(31));
1789 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1790 NUM_VS_STACK_ENTRIES(40));
1791 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1792 NUM_ES_STACK_ENTRIES(16));
1793 } else if ((rdev->family) == CHIP_RV670) {
1794 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1795 NUM_VS_GPRS(44) |
1796 NUM_CLAUSE_TEMP_GPRS(2));
1797 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1798 NUM_ES_GPRS(17));
1799 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1800 NUM_VS_THREADS(78) |
1801 NUM_GS_THREADS(4) |
1802 NUM_ES_THREADS(31));
1803 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) |
1804 NUM_VS_STACK_ENTRIES(64));
1805 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) |
1806 NUM_ES_STACK_ENTRIES(64));
1807 }
1808
1809 WREG32(SQ_CONFIG, sq_config);
1810 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
1811 WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
1812 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1813 WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
1814 WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
1815
1816 if (((rdev->family) == CHIP_RV610) ||
1817 ((rdev->family) == CHIP_RV620) ||
1818 ((rdev->family) == CHIP_RS780) ||
1819 ((rdev->family) == CHIP_RS880)) {
1820 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY));
1821 } else {
1822 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC));
1823 }
1824
1825 /* More default values. 2D/3D driver should adjust as needed */
1826 WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) |
1827 S1_X(0x4) | S1_Y(0xc)));
1828 WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) |
1829 S1_X(0x2) | S1_Y(0x2) |
1830 S2_X(0xa) | S2_Y(0x6) |
1831 S3_X(0x6) | S3_Y(0xa)));
1832 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) |
1833 S1_X(0x4) | S1_Y(0xc) |
1834 S2_X(0x1) | S2_Y(0x6) |
1835 S3_X(0xa) | S3_Y(0xe)));
1836 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) |
1837 S5_X(0x0) | S5_Y(0x0) |
1838 S6_X(0xb) | S6_Y(0x4) |
1839 S7_X(0x7) | S7_Y(0x8)));
1840
1841 WREG32(VGT_STRMOUT_EN, 0);
1842 tmp = rdev->config.r600.max_pipes * 16;
1843 switch (rdev->family) {
1844 case CHIP_RV610:
1845 case CHIP_RV620:
1846 case CHIP_RS780:
1847 case CHIP_RS880:
1848 tmp += 32;
1849 break;
1850 case CHIP_RV670:
1851 tmp += 128;
1852 break;
1853 default:
1854 break;
1855 }
1856 if (tmp > 256) {
1857 tmp = 256;
1858 }
1859 WREG32(VGT_ES_PER_GS, 128);
1860 WREG32(VGT_GS_PER_ES, tmp);
1861 WREG32(VGT_GS_PER_VS, 2);
1862 WREG32(VGT_GS_VERTEX_REUSE, 16);
1863
1864 /* more default values. 2D/3D driver should adjust as needed */
1865 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1866 WREG32(VGT_STRMOUT_EN, 0);
1867 WREG32(SX_MISC, 0);
1868 WREG32(PA_SC_MODE_CNTL, 0);
1869 WREG32(PA_SC_AA_CONFIG, 0);
1870 WREG32(PA_SC_LINE_STIPPLE, 0);
1871 WREG32(SPI_INPUT_Z, 0);
1872 WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
1873 WREG32(CB_COLOR7_FRAG, 0);
1874
1875 /* Clear render buffer base addresses */
1876 WREG32(CB_COLOR0_BASE, 0);
1877 WREG32(CB_COLOR1_BASE, 0);
1878 WREG32(CB_COLOR2_BASE, 0);
1879 WREG32(CB_COLOR3_BASE, 0);
1880 WREG32(CB_COLOR4_BASE, 0);
1881 WREG32(CB_COLOR5_BASE, 0);
1882 WREG32(CB_COLOR6_BASE, 0);
1883 WREG32(CB_COLOR7_BASE, 0);
1884 WREG32(CB_COLOR7_FRAG, 0);
1885
1886 switch (rdev->family) {
1887 case CHIP_RV610:
1888 case CHIP_RV620:
1889 case CHIP_RS780:
1890 case CHIP_RS880:
1891 tmp = TC_L2_SIZE(8);
1892 break;
1893 case CHIP_RV630:
1894 case CHIP_RV635:
1895 tmp = TC_L2_SIZE(4);
1896 break;
1897 case CHIP_R600:
1898 tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT;
1899 break;
1900 default:
1901 tmp = TC_L2_SIZE(0);
1902 break;
1903 }
1904 WREG32(TC_CNTL, tmp);
1905
1906 tmp = RREG32(HDP_HOST_PATH_CNTL);
1907 WREG32(HDP_HOST_PATH_CNTL, tmp);
1908
1909 tmp = RREG32(ARB_POP);
1910 tmp |= ENABLE_TC128;
1911 WREG32(ARB_POP, tmp);
1912
1913 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1914 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
1915 NUM_CLIP_SEQ(3)));
1916 WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095));
1917 }
1918
1919
1920 /*
1921 * Indirect registers accessor
1922 */
1923 u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg)
1924 {
1925 u32 r;
1926
1927 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1928 (void)RREG32(PCIE_PORT_INDEX);
1929 r = RREG32(PCIE_PORT_DATA);
1930 return r;
1931 }
1932
1933 void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
1934 {
1935 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1936 (void)RREG32(PCIE_PORT_INDEX);
1937 WREG32(PCIE_PORT_DATA, (v));
1938 (void)RREG32(PCIE_PORT_DATA);
1939 }
1940
1941 /*
1942 * CP & Ring
1943 */
1944 void r600_cp_stop(struct radeon_device *rdev)
1945 {
1946 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
1947 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1948 WREG32(SCRATCH_UMSK, 0);
1949 }
1950
1951 int r600_init_microcode(struct radeon_device *rdev)
1952 {
1953 struct platform_device *pdev;
1954 const char *chip_name;
1955 const char *rlc_chip_name;
1956 size_t pfp_req_size, me_req_size, rlc_req_size;
1957 char fw_name[30];
1958 int err;
1959
1960 DRM_DEBUG("\n");
1961
1962 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
1963 err = IS_ERR(pdev);
1964 if (err) {
1965 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
1966 return -EINVAL;
1967 }
1968
1969 switch (rdev->family) {
1970 case CHIP_R600:
1971 chip_name = "R600";
1972 rlc_chip_name = "R600";
1973 break;
1974 case CHIP_RV610:
1975 chip_name = "RV610";
1976 rlc_chip_name = "R600";
1977 break;
1978 case CHIP_RV630:
1979 chip_name = "RV630";
1980 rlc_chip_name = "R600";
1981 break;
1982 case CHIP_RV620:
1983 chip_name = "RV620";
1984 rlc_chip_name = "R600";
1985 break;
1986 case CHIP_RV635:
1987 chip_name = "RV635";
1988 rlc_chip_name = "R600";
1989 break;
1990 case CHIP_RV670:
1991 chip_name = "RV670";
1992 rlc_chip_name = "R600";
1993 break;
1994 case CHIP_RS780:
1995 case CHIP_RS880:
1996 chip_name = "RS780";
1997 rlc_chip_name = "R600";
1998 break;
1999 case CHIP_RV770:
2000 chip_name = "RV770";
2001 rlc_chip_name = "R700";
2002 break;
2003 case CHIP_RV730:
2004 case CHIP_RV740:
2005 chip_name = "RV730";
2006 rlc_chip_name = "R700";
2007 break;
2008 case CHIP_RV710:
2009 chip_name = "RV710";
2010 rlc_chip_name = "R700";
2011 break;
2012 case CHIP_CEDAR:
2013 chip_name = "CEDAR";
2014 rlc_chip_name = "CEDAR";
2015 break;
2016 case CHIP_REDWOOD:
2017 chip_name = "REDWOOD";
2018 rlc_chip_name = "REDWOOD";
2019 break;
2020 case CHIP_JUNIPER:
2021 chip_name = "JUNIPER";
2022 rlc_chip_name = "JUNIPER";
2023 break;
2024 case CHIP_CYPRESS:
2025 case CHIP_HEMLOCK:
2026 chip_name = "CYPRESS";
2027 rlc_chip_name = "CYPRESS";
2028 break;
2029 case CHIP_PALM:
2030 chip_name = "PALM";
2031 rlc_chip_name = "SUMO";
2032 break;
2033 case CHIP_SUMO:
2034 chip_name = "SUMO";
2035 rlc_chip_name = "SUMO";
2036 break;
2037 case CHIP_SUMO2:
2038 chip_name = "SUMO2";
2039 rlc_chip_name = "SUMO";
2040 break;
2041 default: BUG();
2042 }
2043
2044 if (rdev->family >= CHIP_CEDAR) {
2045 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
2046 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
2047 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
2048 } else if (rdev->family >= CHIP_RV770) {
2049 pfp_req_size = R700_PFP_UCODE_SIZE * 4;
2050 me_req_size = R700_PM4_UCODE_SIZE * 4;
2051 rlc_req_size = R700_RLC_UCODE_SIZE * 4;
2052 } else {
2053 pfp_req_size = PFP_UCODE_SIZE * 4;
2054 me_req_size = PM4_UCODE_SIZE * 12;
2055 rlc_req_size = RLC_UCODE_SIZE * 4;
2056 }
2057
2058 DRM_INFO("Loading %s Microcode\n", chip_name);
2059
2060 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
2061 err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
2062 if (err)
2063 goto out;
2064 if (rdev->pfp_fw->size != pfp_req_size) {
2065 printk(KERN_ERR
2066 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
2067 rdev->pfp_fw->size, fw_name);
2068 err = -EINVAL;
2069 goto out;
2070 }
2071
2072 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
2073 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
2074 if (err)
2075 goto out;
2076 if (rdev->me_fw->size != me_req_size) {
2077 printk(KERN_ERR
2078 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
2079 rdev->me_fw->size, fw_name);
2080 err = -EINVAL;
2081 }
2082
2083 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
2084 err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev);
2085 if (err)
2086 goto out;
2087 if (rdev->rlc_fw->size != rlc_req_size) {
2088 printk(KERN_ERR
2089 "r600_rlc: Bogus length %zu in firmware \"%s\"\n",
2090 rdev->rlc_fw->size, fw_name);
2091 err = -EINVAL;
2092 }
2093
2094 out:
2095 platform_device_unregister(pdev);
2096
2097 if (err) {
2098 if (err != -EINVAL)
2099 printk(KERN_ERR
2100 "r600_cp: Failed to load firmware \"%s\"\n",
2101 fw_name);
2102 release_firmware(rdev->pfp_fw);
2103 rdev->pfp_fw = NULL;
2104 release_firmware(rdev->me_fw);
2105 rdev->me_fw = NULL;
2106 release_firmware(rdev->rlc_fw);
2107 rdev->rlc_fw = NULL;
2108 }
2109 return err;
2110 }
2111
2112 static int r600_cp_load_microcode(struct radeon_device *rdev)
2113 {
2114 const __be32 *fw_data;
2115 int i;
2116
2117 if (!rdev->me_fw || !rdev->pfp_fw)
2118 return -EINVAL;
2119
2120 r600_cp_stop(rdev);
2121
2122 WREG32(CP_RB_CNTL,
2123 #ifdef __BIG_ENDIAN
2124 BUF_SWAP_32BIT |
2125 #endif
2126 RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
2127
2128 /* Reset cp */
2129 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2130 RREG32(GRBM_SOFT_RESET);
2131 mdelay(15);
2132 WREG32(GRBM_SOFT_RESET, 0);
2133
2134 WREG32(CP_ME_RAM_WADDR, 0);
2135
2136 fw_data = (const __be32 *)rdev->me_fw->data;
2137 WREG32(CP_ME_RAM_WADDR, 0);
2138 for (i = 0; i < PM4_UCODE_SIZE * 3; i++)
2139 WREG32(CP_ME_RAM_DATA,
2140 be32_to_cpup(fw_data++));
2141
2142 fw_data = (const __be32 *)rdev->pfp_fw->data;
2143 WREG32(CP_PFP_UCODE_ADDR, 0);
2144 for (i = 0; i < PFP_UCODE_SIZE; i++)
2145 WREG32(CP_PFP_UCODE_DATA,
2146 be32_to_cpup(fw_data++));
2147
2148 WREG32(CP_PFP_UCODE_ADDR, 0);
2149 WREG32(CP_ME_RAM_WADDR, 0);
2150 WREG32(CP_ME_RAM_RADDR, 0);
2151 return 0;
2152 }
2153
2154 int r600_cp_start(struct radeon_device *rdev)
2155 {
2156 int r;
2157 uint32_t cp_me;
2158
2159 r = radeon_ring_lock(rdev, 7);
2160 if (r) {
2161 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
2162 return r;
2163 }
2164 radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5));
2165 radeon_ring_write(rdev, 0x1);
2166 if (rdev->family >= CHIP_RV770) {
2167 radeon_ring_write(rdev, 0x0);
2168 radeon_ring_write(rdev, rdev->config.rv770.max_hw_contexts - 1);
2169 } else {
2170 radeon_ring_write(rdev, 0x3);
2171 radeon_ring_write(rdev, rdev->config.r600.max_hw_contexts - 1);
2172 }
2173 radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
2174 radeon_ring_write(rdev, 0);
2175 radeon_ring_write(rdev, 0);
2176 radeon_ring_unlock_commit(rdev);
2177
2178 cp_me = 0xff;
2179 WREG32(R_0086D8_CP_ME_CNTL, cp_me);
2180 return 0;
2181 }
2182
2183 int r600_cp_resume(struct radeon_device *rdev)
2184 {
2185 u32 tmp;
2186 u32 rb_bufsz;
2187 int r;
2188
2189 /* Reset cp */
2190 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2191 RREG32(GRBM_SOFT_RESET);
2192 mdelay(15);
2193 WREG32(GRBM_SOFT_RESET, 0);
2194
2195 /* Set ring buffer size */
2196 rb_bufsz = drm_order(rdev->cp.ring_size / 8);
2197 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2198 #ifdef __BIG_ENDIAN
2199 tmp |= BUF_SWAP_32BIT;
2200 #endif
2201 WREG32(CP_RB_CNTL, tmp);
2202 WREG32(CP_SEM_WAIT_TIMER, 0x4);
2203
2204 /* Set the write pointer delay */
2205 WREG32(CP_RB_WPTR_DELAY, 0);
2206
2207 /* Initialize the ring buffer's read and write pointers */
2208 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
2209 WREG32(CP_RB_RPTR_WR, 0);
2210 rdev->cp.wptr = 0;
2211 WREG32(CP_RB_WPTR, rdev->cp.wptr);
2212
2213 /* set the wb address whether it's enabled or not */
2214 WREG32(CP_RB_RPTR_ADDR,
2215 #ifdef __BIG_ENDIAN
2216 RB_RPTR_SWAP(2) |
2217 #endif
2218 ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC));
2219 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
2220 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
2221
2222 if (rdev->wb.enabled)
2223 WREG32(SCRATCH_UMSK, 0xff);
2224 else {
2225 tmp |= RB_NO_UPDATE;
2226 WREG32(SCRATCH_UMSK, 0);
2227 }
2228
2229 mdelay(1);
2230 WREG32(CP_RB_CNTL, tmp);
2231
2232 WREG32(CP_RB_BASE, rdev->cp.gpu_addr >> 8);
2233 WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
2234
2235 rdev->cp.rptr = RREG32(CP_RB_RPTR);
2236
2237 r600_cp_start(rdev);
2238 rdev->cp.ready = true;
2239 r = radeon_ring_test(rdev);
2240 if (r) {
2241 rdev->cp.ready = false;
2242 return r;
2243 }
2244 return 0;
2245 }
2246
2247 void r600_cp_commit(struct radeon_device *rdev)
2248 {
2249 WREG32(CP_RB_WPTR, rdev->cp.wptr);
2250 (void)RREG32(CP_RB_WPTR);
2251 }
2252
2253 void r600_ring_init(struct radeon_device *rdev, unsigned ring_size)
2254 {
2255 u32 rb_bufsz;
2256
2257 /* Align ring size */
2258 rb_bufsz = drm_order(ring_size / 8);
2259 ring_size = (1 << (rb_bufsz + 1)) * 4;
2260 rdev->cp.ring_size = ring_size;
2261 rdev->cp.align_mask = 16 - 1;
2262 }
2263
2264 void r600_cp_fini(struct radeon_device *rdev)
2265 {
2266 r600_cp_stop(rdev);
2267 radeon_ring_fini(rdev);
2268 }
2269
2270
2271 /*
2272 * GPU scratch registers helpers function.
2273 */
2274 void r600_scratch_init(struct radeon_device *rdev)
2275 {
2276 int i;
2277
2278 rdev->scratch.num_reg = 7;
2279 rdev->scratch.reg_base = SCRATCH_REG0;
2280 for (i = 0; i < rdev->scratch.num_reg; i++) {
2281 rdev->scratch.free[i] = true;
2282 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
2283 }
2284 }
2285
2286 int r600_ring_test(struct radeon_device *rdev)
2287 {
2288 uint32_t scratch;
2289 uint32_t tmp = 0;
2290 unsigned i;
2291 int r;
2292
2293 r = radeon_scratch_get(rdev, &scratch);
2294 if (r) {
2295 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
2296 return r;
2297 }
2298 WREG32(scratch, 0xCAFEDEAD);
2299 r = radeon_ring_lock(rdev, 3);
2300 if (r) {
2301 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
2302 radeon_scratch_free(rdev, scratch);
2303 return r;
2304 }
2305 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2306 radeon_ring_write(rdev, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2307 radeon_ring_write(rdev, 0xDEADBEEF);
2308 radeon_ring_unlock_commit(rdev);
2309 for (i = 0; i < rdev->usec_timeout; i++) {
2310 tmp = RREG32(scratch);
2311 if (tmp == 0xDEADBEEF)
2312 break;
2313 DRM_UDELAY(1);
2314 }
2315 if (i < rdev->usec_timeout) {
2316 DRM_INFO("ring test succeeded in %d usecs\n", i);
2317 } else {
2318 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
2319 scratch, tmp);
2320 r = -EINVAL;
2321 }
2322 radeon_scratch_free(rdev, scratch);
2323 return r;
2324 }
2325
2326 void r600_fence_ring_emit(struct radeon_device *rdev,
2327 struct radeon_fence *fence)
2328 {
2329 if (rdev->wb.use_event) {
2330 u64 addr = rdev->wb.gpu_addr + R600_WB_EVENT_OFFSET +
2331 (u64)(rdev->fence_drv.scratch_reg - rdev->scratch.reg_base);
2332 /* EVENT_WRITE_EOP - flush caches, send int */
2333 radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
2334 radeon_ring_write(rdev, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5));
2335 radeon_ring_write(rdev, addr & 0xffffffff);
2336 radeon_ring_write(rdev, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
2337 radeon_ring_write(rdev, fence->seq);
2338 radeon_ring_write(rdev, 0);
2339 } else {
2340 radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE, 0));
2341 radeon_ring_write(rdev, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0));
2342 /* wait for 3D idle clean */
2343 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2344 radeon_ring_write(rdev, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2345 radeon_ring_write(rdev, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit);
2346 /* Emit fence sequence & fire IRQ */
2347 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2348 radeon_ring_write(rdev, ((rdev->fence_drv.scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2349 radeon_ring_write(rdev, fence->seq);
2350 /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */
2351 radeon_ring_write(rdev, PACKET0(CP_INT_STATUS, 0));
2352 radeon_ring_write(rdev, RB_INT_STAT);
2353 }
2354 }
2355
2356 int r600_copy_blit(struct radeon_device *rdev,
2357 uint64_t src_offset,
2358 uint64_t dst_offset,
2359 unsigned num_gpu_pages,
2360 struct radeon_fence *fence)
2361 {
2362 int r;
2363
2364 mutex_lock(&rdev->r600_blit.mutex);
2365 rdev->r600_blit.vb_ib = NULL;
2366 r = r600_blit_prepare_copy(rdev, num_gpu_pages * RADEON_GPU_PAGE_SIZE);
2367 if (r) {
2368 if (rdev->r600_blit.vb_ib)
2369 radeon_ib_free(rdev, &rdev->r600_blit.vb_ib);
2370 mutex_unlock(&rdev->r600_blit.mutex);
2371 return r;
2372 }
2373 r600_kms_blit_copy(rdev, src_offset, dst_offset, num_gpu_pages * RADEON_GPU_PAGE_SIZE);
2374 r600_blit_done_copy(rdev, fence);
2375 mutex_unlock(&rdev->r600_blit.mutex);
2376 return 0;
2377 }
2378
2379 int r600_set_surface_reg(struct radeon_device *rdev, int reg,
2380 uint32_t tiling_flags, uint32_t pitch,
2381 uint32_t offset, uint32_t obj_size)
2382 {
2383 /* FIXME: implement */
2384 return 0;
2385 }
2386
2387 void r600_clear_surface_reg(struct radeon_device *rdev, int reg)
2388 {
2389 /* FIXME: implement */
2390 }
2391
2392 int r600_startup(struct radeon_device *rdev)
2393 {
2394 int r;
2395
2396 /* enable pcie gen2 link */
2397 r600_pcie_gen2_enable(rdev);
2398
2399 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
2400 r = r600_init_microcode(rdev);
2401 if (r) {
2402 DRM_ERROR("Failed to load firmware!\n");
2403 return r;
2404 }
2405 }
2406
2407 r600_mc_program(rdev);
2408 if (rdev->flags & RADEON_IS_AGP) {
2409 r600_agp_enable(rdev);
2410 } else {
2411 r = r600_pcie_gart_enable(rdev);
2412 if (r)
2413 return r;
2414 }
2415 r600_gpu_init(rdev);
2416 r = r600_blit_init(rdev);
2417 if (r) {
2418 r600_blit_fini(rdev);
2419 rdev->asic->copy = NULL;
2420 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
2421 }
2422
2423 /* allocate wb buffer */
2424 r = radeon_wb_init(rdev);
2425 if (r)
2426 return r;
2427
2428 /* Enable IRQ */
2429 r = r600_irq_init(rdev);
2430 if (r) {
2431 DRM_ERROR("radeon: IH init failed (%d).\n", r);
2432 radeon_irq_kms_fini(rdev);
2433 return r;
2434 }
2435 r600_irq_set(rdev);
2436
2437 r = radeon_ring_init(rdev, rdev->cp.ring_size);
2438 if (r)
2439 return r;
2440 r = r600_cp_load_microcode(rdev);
2441 if (r)
2442 return r;
2443 r = r600_cp_resume(rdev);
2444 if (r)
2445 return r;
2446
2447 return 0;
2448 }
2449
2450 void r600_vga_set_state(struct radeon_device *rdev, bool state)
2451 {
2452 uint32_t temp;
2453
2454 temp = RREG32(CONFIG_CNTL);
2455 if (state == false) {
2456 temp &= ~(1<<0);
2457 temp |= (1<<1);
2458 } else {
2459 temp &= ~(1<<1);
2460 }
2461 WREG32(CONFIG_CNTL, temp);
2462 }
2463
2464 int r600_resume(struct radeon_device *rdev)
2465 {
2466 int r;
2467
2468 /* Do not reset GPU before posting, on r600 hw unlike on r500 hw,
2469 * posting will perform necessary task to bring back GPU into good
2470 * shape.
2471 */
2472 /* post card */
2473 atom_asic_init(rdev->mode_info.atom_context);
2474
2475 r = r600_startup(rdev);
2476 if (r) {
2477 DRM_ERROR("r600 startup failed on resume\n");
2478 return r;
2479 }
2480
2481 r = r600_ib_test(rdev);
2482 if (r) {
2483 DRM_ERROR("radeon: failed testing IB (%d).\n", r);
2484 return r;
2485 }
2486
2487 r = r600_audio_init(rdev);
2488 if (r) {
2489 DRM_ERROR("radeon: audio resume failed\n");
2490 return r;
2491 }
2492
2493 return r;
2494 }
2495
2496 int r600_suspend(struct radeon_device *rdev)
2497 {
2498 int r;
2499
2500 r600_audio_fini(rdev);
2501 /* FIXME: we should wait for ring to be empty */
2502 r600_cp_stop(rdev);
2503 rdev->cp.ready = false;
2504 r600_irq_suspend(rdev);
2505 radeon_wb_disable(rdev);
2506 r600_pcie_gart_disable(rdev);
2507 /* unpin shaders bo */
2508 if (rdev->r600_blit.shader_obj) {
2509 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
2510 if (!r) {
2511 radeon_bo_unpin(rdev->r600_blit.shader_obj);
2512 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
2513 }
2514 }
2515 return 0;
2516 }
2517
2518 /* Plan is to move initialization in that function and use
2519 * helper function so that radeon_device_init pretty much
2520 * do nothing more than calling asic specific function. This
2521 * should also allow to remove a bunch of callback function
2522 * like vram_info.
2523 */
2524 int r600_init(struct radeon_device *rdev)
2525 {
2526 int r;
2527
2528 if (r600_debugfs_mc_info_init(rdev)) {
2529 DRM_ERROR("Failed to register debugfs file for mc !\n");
2530 }
2531 /* This don't do much */
2532 r = radeon_gem_init(rdev);
2533 if (r)
2534 return r;
2535 /* Read BIOS */
2536 if (!radeon_get_bios(rdev)) {
2537 if (ASIC_IS_AVIVO(rdev))
2538 return -EINVAL;
2539 }
2540 /* Must be an ATOMBIOS */
2541 if (!rdev->is_atom_bios) {
2542 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
2543 return -EINVAL;
2544 }
2545 r = radeon_atombios_init(rdev);
2546 if (r)
2547 return r;
2548 /* Post card if necessary */
2549 if (!radeon_card_posted(rdev)) {
2550 if (!rdev->bios) {
2551 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
2552 return -EINVAL;
2553 }
2554 DRM_INFO("GPU not posted. posting now...\n");
2555 atom_asic_init(rdev->mode_info.atom_context);
2556 }
2557 /* Initialize scratch registers */
2558 r600_scratch_init(rdev);
2559 /* Initialize surface registers */
2560 radeon_surface_init(rdev);
2561 /* Initialize clocks */
2562 radeon_get_clock_info(rdev->ddev);
2563 /* Fence driver */
2564 r = radeon_fence_driver_init(rdev);
2565 if (r)
2566 return r;
2567 if (rdev->flags & RADEON_IS_AGP) {
2568 r = radeon_agp_init(rdev);
2569 if (r)
2570 radeon_agp_disable(rdev);
2571 }
2572 r = r600_mc_init(rdev);
2573 if (r)
2574 return r;
2575 /* Memory manager */
2576 r = radeon_bo_init(rdev);
2577 if (r)
2578 return r;
2579
2580 r = radeon_irq_kms_init(rdev);
2581 if (r)
2582 return r;
2583
2584 rdev->cp.ring_obj = NULL;
2585 r600_ring_init(rdev, 1024 * 1024);
2586
2587 rdev->ih.ring_obj = NULL;
2588 r600_ih_ring_init(rdev, 64 * 1024);
2589
2590 r = r600_pcie_gart_init(rdev);
2591 if (r)
2592 return r;
2593
2594 rdev->accel_working = true;
2595 r = r600_startup(rdev);
2596 if (r) {
2597 dev_err(rdev->dev, "disabling GPU acceleration\n");
2598 r600_cp_fini(rdev);
2599 r600_irq_fini(rdev);
2600 radeon_wb_fini(rdev);
2601 radeon_irq_kms_fini(rdev);
2602 r600_pcie_gart_fini(rdev);
2603 rdev->accel_working = false;
2604 }
2605 if (rdev->accel_working) {
2606 r = radeon_ib_pool_init(rdev);
2607 if (r) {
2608 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
2609 rdev->accel_working = false;
2610 } else {
2611 r = r600_ib_test(rdev);
2612 if (r) {
2613 dev_err(rdev->dev, "IB test failed (%d).\n", r);
2614 rdev->accel_working = false;
2615 }
2616 }
2617 }
2618
2619 r = r600_audio_init(rdev);
2620 if (r)
2621 return r; /* TODO error handling */
2622 return 0;
2623 }
2624
2625 void r600_fini(struct radeon_device *rdev)
2626 {
2627 r600_audio_fini(rdev);
2628 r600_blit_fini(rdev);
2629 r600_cp_fini(rdev);
2630 r600_irq_fini(rdev);
2631 radeon_wb_fini(rdev);
2632 radeon_ib_pool_fini(rdev);
2633 radeon_irq_kms_fini(rdev);
2634 r600_pcie_gart_fini(rdev);
2635 radeon_agp_fini(rdev);
2636 radeon_gem_fini(rdev);
2637 radeon_fence_driver_fini(rdev);
2638 radeon_bo_fini(rdev);
2639 radeon_atombios_fini(rdev);
2640 kfree(rdev->bios);
2641 rdev->bios = NULL;
2642 }
2643
2644
2645 /*
2646 * CS stuff
2647 */
2648 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
2649 {
2650 /* FIXME: implement */
2651 radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
2652 radeon_ring_write(rdev,
2653 #ifdef __BIG_ENDIAN
2654 (2 << 0) |
2655 #endif
2656 (ib->gpu_addr & 0xFFFFFFFC));
2657 radeon_ring_write(rdev, upper_32_bits(ib->gpu_addr) & 0xFF);
2658 radeon_ring_write(rdev, ib->length_dw);
2659 }
2660
2661 int r600_ib_test(struct radeon_device *rdev)
2662 {
2663 struct radeon_ib *ib;
2664 uint32_t scratch;
2665 uint32_t tmp = 0;
2666 unsigned i;
2667 int r;
2668
2669 r = radeon_scratch_get(rdev, &scratch);
2670 if (r) {
2671 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
2672 return r;
2673 }
2674 WREG32(scratch, 0xCAFEDEAD);
2675 r = radeon_ib_get(rdev, &ib);
2676 if (r) {
2677 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
2678 return r;
2679 }
2680 ib->ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
2681 ib->ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2682 ib->ptr[2] = 0xDEADBEEF;
2683 ib->ptr[3] = PACKET2(0);
2684 ib->ptr[4] = PACKET2(0);
2685 ib->ptr[5] = PACKET2(0);
2686 ib->ptr[6] = PACKET2(0);
2687 ib->ptr[7] = PACKET2(0);
2688 ib->ptr[8] = PACKET2(0);
2689 ib->ptr[9] = PACKET2(0);
2690 ib->ptr[10] = PACKET2(0);
2691 ib->ptr[11] = PACKET2(0);
2692 ib->ptr[12] = PACKET2(0);
2693 ib->ptr[13] = PACKET2(0);
2694 ib->ptr[14] = PACKET2(0);
2695 ib->ptr[15] = PACKET2(0);
2696 ib->length_dw = 16;
2697 r = radeon_ib_schedule(rdev, ib);
2698 if (r) {
2699 radeon_scratch_free(rdev, scratch);
2700 radeon_ib_free(rdev, &ib);
2701 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
2702 return r;
2703 }
2704 r = radeon_fence_wait(ib->fence, false);
2705 if (r) {
2706 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
2707 return r;
2708 }
2709 for (i = 0; i < rdev->usec_timeout; i++) {
2710 tmp = RREG32(scratch);
2711 if (tmp == 0xDEADBEEF)
2712 break;
2713 DRM_UDELAY(1);
2714 }
2715 if (i < rdev->usec_timeout) {
2716 DRM_INFO("ib test succeeded in %u usecs\n", i);
2717 } else {
2718 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
2719 scratch, tmp);
2720 r = -EINVAL;
2721 }
2722 radeon_scratch_free(rdev, scratch);
2723 radeon_ib_free(rdev, &ib);
2724 return r;
2725 }
2726
2727 /*
2728 * Interrupts
2729 *
2730 * Interrupts use a ring buffer on r6xx/r7xx hardware. It works pretty
2731 * the same as the CP ring buffer, but in reverse. Rather than the CPU
2732 * writing to the ring and the GPU consuming, the GPU writes to the ring
2733 * and host consumes. As the host irq handler processes interrupts, it
2734 * increments the rptr. When the rptr catches up with the wptr, all the
2735 * current interrupts have been processed.
2736 */
2737
2738 void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size)
2739 {
2740 u32 rb_bufsz;
2741
2742 /* Align ring size */
2743 rb_bufsz = drm_order(ring_size / 4);
2744 ring_size = (1 << rb_bufsz) * 4;
2745 rdev->ih.ring_size = ring_size;
2746 rdev->ih.ptr_mask = rdev->ih.ring_size - 1;
2747 rdev->ih.rptr = 0;
2748 }
2749
2750 static int r600_ih_ring_alloc(struct radeon_device *rdev)
2751 {
2752 int r;
2753
2754 /* Allocate ring buffer */
2755 if (rdev->ih.ring_obj == NULL) {
2756 r = radeon_bo_create(rdev, rdev->ih.ring_size,
2757 PAGE_SIZE, true,
2758 RADEON_GEM_DOMAIN_GTT,
2759 &rdev->ih.ring_obj);
2760 if (r) {
2761 DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r);
2762 return r;
2763 }
2764 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
2765 if (unlikely(r != 0))
2766 return r;
2767 r = radeon_bo_pin(rdev->ih.ring_obj,
2768 RADEON_GEM_DOMAIN_GTT,
2769 &rdev->ih.gpu_addr);
2770 if (r) {
2771 radeon_bo_unreserve(rdev->ih.ring_obj);
2772 DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r);
2773 return r;
2774 }
2775 r = radeon_bo_kmap(rdev->ih.ring_obj,
2776 (void **)&rdev->ih.ring);
2777 radeon_bo_unreserve(rdev->ih.ring_obj);
2778 if (r) {
2779 DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r);
2780 return r;
2781 }
2782 }
2783 return 0;
2784 }
2785
2786 static void r600_ih_ring_fini(struct radeon_device *rdev)
2787 {
2788 int r;
2789 if (rdev->ih.ring_obj) {
2790 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
2791 if (likely(r == 0)) {
2792 radeon_bo_kunmap(rdev->ih.ring_obj);
2793 radeon_bo_unpin(rdev->ih.ring_obj);
2794 radeon_bo_unreserve(rdev->ih.ring_obj);
2795 }
2796 radeon_bo_unref(&rdev->ih.ring_obj);
2797 rdev->ih.ring = NULL;
2798 rdev->ih.ring_obj = NULL;
2799 }
2800 }
2801
2802 void r600_rlc_stop(struct radeon_device *rdev)
2803 {
2804
2805 if ((rdev->family >= CHIP_RV770) &&
2806 (rdev->family <= CHIP_RV740)) {
2807 /* r7xx asics need to soft reset RLC before halting */
2808 WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC);
2809 RREG32(SRBM_SOFT_RESET);
2810 udelay(15000);
2811 WREG32(SRBM_SOFT_RESET, 0);
2812 RREG32(SRBM_SOFT_RESET);
2813 }
2814
2815 WREG32(RLC_CNTL, 0);
2816 }
2817
2818 static void r600_rlc_start(struct radeon_device *rdev)
2819 {
2820 WREG32(RLC_CNTL, RLC_ENABLE);
2821 }
2822
2823 static int r600_rlc_init(struct radeon_device *rdev)
2824 {
2825 u32 i;
2826 const __be32 *fw_data;
2827
2828 if (!rdev->rlc_fw)
2829 return -EINVAL;
2830
2831 r600_rlc_stop(rdev);
2832
2833 WREG32(RLC_HB_BASE, 0);
2834 WREG32(RLC_HB_CNTL, 0);
2835 WREG32(RLC_HB_RPTR, 0);
2836 WREG32(RLC_HB_WPTR, 0);
2837 if (rdev->family <= CHIP_CAICOS) {
2838 WREG32(RLC_HB_WPTR_LSB_ADDR, 0);
2839 WREG32(RLC_HB_WPTR_MSB_ADDR, 0);
2840 }
2841 WREG32(RLC_MC_CNTL, 0);
2842 WREG32(RLC_UCODE_CNTL, 0);
2843
2844 fw_data = (const __be32 *)rdev->rlc_fw->data;
2845 if (rdev->family >= CHIP_CAYMAN) {
2846 for (i = 0; i < CAYMAN_RLC_UCODE_SIZE; i++) {
2847 WREG32(RLC_UCODE_ADDR, i);
2848 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2849 }
2850 } else if (rdev->family >= CHIP_CEDAR) {
2851 for (i = 0; i < EVERGREEN_RLC_UCODE_SIZE; i++) {
2852 WREG32(RLC_UCODE_ADDR, i);
2853 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2854 }
2855 } else if (rdev->family >= CHIP_RV770) {
2856 for (i = 0; i < R700_RLC_UCODE_SIZE; i++) {
2857 WREG32(RLC_UCODE_ADDR, i);
2858 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2859 }
2860 } else {
2861 for (i = 0; i < RLC_UCODE_SIZE; i++) {
2862 WREG32(RLC_UCODE_ADDR, i);
2863 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2864 }
2865 }
2866 WREG32(RLC_UCODE_ADDR, 0);
2867
2868 r600_rlc_start(rdev);
2869
2870 return 0;
2871 }
2872
2873 static void r600_enable_interrupts(struct radeon_device *rdev)
2874 {
2875 u32 ih_cntl = RREG32(IH_CNTL);
2876 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
2877
2878 ih_cntl |= ENABLE_INTR;
2879 ih_rb_cntl |= IH_RB_ENABLE;
2880 WREG32(IH_CNTL, ih_cntl);
2881 WREG32(IH_RB_CNTL, ih_rb_cntl);
2882 rdev->ih.enabled = true;
2883 }
2884
2885 void r600_disable_interrupts(struct radeon_device *rdev)
2886 {
2887 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
2888 u32 ih_cntl = RREG32(IH_CNTL);
2889
2890 ih_rb_cntl &= ~IH_RB_ENABLE;
2891 ih_cntl &= ~ENABLE_INTR;
2892 WREG32(IH_RB_CNTL, ih_rb_cntl);
2893 WREG32(IH_CNTL, ih_cntl);
2894 /* set rptr, wptr to 0 */
2895 WREG32(IH_RB_RPTR, 0);
2896 WREG32(IH_RB_WPTR, 0);
2897 rdev->ih.enabled = false;
2898 rdev->ih.wptr = 0;
2899 rdev->ih.rptr = 0;
2900 }
2901
2902 static void r600_disable_interrupt_state(struct radeon_device *rdev)
2903 {
2904 u32 tmp;
2905
2906 WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
2907 WREG32(GRBM_INT_CNTL, 0);
2908 WREG32(DxMODE_INT_MASK, 0);
2909 WREG32(D1GRPH_INTERRUPT_CONTROL, 0);
2910 WREG32(D2GRPH_INTERRUPT_CONTROL, 0);
2911 if (ASIC_IS_DCE3(rdev)) {
2912 WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0);
2913 WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0);
2914 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2915 WREG32(DC_HPD1_INT_CONTROL, tmp);
2916 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2917 WREG32(DC_HPD2_INT_CONTROL, tmp);
2918 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2919 WREG32(DC_HPD3_INT_CONTROL, tmp);
2920 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2921 WREG32(DC_HPD4_INT_CONTROL, tmp);
2922 if (ASIC_IS_DCE32(rdev)) {
2923 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2924 WREG32(DC_HPD5_INT_CONTROL, tmp);
2925 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2926 WREG32(DC_HPD6_INT_CONTROL, tmp);
2927 }
2928 } else {
2929 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
2930 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
2931 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2932 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
2933 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2934 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
2935 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2936 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
2937 }
2938 }
2939
2940 int r600_irq_init(struct radeon_device *rdev)
2941 {
2942 int ret = 0;
2943 int rb_bufsz;
2944 u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
2945
2946 /* allocate ring */
2947 ret = r600_ih_ring_alloc(rdev);
2948 if (ret)
2949 return ret;
2950
2951 /* disable irqs */
2952 r600_disable_interrupts(rdev);
2953
2954 /* init rlc */
2955 ret = r600_rlc_init(rdev);
2956 if (ret) {
2957 r600_ih_ring_fini(rdev);
2958 return ret;
2959 }
2960
2961 /* setup interrupt control */
2962 /* set dummy read address to ring address */
2963 WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8);
2964 interrupt_cntl = RREG32(INTERRUPT_CNTL);
2965 /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
2966 * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
2967 */
2968 interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
2969 /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
2970 interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
2971 WREG32(INTERRUPT_CNTL, interrupt_cntl);
2972
2973 WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
2974 rb_bufsz = drm_order(rdev->ih.ring_size / 4);
2975
2976 ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE |
2977 IH_WPTR_OVERFLOW_CLEAR |
2978 (rb_bufsz << 1));
2979
2980 if (rdev->wb.enabled)
2981 ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;
2982
2983 /* set the writeback address whether it's enabled or not */
2984 WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC);
2985 WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF);
2986
2987 WREG32(IH_RB_CNTL, ih_rb_cntl);
2988
2989 /* set rptr, wptr to 0 */
2990 WREG32(IH_RB_RPTR, 0);
2991 WREG32(IH_RB_WPTR, 0);
2992
2993 /* Default settings for IH_CNTL (disabled at first) */
2994 ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10);
2995 /* RPTR_REARM only works if msi's are enabled */
2996 if (rdev->msi_enabled)
2997 ih_cntl |= RPTR_REARM;
2998
2999 #ifdef __BIG_ENDIAN
3000 ih_cntl |= IH_MC_SWAP(IH_MC_SWAP_32BIT);
3001 #endif
3002 WREG32(IH_CNTL, ih_cntl);
3003
3004 /* force the active interrupt state to all disabled */
3005 if (rdev->family >= CHIP_CEDAR)
3006 evergreen_disable_interrupt_state(rdev);
3007 else
3008 r600_disable_interrupt_state(rdev);
3009
3010 /* enable irqs */
3011 r600_enable_interrupts(rdev);
3012
3013 return ret;
3014 }
3015
3016 void r600_irq_suspend(struct radeon_device *rdev)
3017 {
3018 r600_irq_disable(rdev);
3019 r600_rlc_stop(rdev);
3020 }
3021
3022 void r600_irq_fini(struct radeon_device *rdev)
3023 {
3024 r600_irq_suspend(rdev);
3025 r600_ih_ring_fini(rdev);
3026 }
3027
3028 int r600_irq_set(struct radeon_device *rdev)
3029 {
3030 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
3031 u32 mode_int = 0;
3032 u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0;
3033 u32 grbm_int_cntl = 0;
3034 u32 hdmi1, hdmi2;
3035 u32 d1grph = 0, d2grph = 0;
3036
3037 if (!rdev->irq.installed) {
3038 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
3039 return -EINVAL;
3040 }
3041 /* don't enable anything if the ih is disabled */
3042 if (!rdev->ih.enabled) {
3043 r600_disable_interrupts(rdev);
3044 /* force the active interrupt state to all disabled */
3045 r600_disable_interrupt_state(rdev);
3046 return 0;
3047 }
3048
3049 hdmi1 = RREG32(R600_HDMI_BLOCK1 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN;
3050 if (ASIC_IS_DCE3(rdev)) {
3051 hdmi2 = RREG32(R600_HDMI_BLOCK3 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN;
3052 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3053 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3054 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
3055 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
3056 if (ASIC_IS_DCE32(rdev)) {
3057 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
3058 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
3059 }
3060 } else {
3061 hdmi2 = RREG32(R600_HDMI_BLOCK2 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN;
3062 hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3063 hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3064 hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN;
3065 }
3066
3067 if (rdev->irq.sw_int) {
3068 DRM_DEBUG("r600_irq_set: sw int\n");
3069 cp_int_cntl |= RB_INT_ENABLE;
3070 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
3071 }
3072 if (rdev->irq.crtc_vblank_int[0] ||
3073 rdev->irq.pflip[0]) {
3074 DRM_DEBUG("r600_irq_set: vblank 0\n");
3075 mode_int |= D1MODE_VBLANK_INT_MASK;
3076 }
3077 if (rdev->irq.crtc_vblank_int[1] ||
3078 rdev->irq.pflip[1]) {
3079 DRM_DEBUG("r600_irq_set: vblank 1\n");
3080 mode_int |= D2MODE_VBLANK_INT_MASK;
3081 }
3082 if (rdev->irq.hpd[0]) {
3083 DRM_DEBUG("r600_irq_set: hpd 1\n");
3084 hpd1 |= DC_HPDx_INT_EN;
3085 }
3086 if (rdev->irq.hpd[1]) {
3087 DRM_DEBUG("r600_irq_set: hpd 2\n");
3088 hpd2 |= DC_HPDx_INT_EN;
3089 }
3090 if (rdev->irq.hpd[2]) {
3091 DRM_DEBUG("r600_irq_set: hpd 3\n");
3092 hpd3 |= DC_HPDx_INT_EN;
3093 }
3094 if (rdev->irq.hpd[3]) {
3095 DRM_DEBUG("r600_irq_set: hpd 4\n");
3096 hpd4 |= DC_HPDx_INT_EN;
3097 }
3098 if (rdev->irq.hpd[4]) {
3099 DRM_DEBUG("r600_irq_set: hpd 5\n");
3100 hpd5 |= DC_HPDx_INT_EN;
3101 }
3102 if (rdev->irq.hpd[5]) {
3103 DRM_DEBUG("r600_irq_set: hpd 6\n");
3104 hpd6 |= DC_HPDx_INT_EN;
3105 }
3106 if (rdev->irq.hdmi[0]) {
3107 DRM_DEBUG("r600_irq_set: hdmi 1\n");
3108 hdmi1 |= R600_HDMI_INT_EN;
3109 }
3110 if (rdev->irq.hdmi[1]) {
3111 DRM_DEBUG("r600_irq_set: hdmi 2\n");
3112 hdmi2 |= R600_HDMI_INT_EN;
3113 }
3114 if (rdev->irq.gui_idle) {
3115 DRM_DEBUG("gui idle\n");
3116 grbm_int_cntl |= GUI_IDLE_INT_ENABLE;
3117 }
3118
3119 WREG32(CP_INT_CNTL, cp_int_cntl);
3120 WREG32(DxMODE_INT_MASK, mode_int);
3121 WREG32(D1GRPH_INTERRUPT_CONTROL, d1grph);
3122 WREG32(D2GRPH_INTERRUPT_CONTROL, d2grph);
3123 WREG32(GRBM_INT_CNTL, grbm_int_cntl);
3124 WREG32(R600_HDMI_BLOCK1 + R600_HDMI_CNTL, hdmi1);
3125 if (ASIC_IS_DCE3(rdev)) {
3126 WREG32(R600_HDMI_BLOCK3 + R600_HDMI_CNTL, hdmi2);
3127 WREG32(DC_HPD1_INT_CONTROL, hpd1);
3128 WREG32(DC_HPD2_INT_CONTROL, hpd2);
3129 WREG32(DC_HPD3_INT_CONTROL, hpd3);
3130 WREG32(DC_HPD4_INT_CONTROL, hpd4);
3131 if (ASIC_IS_DCE32(rdev)) {
3132 WREG32(DC_HPD5_INT_CONTROL, hpd5);
3133 WREG32(DC_HPD6_INT_CONTROL, hpd6);
3134 }
3135 } else {
3136 WREG32(R600_HDMI_BLOCK2 + R600_HDMI_CNTL, hdmi2);
3137 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
3138 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
3139 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3);
3140 }
3141
3142 return 0;
3143 }
3144
3145 static inline void r600_irq_ack(struct radeon_device *rdev)
3146 {
3147 u32 tmp;
3148
3149 if (ASIC_IS_DCE3(rdev)) {
3150 rdev->irq.stat_regs.r600.disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS);
3151 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE);
3152 rdev->irq.stat_regs.r600.disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2);
3153 } else {
3154 rdev->irq.stat_regs.r600.disp_int = RREG32(DISP_INTERRUPT_STATUS);
3155 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
3156 rdev->irq.stat_regs.r600.disp_int_cont2 = 0;
3157 }
3158 rdev->irq.stat_regs.r600.d1grph_int = RREG32(D1GRPH_INTERRUPT_STATUS);
3159 rdev->irq.stat_regs.r600.d2grph_int = RREG32(D2GRPH_INTERRUPT_STATUS);
3160
3161 if (rdev->irq.stat_regs.r600.d1grph_int & DxGRPH_PFLIP_INT_OCCURRED)
3162 WREG32(D1GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR);
3163 if (rdev->irq.stat_regs.r600.d2grph_int & DxGRPH_PFLIP_INT_OCCURRED)
3164 WREG32(D2GRPH_INTERRUPT_STATUS, DxGRPH_PFLIP_INT_CLEAR);
3165 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT)
3166 WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
3167 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT)
3168 WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
3169 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT)
3170 WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
3171 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT)
3172 WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
3173 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) {
3174 if (ASIC_IS_DCE3(rdev)) {
3175 tmp = RREG32(DC_HPD1_INT_CONTROL);
3176 tmp |= DC_HPDx_INT_ACK;
3177 WREG32(DC_HPD1_INT_CONTROL, tmp);
3178 } else {
3179 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
3180 tmp |= DC_HPDx_INT_ACK;
3181 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
3182 }
3183 }
3184 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) {
3185 if (ASIC_IS_DCE3(rdev)) {
3186 tmp = RREG32(DC_HPD2_INT_CONTROL);
3187 tmp |= DC_HPDx_INT_ACK;
3188 WREG32(DC_HPD2_INT_CONTROL, tmp);
3189 } else {
3190 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
3191 tmp |= DC_HPDx_INT_ACK;
3192 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
3193 }
3194 }
3195 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) {
3196 if (ASIC_IS_DCE3(rdev)) {
3197 tmp = RREG32(DC_HPD3_INT_CONTROL);
3198 tmp |= DC_HPDx_INT_ACK;
3199 WREG32(DC_HPD3_INT_CONTROL, tmp);
3200 } else {
3201 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
3202 tmp |= DC_HPDx_INT_ACK;
3203 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
3204 }
3205 }
3206 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) {
3207 tmp = RREG32(DC_HPD4_INT_CONTROL);
3208 tmp |= DC_HPDx_INT_ACK;
3209 WREG32(DC_HPD4_INT_CONTROL, tmp);
3210 }
3211 if (ASIC_IS_DCE32(rdev)) {
3212 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) {
3213 tmp = RREG32(DC_HPD5_INT_CONTROL);
3214 tmp |= DC_HPDx_INT_ACK;
3215 WREG32(DC_HPD5_INT_CONTROL, tmp);
3216 }
3217 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) {
3218 tmp = RREG32(DC_HPD5_INT_CONTROL);
3219 tmp |= DC_HPDx_INT_ACK;
3220 WREG32(DC_HPD6_INT_CONTROL, tmp);
3221 }
3222 }
3223 if (RREG32(R600_HDMI_BLOCK1 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) {
3224 WREG32_P(R600_HDMI_BLOCK1 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK);
3225 }
3226 if (ASIC_IS_DCE3(rdev)) {
3227 if (RREG32(R600_HDMI_BLOCK3 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) {
3228 WREG32_P(R600_HDMI_BLOCK3 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK);
3229 }
3230 } else {
3231 if (RREG32(R600_HDMI_BLOCK2 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) {
3232 WREG32_P(R600_HDMI_BLOCK2 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK);
3233 }
3234 }
3235 }
3236
3237 void r600_irq_disable(struct radeon_device *rdev)
3238 {
3239 r600_disable_interrupts(rdev);
3240 /* Wait and acknowledge irq */
3241 mdelay(1);
3242 r600_irq_ack(rdev);
3243 r600_disable_interrupt_state(rdev);
3244 }
3245
3246 static inline u32 r600_get_ih_wptr(struct radeon_device *rdev)
3247 {
3248 u32 wptr, tmp;
3249
3250 if (rdev->wb.enabled)
3251 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]);
3252 else
3253 wptr = RREG32(IH_RB_WPTR);
3254
3255 if (wptr & RB_OVERFLOW) {
3256 /* When a ring buffer overflow happen start parsing interrupt
3257 * from the last not overwritten vector (wptr + 16). Hopefully
3258 * this should allow us to catchup.
3259 */
3260 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
3261 wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
3262 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
3263 tmp = RREG32(IH_RB_CNTL);
3264 tmp |= IH_WPTR_OVERFLOW_CLEAR;
3265 WREG32(IH_RB_CNTL, tmp);
3266 }
3267 return (wptr & rdev->ih.ptr_mask);
3268 }
3269
3270 /* r600 IV Ring
3271 * Each IV ring entry is 128 bits:
3272 * [7:0] - interrupt source id
3273 * [31:8] - reserved
3274 * [59:32] - interrupt source data
3275 * [127:60] - reserved
3276 *
3277 * The basic interrupt vector entries
3278 * are decoded as follows:
3279 * src_id src_data description
3280 * 1 0 D1 Vblank
3281 * 1 1 D1 Vline
3282 * 5 0 D2 Vblank
3283 * 5 1 D2 Vline
3284 * 19 0 FP Hot plug detection A
3285 * 19 1 FP Hot plug detection B
3286 * 19 2 DAC A auto-detection
3287 * 19 3 DAC B auto-detection
3288 * 21 4 HDMI block A
3289 * 21 5 HDMI block B
3290 * 176 - CP_INT RB
3291 * 177 - CP_INT IB1
3292 * 178 - CP_INT IB2
3293 * 181 - EOP Interrupt
3294 * 233 - GUI Idle
3295 *
3296 * Note, these are based on r600 and may need to be
3297 * adjusted or added to on newer asics
3298 */
3299
3300 int r600_irq_process(struct radeon_device *rdev)
3301 {
3302 u32 wptr;
3303 u32 rptr;
3304 u32 src_id, src_data;
3305 u32 ring_index;
3306 unsigned long flags;
3307 bool queue_hotplug = false;
3308
3309 if (!rdev->ih.enabled || rdev->shutdown)
3310 return IRQ_NONE;
3311
3312 wptr = r600_get_ih_wptr(rdev);
3313 rptr = rdev->ih.rptr;
3314 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
3315
3316 spin_lock_irqsave(&rdev->ih.lock, flags);
3317
3318 if (rptr == wptr) {
3319 spin_unlock_irqrestore(&rdev->ih.lock, flags);
3320 return IRQ_NONE;
3321 }
3322
3323 restart_ih:
3324 /* display interrupts */
3325 r600_irq_ack(rdev);
3326
3327 rdev->ih.wptr = wptr;
3328 while (rptr != wptr) {
3329 /* wptr/rptr are in bytes! */
3330 ring_index = rptr / 4;
3331 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
3332 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;
3333
3334 switch (src_id) {
3335 case 1: /* D1 vblank/vline */
3336 switch (src_data) {
3337 case 0: /* D1 vblank */
3338 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT) {
3339 if (rdev->irq.crtc_vblank_int[0]) {
3340 drm_handle_vblank(rdev->ddev, 0);
3341 rdev->pm.vblank_sync = true;
3342 wake_up(&rdev->irq.vblank_queue);
3343 }
3344 if (rdev->irq.pflip[0])
3345 radeon_crtc_handle_flip(rdev, 0);
3346 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
3347 DRM_DEBUG("IH: D1 vblank\n");
3348 }
3349 break;
3350 case 1: /* D1 vline */
3351 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT) {
3352 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VLINE_INTERRUPT;
3353 DRM_DEBUG("IH: D1 vline\n");
3354 }
3355 break;
3356 default:
3357 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3358 break;
3359 }
3360 break;
3361 case 5: /* D2 vblank/vline */
3362 switch (src_data) {
3363 case 0: /* D2 vblank */
3364 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT) {
3365 if (rdev->irq.crtc_vblank_int[1]) {
3366 drm_handle_vblank(rdev->ddev, 1);
3367 rdev->pm.vblank_sync = true;
3368 wake_up(&rdev->irq.vblank_queue);
3369 }
3370 if (rdev->irq.pflip[1])
3371 radeon_crtc_handle_flip(rdev, 1);
3372 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VBLANK_INTERRUPT;
3373 DRM_DEBUG("IH: D2 vblank\n");
3374 }
3375 break;
3376 case 1: /* D1 vline */
3377 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT) {
3378 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VLINE_INTERRUPT;
3379 DRM_DEBUG("IH: D2 vline\n");
3380 }
3381 break;
3382 default:
3383 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3384 break;
3385 }
3386 break;
3387 case 19: /* HPD/DAC hotplug */
3388 switch (src_data) {
3389 case 0:
3390 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) {
3391 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD1_INTERRUPT;
3392 queue_hotplug = true;
3393 DRM_DEBUG("IH: HPD1\n");
3394 }
3395 break;
3396 case 1:
3397 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) {
3398 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD2_INTERRUPT;
3399 queue_hotplug = true;
3400 DRM_DEBUG("IH: HPD2\n");
3401 }
3402 break;
3403 case 4:
3404 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) {
3405 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD3_INTERRUPT;
3406 queue_hotplug = true;
3407 DRM_DEBUG("IH: HPD3\n");
3408 }
3409 break;
3410 case 5:
3411 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) {
3412 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD4_INTERRUPT;
3413 queue_hotplug = true;
3414 DRM_DEBUG("IH: HPD4\n");
3415 }
3416 break;
3417 case 10:
3418 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) {
3419 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD5_INTERRUPT;
3420 queue_hotplug = true;
3421 DRM_DEBUG("IH: HPD5\n");
3422 }
3423 break;
3424 case 12:
3425 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) {
3426 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD6_INTERRUPT;
3427 queue_hotplug = true;
3428 DRM_DEBUG("IH: HPD6\n");
3429 }
3430 break;
3431 default:
3432 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3433 break;
3434 }
3435 break;
3436 case 21: /* HDMI */
3437 DRM_DEBUG("IH: HDMI: 0x%x\n", src_data);
3438 r600_audio_schedule_polling(rdev);
3439 break;
3440 case 176: /* CP_INT in ring buffer */
3441 case 177: /* CP_INT in IB1 */
3442 case 178: /* CP_INT in IB2 */
3443 DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
3444 radeon_fence_process(rdev);
3445 break;
3446 case 181: /* CP EOP event */
3447 DRM_DEBUG("IH: CP EOP\n");
3448 radeon_fence_process(rdev);
3449 break;
3450 case 233: /* GUI IDLE */
3451 DRM_DEBUG("IH: GUI idle\n");
3452 rdev->pm.gui_idle = true;
3453 wake_up(&rdev->irq.idle_queue);
3454 break;
3455 default:
3456 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3457 break;
3458 }
3459
3460 /* wptr/rptr are in bytes! */
3461 rptr += 16;
3462 rptr &= rdev->ih.ptr_mask;
3463 }
3464 /* make sure wptr hasn't changed while processing */
3465 wptr = r600_get_ih_wptr(rdev);
3466 if (wptr != rdev->ih.wptr)
3467 goto restart_ih;
3468 if (queue_hotplug)
3469 schedule_work(&rdev->hotplug_work);
3470 rdev->ih.rptr = rptr;
3471 WREG32(IH_RB_RPTR, rdev->ih.rptr);
3472 spin_unlock_irqrestore(&rdev->ih.lock, flags);
3473 return IRQ_HANDLED;
3474 }
3475
3476 /*
3477 * Debugfs info
3478 */
3479 #if defined(CONFIG_DEBUG_FS)
3480
3481 static int r600_debugfs_cp_ring_info(struct seq_file *m, void *data)
3482 {
3483 struct drm_info_node *node = (struct drm_info_node *) m->private;
3484 struct drm_device *dev = node->minor->dev;
3485 struct radeon_device *rdev = dev->dev_private;
3486 unsigned count, i, j;
3487
3488 radeon_ring_free_size(rdev);
3489 count = (rdev->cp.ring_size / 4) - rdev->cp.ring_free_dw;
3490 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(CP_STAT));
3491 seq_printf(m, "CP_RB_WPTR 0x%08x\n", RREG32(CP_RB_WPTR));
3492 seq_printf(m, "CP_RB_RPTR 0x%08x\n", RREG32(CP_RB_RPTR));
3493 seq_printf(m, "driver's copy of the CP_RB_WPTR 0x%08x\n", rdev->cp.wptr);
3494 seq_printf(m, "driver's copy of the CP_RB_RPTR 0x%08x\n", rdev->cp.rptr);
3495 seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
3496 seq_printf(m, "%u dwords in ring\n", count);
3497 i = rdev->cp.rptr;
3498 for (j = 0; j <= count; j++) {
3499 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
3500 i = (i + 1) & rdev->cp.ptr_mask;
3501 }
3502 return 0;
3503 }
3504
3505 static int r600_debugfs_mc_info(struct seq_file *m, void *data)
3506 {
3507 struct drm_info_node *node = (struct drm_info_node *) m->private;
3508 struct drm_device *dev = node->minor->dev;
3509 struct radeon_device *rdev = dev->dev_private;
3510
3511 DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS);
3512 DREG32_SYS(m, rdev, VM_L2_STATUS);
3513 return 0;
3514 }
3515
3516 static struct drm_info_list r600_mc_info_list[] = {
3517 {"r600_mc_info", r600_debugfs_mc_info, 0, NULL},
3518 {"r600_ring_info", r600_debugfs_cp_ring_info, 0, NULL},
3519 };
3520 #endif
3521
3522 int r600_debugfs_mc_info_init(struct radeon_device *rdev)
3523 {
3524 #if defined(CONFIG_DEBUG_FS)
3525 return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list));
3526 #else
3527 return 0;
3528 #endif
3529 }
3530
3531 /**
3532 * r600_ioctl_wait_idle - flush host path cache on wait idle ioctl
3533 * rdev: radeon device structure
3534 * bo: buffer object struct which userspace is waiting for idle
3535 *
3536 * Some R6XX/R7XX doesn't seems to take into account HDP flush performed
3537 * through ring buffer, this leads to corruption in rendering, see
3538 * http://bugzilla.kernel.org/show_bug.cgi?id=15186 to avoid this we
3539 * directly perform HDP flush by writing register through MMIO.
3540 */
3541 void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo)
3542 {
3543 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read
3544 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL.
3545 * This seems to cause problems on some AGP cards. Just use the old
3546 * method for them.
3547 */
3548 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) &&
3549 rdev->vram_scratch.ptr && !(rdev->flags & RADEON_IS_AGP)) {
3550 void __iomem *ptr = (void *)rdev->vram_scratch.ptr;
3551 u32 tmp;
3552
3553 WREG32(HDP_DEBUG1, 0);
3554 tmp = readl((void __iomem *)ptr);
3555 } else
3556 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
3557 }
3558
3559 void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes)
3560 {
3561 u32 link_width_cntl, mask, target_reg;
3562
3563 if (rdev->flags & RADEON_IS_IGP)
3564 return;
3565
3566 if (!(rdev->flags & RADEON_IS_PCIE))
3567 return;
3568
3569 /* x2 cards have a special sequence */
3570 if (ASIC_IS_X2(rdev))
3571 return;
3572
3573 /* FIXME wait for idle */
3574
3575 switch (lanes) {
3576 case 0:
3577 mask = RADEON_PCIE_LC_LINK_WIDTH_X0;
3578 break;
3579 case 1:
3580 mask = RADEON_PCIE_LC_LINK_WIDTH_X1;
3581 break;
3582 case 2:
3583 mask = RADEON_PCIE_LC_LINK_WIDTH_X2;
3584 break;
3585 case 4:
3586 mask = RADEON_PCIE_LC_LINK_WIDTH_X4;
3587 break;
3588 case 8:
3589 mask = RADEON_PCIE_LC_LINK_WIDTH_X8;
3590 break;
3591 case 12:
3592 mask = RADEON_PCIE_LC_LINK_WIDTH_X12;
3593 break;
3594 case 16:
3595 default:
3596 mask = RADEON_PCIE_LC_LINK_WIDTH_X16;
3597 break;
3598 }
3599
3600 link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
3601
3602 if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) ==
3603 (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT))
3604 return;
3605
3606 if (link_width_cntl & R600_PCIE_LC_UPCONFIGURE_DIS)
3607 return;
3608
3609 link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK |
3610 RADEON_PCIE_LC_RECONFIG_NOW |
3611 R600_PCIE_LC_RENEGOTIATE_EN |
3612 R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE);
3613 link_width_cntl |= mask;
3614
3615 WREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3616
3617 /* some northbridges can renegotiate the link rather than requiring
3618 * a complete re-config.
3619 * e.g., AMD 780/790 northbridges (pci ids: 0x5956, 0x5957, 0x5958, etc.)
3620 */
3621 if (link_width_cntl & R600_PCIE_LC_RENEGOTIATION_SUPPORT)
3622 link_width_cntl |= R600_PCIE_LC_RENEGOTIATE_EN | R600_PCIE_LC_UPCONFIGURE_SUPPORT;
3623 else
3624 link_width_cntl |= R600_PCIE_LC_RECONFIG_ARC_MISSING_ESCAPE;
3625
3626 WREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl |
3627 RADEON_PCIE_LC_RECONFIG_NOW));
3628
3629 if (rdev->family >= CHIP_RV770)
3630 target_reg = R700_TARGET_AND_CURRENT_PROFILE_INDEX;
3631 else
3632 target_reg = R600_TARGET_AND_CURRENT_PROFILE_INDEX;
3633
3634 /* wait for lane set to complete */
3635 link_width_cntl = RREG32(target_reg);
3636 while (link_width_cntl == 0xffffffff)
3637 link_width_cntl = RREG32(target_reg);
3638
3639 }
3640
3641 int r600_get_pcie_lanes(struct radeon_device *rdev)
3642 {
3643 u32 link_width_cntl;
3644
3645 if (rdev->flags & RADEON_IS_IGP)
3646 return 0;
3647
3648 if (!(rdev->flags & RADEON_IS_PCIE))
3649 return 0;
3650
3651 /* x2 cards have a special sequence */
3652 if (ASIC_IS_X2(rdev))
3653 return 0;
3654
3655 /* FIXME wait for idle */
3656
3657 link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
3658
3659 switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) {
3660 case RADEON_PCIE_LC_LINK_WIDTH_X0:
3661 return 0;
3662 case RADEON_PCIE_LC_LINK_WIDTH_X1:
3663 return 1;
3664 case RADEON_PCIE_LC_LINK_WIDTH_X2:
3665 return 2;
3666 case RADEON_PCIE_LC_LINK_WIDTH_X4:
3667 return 4;
3668 case RADEON_PCIE_LC_LINK_WIDTH_X8:
3669 return 8;
3670 case RADEON_PCIE_LC_LINK_WIDTH_X16:
3671 default:
3672 return 16;
3673 }
3674 }
3675
3676 static void r600_pcie_gen2_enable(struct radeon_device *rdev)
3677 {
3678 u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp;
3679 u16 link_cntl2;
3680
3681 if (radeon_pcie_gen2 == 0)
3682 return;
3683
3684 if (rdev->flags & RADEON_IS_IGP)
3685 return;
3686
3687 if (!(rdev->flags & RADEON_IS_PCIE))
3688 return;
3689
3690 /* x2 cards have a special sequence */
3691 if (ASIC_IS_X2(rdev))
3692 return;
3693
3694 /* only RV6xx+ chips are supported */
3695 if (rdev->family <= CHIP_R600)
3696 return;
3697
3698 /* 55 nm r6xx asics */
3699 if ((rdev->family == CHIP_RV670) ||
3700 (rdev->family == CHIP_RV620) ||
3701 (rdev->family == CHIP_RV635)) {
3702 /* advertise upconfig capability */
3703 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3704 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
3705 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3706 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3707 if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) {
3708 lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT;
3709 link_width_cntl &= ~(LC_LINK_WIDTH_MASK |
3710 LC_RECONFIG_ARC_MISSING_ESCAPE);
3711 link_width_cntl |= lanes | LC_RECONFIG_NOW | LC_RENEGOTIATE_EN;
3712 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3713 } else {
3714 link_width_cntl |= LC_UPCONFIGURE_DIS;
3715 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3716 }
3717 }
3718
3719 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3720 if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
3721 (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
3722
3723 /* 55 nm r6xx asics */
3724 if ((rdev->family == CHIP_RV670) ||
3725 (rdev->family == CHIP_RV620) ||
3726 (rdev->family == CHIP_RV635)) {
3727 WREG32(MM_CFGREGS_CNTL, 0x8);
3728 link_cntl2 = RREG32(0x4088);
3729 WREG32(MM_CFGREGS_CNTL, 0);
3730 /* not supported yet */
3731 if (link_cntl2 & SELECTABLE_DEEMPHASIS)
3732 return;
3733 }
3734
3735 speed_cntl &= ~LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK;
3736 speed_cntl |= (0x3 << LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT);
3737 speed_cntl &= ~LC_VOLTAGE_TIMER_SEL_MASK;
3738 speed_cntl &= ~LC_FORCE_DIS_HW_SPEED_CHANGE;
3739 speed_cntl |= LC_FORCE_EN_HW_SPEED_CHANGE;
3740 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3741
3742 tmp = RREG32(0x541c);
3743 WREG32(0x541c, tmp | 0x8);
3744 WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN);
3745 link_cntl2 = RREG16(0x4088);
3746 link_cntl2 &= ~TARGET_LINK_SPEED_MASK;
3747 link_cntl2 |= 0x2;
3748 WREG16(0x4088, link_cntl2);
3749 WREG32(MM_CFGREGS_CNTL, 0);
3750
3751 if ((rdev->family == CHIP_RV670) ||
3752 (rdev->family == CHIP_RV620) ||
3753 (rdev->family == CHIP_RV635)) {
3754 training_cntl = RREG32_PCIE_P(PCIE_LC_TRAINING_CNTL);
3755 training_cntl &= ~LC_POINT_7_PLUS_EN;
3756 WREG32_PCIE_P(PCIE_LC_TRAINING_CNTL, training_cntl);
3757 } else {
3758 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3759 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
3760 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3761 }
3762
3763 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3764 speed_cntl |= LC_GEN2_EN_STRAP;
3765 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3766
3767 } else {
3768 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3769 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
3770 if (1)
3771 link_width_cntl |= LC_UPCONFIGURE_DIS;
3772 else
3773 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
3774 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3775 }
3776 }
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree