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ASoC: Don't go through cache when applying WM5100 rev A updates
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / sound / soc / codecs / wm5100.c
blobd0beeec9b045a525123a762833a14b0fabf91d4d
1 /*
2 * wm5100.c -- WM5100 ALSA SoC Audio driver
3 *
4 * Copyright 2011 Wolfson Microelectronics plc
5 *
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
15 #include <linux/init.h>
16 #include <linux/delay.h>
17 #include <linux/pm.h>
18 #include <linux/gcd.h>
19 #include <linux/gpio.h>
20 #include <linux/i2c.h>
21 #include <linux/platform_device.h>
22 #include <linux/regulator/consumer.h>
23 #include <linux/regulator/fixed.h>
24 #include <linux/slab.h>
25 #include <sound/core.h>
26 #include <sound/pcm.h>
27 #include <sound/pcm_params.h>
28 #include <sound/soc.h>
29 #include <sound/jack.h>
30 #include <sound/initval.h>
31 #include <sound/tlv.h>
32 #include <sound/wm5100.h>
33
34 #include "wm5100.h"
35
36 #define WM5100_NUM_CORE_SUPPLIES 2
37 static const char *wm5100_core_supply_names[WM5100_NUM_CORE_SUPPLIES] = {
38 "DBVDD1",
39 "LDOVDD", /* If DCVDD is supplied externally specify as LDOVDD */
40 };
41
42 #define WM5100_AIFS 3
43 #define WM5100_SYNC_SRS 3
44
45 struct wm5100_fll {
46 int fref;
47 int fout;
48 int src;
49 struct completion lock;
50 };
51
52 /* codec private data */
53 struct wm5100_priv {
54 struct snd_soc_codec *codec;
55
56 struct regulator_bulk_data core_supplies[WM5100_NUM_CORE_SUPPLIES];
57 struct regulator *cpvdd;
58 struct regulator *dbvdd2;
59 struct regulator *dbvdd3;
60
61 int rev;
62
63 int sysclk;
64 int asyncclk;
65
66 bool aif_async[WM5100_AIFS];
67 bool aif_symmetric[WM5100_AIFS];
68 int sr_ref[WM5100_SYNC_SRS];
69
70 bool out_ena[2];
71
72 struct snd_soc_jack *jack;
73 bool jack_detecting;
74 bool jack_mic;
75 int jack_mode;
76
77 struct wm5100_fll fll[2];
78
79 struct wm5100_pdata pdata;
80
81 #ifdef CONFIG_GPIOLIB
82 struct gpio_chip gpio_chip;
83 #endif
84 };
85
86 static int wm5100_sr_code[] = {
87 0,
88 12000,
89 24000,
90 48000,
91 96000,
92 192000,
93 384000,
94 768000,
95 0,
96 11025,
97 22050,
98 44100,
99 88200,
100 176400,
101 352800,
102 705600,
103 4000,
104 8000,
105 16000,
106 32000,
107 64000,
108 128000,
109 256000,
110 512000,
111 };
112
113 static int wm5100_sr_regs[WM5100_SYNC_SRS] = {
114 WM5100_CLOCKING_4,
115 WM5100_CLOCKING_5,
116 WM5100_CLOCKING_6,
117 };
118
119 static int wm5100_alloc_sr(struct snd_soc_codec *codec, int rate)
120 {
121 struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
122 int sr_code, sr_free, i;
123
124 for (i = 0; i < ARRAY_SIZE(wm5100_sr_code); i++)
125 if (wm5100_sr_code[i] == rate)
126 break;
127 if (i == ARRAY_SIZE(wm5100_sr_code)) {
128 dev_err(codec->dev, "Unsupported sample rate: %dHz\n", rate);
129 return -EINVAL;
130 }
131 sr_code = i;
132
133 if ((wm5100->sysclk % rate) == 0) {
134 /* Is this rate already in use? */
135 sr_free = -1;
136 for (i = 0; i < ARRAY_SIZE(wm5100_sr_regs); i++) {
137 if (!wm5100->sr_ref[i] && sr_free == -1) {
138 sr_free = i;
139 continue;
140 }
141 if ((snd_soc_read(codec, wm5100_sr_regs[i]) &
142 WM5100_SAMPLE_RATE_1_MASK) == sr_code)
143 break;
144 }
145
146 if (i < ARRAY_SIZE(wm5100_sr_regs)) {
147 wm5100->sr_ref[i]++;
148 dev_dbg(codec->dev, "SR %dHz, slot %d, ref %d\n",
149 rate, i, wm5100->sr_ref[i]);
150 return i;
151 }
152
153 if (sr_free == -1) {
154 dev_err(codec->dev, "All SR slots already in use\n");
155 return -EBUSY;
156 }
157
158 dev_dbg(codec->dev, "Allocating SR slot %d for %dHz\n",
159 sr_free, rate);
160 wm5100->sr_ref[sr_free]++;
161 snd_soc_update_bits(codec, wm5100_sr_regs[sr_free],
162 WM5100_SAMPLE_RATE_1_MASK,
163 sr_code);
164
165 return sr_free;
166
167 } else {
168 dev_err(codec->dev,
169 "SR %dHz incompatible with %dHz SYSCLK and %dHz ASYNCCLK\n",
170 rate, wm5100->sysclk, wm5100->asyncclk);
171 return -EINVAL;
172 }
173 }
174
175 static void wm5100_free_sr(struct snd_soc_codec *codec, int rate)
176 {
177 struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
178 int i, sr_code;
179
180 for (i = 0; i < ARRAY_SIZE(wm5100_sr_code); i++)
181 if (wm5100_sr_code[i] == rate)
182 break;
183 if (i == ARRAY_SIZE(wm5100_sr_code)) {
184 dev_err(codec->dev, "Unsupported sample rate: %dHz\n", rate);
185 return;
186 }
187 sr_code = wm5100_sr_code[i];
188
189 for (i = 0; i < ARRAY_SIZE(wm5100_sr_regs); i++) {
190 if (!wm5100->sr_ref[i])
191 continue;
192
193 if ((snd_soc_read(codec, wm5100_sr_regs[i]) &
194 WM5100_SAMPLE_RATE_1_MASK) == sr_code)
195 break;
196 }
197 if (i < ARRAY_SIZE(wm5100_sr_regs)) {
198 wm5100->sr_ref[i]--;
199 dev_dbg(codec->dev, "Dereference SR %dHz, count now %d\n",
200 rate, wm5100->sr_ref[i]);
201 } else {
202 dev_warn(codec->dev, "Freeing unreferenced sample rate %dHz\n",
203 rate);
204 }
205 }
206
207 static int wm5100_reset(struct snd_soc_codec *codec)
208 {
209 struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
210
211 if (wm5100->pdata.reset) {
212 gpio_set_value_cansleep(wm5100->pdata.reset, 0);
213 gpio_set_value_cansleep(wm5100->pdata.reset, 1);
214
215 return 0;
216 } else {
217 return snd_soc_write(codec, WM5100_SOFTWARE_RESET, 0);
218 }
219 }
220
221 static DECLARE_TLV_DB_SCALE(in_tlv, -6300, 100, 0);
222 static DECLARE_TLV_DB_SCALE(eq_tlv, -1200, 100, 0);
223 static DECLARE_TLV_DB_SCALE(mixer_tlv, -3200, 100, 0);
224 static DECLARE_TLV_DB_SCALE(out_tlv, -6400, 100, 0);
225 static DECLARE_TLV_DB_SCALE(digital_tlv, -6400, 50, 0);
226
227 static const char *wm5100_mixer_texts[] = {
228 "None",
229 "Tone Generator 1",
230 "Tone Generator 2",
231 "AEC loopback",
232 "IN1L",
233 "IN1R",
234 "IN2L",
235 "IN2R",
236 "IN3L",
237 "IN3R",
238 "IN4L",
239 "IN4R",
240 "AIF1RX1",
241 "AIF1RX2",
242 "AIF1RX3",
243 "AIF1RX4",
244 "AIF1RX5",
245 "AIF1RX6",
246 "AIF1RX7",
247 "AIF1RX8",
248 "AIF2RX1",
249 "AIF2RX2",
250 "AIF3RX1",
251 "AIF3RX2",
252 "EQ1",
253 "EQ2",
254 "EQ3",
255 "EQ4",
256 "DRC1L",
257 "DRC1R",
258 "LHPF1",
259 "LHPF2",
260 "LHPF3",
261 "LHPF4",
262 "DSP1.1",
263 "DSP1.2",
264 "DSP1.3",
265 "DSP1.4",
266 "DSP1.5",
267 "DSP1.6",
268 "DSP2.1",
269 "DSP2.2",
270 "DSP2.3",
271 "DSP2.4",
272 "DSP2.5",
273 "DSP2.6",
274 "DSP3.1",
275 "DSP3.2",
276 "DSP3.3",
277 "DSP3.4",
278 "DSP3.5",
279 "DSP3.6",
280 "ASRC1L",
281 "ASRC1R",
282 "ASRC2L",
283 "ASRC2R",
284 "ISRC1INT1",
285 "ISRC1INT2",
286 "ISRC1INT3",
287 "ISRC1INT4",
288 "ISRC2INT1",
289 "ISRC2INT2",
290 "ISRC2INT3",
291 "ISRC2INT4",
292 "ISRC1DEC1",
293 "ISRC1DEC2",
294 "ISRC1DEC3",
295 "ISRC1DEC4",
296 "ISRC2DEC1",
297 "ISRC2DEC2",
298 "ISRC2DEC3",
299 "ISRC2DEC4",
300 };
301
302 static int wm5100_mixer_values[] = {
303 0x00,
304 0x04, /* Tone */
305 0x05,
306 0x08, /* AEC */
307 0x10, /* Input */
308 0x11,
309 0x12,
310 0x13,
311 0x14,
312 0x15,
313 0x16,
314 0x17,
315 0x20, /* AIF */
316 0x21,
317 0x22,
318 0x23,
319 0x24,
320 0x25,
321 0x26,
322 0x27,
323 0x28,
324 0x29,
325 0x30, /* AIF3 - check */
326 0x31,
327 0x50, /* EQ */
328 0x51,
329 0x52,
330 0x53,
331 0x54,
332 0x58, /* DRC */
333 0x59,
334 0x60, /* LHPF1 */
335 0x61, /* LHPF2 */
336 0x62, /* LHPF3 */
337 0x63, /* LHPF4 */
338 0x68, /* DSP1 */
339 0x69,
340 0x6a,
341 0x6b,
342 0x6c,
343 0x6d,
344 0x70, /* DSP2 */
345 0x71,
346 0x72,
347 0x73,
348 0x74,
349 0x75,
350 0x78, /* DSP3 */
351 0x79,
352 0x7a,
353 0x7b,
354 0x7c,
355 0x7d,
356 0x90, /* ASRC1 */
357 0x91,
358 0x92, /* ASRC2 */
359 0x93,
360 0xa0, /* ISRC1DEC1 */
361 0xa1,
362 0xa2,
363 0xa3,
364 0xa4, /* ISRC1INT1 */
365 0xa5,
366 0xa6,
367 0xa7,
368 0xa8, /* ISRC2DEC1 */
369 0xa9,
370 0xaa,
371 0xab,
372 0xac, /* ISRC2INT1 */
373 0xad,
374 0xae,
375 0xaf,
376 };
377
378 #define WM5100_MIXER_CONTROLS(name, base) \
379 SOC_SINGLE_TLV(name " Input 1 Volume", base + 1 , \
380 WM5100_MIXER_VOL_SHIFT, 80, 0, mixer_tlv), \
381 SOC_SINGLE_TLV(name " Input 2 Volume", base + 3 , \
382 WM5100_MIXER_VOL_SHIFT, 80, 0, mixer_tlv), \
383 SOC_SINGLE_TLV(name " Input 3 Volume", base + 5 , \
384 WM5100_MIXER_VOL_SHIFT, 80, 0, mixer_tlv), \
385 SOC_SINGLE_TLV(name " Input 4 Volume", base + 7 , \
386 WM5100_MIXER_VOL_SHIFT, 80, 0, mixer_tlv)
387
388 #define WM5100_MUX_ENUM_DECL(name, reg) \
389 SOC_VALUE_ENUM_SINGLE_DECL(name, reg, 0, 0xff, \
390 wm5100_mixer_texts, wm5100_mixer_values)
391
392 #define WM5100_MUX_CTL_DECL(name) \
393 const struct snd_kcontrol_new name##_mux = \
394 SOC_DAPM_VALUE_ENUM("Route", name##_enum)
395
396 #define WM5100_MIXER_ENUMS(name, base_reg) \
397 static WM5100_MUX_ENUM_DECL(name##_in1_enum, base_reg); \
398 static WM5100_MUX_ENUM_DECL(name##_in2_enum, base_reg + 2); \
399 static WM5100_MUX_ENUM_DECL(name##_in3_enum, base_reg + 4); \
400 static WM5100_MUX_ENUM_DECL(name##_in4_enum, base_reg + 6); \
401 static WM5100_MUX_CTL_DECL(name##_in1); \
402 static WM5100_MUX_CTL_DECL(name##_in2); \
403 static WM5100_MUX_CTL_DECL(name##_in3); \
404 static WM5100_MUX_CTL_DECL(name##_in4)
405
406 WM5100_MIXER_ENUMS(HPOUT1L, WM5100_OUT1LMIX_INPUT_1_SOURCE);
407 WM5100_MIXER_ENUMS(HPOUT1R, WM5100_OUT1RMIX_INPUT_1_SOURCE);
408 WM5100_MIXER_ENUMS(HPOUT2L, WM5100_OUT2LMIX_INPUT_1_SOURCE);
409 WM5100_MIXER_ENUMS(HPOUT2R, WM5100_OUT2RMIX_INPUT_1_SOURCE);
410 WM5100_MIXER_ENUMS(HPOUT3L, WM5100_OUT3LMIX_INPUT_1_SOURCE);
411 WM5100_MIXER_ENUMS(HPOUT3R, WM5100_OUT3RMIX_INPUT_1_SOURCE);
412
413 WM5100_MIXER_ENUMS(SPKOUTL, WM5100_OUT4LMIX_INPUT_1_SOURCE);
414 WM5100_MIXER_ENUMS(SPKOUTR, WM5100_OUT4RMIX_INPUT_1_SOURCE);
415 WM5100_MIXER_ENUMS(SPKDAT1L, WM5100_OUT5LMIX_INPUT_1_SOURCE);
416 WM5100_MIXER_ENUMS(SPKDAT1R, WM5100_OUT5RMIX_INPUT_1_SOURCE);
417 WM5100_MIXER_ENUMS(SPKDAT2L, WM5100_OUT6LMIX_INPUT_1_SOURCE);
418 WM5100_MIXER_ENUMS(SPKDAT2R, WM5100_OUT6RMIX_INPUT_1_SOURCE);
419
420 WM5100_MIXER_ENUMS(PWM1, WM5100_PWM1MIX_INPUT_1_SOURCE);
421 WM5100_MIXER_ENUMS(PWM2, WM5100_PWM1MIX_INPUT_1_SOURCE);
422
423 WM5100_MIXER_ENUMS(AIF1TX1, WM5100_AIF1TX1MIX_INPUT_1_SOURCE);
424 WM5100_MIXER_ENUMS(AIF1TX2, WM5100_AIF1TX2MIX_INPUT_1_SOURCE);
425 WM5100_MIXER_ENUMS(AIF1TX3, WM5100_AIF1TX3MIX_INPUT_1_SOURCE);
426 WM5100_MIXER_ENUMS(AIF1TX4, WM5100_AIF1TX4MIX_INPUT_1_SOURCE);
427 WM5100_MIXER_ENUMS(AIF1TX5, WM5100_AIF1TX5MIX_INPUT_1_SOURCE);
428 WM5100_MIXER_ENUMS(AIF1TX6, WM5100_AIF1TX6MIX_INPUT_1_SOURCE);
429 WM5100_MIXER_ENUMS(AIF1TX7, WM5100_AIF1TX7MIX_INPUT_1_SOURCE);
430 WM5100_MIXER_ENUMS(AIF1TX8, WM5100_AIF1TX8MIX_INPUT_1_SOURCE);
431
432 WM5100_MIXER_ENUMS(AIF2TX1, WM5100_AIF2TX1MIX_INPUT_1_SOURCE);
433 WM5100_MIXER_ENUMS(AIF2TX2, WM5100_AIF2TX2MIX_INPUT_1_SOURCE);
434
435 WM5100_MIXER_ENUMS(AIF3TX1, WM5100_AIF1TX1MIX_INPUT_1_SOURCE);
436 WM5100_MIXER_ENUMS(AIF3TX2, WM5100_AIF1TX2MIX_INPUT_1_SOURCE);
437
438 WM5100_MIXER_ENUMS(EQ1, WM5100_EQ1MIX_INPUT_1_SOURCE);
439 WM5100_MIXER_ENUMS(EQ2, WM5100_EQ2MIX_INPUT_1_SOURCE);
440 WM5100_MIXER_ENUMS(EQ3, WM5100_EQ3MIX_INPUT_1_SOURCE);
441 WM5100_MIXER_ENUMS(EQ4, WM5100_EQ4MIX_INPUT_1_SOURCE);
442
443 WM5100_MIXER_ENUMS(DRC1L, WM5100_DRC1LMIX_INPUT_1_SOURCE);
444 WM5100_MIXER_ENUMS(DRC1R, WM5100_DRC1RMIX_INPUT_1_SOURCE);
445
446 WM5100_MIXER_ENUMS(LHPF1, WM5100_HPLP1MIX_INPUT_1_SOURCE);
447 WM5100_MIXER_ENUMS(LHPF2, WM5100_HPLP2MIX_INPUT_1_SOURCE);
448 WM5100_MIXER_ENUMS(LHPF3, WM5100_HPLP3MIX_INPUT_1_SOURCE);
449 WM5100_MIXER_ENUMS(LHPF4, WM5100_HPLP4MIX_INPUT_1_SOURCE);
450
451 #define WM5100_MUX(name, ctrl) \
452 SND_SOC_DAPM_VALUE_MUX(name, SND_SOC_NOPM, 0, 0, ctrl)
453
454 #define WM5100_MIXER_WIDGETS(name, name_str) \
455 WM5100_MUX(name_str " Input 1", &name##_in1_mux), \
456 WM5100_MUX(name_str " Input 2", &name##_in2_mux), \
457 WM5100_MUX(name_str " Input 3", &name##_in3_mux), \
458 WM5100_MUX(name_str " Input 4", &name##_in4_mux), \
459 SND_SOC_DAPM_MIXER(name_str " Mixer", SND_SOC_NOPM, 0, 0, NULL, 0)
460
461 #define WM5100_MIXER_INPUT_ROUTES(name) \
462 { name, "Tone Generator 1", "Tone Generator 1" }, \
463 { name, "Tone Generator 2", "Tone Generator 2" }, \
464 { name, "IN1L", "IN1L PGA" }, \
465 { name, "IN1R", "IN1R PGA" }, \
466 { name, "IN2L", "IN2L PGA" }, \
467 { name, "IN2R", "IN2R PGA" }, \
468 { name, "IN3L", "IN3L PGA" }, \
469 { name, "IN3R", "IN3R PGA" }, \
470 { name, "IN4L", "IN4L PGA" }, \
471 { name, "IN4R", "IN4R PGA" }, \
472 { name, "AIF1RX1", "AIF1RX1" }, \
473 { name, "AIF1RX2", "AIF1RX2" }, \
474 { name, "AIF1RX3", "AIF1RX3" }, \
475 { name, "AIF1RX4", "AIF1RX4" }, \
476 { name, "AIF1RX5", "AIF1RX5" }, \
477 { name, "AIF1RX6", "AIF1RX6" }, \
478 { name, "AIF1RX7", "AIF1RX7" }, \
479 { name, "AIF1RX8", "AIF1RX8" }, \
480 { name, "AIF2RX1", "AIF2RX1" }, \
481 { name, "AIF2RX2", "AIF2RX2" }, \
482 { name, "AIF3RX1", "AIF3RX1" }, \
483 { name, "AIF3RX2", "AIF3RX2" }, \
484 { name, "EQ1", "EQ1" }, \
485 { name, "EQ2", "EQ2" }, \
486 { name, "EQ3", "EQ3" }, \
487 { name, "EQ4", "EQ4" }, \
488 { name, "DRC1L", "DRC1L" }, \
489 { name, "DRC1R", "DRC1R" }, \
490 { name, "LHPF1", "LHPF1" }, \
491 { name, "LHPF2", "LHPF2" }, \
492 { name, "LHPF3", "LHPF3" }, \
493 { name, "LHPF4", "LHPF4" }
494
495 #define WM5100_MIXER_ROUTES(widget, name) \
496 { widget, NULL, name " Mixer" }, \
497 { name " Mixer", NULL, name " Input 1" }, \
498 { name " Mixer", NULL, name " Input 2" }, \
499 { name " Mixer", NULL, name " Input 3" }, \
500 { name " Mixer", NULL, name " Input 4" }, \
501 WM5100_MIXER_INPUT_ROUTES(name " Input 1"), \
502 WM5100_MIXER_INPUT_ROUTES(name " Input 2"), \
503 WM5100_MIXER_INPUT_ROUTES(name " Input 3"), \
504 WM5100_MIXER_INPUT_ROUTES(name " Input 4")
505
506 static const char *wm5100_lhpf_mode_text[] = {
507 "Low-pass", "High-pass"
508 };
509
510 static const struct soc_enum wm5100_lhpf1_mode =
511 SOC_ENUM_SINGLE(WM5100_HPLPF1_1, WM5100_LHPF1_MODE_SHIFT, 2,
512 wm5100_lhpf_mode_text);
513
514 static const struct soc_enum wm5100_lhpf2_mode =
515 SOC_ENUM_SINGLE(WM5100_HPLPF2_1, WM5100_LHPF2_MODE_SHIFT, 2,
516 wm5100_lhpf_mode_text);
517
518 static const struct soc_enum wm5100_lhpf3_mode =
519 SOC_ENUM_SINGLE(WM5100_HPLPF3_1, WM5100_LHPF3_MODE_SHIFT, 2,
520 wm5100_lhpf_mode_text);
521
522 static const struct soc_enum wm5100_lhpf4_mode =
523 SOC_ENUM_SINGLE(WM5100_HPLPF4_1, WM5100_LHPF4_MODE_SHIFT, 2,
524 wm5100_lhpf_mode_text);
525
526 static const struct snd_kcontrol_new wm5100_snd_controls[] = {
527 SOC_SINGLE("IN1 High Performance Switch", WM5100_IN1L_CONTROL,
528 WM5100_IN1_OSR_SHIFT, 1, 0),
529 SOC_SINGLE("IN2 High Performance Switch", WM5100_IN2L_CONTROL,
530 WM5100_IN2_OSR_SHIFT, 1, 0),
531 SOC_SINGLE("IN3 High Performance Switch", WM5100_IN3L_CONTROL,
532 WM5100_IN3_OSR_SHIFT, 1, 0),
533 SOC_SINGLE("IN4 High Performance Switch", WM5100_IN4L_CONTROL,
534 WM5100_IN4_OSR_SHIFT, 1, 0),
535
536 /* Only applicable for analogue inputs */
537 SOC_DOUBLE_R_TLV("IN1 Volume", WM5100_IN1L_CONTROL, WM5100_IN1R_CONTROL,
538 WM5100_IN1L_PGA_VOL_SHIFT, 94, 0, in_tlv),
539 SOC_DOUBLE_R_TLV("IN2 Volume", WM5100_IN2L_CONTROL, WM5100_IN2R_CONTROL,
540 WM5100_IN2L_PGA_VOL_SHIFT, 94, 0, in_tlv),
541 SOC_DOUBLE_R_TLV("IN3 Volume", WM5100_IN3L_CONTROL, WM5100_IN3R_CONTROL,
542 WM5100_IN3L_PGA_VOL_SHIFT, 94, 0, in_tlv),
543 SOC_DOUBLE_R_TLV("IN4 Volume", WM5100_IN4L_CONTROL, WM5100_IN4R_CONTROL,
544 WM5100_IN4L_PGA_VOL_SHIFT, 94, 0, in_tlv),
545
546 SOC_DOUBLE_R_TLV("IN1 Digital Volume", WM5100_ADC_DIGITAL_VOLUME_1L,
547 WM5100_ADC_DIGITAL_VOLUME_1R, WM5100_IN1L_VOL_SHIFT, 191,
548 0, digital_tlv),
549 SOC_DOUBLE_R_TLV("IN2 Digital Volume", WM5100_ADC_DIGITAL_VOLUME_2L,
550 WM5100_ADC_DIGITAL_VOLUME_2R, WM5100_IN2L_VOL_SHIFT, 191,
551 0, digital_tlv),
552 SOC_DOUBLE_R_TLV("IN3 Digital Volume", WM5100_ADC_DIGITAL_VOLUME_3L,
553 WM5100_ADC_DIGITAL_VOLUME_3R, WM5100_IN3L_VOL_SHIFT, 191,
554 0, digital_tlv),
555 SOC_DOUBLE_R_TLV("IN4 Digital Volume", WM5100_ADC_DIGITAL_VOLUME_4L,
556 WM5100_ADC_DIGITAL_VOLUME_4R, WM5100_IN4L_VOL_SHIFT, 191,
557 0, digital_tlv),
558
559 SOC_DOUBLE_R("IN1 Switch", WM5100_ADC_DIGITAL_VOLUME_1L,
560 WM5100_ADC_DIGITAL_VOLUME_1R, WM5100_IN1L_MUTE_SHIFT, 1, 1),
561 SOC_DOUBLE_R("IN2 Switch", WM5100_ADC_DIGITAL_VOLUME_2L,
562 WM5100_ADC_DIGITAL_VOLUME_2R, WM5100_IN2L_MUTE_SHIFT, 1, 1),
563 SOC_DOUBLE_R("IN3 Switch", WM5100_ADC_DIGITAL_VOLUME_3L,
564 WM5100_ADC_DIGITAL_VOLUME_3R, WM5100_IN3L_MUTE_SHIFT, 1, 1),
565 SOC_DOUBLE_R("IN4 Switch", WM5100_ADC_DIGITAL_VOLUME_4L,
566 WM5100_ADC_DIGITAL_VOLUME_4R, WM5100_IN4L_MUTE_SHIFT, 1, 1),
567
568 SOC_SINGLE("HPOUT1 High Performance Switch", WM5100_OUT_VOLUME_1L,
569 WM5100_OUT1_OSR_SHIFT, 1, 0),
570 SOC_SINGLE("HPOUT2 High Performance Switch", WM5100_OUT_VOLUME_2L,
571 WM5100_OUT2_OSR_SHIFT, 1, 0),
572 SOC_SINGLE("HPOUT3 High Performance Switch", WM5100_OUT_VOLUME_3L,
573 WM5100_OUT3_OSR_SHIFT, 1, 0),
574 SOC_SINGLE("SPKOUT High Performance Switch", WM5100_OUT_VOLUME_4L,
575 WM5100_OUT4_OSR_SHIFT, 1, 0),
576 SOC_SINGLE("SPKDAT1 High Performance Switch", WM5100_DAC_VOLUME_LIMIT_5L,
577 WM5100_OUT5_OSR_SHIFT, 1, 0),
578 SOC_SINGLE("SPKDAT2 High Performance Switch", WM5100_DAC_VOLUME_LIMIT_6L,
579 WM5100_OUT6_OSR_SHIFT, 1, 0),
580
581 SOC_DOUBLE_R_TLV("HPOUT1 Digital Volume", WM5100_DAC_DIGITAL_VOLUME_1L,
582 WM5100_DAC_DIGITAL_VOLUME_1R, WM5100_OUT1L_VOL_SHIFT, 159, 0,
583 digital_tlv),
584 SOC_DOUBLE_R_TLV("HPOUT2 Digital Volume", WM5100_DAC_DIGITAL_VOLUME_2L,
585 WM5100_DAC_DIGITAL_VOLUME_2R, WM5100_OUT2L_VOL_SHIFT, 159, 0,
586 digital_tlv),
587 SOC_DOUBLE_R_TLV("HPOUT3 Digital Volume", WM5100_DAC_DIGITAL_VOLUME_3L,
588 WM5100_DAC_DIGITAL_VOLUME_3R, WM5100_OUT3L_VOL_SHIFT, 159, 0,
589 digital_tlv),
590 SOC_DOUBLE_R_TLV("SPKOUT Digital Volume", WM5100_DAC_DIGITAL_VOLUME_4L,
591 WM5100_DAC_DIGITAL_VOLUME_4R, WM5100_OUT4L_VOL_SHIFT, 159, 0,
592 digital_tlv),
593 SOC_DOUBLE_R_TLV("SPKDAT1 Digital Volume", WM5100_DAC_DIGITAL_VOLUME_5L,
594 WM5100_DAC_DIGITAL_VOLUME_5R, WM5100_OUT5L_VOL_SHIFT, 159, 0,
595 digital_tlv),
596 SOC_DOUBLE_R_TLV("SPKDAT2 Digital Volume", WM5100_DAC_DIGITAL_VOLUME_6L,
597 WM5100_DAC_DIGITAL_VOLUME_6R, WM5100_OUT6L_VOL_SHIFT, 159, 0,
598 digital_tlv),
599
600 SOC_DOUBLE_R("HPOUT1 Digital Switch", WM5100_DAC_DIGITAL_VOLUME_1L,
601 WM5100_DAC_DIGITAL_VOLUME_1R, WM5100_OUT1L_MUTE_SHIFT, 1, 1),
602 SOC_DOUBLE_R("HPOUT2 Digital Switch", WM5100_DAC_DIGITAL_VOLUME_2L,
603 WM5100_DAC_DIGITAL_VOLUME_2R, WM5100_OUT2L_MUTE_SHIFT, 1, 1),
604 SOC_DOUBLE_R("HPOUT3 Digital Switch", WM5100_DAC_DIGITAL_VOLUME_3L,
605 WM5100_DAC_DIGITAL_VOLUME_3R, WM5100_OUT3L_MUTE_SHIFT, 1, 1),
606 SOC_DOUBLE_R("SPKOUT Digital Switch", WM5100_DAC_DIGITAL_VOLUME_4L,
607 WM5100_DAC_DIGITAL_VOLUME_4R, WM5100_OUT4L_MUTE_SHIFT, 1, 1),
608 SOC_DOUBLE_R("SPKDAT1 Digital Switch", WM5100_DAC_DIGITAL_VOLUME_5L,
609 WM5100_DAC_DIGITAL_VOLUME_5R, WM5100_OUT5L_MUTE_SHIFT, 1, 1),
610 SOC_DOUBLE_R("SPKDAT2 Digital Switch", WM5100_DAC_DIGITAL_VOLUME_6L,
611 WM5100_DAC_DIGITAL_VOLUME_6R, WM5100_OUT6L_MUTE_SHIFT, 1, 1),
612
613 /* FIXME: Only valid from -12dB to 0dB (52-64) */
614 SOC_DOUBLE_R_TLV("HPOUT1 Volume", WM5100_OUT_VOLUME_1L, WM5100_OUT_VOLUME_1R,
615 WM5100_OUT1L_PGA_VOL_SHIFT, 64, 0, out_tlv),
616 SOC_DOUBLE_R_TLV("HPOUT2 Volume", WM5100_OUT_VOLUME_2L, WM5100_OUT_VOLUME_2R,
617 WM5100_OUT2L_PGA_VOL_SHIFT, 64, 0, out_tlv),
618 SOC_DOUBLE_R_TLV("HPOUT3 Volume", WM5100_OUT_VOLUME_3L, WM5100_OUT_VOLUME_3R,
619 WM5100_OUT2L_PGA_VOL_SHIFT, 64, 0, out_tlv),
620
621 SOC_DOUBLE("SPKDAT1 Switch", WM5100_PDM_SPK1_CTRL_1, WM5100_SPK1L_MUTE_SHIFT,
622 WM5100_SPK1R_MUTE_SHIFT, 1, 1),
623 SOC_DOUBLE("SPKDAT2 Switch", WM5100_PDM_SPK2_CTRL_1, WM5100_SPK2L_MUTE_SHIFT,
624 WM5100_SPK2R_MUTE_SHIFT, 1, 1),
625
626 SOC_SINGLE_TLV("EQ1 Band 1 Volume", WM5100_EQ1_1, WM5100_EQ1_B1_GAIN_SHIFT,
627 24, 0, eq_tlv),
628 SOC_SINGLE_TLV("EQ1 Band 2 Volume", WM5100_EQ1_1, WM5100_EQ1_B2_GAIN_SHIFT,
629 24, 0, eq_tlv),
630 SOC_SINGLE_TLV("EQ1 Band 3 Volume", WM5100_EQ1_1, WM5100_EQ1_B3_GAIN_SHIFT,
631 24, 0, eq_tlv),
632 SOC_SINGLE_TLV("EQ1 Band 4 Volume", WM5100_EQ1_2, WM5100_EQ1_B4_GAIN_SHIFT,
633 24, 0, eq_tlv),
634 SOC_SINGLE_TLV("EQ1 Band 5 Volume", WM5100_EQ1_2, WM5100_EQ1_B5_GAIN_SHIFT,
635 24, 0, eq_tlv),
636
637 SOC_SINGLE_TLV("EQ2 Band 1 Volume", WM5100_EQ2_1, WM5100_EQ2_B1_GAIN_SHIFT,
638 24, 0, eq_tlv),
639 SOC_SINGLE_TLV("EQ2 Band 2 Volume", WM5100_EQ2_1, WM5100_EQ2_B2_GAIN_SHIFT,
640 24, 0, eq_tlv),
641 SOC_SINGLE_TLV("EQ2 Band 3 Volume", WM5100_EQ2_1, WM5100_EQ2_B3_GAIN_SHIFT,
642 24, 0, eq_tlv),
643 SOC_SINGLE_TLV("EQ2 Band 4 Volume", WM5100_EQ2_2, WM5100_EQ2_B4_GAIN_SHIFT,
644 24, 0, eq_tlv),
645 SOC_SINGLE_TLV("EQ2 Band 5 Volume", WM5100_EQ2_2, WM5100_EQ2_B5_GAIN_SHIFT,
646 24, 0, eq_tlv),
647
648 SOC_SINGLE_TLV("EQ3 Band 1 Volume", WM5100_EQ1_1, WM5100_EQ3_B1_GAIN_SHIFT,
649 24, 0, eq_tlv),
650 SOC_SINGLE_TLV("EQ3 Band 2 Volume", WM5100_EQ3_1, WM5100_EQ3_B2_GAIN_SHIFT,
651 24, 0, eq_tlv),
652 SOC_SINGLE_TLV("EQ3 Band 3 Volume", WM5100_EQ3_1, WM5100_EQ3_B3_GAIN_SHIFT,
653 24, 0, eq_tlv),
654 SOC_SINGLE_TLV("EQ3 Band 4 Volume", WM5100_EQ3_2, WM5100_EQ3_B4_GAIN_SHIFT,
655 24, 0, eq_tlv),
656 SOC_SINGLE_TLV("EQ3 Band 5 Volume", WM5100_EQ3_2, WM5100_EQ3_B5_GAIN_SHIFT,
657 24, 0, eq_tlv),
658
659 SOC_SINGLE_TLV("EQ4 Band 1 Volume", WM5100_EQ4_1, WM5100_EQ4_B1_GAIN_SHIFT,
660 24, 0, eq_tlv),
661 SOC_SINGLE_TLV("EQ4 Band 2 Volume", WM5100_EQ4_1, WM5100_EQ4_B2_GAIN_SHIFT,
662 24, 0, eq_tlv),
663 SOC_SINGLE_TLV("EQ4 Band 3 Volume", WM5100_EQ4_1, WM5100_EQ4_B3_GAIN_SHIFT,
664 24, 0, eq_tlv),
665 SOC_SINGLE_TLV("EQ4 Band 4 Volume", WM5100_EQ4_2, WM5100_EQ4_B4_GAIN_SHIFT,
666 24, 0, eq_tlv),
667 SOC_SINGLE_TLV("EQ4 Band 5 Volume", WM5100_EQ4_2, WM5100_EQ4_B5_GAIN_SHIFT,
668 24, 0, eq_tlv),
669
670 SOC_ENUM("LHPF1 Mode", wm5100_lhpf1_mode),
671 SOC_ENUM("LHPF2 Mode", wm5100_lhpf2_mode),
672 SOC_ENUM("LHPF3 Mode", wm5100_lhpf3_mode),
673 SOC_ENUM("LHPF4 Mode", wm5100_lhpf4_mode),
674
675 WM5100_MIXER_CONTROLS("HPOUT1L", WM5100_OUT1LMIX_INPUT_1_SOURCE),
676 WM5100_MIXER_CONTROLS("HPOUT1R", WM5100_OUT1RMIX_INPUT_1_SOURCE),
677 WM5100_MIXER_CONTROLS("HPOUT2L", WM5100_OUT2LMIX_INPUT_1_SOURCE),
678 WM5100_MIXER_CONTROLS("HPOUT2R", WM5100_OUT2RMIX_INPUT_1_SOURCE),
679 WM5100_MIXER_CONTROLS("HPOUT3L", WM5100_OUT3LMIX_INPUT_1_SOURCE),
680 WM5100_MIXER_CONTROLS("HPOUT3R", WM5100_OUT3RMIX_INPUT_1_SOURCE),
681
682 WM5100_MIXER_CONTROLS("SPKOUTL", WM5100_OUT4LMIX_INPUT_1_SOURCE),
683 WM5100_MIXER_CONTROLS("SPKOUTR", WM5100_OUT4RMIX_INPUT_1_SOURCE),
684 WM5100_MIXER_CONTROLS("SPKDAT1L", WM5100_OUT5LMIX_INPUT_1_SOURCE),
685 WM5100_MIXER_CONTROLS("SPKDAT1R", WM5100_OUT5RMIX_INPUT_1_SOURCE),
686 WM5100_MIXER_CONTROLS("SPKDAT2L", WM5100_OUT6LMIX_INPUT_1_SOURCE),
687 WM5100_MIXER_CONTROLS("SPKDAT2R", WM5100_OUT6RMIX_INPUT_1_SOURCE),
688
689 WM5100_MIXER_CONTROLS("PWM1", WM5100_PWM1MIX_INPUT_1_SOURCE),
690 WM5100_MIXER_CONTROLS("PWM2", WM5100_PWM2MIX_INPUT_1_SOURCE),
691
692 WM5100_MIXER_CONTROLS("AIF1TX1", WM5100_AIF1TX1MIX_INPUT_1_SOURCE),
693 WM5100_MIXER_CONTROLS("AIF1TX2", WM5100_AIF1TX2MIX_INPUT_1_SOURCE),
694 WM5100_MIXER_CONTROLS("AIF1TX3", WM5100_AIF1TX3MIX_INPUT_1_SOURCE),
695 WM5100_MIXER_CONTROLS("AIF1TX4", WM5100_AIF1TX4MIX_INPUT_1_SOURCE),
696 WM5100_MIXER_CONTROLS("AIF1TX5", WM5100_AIF1TX5MIX_INPUT_1_SOURCE),
697 WM5100_MIXER_CONTROLS("AIF1TX6", WM5100_AIF1TX6MIX_INPUT_1_SOURCE),
698 WM5100_MIXER_CONTROLS("AIF1TX7", WM5100_AIF1TX7MIX_INPUT_1_SOURCE),
699 WM5100_MIXER_CONTROLS("AIF1TX8", WM5100_AIF1TX8MIX_INPUT_1_SOURCE),
700
701 WM5100_MIXER_CONTROLS("AIF2TX1", WM5100_AIF2TX1MIX_INPUT_1_SOURCE),
702 WM5100_MIXER_CONTROLS("AIF2TX2", WM5100_AIF2TX2MIX_INPUT_1_SOURCE),
703
704 WM5100_MIXER_CONTROLS("AIF3TX1", WM5100_AIF3TX1MIX_INPUT_1_SOURCE),
705 WM5100_MIXER_CONTROLS("AIF3TX2", WM5100_AIF3TX2MIX_INPUT_1_SOURCE),
706
707 WM5100_MIXER_CONTROLS("EQ1", WM5100_EQ1MIX_INPUT_1_SOURCE),
708 WM5100_MIXER_CONTROLS("EQ2", WM5100_EQ2MIX_INPUT_1_SOURCE),
709 WM5100_MIXER_CONTROLS("EQ3", WM5100_EQ3MIX_INPUT_1_SOURCE),
710 WM5100_MIXER_CONTROLS("EQ4", WM5100_EQ4MIX_INPUT_1_SOURCE),
711
712 WM5100_MIXER_CONTROLS("DRC1L", WM5100_DRC1LMIX_INPUT_1_SOURCE),
713 WM5100_MIXER_CONTROLS("DRC1R", WM5100_DRC1RMIX_INPUT_1_SOURCE),
714
715 WM5100_MIXER_CONTROLS("LHPF1", WM5100_HPLP1MIX_INPUT_1_SOURCE),
716 WM5100_MIXER_CONTROLS("LHPF2", WM5100_HPLP2MIX_INPUT_1_SOURCE),
717 WM5100_MIXER_CONTROLS("LHPF3", WM5100_HPLP3MIX_INPUT_1_SOURCE),
718 WM5100_MIXER_CONTROLS("LHPF4", WM5100_HPLP4MIX_INPUT_1_SOURCE),
719 };
720
721 static void wm5100_seq_notifier(struct snd_soc_dapm_context *dapm,
722 enum snd_soc_dapm_type event, int subseq)
723 {
724 struct snd_soc_codec *codec = container_of(dapm,
725 struct snd_soc_codec, dapm);
726 struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
727 u16 val, expect, i;
728
729 /* Wait for the outputs to flag themselves as enabled */
730 if (wm5100->out_ena[0]) {
731 expect = snd_soc_read(codec, WM5100_CHANNEL_ENABLES_1);
732 for (i = 0; i < 200; i++) {
733 val = snd_soc_read(codec, WM5100_OUTPUT_STATUS_1);
734 if (val == expect) {
735 wm5100->out_ena[0] = false;
736 break;
737 }
738 }
739 if (i == 200) {
740 dev_err(codec->dev, "Timeout waiting for OUTPUT1 %x\n",
741 expect);
742 }
743 }
744
745 if (wm5100->out_ena[1]) {
746 expect = snd_soc_read(codec, WM5100_OUTPUT_ENABLES_2);
747 for (i = 0; i < 200; i++) {
748 val = snd_soc_read(codec, WM5100_OUTPUT_STATUS_2);
749 if (val == expect) {
750 wm5100->out_ena[1] = false;
751 break;
752 }
753 }
754 if (i == 200) {
755 dev_err(codec->dev, "Timeout waiting for OUTPUT2 %x\n",
756 expect);
757 }
758 }
759 }
760
761 static int wm5100_out_ev(struct snd_soc_dapm_widget *w,
762 struct snd_kcontrol *kcontrol,
763 int event)
764 {
765 struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(w->codec);
766
767 switch (w->reg) {
768 case WM5100_CHANNEL_ENABLES_1:
769 wm5100->out_ena[0] = true;
770 break;
771 case WM5100_OUTPUT_ENABLES_2:
772 wm5100->out_ena[0] = true;
773 break;
774 default:
775 break;
776 }
777
778 return 0;
779 }
780
781 static int wm5100_cp_ev(struct snd_soc_dapm_widget *w,
782 struct snd_kcontrol *kcontrol,
783 int event)
784 {
785 struct snd_soc_codec *codec = w->codec;
786 struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
787 int ret;
788
789 switch (event) {
790 case SND_SOC_DAPM_PRE_PMU:
791 ret = regulator_enable(wm5100->cpvdd);
792 if (ret != 0) {
793 dev_err(codec->dev, "Failed to enable CPVDD: %d\n",
794 ret);
795 return ret;
796 }
797 return ret;
798
799 case SND_SOC_DAPM_POST_PMD:
800 ret = regulator_disable_deferred(wm5100->cpvdd, 20);
801 if (ret != 0) {
802 dev_err(codec->dev, "Failed to disable CPVDD: %d\n",
803 ret);
804 return ret;
805 }
806 return ret;
807
808 default:
809 BUG();
810 return 0;
811 }
812 }
813
814 static int wm5100_dbvdd_ev(struct snd_soc_dapm_widget *w,
815 struct snd_kcontrol *kcontrol,
816 int event)
817 {
818 struct snd_soc_codec *codec = w->codec;
819 struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
820 struct regulator *regulator;
821 int ret;
822
823 switch (w->shift) {
824 case 2:
825 regulator = wm5100->dbvdd2;
826 break;
827 case 3:
828 regulator = wm5100->dbvdd3;
829 break;
830 default:
831 BUG();
832 return 0;
833 }
834
835 switch (event) {
836 case SND_SOC_DAPM_PRE_PMU:
837 ret = regulator_enable(regulator);
838 if (ret != 0) {
839 dev_err(codec->dev, "Failed to enable DBVDD%d: %d\n",
840 w->shift, ret);
841 return ret;
842 }
843 return ret;
844
845 case SND_SOC_DAPM_POST_PMD:
846 ret = regulator_disable(regulator);
847 if (ret != 0) {
848 dev_err(codec->dev, "Failed to enable DBVDD%d: %d\n",
849 w->shift, ret);
850 return ret;
851 }
852 return ret;
853
854 default:
855 BUG();
856 return 0;
857 }
858 }
859
860 static void wm5100_log_status3(struct snd_soc_codec *codec, int val)
861 {
862 if (val & WM5100_SPK_SHUTDOWN_WARN_EINT)
863 dev_crit(codec->dev, "Speaker shutdown warning\n");
864 if (val & WM5100_SPK_SHUTDOWN_EINT)
865 dev_crit(codec->dev, "Speaker shutdown\n");
866 if (val & WM5100_CLKGEN_ERR_EINT)
867 dev_crit(codec->dev, "SYSCLK underclocked\n");
868 if (val & WM5100_CLKGEN_ERR_ASYNC_EINT)
869 dev_crit(codec->dev, "ASYNCCLK underclocked\n");
870 }
871
872 static void wm5100_log_status4(struct snd_soc_codec *codec, int val)
873 {
874 if (val & WM5100_AIF3_ERR_EINT)
875 dev_err(codec->dev, "AIF3 configuration error\n");
876 if (val & WM5100_AIF2_ERR_EINT)
877 dev_err(codec->dev, "AIF2 configuration error\n");
878 if (val & WM5100_AIF1_ERR_EINT)
879 dev_err(codec->dev, "AIF1 configuration error\n");
880 if (val & WM5100_CTRLIF_ERR_EINT)
881 dev_err(codec->dev, "Control interface error\n");
882 if (val & WM5100_ISRC2_UNDERCLOCKED_EINT)
883 dev_err(codec->dev, "ISRC2 underclocked\n");
884 if (val & WM5100_ISRC1_UNDERCLOCKED_EINT)
885 dev_err(codec->dev, "ISRC1 underclocked\n");
886 if (val & WM5100_FX_UNDERCLOCKED_EINT)
887 dev_err(codec->dev, "FX underclocked\n");
888 if (val & WM5100_AIF3_UNDERCLOCKED_EINT)
889 dev_err(codec->dev, "AIF3 underclocked\n");
890 if (val & WM5100_AIF2_UNDERCLOCKED_EINT)
891 dev_err(codec->dev, "AIF2 underclocked\n");
892 if (val & WM5100_AIF1_UNDERCLOCKED_EINT)
893 dev_err(codec->dev, "AIF1 underclocked\n");
894 if (val & WM5100_ASRC_UNDERCLOCKED_EINT)
895 dev_err(codec->dev, "ASRC underclocked\n");
896 if (val & WM5100_DAC_UNDERCLOCKED_EINT)
897 dev_err(codec->dev, "DAC underclocked\n");
898 if (val & WM5100_ADC_UNDERCLOCKED_EINT)
899 dev_err(codec->dev, "ADC underclocked\n");
900 if (val & WM5100_MIXER_UNDERCLOCKED_EINT)
901 dev_err(codec->dev, "Mixer underclocked\n");
902 }
903
904 static int wm5100_post_ev(struct snd_soc_dapm_widget *w,
905 struct snd_kcontrol *kcontrol,
906 int event)
907 {
908 struct snd_soc_codec *codec = w->codec;
909 int ret;
910
911 ret = snd_soc_read(codec, WM5100_INTERRUPT_RAW_STATUS_3);
912 ret &= WM5100_SPK_SHUTDOWN_WARN_STS |
913 WM5100_SPK_SHUTDOWN_STS | WM5100_CLKGEN_ERR_STS |
914 WM5100_CLKGEN_ERR_ASYNC_STS;
915 wm5100_log_status3(codec, ret);
916
917 ret = snd_soc_read(codec, WM5100_INTERRUPT_RAW_STATUS_4);
918 wm5100_log_status4(codec, ret);
919
920 return 0;
921 }
922
923 static const struct snd_soc_dapm_widget wm5100_dapm_widgets[] = {
924 SND_SOC_DAPM_SUPPLY("SYSCLK", WM5100_CLOCKING_3, WM5100_SYSCLK_ENA_SHIFT, 0,
925 NULL, 0),
926 SND_SOC_DAPM_SUPPLY("ASYNCCLK", WM5100_CLOCKING_6, WM5100_ASYNC_CLK_ENA_SHIFT,
927 0, NULL, 0),
928
929 SND_SOC_DAPM_SUPPLY("CP1", WM5100_HP_CHARGE_PUMP_1, WM5100_CP1_ENA_SHIFT, 0,
930 wm5100_cp_ev,
931 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
932 SND_SOC_DAPM_SUPPLY("CP2", WM5100_MIC_CHARGE_PUMP_1, WM5100_CP2_ENA_SHIFT, 0,
933 NULL, 0),
934 SND_SOC_DAPM_SUPPLY("CP2 Active", WM5100_MIC_CHARGE_PUMP_1,
935 WM5100_CP2_BYPASS_SHIFT, 1, wm5100_cp_ev,
936 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
937 SND_SOC_DAPM_SUPPLY("DBVDD2", SND_SOC_NOPM, 2, 0, wm5100_dbvdd_ev,
938 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
939 SND_SOC_DAPM_SUPPLY("DBVDD3", SND_SOC_NOPM, 3, 0, wm5100_dbvdd_ev,
940 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
941
942 SND_SOC_DAPM_SUPPLY("MICBIAS1", WM5100_MIC_BIAS_CTRL_1, WM5100_MICB1_ENA_SHIFT,
943 0, NULL, 0),
944 SND_SOC_DAPM_SUPPLY("MICBIAS2", WM5100_MIC_BIAS_CTRL_2, WM5100_MICB2_ENA_SHIFT,
945 0, NULL, 0),
946 SND_SOC_DAPM_SUPPLY("MICBIAS3", WM5100_MIC_BIAS_CTRL_3, WM5100_MICB3_ENA_SHIFT,
947 0, NULL, 0),
948
949 SND_SOC_DAPM_INPUT("IN1L"),
950 SND_SOC_DAPM_INPUT("IN1R"),
951 SND_SOC_DAPM_INPUT("IN2L"),
952 SND_SOC_DAPM_INPUT("IN2R"),
953 SND_SOC_DAPM_INPUT("IN3L"),
954 SND_SOC_DAPM_INPUT("IN3R"),
955 SND_SOC_DAPM_INPUT("IN4L"),
956 SND_SOC_DAPM_INPUT("IN4R"),
957 SND_SOC_DAPM_INPUT("TONE"),
958
959 SND_SOC_DAPM_PGA_E("IN1L PGA", WM5100_INPUT_ENABLES, WM5100_IN1L_ENA_SHIFT, 0,
960 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
961 SND_SOC_DAPM_PGA_E("IN1R PGA", WM5100_INPUT_ENABLES, WM5100_IN1R_ENA_SHIFT, 0,
962 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
963 SND_SOC_DAPM_PGA_E("IN2L PGA", WM5100_INPUT_ENABLES, WM5100_IN2L_ENA_SHIFT, 0,
964 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
965 SND_SOC_DAPM_PGA_E("IN2R PGA", WM5100_INPUT_ENABLES, WM5100_IN2R_ENA_SHIFT, 0,
966 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
967 SND_SOC_DAPM_PGA_E("IN3L PGA", WM5100_INPUT_ENABLES, WM5100_IN3L_ENA_SHIFT, 0,
968 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
969 SND_SOC_DAPM_PGA_E("IN3R PGA", WM5100_INPUT_ENABLES, WM5100_IN3R_ENA_SHIFT, 0,
970 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
971 SND_SOC_DAPM_PGA_E("IN4L PGA", WM5100_INPUT_ENABLES, WM5100_IN4L_ENA_SHIFT, 0,
972 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
973 SND_SOC_DAPM_PGA_E("IN4R PGA", WM5100_INPUT_ENABLES, WM5100_IN4R_ENA_SHIFT, 0,
974 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
975
976 SND_SOC_DAPM_PGA("Tone Generator 1", WM5100_TONE_GENERATOR_1,
977 WM5100_TONE1_ENA_SHIFT, 0, NULL, 0),
978 SND_SOC_DAPM_PGA("Tone Generator 2", WM5100_TONE_GENERATOR_1,
979 WM5100_TONE2_ENA_SHIFT, 0, NULL, 0),
980
981 SND_SOC_DAPM_AIF_IN("AIF1RX1", "AIF1 Playback", 0,
982 WM5100_AUDIO_IF_1_27, WM5100_AIF1RX1_ENA_SHIFT, 0),
983 SND_SOC_DAPM_AIF_IN("AIF1RX2", "AIF1 Playback", 1,
984 WM5100_AUDIO_IF_1_27, WM5100_AIF1RX2_ENA_SHIFT, 0),
985 SND_SOC_DAPM_AIF_IN("AIF1RX3", "AIF1 Playback", 2,
986 WM5100_AUDIO_IF_1_27, WM5100_AIF1RX3_ENA_SHIFT, 0),
987 SND_SOC_DAPM_AIF_IN("AIF1RX4", "AIF1 Playback", 3,
988 WM5100_AUDIO_IF_1_27, WM5100_AIF1RX4_ENA_SHIFT, 0),
989 SND_SOC_DAPM_AIF_IN("AIF1RX5", "AIF1 Playback", 4,
990 WM5100_AUDIO_IF_1_27, WM5100_AIF1RX5_ENA_SHIFT, 0),
991 SND_SOC_DAPM_AIF_IN("AIF1RX6", "AIF1 Playback", 5,
992 WM5100_AUDIO_IF_1_27, WM5100_AIF1RX6_ENA_SHIFT, 0),
993 SND_SOC_DAPM_AIF_IN("AIF1RX7", "AIF1 Playback", 6,
994 WM5100_AUDIO_IF_1_27, WM5100_AIF1RX7_ENA_SHIFT, 0),
995 SND_SOC_DAPM_AIF_IN("AIF1RX8", "AIF1 Playback", 7,
996 WM5100_AUDIO_IF_1_27, WM5100_AIF1RX8_ENA_SHIFT, 0),
997
998 SND_SOC_DAPM_AIF_IN("AIF2RX1", "AIF2 Playback", 0,
999 WM5100_AUDIO_IF_2_27, WM5100_AIF2RX1_ENA_SHIFT, 0),
1000 SND_SOC_DAPM_AIF_IN("AIF2RX2", "AIF2 Playback", 1,
1001 WM5100_AUDIO_IF_2_27, WM5100_AIF2RX2_ENA_SHIFT, 0),
1002
1003 SND_SOC_DAPM_AIF_IN("AIF3RX1", "AIF3 Playback", 0,
1004 WM5100_AUDIO_IF_3_27, WM5100_AIF3RX1_ENA_SHIFT, 0),
1005 SND_SOC_DAPM_AIF_IN("AIF3RX2", "AIF3 Playback", 1,
1006 WM5100_AUDIO_IF_3_27, WM5100_AIF3RX2_ENA_SHIFT, 0),
1007
1008 SND_SOC_DAPM_AIF_OUT("AIF1TX1", "AIF1 Capture", 0,
1009 WM5100_AUDIO_IF_1_26, WM5100_AIF1TX1_ENA_SHIFT, 0),
1010 SND_SOC_DAPM_AIF_OUT("AIF1TX2", "AIF1 Capture", 1,
1011 WM5100_AUDIO_IF_1_26, WM5100_AIF1TX2_ENA_SHIFT, 0),
1012 SND_SOC_DAPM_AIF_OUT("AIF1TX3", "AIF1 Capture", 2,
1013 WM5100_AUDIO_IF_1_26, WM5100_AIF1TX3_ENA_SHIFT, 0),
1014 SND_SOC_DAPM_AIF_OUT("AIF1TX4", "AIF1 Capture", 3,
1015 WM5100_AUDIO_IF_1_26, WM5100_AIF1TX4_ENA_SHIFT, 0),
1016 SND_SOC_DAPM_AIF_OUT("AIF1TX5", "AIF1 Capture", 4,
1017 WM5100_AUDIO_IF_1_26, WM5100_AIF1TX5_ENA_SHIFT, 0),
1018 SND_SOC_DAPM_AIF_OUT("AIF1TX6", "AIF1 Capture", 5,
1019 WM5100_AUDIO_IF_1_26, WM5100_AIF1TX6_ENA_SHIFT, 0),
1020 SND_SOC_DAPM_AIF_OUT("AIF1TX7", "AIF1 Capture", 6,
1021 WM5100_AUDIO_IF_1_26, WM5100_AIF1TX7_ENA_SHIFT, 0),
1022 SND_SOC_DAPM_AIF_OUT("AIF1TX8", "AIF1 Capture", 7,
1023 WM5100_AUDIO_IF_1_26, WM5100_AIF1TX8_ENA_SHIFT, 0),
1024
1025 SND_SOC_DAPM_AIF_OUT("AIF2TX1", "AIF2 Capture", 0,
1026 WM5100_AUDIO_IF_2_26, WM5100_AIF2TX1_ENA_SHIFT, 0),
1027 SND_SOC_DAPM_AIF_OUT("AIF2TX2", "AIF2 Capture", 1,
1028 WM5100_AUDIO_IF_2_26, WM5100_AIF2TX2_ENA_SHIFT, 0),
1029
1030 SND_SOC_DAPM_AIF_OUT("AIF3TX1", "AIF3 Capture", 0,
1031 WM5100_AUDIO_IF_3_26, WM5100_AIF3TX1_ENA_SHIFT, 0),
1032 SND_SOC_DAPM_AIF_OUT("AIF3TX2", "AIF3 Capture", 1,
1033 WM5100_AUDIO_IF_3_26, WM5100_AIF3TX2_ENA_SHIFT, 0),
1034
1035 SND_SOC_DAPM_PGA_E("OUT6L", WM5100_OUTPUT_ENABLES_2, WM5100_OUT6L_ENA_SHIFT, 0,
1036 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
1037 SND_SOC_DAPM_PGA_E("OUT6R", WM5100_OUTPUT_ENABLES_2, WM5100_OUT6R_ENA_SHIFT, 0,
1038 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
1039 SND_SOC_DAPM_PGA_E("OUT5L", WM5100_OUTPUT_ENABLES_2, WM5100_OUT5L_ENA_SHIFT, 0,
1040 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
1041 SND_SOC_DAPM_PGA_E("OUT5R", WM5100_OUTPUT_ENABLES_2, WM5100_OUT5R_ENA_SHIFT, 0,
1042 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
1043 SND_SOC_DAPM_PGA_E("OUT4L", WM5100_OUTPUT_ENABLES_2, WM5100_OUT4L_ENA_SHIFT, 0,
1044 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
1045 SND_SOC_DAPM_PGA_E("OUT4R", WM5100_OUTPUT_ENABLES_2, WM5100_OUT4R_ENA_SHIFT, 0,
1046 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
1047 SND_SOC_DAPM_PGA_E("OUT3L", WM5100_CHANNEL_ENABLES_1, WM5100_HP3L_ENA_SHIFT, 0,
1048 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
1049 SND_SOC_DAPM_PGA_E("OUT3R", WM5100_CHANNEL_ENABLES_1, WM5100_HP3R_ENA_SHIFT, 0,
1050 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
1051 SND_SOC_DAPM_PGA_E("OUT2L", WM5100_CHANNEL_ENABLES_1, WM5100_HP2L_ENA_SHIFT, 0,
1052 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
1053 SND_SOC_DAPM_PGA_E("OUT2R", WM5100_CHANNEL_ENABLES_1, WM5100_HP2R_ENA_SHIFT, 0,
1054 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
1055 SND_SOC_DAPM_PGA_E("OUT1L", WM5100_CHANNEL_ENABLES_1, WM5100_HP1L_ENA_SHIFT, 0,
1056 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
1057 SND_SOC_DAPM_PGA_E("OUT1R", WM5100_CHANNEL_ENABLES_1, WM5100_HP1R_ENA_SHIFT, 0,
1058 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
1059 SND_SOC_DAPM_PGA_E("PWM1 Driver", WM5100_PWM_DRIVE_1, WM5100_PWM1_ENA_SHIFT, 0,
1060 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
1061 SND_SOC_DAPM_PGA_E("PWM2 Driver", WM5100_PWM_DRIVE_1, WM5100_PWM2_ENA_SHIFT, 0,
1062 NULL, 0, wm5100_out_ev, SND_SOC_DAPM_POST_PMU),
1063
1064 SND_SOC_DAPM_PGA("EQ1", WM5100_EQ1_1, WM5100_EQ1_ENA_SHIFT, 0, NULL, 0),
1065 SND_SOC_DAPM_PGA("EQ2", WM5100_EQ2_1, WM5100_EQ2_ENA_SHIFT, 0, NULL, 0),
1066 SND_SOC_DAPM_PGA("EQ3", WM5100_EQ3_1, WM5100_EQ3_ENA_SHIFT, 0, NULL, 0),
1067 SND_SOC_DAPM_PGA("EQ4", WM5100_EQ4_1, WM5100_EQ4_ENA_SHIFT, 0, NULL, 0),
1068
1069 SND_SOC_DAPM_PGA("DRC1L", WM5100_DRC1_CTRL1, WM5100_DRCL_ENA_SHIFT, 0,
1070 NULL, 0),
1071 SND_SOC_DAPM_PGA("DRC1R", WM5100_DRC1_CTRL1, WM5100_DRCR_ENA_SHIFT, 0,
1072 NULL, 0),
1073
1074 SND_SOC_DAPM_PGA("LHPF1", WM5100_HPLPF1_1, WM5100_LHPF1_ENA_SHIFT, 0,
1075 NULL, 0),
1076 SND_SOC_DAPM_PGA("LHPF2", WM5100_HPLPF2_1, WM5100_LHPF2_ENA_SHIFT, 0,
1077 NULL, 0),
1078 SND_SOC_DAPM_PGA("LHPF3", WM5100_HPLPF3_1, WM5100_LHPF3_ENA_SHIFT, 0,
1079 NULL, 0),
1080 SND_SOC_DAPM_PGA("LHPF4", WM5100_HPLPF4_1, WM5100_LHPF4_ENA_SHIFT, 0,
1081 NULL, 0),
1082
1083 WM5100_MIXER_WIDGETS(EQ1, "EQ1"),
1084 WM5100_MIXER_WIDGETS(EQ2, "EQ2"),
1085 WM5100_MIXER_WIDGETS(EQ3, "EQ3"),
1086 WM5100_MIXER_WIDGETS(EQ4, "EQ4"),
1087
1088 WM5100_MIXER_WIDGETS(DRC1L, "DRC1L"),
1089 WM5100_MIXER_WIDGETS(DRC1R, "DRC1R"),
1090
1091 WM5100_MIXER_WIDGETS(LHPF1, "LHPF1"),
1092 WM5100_MIXER_WIDGETS(LHPF2, "LHPF2"),
1093 WM5100_MIXER_WIDGETS(LHPF3, "LHPF3"),
1094 WM5100_MIXER_WIDGETS(LHPF4, "LHPF4"),
1095
1096 WM5100_MIXER_WIDGETS(AIF1TX1, "AIF1TX1"),
1097 WM5100_MIXER_WIDGETS(AIF1TX2, "AIF1TX2"),
1098 WM5100_MIXER_WIDGETS(AIF1TX3, "AIF1TX3"),
1099 WM5100_MIXER_WIDGETS(AIF1TX4, "AIF1TX4"),
1100 WM5100_MIXER_WIDGETS(AIF1TX5, "AIF1TX5"),
1101 WM5100_MIXER_WIDGETS(AIF1TX6, "AIF1TX6"),
1102 WM5100_MIXER_WIDGETS(AIF1TX7, "AIF1TX7"),
1103 WM5100_MIXER_WIDGETS(AIF1TX8, "AIF1TX8"),
1104
1105 WM5100_MIXER_WIDGETS(AIF2TX1, "AIF2TX1"),
1106 WM5100_MIXER_WIDGETS(AIF2TX2, "AIF2TX2"),
1107
1108 WM5100_MIXER_WIDGETS(AIF3TX1, "AIF3TX1"),
1109 WM5100_MIXER_WIDGETS(AIF3TX2, "AIF3TX2"),
1110
1111 WM5100_MIXER_WIDGETS(HPOUT1L, "HPOUT1L"),
1112 WM5100_MIXER_WIDGETS(HPOUT1R, "HPOUT1R"),
1113 WM5100_MIXER_WIDGETS(HPOUT2L, "HPOUT2L"),
1114 WM5100_MIXER_WIDGETS(HPOUT2R, "HPOUT2R"),
1115 WM5100_MIXER_WIDGETS(HPOUT3L, "HPOUT3L"),
1116 WM5100_MIXER_WIDGETS(HPOUT3R, "HPOUT3R"),
1117
1118 WM5100_MIXER_WIDGETS(SPKOUTL, "SPKOUTL"),
1119 WM5100_MIXER_WIDGETS(SPKOUTR, "SPKOUTR"),
1120 WM5100_MIXER_WIDGETS(SPKDAT1L, "SPKDAT1L"),
1121 WM5100_MIXER_WIDGETS(SPKDAT1R, "SPKDAT1R"),
1122 WM5100_MIXER_WIDGETS(SPKDAT2L, "SPKDAT2L"),
1123 WM5100_MIXER_WIDGETS(SPKDAT2R, "SPKDAT2R"),
1124
1125 WM5100_MIXER_WIDGETS(PWM1, "PWM1"),
1126 WM5100_MIXER_WIDGETS(PWM2, "PWM2"),
1127
1128 SND_SOC_DAPM_OUTPUT("HPOUT1L"),
1129 SND_SOC_DAPM_OUTPUT("HPOUT1R"),
1130 SND_SOC_DAPM_OUTPUT("HPOUT2L"),
1131 SND_SOC_DAPM_OUTPUT("HPOUT2R"),
1132 SND_SOC_DAPM_OUTPUT("HPOUT3L"),
1133 SND_SOC_DAPM_OUTPUT("HPOUT3R"),
1134 SND_SOC_DAPM_OUTPUT("SPKOUTL"),
1135 SND_SOC_DAPM_OUTPUT("SPKOUTR"),
1136 SND_SOC_DAPM_OUTPUT("SPKDAT1"),
1137 SND_SOC_DAPM_OUTPUT("SPKDAT2"),
1138 SND_SOC_DAPM_OUTPUT("PWM1"),
1139 SND_SOC_DAPM_OUTPUT("PWM2"),
1140 };
1141
1142 /* We register a _POST event if we don't have IRQ support so we can
1143 * look at the error status from the CODEC - if we've got the IRQ
1144 * hooked up then we will get prompted to look by an interrupt.
1145 */
1146 static const struct snd_soc_dapm_widget wm5100_dapm_widgets_noirq[] = {
1147 SND_SOC_DAPM_POST("Post", wm5100_post_ev),
1148 };
1149
1150 static const struct snd_soc_dapm_route wm5100_dapm_routes[] = {
1151 { "IN1L", NULL, "SYSCLK" },
1152 { "IN1R", NULL, "SYSCLK" },
1153 { "IN2L", NULL, "SYSCLK" },
1154 { "IN2R", NULL, "SYSCLK" },
1155 { "IN3L", NULL, "SYSCLK" },
1156 { "IN3R", NULL, "SYSCLK" },
1157 { "IN4L", NULL, "SYSCLK" },
1158 { "IN4R", NULL, "SYSCLK" },
1159
1160 { "OUT1L", NULL, "SYSCLK" },
1161 { "OUT1R", NULL, "SYSCLK" },
1162 { "OUT2L", NULL, "SYSCLK" },
1163 { "OUT2R", NULL, "SYSCLK" },
1164 { "OUT3L", NULL, "SYSCLK" },
1165 { "OUT3R", NULL, "SYSCLK" },
1166 { "OUT4L", NULL, "SYSCLK" },
1167 { "OUT4R", NULL, "SYSCLK" },
1168 { "OUT5L", NULL, "SYSCLK" },
1169 { "OUT5R", NULL, "SYSCLK" },
1170 { "OUT6L", NULL, "SYSCLK" },
1171 { "OUT6R", NULL, "SYSCLK" },
1172
1173 { "AIF1RX1", NULL, "SYSCLK" },
1174 { "AIF1RX2", NULL, "SYSCLK" },
1175 { "AIF1RX3", NULL, "SYSCLK" },
1176 { "AIF1RX4", NULL, "SYSCLK" },
1177 { "AIF1RX5", NULL, "SYSCLK" },
1178 { "AIF1RX6", NULL, "SYSCLK" },
1179 { "AIF1RX7", NULL, "SYSCLK" },
1180 { "AIF1RX8", NULL, "SYSCLK" },
1181
1182 { "AIF2RX1", NULL, "SYSCLK" },
1183 { "AIF2RX1", NULL, "DBVDD2" },
1184 { "AIF2RX2", NULL, "SYSCLK" },
1185 { "AIF2RX2", NULL, "DBVDD2" },
1186
1187 { "AIF3RX1", NULL, "SYSCLK" },
1188 { "AIF3RX1", NULL, "DBVDD3" },
1189 { "AIF3RX2", NULL, "SYSCLK" },
1190 { "AIF3RX2", NULL, "DBVDD3" },
1191
1192 { "AIF1TX1", NULL, "SYSCLK" },
1193 { "AIF1TX2", NULL, "SYSCLK" },
1194 { "AIF1TX3", NULL, "SYSCLK" },
1195 { "AIF1TX4", NULL, "SYSCLK" },
1196 { "AIF1TX5", NULL, "SYSCLK" },
1197 { "AIF1TX6", NULL, "SYSCLK" },
1198 { "AIF1TX7", NULL, "SYSCLK" },
1199 { "AIF1TX8", NULL, "SYSCLK" },
1200
1201 { "AIF2TX1", NULL, "SYSCLK" },
1202 { "AIF2TX1", NULL, "DBVDD2" },
1203 { "AIF2TX2", NULL, "SYSCLK" },
1204 { "AIF2TX2", NULL, "DBVDD2" },
1205
1206 { "AIF3TX1", NULL, "SYSCLK" },
1207 { "AIF3TX1", NULL, "DBVDD3" },
1208 { "AIF3TX2", NULL, "SYSCLK" },
1209 { "AIF3TX2", NULL, "DBVDD3" },
1210
1211 { "MICBIAS1", NULL, "CP2" },
1212 { "MICBIAS2", NULL, "CP2" },
1213 { "MICBIAS3", NULL, "CP2" },
1214
1215 { "IN1L PGA", NULL, "CP2" },
1216 { "IN1R PGA", NULL, "CP2" },
1217 { "IN2L PGA", NULL, "CP2" },
1218 { "IN2R PGA", NULL, "CP2" },
1219 { "IN3L PGA", NULL, "CP2" },
1220 { "IN3R PGA", NULL, "CP2" },
1221 { "IN4L PGA", NULL, "CP2" },
1222 { "IN4R PGA", NULL, "CP2" },
1223
1224 { "IN1L PGA", NULL, "CP2 Active" },
1225 { "IN1R PGA", NULL, "CP2 Active" },
1226 { "IN2L PGA", NULL, "CP2 Active" },
1227 { "IN2R PGA", NULL, "CP2 Active" },
1228 { "IN3L PGA", NULL, "CP2 Active" },
1229 { "IN3R PGA", NULL, "CP2 Active" },
1230 { "IN4L PGA", NULL, "CP2 Active" },
1231 { "IN4R PGA", NULL, "CP2 Active" },
1232
1233 { "OUT1L", NULL, "CP1" },
1234 { "OUT1R", NULL, "CP1" },
1235 { "OUT2L", NULL, "CP1" },
1236 { "OUT2R", NULL, "CP1" },
1237 { "OUT3L", NULL, "CP1" },
1238 { "OUT3R", NULL, "CP1" },
1239
1240 { "Tone Generator 1", NULL, "TONE" },
1241 { "Tone Generator 2", NULL, "TONE" },
1242
1243 { "IN1L PGA", NULL, "IN1L" },
1244 { "IN1R PGA", NULL, "IN1R" },
1245 { "IN2L PGA", NULL, "IN2L" },
1246 { "IN2R PGA", NULL, "IN2R" },
1247 { "IN3L PGA", NULL, "IN3L" },
1248 { "IN3R PGA", NULL, "IN3R" },
1249 { "IN4L PGA", NULL, "IN4L" },
1250 { "IN4R PGA", NULL, "IN4R" },
1251
1252 WM5100_MIXER_ROUTES("OUT1L", "HPOUT1L"),
1253 WM5100_MIXER_ROUTES("OUT1R", "HPOUT1R"),
1254 WM5100_MIXER_ROUTES("OUT2L", "HPOUT2L"),
1255 WM5100_MIXER_ROUTES("OUT2R", "HPOUT2R"),
1256 WM5100_MIXER_ROUTES("OUT3L", "HPOUT3L"),
1257 WM5100_MIXER_ROUTES("OUT3R", "HPOUT3R"),
1258
1259 WM5100_MIXER_ROUTES("OUT4L", "SPKOUTL"),
1260 WM5100_MIXER_ROUTES("OUT4R", "SPKOUTR"),
1261 WM5100_MIXER_ROUTES("OUT5L", "SPKDAT1L"),
1262 WM5100_MIXER_ROUTES("OUT5R", "SPKDAT1R"),
1263 WM5100_MIXER_ROUTES("OUT6L", "SPKDAT2L"),
1264 WM5100_MIXER_ROUTES("OUT6R", "SPKDAT2R"),
1265
1266 WM5100_MIXER_ROUTES("PWM1 Driver", "PWM1"),
1267 WM5100_MIXER_ROUTES("PWM2 Driver", "PWM2"),
1268
1269 WM5100_MIXER_ROUTES("AIF1TX1", "AIF1TX1"),
1270 WM5100_MIXER_ROUTES("AIF1TX2", "AIF1TX2"),
1271 WM5100_MIXER_ROUTES("AIF1TX3", "AIF1TX3"),
1272 WM5100_MIXER_ROUTES("AIF1TX4", "AIF1TX4"),
1273 WM5100_MIXER_ROUTES("AIF1TX5", "AIF1TX5"),
1274 WM5100_MIXER_ROUTES("AIF1TX6", "AIF1TX6"),
1275 WM5100_MIXER_ROUTES("AIF1TX7", "AIF1TX7"),
1276 WM5100_MIXER_ROUTES("AIF1TX8", "AIF1TX8"),
1277
1278 WM5100_MIXER_ROUTES("AIF2TX1", "AIF2TX1"),
1279 WM5100_MIXER_ROUTES("AIF2TX2", "AIF2TX2"),
1280
1281 WM5100_MIXER_ROUTES("AIF3TX1", "AIF3TX1"),
1282 WM5100_MIXER_ROUTES("AIF3TX2", "AIF3TX2"),
1283
1284 WM5100_MIXER_ROUTES("EQ1", "EQ1"),
1285 WM5100_MIXER_ROUTES("EQ2", "EQ2"),
1286 WM5100_MIXER_ROUTES("EQ3", "EQ3"),
1287 WM5100_MIXER_ROUTES("EQ4", "EQ4"),
1288
1289 WM5100_MIXER_ROUTES("DRC1L", "DRC1L"),
1290 WM5100_MIXER_ROUTES("DRC1R", "DRC1R"),
1291
1292 WM5100_MIXER_ROUTES("LHPF1", "LHPF1"),
1293 WM5100_MIXER_ROUTES("LHPF2", "LHPF2"),
1294 WM5100_MIXER_ROUTES("LHPF3", "LHPF3"),
1295 WM5100_MIXER_ROUTES("LHPF4", "LHPF4"),
1296
1297 { "HPOUT1L", NULL, "OUT1L" },
1298 { "HPOUT1R", NULL, "OUT1R" },
1299 { "HPOUT2L", NULL, "OUT2L" },
1300 { "HPOUT2R", NULL, "OUT2R" },
1301 { "HPOUT3L", NULL, "OUT3L" },
1302 { "HPOUT3R", NULL, "OUT3R" },
1303 { "SPKOUTL", NULL, "OUT4L" },
1304 { "SPKOUTR", NULL, "OUT4R" },
1305 { "SPKDAT1", NULL, "OUT5L" },
1306 { "SPKDAT1", NULL, "OUT5R" },
1307 { "SPKDAT2", NULL, "OUT6L" },
1308 { "SPKDAT2", NULL, "OUT6R" },
1309 { "PWM1", NULL, "PWM1 Driver" },
1310 { "PWM2", NULL, "PWM2 Driver" },
1311 };
1312
1313 static struct {
1314 int reg;
1315 int val;
1316 } wm5100_reva_patches[] = {
1317 { WM5100_AUDIO_IF_1_10, 0 },
1318 { WM5100_AUDIO_IF_1_11, 1 },
1319 { WM5100_AUDIO_IF_1_12, 2 },
1320 { WM5100_AUDIO_IF_1_13, 3 },
1321 { WM5100_AUDIO_IF_1_14, 4 },
1322 { WM5100_AUDIO_IF_1_15, 5 },
1323 { WM5100_AUDIO_IF_1_16, 6 },
1324 { WM5100_AUDIO_IF_1_17, 7 },
1325
1326 { WM5100_AUDIO_IF_1_18, 0 },
1327 { WM5100_AUDIO_IF_1_19, 1 },
1328 { WM5100_AUDIO_IF_1_20, 2 },
1329 { WM5100_AUDIO_IF_1_21, 3 },
1330 { WM5100_AUDIO_IF_1_22, 4 },
1331 { WM5100_AUDIO_IF_1_23, 5 },
1332 { WM5100_AUDIO_IF_1_24, 6 },
1333 { WM5100_AUDIO_IF_1_25, 7 },
1334
1335 { WM5100_AUDIO_IF_2_10, 0 },
1336 { WM5100_AUDIO_IF_2_11, 1 },
1337
1338 { WM5100_AUDIO_IF_2_18, 0 },
1339 { WM5100_AUDIO_IF_2_19, 1 },
1340
1341 { WM5100_AUDIO_IF_3_10, 0 },
1342 { WM5100_AUDIO_IF_3_11, 1 },
1343
1344 { WM5100_AUDIO_IF_3_18, 0 },
1345 { WM5100_AUDIO_IF_3_19, 1 },
1346 };
1347
1348 static int wm5100_set_bias_level(struct snd_soc_codec *codec,
1349 enum snd_soc_bias_level level)
1350 {
1351 struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
1352 int ret, i;
1353
1354 switch (level) {
1355 case SND_SOC_BIAS_ON:
1356 break;
1357
1358 case SND_SOC_BIAS_PREPARE:
1359 break;
1360
1361 case SND_SOC_BIAS_STANDBY:
1362 if (codec->dapm.bias_level == SND_SOC_BIAS_OFF) {
1363 ret = regulator_bulk_enable(ARRAY_SIZE(wm5100->core_supplies),
1364 wm5100->core_supplies);
1365 if (ret != 0) {
1366 dev_err(codec->dev,
1367 "Failed to enable supplies: %d\n",
1368 ret);
1369 return ret;
1370 }
1371
1372 if (wm5100->pdata.ldo_ena) {
1373 gpio_set_value_cansleep(wm5100->pdata.ldo_ena,
1374 1);
1375 msleep(2);
1376 }
1377
1378 codec->cache_only = false;
1379
1380 switch (wm5100->rev) {
1381 case 0:
1382 regcache_cache_bypass(wm5100->regmap, true);
1383 snd_soc_write(codec, 0x11, 0x3);
1384 snd_soc_write(codec, 0x203, 0xc);
1385 snd_soc_write(codec, 0x206, 0);
1386 snd_soc_write(codec, 0x207, 0xf0);
1387 snd_soc_write(codec, 0x208, 0x3c);
1388 snd_soc_write(codec, 0x209, 0);
1389 snd_soc_write(codec, 0x211, 0x20d8);
1390 snd_soc_write(codec, 0x11, 0);
1391
1392 for (i = 0;
1393 i < ARRAY_SIZE(wm5100_reva_patches);
1394 i++)
1395 snd_soc_write(codec,
1396 wm5100_reva_patches[i].reg,
1397 wm5100_reva_patches[i].val);
1398 regcache_cache_bypass(wm5100->regmap, false);
1399 break;
1400 default:
1401 break;
1402 }
1403
1404 snd_soc_cache_sync(codec);
1405 }
1406 break;
1407
1408 case SND_SOC_BIAS_OFF:
1409 regcache_cache_only(wm5100->regmap, true);
1410 if (wm5100->pdata.ldo_ena)
1411 gpio_set_value_cansleep(wm5100->pdata.ldo_ena, 0);
1412 regulator_bulk_disable(ARRAY_SIZE(wm5100->core_supplies),
1413 wm5100->core_supplies);
1414 break;
1415 }
1416 codec->dapm.bias_level = level;
1417
1418 return 0;
1419 }
1420
1421 static int wm5100_dai_to_base(struct snd_soc_dai *dai)
1422 {
1423 switch (dai->id) {
1424 case 0:
1425 return WM5100_AUDIO_IF_1_1 - 1;
1426 case 1:
1427 return WM5100_AUDIO_IF_2_1 - 1;
1428 case 2:
1429 return WM5100_AUDIO_IF_3_1 - 1;
1430 default:
1431 BUG();
1432 return -EINVAL;
1433 }
1434 }
1435
1436 static int wm5100_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1437 {
1438 struct snd_soc_codec *codec = dai->codec;
1439 int lrclk, bclk, mask, base;
1440
1441 base = wm5100_dai_to_base(dai);
1442 if (base < 0)
1443 return base;
1444
1445 lrclk = 0;
1446 bclk = 0;
1447
1448 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1449 case SND_SOC_DAIFMT_DSP_A:
1450 mask = 0;
1451 break;
1452 case SND_SOC_DAIFMT_DSP_B:
1453 mask = 1;
1454 break;
1455 case SND_SOC_DAIFMT_I2S:
1456 mask = 2;
1457 break;
1458 case SND_SOC_DAIFMT_LEFT_J:
1459 mask = 3;
1460 break;
1461 default:
1462 dev_err(codec->dev, "Unsupported DAI format %d\n",
1463 fmt & SND_SOC_DAIFMT_FORMAT_MASK);
1464 return -EINVAL;
1465 }
1466
1467 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1468 case SND_SOC_DAIFMT_CBS_CFS:
1469 break;
1470 case SND_SOC_DAIFMT_CBS_CFM:
1471 lrclk |= WM5100_AIF1TX_LRCLK_MSTR;
1472 break;
1473 case SND_SOC_DAIFMT_CBM_CFS:
1474 bclk |= WM5100_AIF1_BCLK_MSTR;
1475 break;
1476 case SND_SOC_DAIFMT_CBM_CFM:
1477 lrclk |= WM5100_AIF1TX_LRCLK_MSTR;
1478 bclk |= WM5100_AIF1_BCLK_MSTR;
1479 break;
1480 default:
1481 dev_err(codec->dev, "Unsupported master mode %d\n",
1482 fmt & SND_SOC_DAIFMT_MASTER_MASK);
1483 return -EINVAL;
1484 }
1485
1486 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1487 case SND_SOC_DAIFMT_NB_NF:
1488 break;
1489 case SND_SOC_DAIFMT_IB_IF:
1490 bclk |= WM5100_AIF1_BCLK_INV;
1491 lrclk |= WM5100_AIF1TX_LRCLK_INV;
1492 break;
1493 case SND_SOC_DAIFMT_IB_NF:
1494 bclk |= WM5100_AIF1_BCLK_INV;
1495 break;
1496 case SND_SOC_DAIFMT_NB_IF:
1497 lrclk |= WM5100_AIF1TX_LRCLK_INV;
1498 break;
1499 default:
1500 return -EINVAL;
1501 }
1502
1503 snd_soc_update_bits(codec, base + 1, WM5100_AIF1_BCLK_MSTR |
1504 WM5100_AIF1_BCLK_INV, bclk);
1505 snd_soc_update_bits(codec, base + 2, WM5100_AIF1TX_LRCLK_MSTR |
1506 WM5100_AIF1TX_LRCLK_INV, lrclk);
1507 snd_soc_update_bits(codec, base + 3, WM5100_AIF1TX_LRCLK_MSTR |
1508 WM5100_AIF1TX_LRCLK_INV, lrclk);
1509 snd_soc_update_bits(codec, base + 5, WM5100_AIF1_FMT_MASK, mask);
1510
1511 return 0;
1512 }
1513
1514 #define WM5100_NUM_BCLK_RATES 19
1515
1516 static int wm5100_bclk_rates_dat[WM5100_NUM_BCLK_RATES] = {
1517 32000,
1518 48000,
1519 64000,
1520 96000,
1521 128000,
1522 192000,
1523 256000,
1524 384000,
1525 512000,
1526 768000,
1527 1024000,
1528 1536000,
1529 2048000,
1530 3072000,
1531 4096000,
1532 6144000,
1533 8192000,
1534 12288000,
1535 24576000,
1536 };
1537
1538 static int wm5100_bclk_rates_cd[WM5100_NUM_BCLK_RATES] = {
1539 29400,
1540 44100,
1541 58800,
1542 88200,
1543 117600,
1544 176400,
1545 235200,
1546 352800,
1547 470400,
1548 705600,
1549 940800,
1550 1411200,
1551 1881600,
1552 2882400,
1553 3763200,
1554 5644800,
1555 7526400,
1556 11289600,
1557 22579600,
1558 };
1559
1560 static int wm5100_hw_params(struct snd_pcm_substream *substream,
1561 struct snd_pcm_hw_params *params,
1562 struct snd_soc_dai *dai)
1563 {
1564 struct snd_soc_codec *codec = dai->codec;
1565 struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
1566 bool async = wm5100->aif_async[dai->id];
1567 int i, base, bclk, aif_rate, lrclk, wl, fl, sr;
1568 int *bclk_rates;
1569
1570 base = wm5100_dai_to_base(dai);
1571 if (base < 0)
1572 return base;
1573
1574 /* Data sizes if not using TDM */
1575 wl = snd_pcm_format_width(params_format(params));
1576 if (wl < 0)
1577 return wl;
1578 fl = snd_soc_params_to_frame_size(params);
1579 if (fl < 0)
1580 return fl;
1581
1582 dev_dbg(codec->dev, "Word length %d bits, frame length %d bits\n",
1583 wl, fl);
1584
1585 /* Target BCLK rate */
1586 bclk = snd_soc_params_to_bclk(params);
1587 if (bclk < 0)
1588 return bclk;
1589
1590 /* Root for BCLK depends on SYS/ASYNCCLK */
1591 if (!async) {
1592 aif_rate = wm5100->sysclk;
1593 sr = wm5100_alloc_sr(codec, params_rate(params));
1594 if (sr < 0)
1595 return sr;
1596 } else {
1597 /* If we're in ASYNCCLK set the ASYNC sample rate */
1598 aif_rate = wm5100->asyncclk;
1599 sr = 3;
1600
1601 for (i = 0; i < ARRAY_SIZE(wm5100_sr_code); i++)
1602 if (params_rate(params) == wm5100_sr_code[i])
1603 break;
1604 if (i == ARRAY_SIZE(wm5100_sr_code)) {
1605 dev_err(codec->dev, "Invalid rate %dHzn",
1606 params_rate(params));
1607 return -EINVAL;
1608 }
1609
1610 /* TODO: We should really check for symmetry */
1611 snd_soc_update_bits(codec, WM5100_CLOCKING_8,
1612 WM5100_ASYNC_SAMPLE_RATE_MASK, i);
1613 }
1614
1615 if (!aif_rate) {
1616 dev_err(codec->dev, "%s has no rate set\n",
1617 async ? "ASYNCCLK" : "SYSCLK");
1618 return -EINVAL;
1619 }
1620
1621 dev_dbg(codec->dev, "Target BCLK is %dHz, using %dHz %s\n",
1622 bclk, aif_rate, async ? "ASYNCCLK" : "SYSCLK");
1623
1624 if (aif_rate % 4000)
1625 bclk_rates = wm5100_bclk_rates_cd;
1626 else
1627 bclk_rates = wm5100_bclk_rates_dat;
1628
1629 for (i = 0; i < WM5100_NUM_BCLK_RATES; i++)
1630 if (bclk_rates[i] >= bclk && (bclk_rates[i] % bclk == 0))
1631 break;
1632 if (i == WM5100_NUM_BCLK_RATES) {
1633 dev_err(codec->dev,
1634 "No valid BCLK for %dHz found from %dHz %s\n",
1635 bclk, aif_rate, async ? "ASYNCCLK" : "SYSCLK");
1636 return -EINVAL;
1637 }
1638
1639 bclk = i;
1640 dev_dbg(codec->dev, "Setting %dHz BCLK\n", bclk_rates[bclk]);
1641 snd_soc_update_bits(codec, base + 1, WM5100_AIF1_BCLK_FREQ_MASK, bclk);
1642
1643 lrclk = bclk_rates[bclk] / params_rate(params);
1644 dev_dbg(codec->dev, "Setting %dHz LRCLK\n", bclk_rates[bclk] / lrclk);
1645 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK ||
1646 wm5100->aif_symmetric[dai->id])
1647 snd_soc_update_bits(codec, base + 7,
1648 WM5100_AIF1RX_BCPF_MASK, lrclk);
1649 else
1650 snd_soc_update_bits(codec, base + 6,
1651 WM5100_AIF1TX_BCPF_MASK, lrclk);
1652
1653 i = (wl << WM5100_AIF1TX_WL_SHIFT) | fl;
1654 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1655 snd_soc_update_bits(codec, base + 9,
1656 WM5100_AIF1RX_WL_MASK |
1657 WM5100_AIF1RX_SLOT_LEN_MASK, i);
1658 else
1659 snd_soc_update_bits(codec, base + 8,
1660 WM5100_AIF1TX_WL_MASK |
1661 WM5100_AIF1TX_SLOT_LEN_MASK, i);
1662
1663 snd_soc_update_bits(codec, base + 4, WM5100_AIF1_RATE_MASK, sr);
1664
1665 return 0;
1666 }
1667
1668 static struct snd_soc_dai_ops wm5100_dai_ops = {
1669 .set_fmt = wm5100_set_fmt,
1670 .hw_params = wm5100_hw_params,
1671 };
1672
1673 static int wm5100_set_sysclk(struct snd_soc_codec *codec, int clk_id,
1674 int source, unsigned int freq, int dir)
1675 {
1676 struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
1677 int *rate_store;
1678 int fval, audio_rate, ret, reg;
1679
1680 switch (clk_id) {
1681 case WM5100_CLK_SYSCLK:
1682 reg = WM5100_CLOCKING_3;
1683 rate_store = &wm5100->sysclk;
1684 break;
1685 case WM5100_CLK_ASYNCCLK:
1686 reg = WM5100_CLOCKING_7;
1687 rate_store = &wm5100->asyncclk;
1688 break;
1689 case WM5100_CLK_32KHZ:
1690 /* The 32kHz clock is slightly different to the others */
1691 switch (source) {
1692 case WM5100_CLKSRC_MCLK1:
1693 case WM5100_CLKSRC_MCLK2:
1694 case WM5100_CLKSRC_SYSCLK:
1695 snd_soc_update_bits(codec, WM5100_CLOCKING_1,
1696 WM5100_CLK_32K_SRC_MASK,
1697 source);
1698 break;
1699 default:
1700 return -EINVAL;
1701 }
1702 return 0;
1703
1704 case WM5100_CLK_AIF1:
1705 case WM5100_CLK_AIF2:
1706 case WM5100_CLK_AIF3:
1707 /* Not real clocks, record which clock domain they're in */
1708 switch (source) {
1709 case WM5100_CLKSRC_SYSCLK:
1710 wm5100->aif_async[clk_id - 1] = false;
1711 break;
1712 case WM5100_CLKSRC_ASYNCCLK:
1713 wm5100->aif_async[clk_id - 1] = true;
1714 break;
1715 default:
1716 dev_err(codec->dev, "Invalid source %d\n", source);
1717 return -EINVAL;
1718 }
1719 return 0;
1720
1721 case WM5100_CLK_OPCLK:
1722 switch (freq) {
1723 case 5644800:
1724 case 6144000:
1725 snd_soc_update_bits(codec, WM5100_MISC_GPIO_1,
1726 WM5100_OPCLK_SEL_MASK, 0);
1727 break;
1728 case 11289600:
1729 case 12288000:
1730 snd_soc_update_bits(codec, WM5100_MISC_GPIO_1,
1731 WM5100_OPCLK_SEL_MASK, 0);
1732 break;
1733 case 22579200:
1734 case 24576000:
1735 snd_soc_update_bits(codec, WM5100_MISC_GPIO_1,
1736 WM5100_OPCLK_SEL_MASK, 0);
1737 break;
1738 default:
1739 dev_err(codec->dev, "Unsupported OPCLK %dHz\n",
1740 freq);
1741 return -EINVAL;
1742 }
1743 return 0;
1744
1745 default:
1746 dev_err(codec->dev, "Unknown clock %d\n", clk_id);
1747 return -EINVAL;
1748 }
1749
1750 switch (source) {
1751 case WM5100_CLKSRC_SYSCLK:
1752 case WM5100_CLKSRC_ASYNCCLK:
1753 dev_err(codec->dev, "Invalid source %d\n", source);
1754 return -EINVAL;
1755 }
1756
1757 switch (freq) {
1758 case 5644800:
1759 case 6144000:
1760 fval = 0;
1761 break;
1762 case 11289600:
1763 case 12288000:
1764 fval = 1;
1765 break;
1766 case 22579200:
1767 case 24576000:
1768 fval = 2;
1769 break;
1770 default:
1771 dev_err(codec->dev, "Invalid clock rate: %d\n", freq);
1772 return -EINVAL;
1773 }
1774
1775 switch (freq) {
1776 case 5644800:
1777 case 11289600:
1778 case 22579200:
1779 audio_rate = 44100;
1780 break;
1781
1782 case 6144000:
1783 case 12288000:
1784 case 24576000:
1785 audio_rate = 48000;
1786 break;
1787
1788 default:
1789 BUG();
1790 audio_rate = 0;
1791 break;
1792 }
1793
1794 /* TODO: Check if MCLKs are in use and enable/disable pulls to
1795 * match.
1796 */
1797
1798 snd_soc_update_bits(codec, reg, WM5100_SYSCLK_FREQ_MASK |
1799 WM5100_SYSCLK_SRC_MASK,
1800 fval << WM5100_SYSCLK_FREQ_SHIFT | source);
1801
1802 /* If this is SYSCLK then configure the clock rate for the
1803 * internal audio functions to the natural sample rate for
1804 * this clock rate.
1805 */
1806 if (clk_id == WM5100_CLK_SYSCLK) {
1807 dev_dbg(codec->dev, "Setting primary audio rate to %dHz",
1808 audio_rate);
1809 if (0 && *rate_store)
1810 wm5100_free_sr(codec, audio_rate);
1811 ret = wm5100_alloc_sr(codec, audio_rate);
1812 if (ret != 0)
1813 dev_warn(codec->dev, "Primary audio slot is %d\n",
1814 ret);
1815 }
1816
1817 *rate_store = freq;
1818
1819 return 0;
1820 }
1821
1822 struct _fll_div {
1823 u16 fll_fratio;
1824 u16 fll_outdiv;
1825 u16 fll_refclk_div;
1826 u16 n;
1827 u16 theta;
1828 u16 lambda;
1829 };
1830
1831 static struct {
1832 unsigned int min;
1833 unsigned int max;
1834 u16 fll_fratio;
1835 int ratio;
1836 } fll_fratios[] = {
1837 { 0, 64000, 4, 16 },
1838 { 64000, 128000, 3, 8 },
1839 { 128000, 256000, 2, 4 },
1840 { 256000, 1000000, 1, 2 },
1841 { 1000000, 13500000, 0, 1 },
1842 };
1843
1844 static int fll_factors(struct _fll_div *fll_div, unsigned int Fref,
1845 unsigned int Fout)
1846 {
1847 unsigned int target;
1848 unsigned int div;
1849 unsigned int fratio, gcd_fll;
1850 int i;
1851
1852 /* Fref must be <=13.5MHz */
1853 div = 1;
1854 fll_div->fll_refclk_div = 0;
1855 while ((Fref / div) > 13500000) {
1856 div *= 2;
1857 fll_div->fll_refclk_div++;
1858
1859 if (div > 8) {
1860 pr_err("Can't scale %dMHz input down to <=13.5MHz\n",
1861 Fref);
1862 return -EINVAL;
1863 }
1864 }
1865
1866 pr_debug("FLL Fref=%u Fout=%u\n", Fref, Fout);
1867
1868 /* Apply the division for our remaining calculations */
1869 Fref /= div;
1870
1871 /* Fvco should be 90-100MHz; don't check the upper bound */
1872 div = 2;
1873 while (Fout * div < 90000000) {
1874 div++;
1875 if (div > 64) {
1876 pr_err("Unable to find FLL_OUTDIV for Fout=%uHz\n",
1877 Fout);
1878 return -EINVAL;
1879 }
1880 }
1881 target = Fout * div;
1882 fll_div->fll_outdiv = div - 1;
1883
1884 pr_debug("FLL Fvco=%dHz\n", target);
1885
1886 /* Find an appropraite FLL_FRATIO and factor it out of the target */
1887 for (i = 0; i < ARRAY_SIZE(fll_fratios); i++) {
1888 if (fll_fratios[i].min <= Fref && Fref <= fll_fratios[i].max) {
1889 fll_div->fll_fratio = fll_fratios[i].fll_fratio;
1890 fratio = fll_fratios[i].ratio;
1891 break;
1892 }
1893 }
1894 if (i == ARRAY_SIZE(fll_fratios)) {
1895 pr_err("Unable to find FLL_FRATIO for Fref=%uHz\n", Fref);
1896 return -EINVAL;
1897 }
1898
1899 fll_div->n = target / (fratio * Fref);
1900
1901 if (target % Fref == 0) {
1902 fll_div->theta = 0;
1903 fll_div->lambda = 0;
1904 } else {
1905 gcd_fll = gcd(target, fratio * Fref);
1906
1907 fll_div->theta = (target - (fll_div->n * fratio * Fref))
1908 / gcd_fll;
1909 fll_div->lambda = (fratio * Fref) / gcd_fll;
1910 }
1911
1912 pr_debug("FLL N=%x THETA=%x LAMBDA=%x\n",
1913 fll_div->n, fll_div->theta, fll_div->lambda);
1914 pr_debug("FLL_FRATIO=%x(%d) FLL_OUTDIV=%x FLL_REFCLK_DIV=%x\n",
1915 fll_div->fll_fratio, fratio, fll_div->fll_outdiv,
1916 fll_div->fll_refclk_div);
1917
1918 return 0;
1919 }
1920
1921 static int wm5100_set_fll(struct snd_soc_codec *codec, int fll_id, int source,
1922 unsigned int Fref, unsigned int Fout)
1923 {
1924 struct i2c_client *i2c = to_i2c_client(codec->dev);
1925 struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
1926 struct _fll_div factors;
1927 struct wm5100_fll *fll;
1928 int ret, base, lock, i, timeout;
1929
1930 switch (fll_id) {
1931 case WM5100_FLL1:
1932 fll = &wm5100->fll[0];
1933 base = WM5100_FLL1_CONTROL_1 - 1;
1934 lock = WM5100_FLL1_LOCK_STS;
1935 break;
1936 case WM5100_FLL2:
1937 fll = &wm5100->fll[1];
1938 base = WM5100_FLL2_CONTROL_2 - 1;
1939 lock = WM5100_FLL2_LOCK_STS;
1940 break;
1941 default:
1942 dev_err(codec->dev, "Unknown FLL %d\n",fll_id);
1943 return -EINVAL;
1944 }
1945
1946 if (!Fout) {
1947 dev_dbg(codec->dev, "FLL%d disabled", fll_id);
1948 fll->fout = 0;
1949 snd_soc_update_bits(codec, base + 1, WM5100_FLL1_ENA, 0);
1950 return 0;
1951 }
1952
1953 switch (source) {
1954 case WM5100_FLL_SRC_MCLK1:
1955 case WM5100_FLL_SRC_MCLK2:
1956 case WM5100_FLL_SRC_FLL1:
1957 case WM5100_FLL_SRC_FLL2:
1958 case WM5100_FLL_SRC_AIF1BCLK:
1959 case WM5100_FLL_SRC_AIF2BCLK:
1960 case WM5100_FLL_SRC_AIF3BCLK:
1961 break;
1962 default:
1963 dev_err(codec->dev, "Invalid FLL source %d\n", source);
1964 return -EINVAL;
1965 }
1966
1967 ret = fll_factors(&factors, Fref, Fout);
1968 if (ret < 0)
1969 return ret;
1970
1971 /* Disable the FLL while we reconfigure */
1972 snd_soc_update_bits(codec, base + 1, WM5100_FLL1_ENA, 0);
1973
1974 snd_soc_update_bits(codec, base + 2,
1975 WM5100_FLL1_OUTDIV_MASK | WM5100_FLL1_FRATIO_MASK,
1976 (factors.fll_outdiv << WM5100_FLL1_OUTDIV_SHIFT) |
1977 factors.fll_fratio);
1978 snd_soc_update_bits(codec, base + 3, WM5100_FLL1_THETA_MASK,
1979 factors.theta);
1980 snd_soc_update_bits(codec, base + 5, WM5100_FLL1_N_MASK, factors.n);
1981 snd_soc_update_bits(codec, base + 6,
1982 WM5100_FLL1_REFCLK_DIV_MASK |
1983 WM5100_FLL1_REFCLK_SRC_MASK,
1984 (factors.fll_refclk_div
1985 << WM5100_FLL1_REFCLK_DIV_SHIFT) | source);
1986 snd_soc_update_bits(codec, base + 7, WM5100_FLL1_LAMBDA_MASK,
1987 factors.lambda);
1988
1989 /* Clear any pending completions */
1990 try_wait_for_completion(&fll->lock);
1991
1992 snd_soc_update_bits(codec, base + 1, WM5100_FLL1_ENA, WM5100_FLL1_ENA);
1993
1994 if (i2c->irq)
1995 timeout = 2;
1996 else
1997 timeout = 50;
1998
1999 /* Poll for the lock; will use interrupt when we can test */
2000 for (i = 0; i < timeout; i++) {
2001 if (i2c->irq) {
2002 ret = wait_for_completion_timeout(&fll->lock,
2003 msecs_to_jiffies(25));
2004 if (ret > 0)
2005 break;
2006 } else {
2007 msleep(1);
2008 }
2009
2010 ret = snd_soc_read(codec,
2011 WM5100_INTERRUPT_RAW_STATUS_3);
2012 if (ret < 0) {
2013 dev_err(codec->dev,
2014 "Failed to read FLL status: %d\n",
2015 ret);
2016 continue;
2017 }
2018 if (ret & lock)
2019 break;
2020 }
2021 if (i == timeout) {
2022 dev_err(codec->dev, "FLL%d lock timed out\n", fll_id);
2023 return -ETIMEDOUT;
2024 }
2025
2026 fll->src = source;
2027 fll->fref = Fref;
2028 fll->fout = Fout;
2029
2030 dev_dbg(codec->dev, "FLL%d running %dHz->%dHz\n", fll_id,
2031 Fref, Fout);
2032
2033 return 0;
2034 }
2035
2036 /* Actually go much higher */
2037 #define WM5100_RATES SNDRV_PCM_RATE_8000_192000
2038
2039 #define WM5100_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
2040 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
2041
2042 static struct snd_soc_dai_driver wm5100_dai[] = {
2043 {
2044 .name = "wm5100-aif1",
2045 .playback = {
2046 .stream_name = "AIF1 Playback",
2047 .channels_min = 2,
2048 .channels_max = 2,
2049 .rates = WM5100_RATES,
2050 .formats = WM5100_FORMATS,
2051 },
2052 .capture = {
2053 .stream_name = "AIF1 Capture",
2054 .channels_min = 2,
2055 .channels_max = 2,
2056 .rates = WM5100_RATES,
2057 .formats = WM5100_FORMATS,
2058 },
2059 .ops = &wm5100_dai_ops,
2060 },
2061 {
2062 .name = "wm5100-aif2",
2063 .id = 1,
2064 .playback = {
2065 .stream_name = "AIF2 Playback",
2066 .channels_min = 2,
2067 .channels_max = 2,
2068 .rates = WM5100_RATES,
2069 .formats = WM5100_FORMATS,
2070 },
2071 .capture = {
2072 .stream_name = "AIF2 Capture",
2073 .channels_min = 2,
2074 .channels_max = 2,
2075 .rates = WM5100_RATES,
2076 .formats = WM5100_FORMATS,
2077 },
2078 .ops = &wm5100_dai_ops,
2079 },
2080 {
2081 .name = "wm5100-aif3",
2082 .id = 2,
2083 .playback = {
2084 .stream_name = "AIF3 Playback",
2085 .channels_min = 2,
2086 .channels_max = 2,
2087 .rates = WM5100_RATES,
2088 .formats = WM5100_FORMATS,
2089 },
2090 .capture = {
2091 .stream_name = "AIF3 Capture",
2092 .channels_min = 2,
2093 .channels_max = 2,
2094 .rates = WM5100_RATES,
2095 .formats = WM5100_FORMATS,
2096 },
2097 .ops = &wm5100_dai_ops,
2098 },
2099 };
2100
2101 static int wm5100_dig_vu[] = {
2102 WM5100_ADC_DIGITAL_VOLUME_1L,
2103 WM5100_ADC_DIGITAL_VOLUME_1R,
2104 WM5100_ADC_DIGITAL_VOLUME_2L,
2105 WM5100_ADC_DIGITAL_VOLUME_2R,
2106 WM5100_ADC_DIGITAL_VOLUME_3L,
2107 WM5100_ADC_DIGITAL_VOLUME_3R,
2108 WM5100_ADC_DIGITAL_VOLUME_4L,
2109 WM5100_ADC_DIGITAL_VOLUME_4R,
2110
2111 WM5100_DAC_DIGITAL_VOLUME_1L,
2112 WM5100_DAC_DIGITAL_VOLUME_1R,
2113 WM5100_DAC_DIGITAL_VOLUME_2L,
2114 WM5100_DAC_DIGITAL_VOLUME_2R,
2115 WM5100_DAC_DIGITAL_VOLUME_3L,
2116 WM5100_DAC_DIGITAL_VOLUME_3R,
2117 WM5100_DAC_DIGITAL_VOLUME_4L,
2118 WM5100_DAC_DIGITAL_VOLUME_4R,
2119 WM5100_DAC_DIGITAL_VOLUME_5L,
2120 WM5100_DAC_DIGITAL_VOLUME_5R,
2121 WM5100_DAC_DIGITAL_VOLUME_6L,
2122 WM5100_DAC_DIGITAL_VOLUME_6R,
2123 };
2124
2125 static void wm5100_set_detect_mode(struct snd_soc_codec *codec, int the_mode)
2126 {
2127 struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
2128 struct wm5100_jack_mode *mode = &wm5100->pdata.jack_modes[the_mode];
2129
2130 BUG_ON(the_mode >= ARRAY_SIZE(wm5100->pdata.jack_modes));
2131
2132 gpio_set_value_cansleep(wm5100->pdata.hp_pol, mode->hp_pol);
2133 snd_soc_update_bits(codec, WM5100_ACCESSORY_DETECT_MODE_1,
2134 WM5100_ACCDET_BIAS_SRC_MASK |
2135 WM5100_ACCDET_SRC,
2136 (mode->bias << WM5100_ACCDET_BIAS_SRC_SHIFT) |
2137 mode->micd_src << WM5100_ACCDET_SRC_SHIFT);
2138 snd_soc_update_bits(codec, WM5100_MISC_CONTROL,
2139 WM5100_HPCOM_SRC,
2140 mode->micd_src << WM5100_HPCOM_SRC_SHIFT);
2141
2142 wm5100->jack_mode = the_mode;
2143
2144 dev_dbg(codec->dev, "Set microphone polarity to %d\n",
2145 wm5100->jack_mode);
2146 }
2147
2148 static void wm5100_micd_irq(struct snd_soc_codec *codec)
2149 {
2150 struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
2151 int val;
2152
2153 val = snd_soc_read(codec, WM5100_MIC_DETECT_3);
2154
2155 dev_dbg(codec->dev, "Microphone event: %x\n", val);
2156
2157 if (!(val & WM5100_ACCDET_VALID)) {
2158 dev_warn(codec->dev, "Microphone detection state invalid\n");
2159 return;
2160 }
2161
2162 /* No accessory, reset everything and report removal */
2163 if (!(val & WM5100_ACCDET_STS)) {
2164 dev_dbg(codec->dev, "Jack removal detected\n");
2165 wm5100->jack_mic = false;
2166 wm5100->jack_detecting = true;
2167 snd_soc_jack_report(wm5100->jack, 0,
2168 SND_JACK_LINEOUT | SND_JACK_HEADSET |
2169 SND_JACK_BTN_0);
2170
2171 snd_soc_update_bits(codec, WM5100_MIC_DETECT_1,
2172 WM5100_ACCDET_RATE_MASK,
2173 WM5100_ACCDET_RATE_MASK);
2174 return;
2175 }
2176
2177 /* If the measurement is very high we've got a microphone,
2178 * either we just detected one or if we already reported then
2179 * we've got a button release event.
2180 */
2181 if (val & 0x400) {
2182 if (wm5100->jack_detecting) {
2183 dev_dbg(codec->dev, "Microphone detected\n");
2184 wm5100->jack_mic = true;
2185 snd_soc_jack_report(wm5100->jack,
2186 SND_JACK_HEADSET,
2187 SND_JACK_HEADSET | SND_JACK_BTN_0);
2188
2189 /* Increase poll rate to give better responsiveness
2190 * for buttons */
2191 snd_soc_update_bits(codec, WM5100_MIC_DETECT_1,
2192 WM5100_ACCDET_RATE_MASK,
2193 5 << WM5100_ACCDET_RATE_SHIFT);
2194 } else {
2195 dev_dbg(codec->dev, "Mic button up\n");
2196 snd_soc_jack_report(wm5100->jack, 0, SND_JACK_BTN_0);
2197 }
2198
2199 return;
2200 }
2201
2202 /* If we detected a lower impedence during initial startup
2203 * then we probably have the wrong polarity, flip it. Don't
2204 * do this for the lowest impedences to speed up detection of
2205 * plain headphones.
2206 */
2207 if (wm5100->jack_detecting && (val & 0x3f8)) {
2208 wm5100_set_detect_mode(codec, !wm5100->jack_mode);
2209
2210 return;
2211 }
2212
2213 /* Don't distinguish between buttons, just report any low
2214 * impedence as BTN_0.
2215 */
2216 if (val & 0x3fc) {
2217 if (wm5100->jack_mic) {
2218 dev_dbg(codec->dev, "Mic button detected\n");
2219 snd_soc_jack_report(wm5100->jack, SND_JACK_BTN_0,
2220 SND_JACK_BTN_0);
2221 } else if (wm5100->jack_detecting) {
2222 dev_dbg(codec->dev, "Headphone detected\n");
2223 snd_soc_jack_report(wm5100->jack, SND_JACK_HEADPHONE,
2224 SND_JACK_HEADPHONE);
2225
2226 /* Increase the detection rate a bit for
2227 * responsiveness.
2228 */
2229 snd_soc_update_bits(codec, WM5100_MIC_DETECT_1,
2230 WM5100_ACCDET_RATE_MASK,
2231 7 << WM5100_ACCDET_RATE_SHIFT);
2232 }
2233 }
2234 }
2235
2236 int wm5100_detect(struct snd_soc_codec *codec, struct snd_soc_jack *jack)
2237 {
2238 struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
2239
2240 if (jack) {
2241 wm5100->jack = jack;
2242 wm5100->jack_detecting = true;
2243
2244 wm5100_set_detect_mode(codec, 0);
2245
2246 /* Slowest detection rate, gives debounce for initial
2247 * detection */
2248 snd_soc_update_bits(codec, WM5100_MIC_DETECT_1,
2249 WM5100_ACCDET_BIAS_STARTTIME_MASK |
2250 WM5100_ACCDET_RATE_MASK,
2251 (7 << WM5100_ACCDET_BIAS_STARTTIME_SHIFT) |
2252 WM5100_ACCDET_RATE_MASK);
2253
2254 /* We need the charge pump to power MICBIAS */
2255 snd_soc_dapm_force_enable_pin(&codec->dapm, "CP2");
2256 snd_soc_dapm_force_enable_pin(&codec->dapm, "SYSCLK");
2257 snd_soc_dapm_sync(&codec->dapm);
2258
2259 /* We start off just enabling microphone detection - even a
2260 * plain headphone will trigger detection.
2261 */
2262 snd_soc_update_bits(codec, WM5100_MIC_DETECT_1,
2263 WM5100_ACCDET_ENA, WM5100_ACCDET_ENA);
2264
2265 snd_soc_update_bits(codec, WM5100_INTERRUPT_STATUS_3_MASK,
2266 WM5100_IM_ACCDET_EINT, 0);
2267 } else {
2268 snd_soc_update_bits(codec, WM5100_INTERRUPT_STATUS_3_MASK,
2269 WM5100_IM_HPDET_EINT |
2270 WM5100_IM_ACCDET_EINT,
2271 WM5100_IM_HPDET_EINT |
2272 WM5100_IM_ACCDET_EINT);
2273 snd_soc_update_bits(codec, WM5100_MIC_DETECT_1,
2274 WM5100_ACCDET_ENA, 0);
2275 wm5100->jack = NULL;
2276 }
2277
2278 return 0;
2279 }
2280
2281 static irqreturn_t wm5100_irq(int irq, void *data)
2282 {
2283 struct snd_soc_codec *codec = data;
2284 struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
2285 irqreturn_t status = IRQ_NONE;
2286 int irq_val;
2287
2288 irq_val = snd_soc_read(codec, WM5100_INTERRUPT_STATUS_3);
2289 if (irq_val < 0) {
2290 dev_err(codec->dev, "Failed to read IRQ status 3: %d\n",
2291 irq_val);
2292 irq_val = 0;
2293 }
2294 irq_val &= ~snd_soc_read(codec, WM5100_INTERRUPT_STATUS_3_MASK);
2295
2296 snd_soc_write(codec, WM5100_INTERRUPT_STATUS_3, irq_val);
2297
2298 if (irq_val)
2299 status = IRQ_HANDLED;
2300
2301 wm5100_log_status3(codec, irq_val);
2302
2303 if (irq_val & WM5100_FLL1_LOCK_EINT) {
2304 dev_dbg(codec->dev, "FLL1 locked\n");
2305 complete(&wm5100->fll[0].lock);
2306 }
2307 if (irq_val & WM5100_FLL2_LOCK_EINT) {
2308 dev_dbg(codec->dev, "FLL2 locked\n");
2309 complete(&wm5100->fll[1].lock);
2310 }
2311
2312 if (irq_val & WM5100_ACCDET_EINT)
2313 wm5100_micd_irq(codec);
2314
2315 irq_val = snd_soc_read(codec, WM5100_INTERRUPT_STATUS_4);
2316 if (irq_val < 0) {
2317 dev_err(codec->dev, "Failed to read IRQ status 4: %d\n",
2318 irq_val);
2319 irq_val = 0;
2320 }
2321 irq_val &= ~snd_soc_read(codec, WM5100_INTERRUPT_STATUS_4_MASK);
2322
2323 if (irq_val)
2324 status = IRQ_HANDLED;
2325
2326 snd_soc_write(codec, WM5100_INTERRUPT_STATUS_4, irq_val);
2327
2328 wm5100_log_status4(codec, irq_val);
2329
2330 return status;
2331 }
2332
2333 static irqreturn_t wm5100_edge_irq(int irq, void *data)
2334 {
2335 irqreturn_t ret = IRQ_NONE;
2336 irqreturn_t val;
2337
2338 do {
2339 val = wm5100_irq(irq, data);
2340 if (val != IRQ_NONE)
2341 ret = val;
2342 } while (val != IRQ_NONE);
2343
2344 return ret;
2345 }
2346
2347 #ifdef CONFIG_GPIOLIB
2348 static inline struct wm5100_priv *gpio_to_wm5100(struct gpio_chip *chip)
2349 {
2350 return container_of(chip, struct wm5100_priv, gpio_chip);
2351 }
2352
2353 static void wm5100_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
2354 {
2355 struct wm5100_priv *wm5100 = gpio_to_wm5100(chip);
2356 struct snd_soc_codec *codec = wm5100->codec;
2357
2358 snd_soc_update_bits(codec, WM5100_GPIO_CTRL_1 + offset,
2359 WM5100_GP1_LVL, !!value << WM5100_GP1_LVL_SHIFT);
2360 }
2361
2362 static int wm5100_gpio_direction_out(struct gpio_chip *chip,
2363 unsigned offset, int value)
2364 {
2365 struct wm5100_priv *wm5100 = gpio_to_wm5100(chip);
2366 struct snd_soc_codec *codec = wm5100->codec;
2367 int val, ret;
2368
2369 val = (1 << WM5100_GP1_FN_SHIFT) | (!!value << WM5100_GP1_LVL_SHIFT);
2370
2371 ret = snd_soc_update_bits(codec, WM5100_GPIO_CTRL_1 + offset,
2372 WM5100_GP1_FN_MASK | WM5100_GP1_DIR |
2373 WM5100_GP1_LVL, val);
2374 if (ret < 0)
2375 return ret;
2376 else
2377 return 0;
2378 }
2379
2380 static int wm5100_gpio_get(struct gpio_chip *chip, unsigned offset)
2381 {
2382 struct wm5100_priv *wm5100 = gpio_to_wm5100(chip);
2383 struct snd_soc_codec *codec = wm5100->codec;
2384 int ret;
2385
2386 ret = snd_soc_read(codec, WM5100_GPIO_CTRL_1 + offset);
2387 if (ret < 0)
2388 return ret;
2389
2390 return (ret & WM5100_GP1_LVL) != 0;
2391 }
2392
2393 static int wm5100_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
2394 {
2395 struct wm5100_priv *wm5100 = gpio_to_wm5100(chip);
2396 struct snd_soc_codec *codec = wm5100->codec;
2397
2398 return snd_soc_update_bits(codec, WM5100_GPIO_CTRL_1 + offset,
2399 WM5100_GP1_FN_MASK | WM5100_GP1_DIR,
2400 (1 << WM5100_GP1_FN_SHIFT) |
2401 (1 << WM5100_GP1_DIR_SHIFT));
2402 }
2403
2404 static struct gpio_chip wm5100_template_chip = {
2405 .label = "wm5100",
2406 .owner = THIS_MODULE,
2407 .direction_output = wm5100_gpio_direction_out,
2408 .set = wm5100_gpio_set,
2409 .direction_input = wm5100_gpio_direction_in,
2410 .get = wm5100_gpio_get,
2411 .can_sleep = 1,
2412 };
2413
2414 static void wm5100_init_gpio(struct snd_soc_codec *codec)
2415 {
2416 struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
2417 int ret;
2418
2419 wm5100->gpio_chip = wm5100_template_chip;
2420 wm5100->gpio_chip.ngpio = 6;
2421 wm5100->gpio_chip.dev = codec->dev;
2422
2423 if (wm5100->pdata.gpio_base)
2424 wm5100->gpio_chip.base = wm5100->pdata.gpio_base;
2425 else
2426 wm5100->gpio_chip.base = -1;
2427
2428 ret = gpiochip_add(&wm5100->gpio_chip);
2429 if (ret != 0)
2430 dev_err(codec->dev, "Failed to add GPIOs: %d\n", ret);
2431 }
2432
2433 static void wm5100_free_gpio(struct snd_soc_codec *codec)
2434 {
2435 struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
2436 int ret;
2437
2438 ret = gpiochip_remove(&wm5100->gpio_chip);
2439 if (ret != 0)
2440 dev_err(codec->dev, "Failed to remove GPIOs: %d\n", ret);
2441 }
2442 #else
2443 static void wm5100_init_gpio(struct snd_soc_codec *codec)
2444 {
2445 }
2446
2447 static void wm5100_free_gpio(struct snd_soc_codec *codec)
2448 {
2449 }
2450 #endif
2451
2452 static int wm5100_probe(struct snd_soc_codec *codec)
2453 {
2454 struct i2c_client *i2c = to_i2c_client(codec->dev);
2455 struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
2456 int ret, i, irq_flags;
2457
2458 wm5100->codec = codec;
2459
2460 ret = snd_soc_codec_set_cache_io(codec, 16, 16, SND_SOC_I2C);
2461 if (ret != 0) {
2462 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
2463 return ret;
2464 }
2465
2466 for (i = 0; i < ARRAY_SIZE(wm5100->core_supplies); i++)
2467 wm5100->core_supplies[i].supply = wm5100_core_supply_names[i];
2468
2469 ret = regulator_bulk_get(&i2c->dev, ARRAY_SIZE(wm5100->core_supplies),
2470 wm5100->core_supplies);
2471 if (ret != 0) {
2472 dev_err(codec->dev, "Failed to request core supplies: %d\n",
2473 ret);
2474 return ret;
2475 }
2476
2477 wm5100->cpvdd = regulator_get(&i2c->dev, "CPVDD");
2478 if (IS_ERR(wm5100->cpvdd)) {
2479 ret = PTR_ERR(wm5100->cpvdd);
2480 dev_err(&i2c->dev, "Failed to get CPVDD: %d\n", ret);
2481 goto err_core;
2482 }
2483
2484 wm5100->dbvdd2 = regulator_get(&i2c->dev, "DBVDD2");
2485 if (IS_ERR(wm5100->dbvdd2)) {
2486 ret = PTR_ERR(wm5100->dbvdd2);
2487 dev_err(&i2c->dev, "Failed to get DBVDD2: %d\n", ret);
2488 goto err_cpvdd;
2489 }
2490
2491 wm5100->dbvdd3 = regulator_get(&i2c->dev, "DBVDD3");
2492 if (IS_ERR(wm5100->dbvdd3)) {
2493 ret = PTR_ERR(wm5100->dbvdd3);
2494 dev_err(&i2c->dev, "Failed to get DBVDD2: %d\n", ret);
2495 goto err_dbvdd2;
2496 }
2497
2498 ret = regulator_bulk_enable(ARRAY_SIZE(wm5100->core_supplies),
2499 wm5100->core_supplies);
2500 if (ret != 0) {
2501 dev_err(codec->dev, "Failed to enable core supplies: %d\n",
2502 ret);
2503 goto err_dbvdd3;
2504 }
2505
2506 if (wm5100->pdata.ldo_ena) {
2507 ret = gpio_request_one(wm5100->pdata.ldo_ena,
2508 GPIOF_OUT_INIT_HIGH, "WM5100 LDOENA");
2509 if (ret < 0) {
2510 dev_err(&i2c->dev, "Failed to request LDOENA %d: %d\n",
2511 wm5100->pdata.ldo_ena, ret);
2512 goto err_enable;
2513 }
2514 msleep(2);
2515 }
2516
2517 if (wm5100->pdata.reset) {
2518 ret = gpio_request_one(wm5100->pdata.reset,
2519 GPIOF_OUT_INIT_HIGH, "WM5100 /RESET");
2520 if (ret < 0) {
2521 dev_err(&i2c->dev, "Failed to request /RESET %d: %d\n",
2522 wm5100->pdata.reset, ret);
2523 goto err_ldo;
2524 }
2525 }
2526
2527 ret = snd_soc_read(codec, WM5100_SOFTWARE_RESET);
2528 if (ret < 0) {
2529 dev_err(codec->dev, "Failed to read ID register\n");
2530 goto err_reset;
2531 }
2532 switch (ret) {
2533 case 0x8997:
2534 case 0x5100:
2535 break;
2536
2537 default:
2538 dev_err(codec->dev, "Device is not a WM5100, ID is %x\n", ret);
2539 ret = -EINVAL;
2540 goto err_reset;
2541 }
2542
2543 ret = snd_soc_read(codec, WM5100_DEVICE_REVISION);
2544 if (ret < 0) {
2545 dev_err(codec->dev, "Failed to read revision register\n");
2546 goto err_reset;
2547 }
2548 wm5100->rev = ret & WM5100_DEVICE_REVISION_MASK;
2549
2550 dev_info(codec->dev, "revision %c\n", wm5100->rev + 'A');
2551
2552 ret = wm5100_reset(codec);
2553 if (ret < 0) {
2554 dev_err(codec->dev, "Failed to issue reset\n");
2555 goto err_reset;
2556 }
2557
2558 codec->cache_only = true;
2559
2560 wm5100_init_gpio(codec);
2561
2562 for (i = 0; i < ARRAY_SIZE(wm5100_dig_vu); i++)
2563 snd_soc_update_bits(codec, wm5100_dig_vu[i], WM5100_OUT_VU,
2564 WM5100_OUT_VU);
2565
2566 for (i = 0; i < ARRAY_SIZE(wm5100->pdata.in_mode); i++) {
2567 snd_soc_update_bits(codec, WM5100_IN1L_CONTROL,
2568 WM5100_IN1_MODE_MASK |
2569 WM5100_IN1_DMIC_SUP_MASK,
2570 (wm5100->pdata.in_mode[i] <<
2571 WM5100_IN1_MODE_SHIFT) |
2572 (wm5100->pdata.dmic_sup[i] <<
2573 WM5100_IN1_DMIC_SUP_SHIFT));
2574 }
2575
2576 for (i = 0; i < ARRAY_SIZE(wm5100->pdata.gpio_defaults); i++) {
2577 if (!wm5100->pdata.gpio_defaults[i])
2578 continue;
2579
2580 snd_soc_write(codec, WM5100_GPIO_CTRL_1 + i,
2581 wm5100->pdata.gpio_defaults[i]);
2582 }
2583
2584 /* Don't debounce interrupts to support use of SYSCLK only */
2585 snd_soc_write(codec, WM5100_IRQ_DEBOUNCE_1, 0);
2586 snd_soc_write(codec, WM5100_IRQ_DEBOUNCE_2, 0);
2587
2588 /* TODO: check if we're symmetric */
2589
2590 if (i2c->irq) {
2591 if (wm5100->pdata.irq_flags)
2592 irq_flags = wm5100->pdata.irq_flags;
2593 else
2594 irq_flags = IRQF_TRIGGER_LOW;
2595
2596 irq_flags |= IRQF_ONESHOT;
2597
2598 if (irq_flags & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING))
2599 ret = request_threaded_irq(i2c->irq, NULL,
2600 wm5100_edge_irq,
2601 irq_flags, "wm5100", codec);
2602 else
2603 ret = request_threaded_irq(i2c->irq, NULL, wm5100_irq,
2604 irq_flags, "wm5100", codec);
2605
2606 if (ret != 0) {
2607 dev_err(codec->dev, "Failed to request IRQ %d: %d\n",
2608 i2c->irq, ret);
2609 } else {
2610 /* Enable default interrupts */
2611 snd_soc_update_bits(codec,
2612 WM5100_INTERRUPT_STATUS_3_MASK,
2613 WM5100_IM_SPK_SHUTDOWN_WARN_EINT |
2614 WM5100_IM_SPK_SHUTDOWN_EINT |
2615 WM5100_IM_ASRC2_LOCK_EINT |
2616 WM5100_IM_ASRC1_LOCK_EINT |
2617 WM5100_IM_FLL2_LOCK_EINT |
2618 WM5100_IM_FLL1_LOCK_EINT |
2619 WM5100_CLKGEN_ERR_EINT |
2620 WM5100_CLKGEN_ERR_ASYNC_EINT, 0);
2621
2622 snd_soc_update_bits(codec,
2623 WM5100_INTERRUPT_STATUS_4_MASK,
2624 WM5100_AIF3_ERR_EINT |
2625 WM5100_AIF2_ERR_EINT |
2626 WM5100_AIF1_ERR_EINT |
2627 WM5100_CTRLIF_ERR_EINT |
2628 WM5100_ISRC2_UNDERCLOCKED_EINT |
2629 WM5100_ISRC1_UNDERCLOCKED_EINT |
2630 WM5100_FX_UNDERCLOCKED_EINT |
2631 WM5100_AIF3_UNDERCLOCKED_EINT |
2632 WM5100_AIF2_UNDERCLOCKED_EINT |
2633 WM5100_AIF1_UNDERCLOCKED_EINT |
2634 WM5100_ASRC_UNDERCLOCKED_EINT |
2635 WM5100_DAC_UNDERCLOCKED_EINT |
2636 WM5100_ADC_UNDERCLOCKED_EINT |
2637 WM5100_MIXER_UNDERCLOCKED_EINT, 0);
2638 }
2639 } else {
2640 snd_soc_dapm_new_controls(&codec->dapm,
2641 wm5100_dapm_widgets_noirq,
2642 ARRAY_SIZE(wm5100_dapm_widgets_noirq));
2643 }
2644
2645 if (wm5100->pdata.hp_pol) {
2646 ret = gpio_request_one(wm5100->pdata.hp_pol,
2647 GPIOF_OUT_INIT_HIGH, "WM5100 HP_POL");
2648 if (ret < 0) {
2649 dev_err(&i2c->dev, "Failed to request HP_POL %d: %d\n",
2650 wm5100->pdata.hp_pol, ret);
2651 goto err_gpio;
2652 }
2653 }
2654
2655 /* We'll get woken up again when the system has something useful
2656 * for us to do.
2657 */
2658 if (wm5100->pdata.ldo_ena)
2659 gpio_set_value_cansleep(wm5100->pdata.ldo_ena, 0);
2660 regulator_bulk_disable(ARRAY_SIZE(wm5100->core_supplies),
2661 wm5100->core_supplies);
2662
2663 return 0;
2664
2665 err_gpio:
2666 if (i2c->irq)
2667 free_irq(i2c->irq, codec);
2668 wm5100_free_gpio(codec);
2669 err_reset:
2670 if (wm5100->pdata.reset) {
2671 gpio_set_value_cansleep(wm5100->pdata.reset, 1);
2672 gpio_free(wm5100->pdata.reset);
2673 }
2674 err_ldo:
2675 if (wm5100->pdata.ldo_ena) {
2676 gpio_set_value_cansleep(wm5100->pdata.ldo_ena, 0);
2677 gpio_free(wm5100->pdata.ldo_ena);
2678 }
2679 err_enable:
2680 regulator_bulk_disable(ARRAY_SIZE(wm5100->core_supplies),
2681 wm5100->core_supplies);
2682 err_dbvdd3:
2683 regulator_put(wm5100->dbvdd3);
2684 err_dbvdd2:
2685 regulator_put(wm5100->dbvdd2);
2686 err_cpvdd:
2687 regulator_put(wm5100->cpvdd);
2688 err_core:
2689 regulator_bulk_free(ARRAY_SIZE(wm5100->core_supplies),
2690 wm5100->core_supplies);
2691
2692 return ret;
2693 }
2694
2695 static int wm5100_remove(struct snd_soc_codec *codec)
2696 {
2697 struct wm5100_priv *wm5100 = snd_soc_codec_get_drvdata(codec);
2698 struct i2c_client *i2c = to_i2c_client(codec->dev);
2699
2700 wm5100_set_bias_level(codec, SND_SOC_BIAS_OFF);
2701 if (wm5100->pdata.hp_pol) {
2702 gpio_free(wm5100->pdata.hp_pol);
2703 }
2704 if (i2c->irq)
2705 free_irq(i2c->irq, codec);
2706 wm5100_free_gpio(codec);
2707 if (wm5100->pdata.reset) {
2708 gpio_set_value_cansleep(wm5100->pdata.reset, 1);
2709 gpio_free(wm5100->pdata.reset);
2710 }
2711 if (wm5100->pdata.ldo_ena) {
2712 gpio_set_value_cansleep(wm5100->pdata.ldo_ena, 0);
2713 gpio_free(wm5100->pdata.ldo_ena);
2714 }
2715 regulator_put(wm5100->dbvdd3);
2716 regulator_put(wm5100->dbvdd2);
2717 regulator_put(wm5100->cpvdd);
2718 regulator_bulk_free(ARRAY_SIZE(wm5100->core_supplies),
2719 wm5100->core_supplies);
2720 return 0;
2721 }
2722
2723 static struct snd_soc_codec_driver soc_codec_dev_wm5100 = {
2724 .probe = wm5100_probe,
2725 .remove = wm5100_remove,
2726
2727 .set_sysclk = wm5100_set_sysclk,
2728 .set_pll = wm5100_set_fll,
2729 .set_bias_level = wm5100_set_bias_level,
2730 .idle_bias_off = 1,
2731
2732 .seq_notifier = wm5100_seq_notifier,
2733 .controls = wm5100_snd_controls,
2734 .num_controls = ARRAY_SIZE(wm5100_snd_controls),
2735 .dapm_widgets = wm5100_dapm_widgets,
2736 .num_dapm_widgets = ARRAY_SIZE(wm5100_dapm_widgets),
2737 .dapm_routes = wm5100_dapm_routes,
2738 .num_dapm_routes = ARRAY_SIZE(wm5100_dapm_routes),
2739
2740 .reg_cache_size = ARRAY_SIZE(wm5100_reg_defaults),
2741 .reg_word_size = sizeof(u16),
2742 .compress_type = SND_SOC_RBTREE_COMPRESSION,
2743 .reg_cache_default = wm5100_reg_defaults,
2744
2745 .volatile_register = wm5100_volatile_register,
2746 .readable_register = wm5100_readable_register,
2747 };
2748
2749 static __devinit int wm5100_i2c_probe(struct i2c_client *i2c,
2750 const struct i2c_device_id *id)
2751 {
2752 struct wm5100_pdata *pdata = dev_get_platdata(&i2c->dev);
2753 struct wm5100_priv *wm5100;
2754 int ret, i;
2755
2756 wm5100 = kzalloc(sizeof(struct wm5100_priv), GFP_KERNEL);
2757 if (wm5100 == NULL)
2758 return -ENOMEM;
2759
2760 for (i = 0; i < ARRAY_SIZE(wm5100->fll); i++)
2761 init_completion(&wm5100->fll[i].lock);
2762
2763 if (pdata)
2764 wm5100->pdata = *pdata;
2765
2766 i2c_set_clientdata(i2c, wm5100);
2767
2768 ret = snd_soc_register_codec(&i2c->dev,
2769 &soc_codec_dev_wm5100, wm5100_dai,
2770 ARRAY_SIZE(wm5100_dai));
2771 if (ret < 0) {
2772 dev_err(&i2c->dev, "Failed to register WM5100: %d\n", ret);
2773 kfree(wm5100);
2774 }
2775
2776 return ret;
2777 }
2778
2779 static __devexit int wm5100_i2c_remove(struct i2c_client *client)
2780 {
2781 snd_soc_unregister_codec(&client->dev);
2782 kfree(i2c_get_clientdata(client));
2783 return 0;
2784 }
2785
2786 static const struct i2c_device_id wm5100_i2c_id[] = {
2787 { "wm5100", 0 },
2788 { }
2789 };
2790 MODULE_DEVICE_TABLE(i2c, wm5100_i2c_id);
2791
2792 static struct i2c_driver wm5100_i2c_driver = {
2793 .driver = {
2794 .name = "wm5100",
2795 .owner = THIS_MODULE,
2796 },
2797 .probe = wm5100_i2c_probe,
2798 .remove = __devexit_p(wm5100_i2c_remove),
2799 .id_table = wm5100_i2c_id,
2800 };
2801
2802 static int __init wm5100_modinit(void)
2803 {
2804 return i2c_add_driver(&wm5100_i2c_driver);
2805 }
2806 module_init(wm5100_modinit);
2807
2808 static void __exit wm5100_exit(void)
2809 {
2810 i2c_del_driver(&wm5100_i2c_driver);
2811 }
2812 module_exit(wm5100_exit);
2813
2814 MODULE_DESCRIPTION("ASoC WM5100 driver");
2815 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
2816 MODULE_LICENSE("GPL");
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree