1 /******************************************************************************
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
8 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
24 * The full GNU General Public License is included in this distribution
25 * in the file called LICENSE.GPL.
27 * Contact Information:
28 * Intel Linux Wireless <ilw@linux.intel.com>
29 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
33 * Copyright(c) 2005 - 2011 Intel Corporation. All rights reserved.
34 * All rights reserved.
36 * Redistribution and use in source and binary forms, with or without
37 * modification, are permitted provided that the following conditions
40 * * Redistributions of source code must retain the above copyright
41 * notice, this list of conditions and the following disclaimer.
42 * * Redistributions in binary form must reproduce the above copyright
43 * notice, this list of conditions and the following disclaimer in
44 * the documentation and/or other materials provided with the
46 * * Neither the name Intel Corporation nor the names of its
47 * contributors may be used to endorse or promote products derived
48 * from this software without specific prior written permission.
50 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
51 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
52 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
53 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
54 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
55 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
56 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
57 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
58 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
59 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
60 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
61 *****************************************************************************/
64 #include <linux/kernel.h>
65 #include <linux/module.h>
66 #include <linux/slab.h>
67 #include <linux/init.h>
69 #include <net/mac80211.h>
71 #include "iwl-commands.h"
74 #include "iwl-debug.h"
75 #include "iwl-eeprom.h"
78 /************************** EEPROM BANDS ****************************
80 * The iwl_eeprom_band definitions below provide the mapping from the
81 * EEPROM contents to the specific channel number supported for each
84 * For example, iwl_priv->eeprom.band_3_channels[4] from the band_3
85 * definition below maps to physical channel 42 in the 5.2GHz spectrum.
86 * The specific geography and calibration information for that channel
87 * is contained in the eeprom map itself.
89 * During init, we copy the eeprom information and channel map
90 * information into priv->channel_info_24/52 and priv->channel_map_24/52
92 * channel_map_24/52 provides the index in the channel_info array for a
93 * given channel. We have to have two separate maps as there is channel
94 * overlap with the 2.4GHz and 5.2GHz spectrum as seen in band_1 and
97 * A value of 0xff stored in the channel_map indicates that the channel
98 * is not supported by the hardware at all.
100 * A value of 0xfe in the channel_map indicates that the channel is not
101 * valid for Tx with the current hardware. This means that
102 * while the system can tune and receive on a given channel, it may not
103 * be able to associate or transmit any frames on that
104 * channel. There is no corresponding channel information for that
107 *********************************************************************/
110 const u8 iwl_eeprom_band_1
[14] = {
111 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
115 static const u8 iwl_eeprom_band_2
[] = { /* 4915-5080MHz */
116 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16
119 static const u8 iwl_eeprom_band_3
[] = { /* 5170-5320MHz */
120 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64
123 static const u8 iwl_eeprom_band_4
[] = { /* 5500-5700MHz */
124 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140
127 static const u8 iwl_eeprom_band_5
[] = { /* 5725-5825MHz */
128 145, 149, 153, 157, 161, 165
131 static const u8 iwl_eeprom_band_6
[] = { /* 2.4 ht40 channel */
135 static const u8 iwl_eeprom_band_7
[] = { /* 5.2 ht40 channel */
136 36, 44, 52, 60, 100, 108, 116, 124, 132, 149, 157
139 /******************************************************************************
141 * EEPROM related functions
143 ******************************************************************************/
145 static int iwl_eeprom_verify_signature(struct iwl_priv
*priv
)
147 u32 gp
= iwl_read32(priv
, CSR_EEPROM_GP
) & CSR_EEPROM_GP_VALID_MSK
;
150 IWL_DEBUG_EEPROM(priv
, "EEPROM signature=0x%08x\n", gp
);
152 case CSR_EEPROM_GP_BAD_SIG_EEP_GOOD_SIG_OTP
:
153 if (priv
->nvm_device_type
!= NVM_DEVICE_TYPE_OTP
) {
154 IWL_ERR(priv
, "EEPROM with bad signature: 0x%08x\n",
159 case CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K
:
160 case CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K
:
161 if (priv
->nvm_device_type
!= NVM_DEVICE_TYPE_EEPROM
) {
162 IWL_ERR(priv
, "OTP with bad signature: 0x%08x\n", gp
);
166 case CSR_EEPROM_GP_BAD_SIGNATURE_BOTH_EEP_AND_OTP
:
168 IWL_ERR(priv
, "bad EEPROM/OTP signature, type=%s, "
169 "EEPROM_GP=0x%08x\n",
170 (priv
->nvm_device_type
== NVM_DEVICE_TYPE_OTP
)
171 ? "OTP" : "EEPROM", gp
);
178 static void iwl_set_otp_access(struct iwl_priv
*priv
, enum iwl_access_mode mode
)
182 otpgp
= iwl_read32(priv
, CSR_OTP_GP_REG
);
183 if (mode
== IWL_OTP_ACCESS_ABSOLUTE
)
184 iwl_clear_bit(priv
, CSR_OTP_GP_REG
,
185 CSR_OTP_GP_REG_OTP_ACCESS_MODE
);
187 iwl_set_bit(priv
, CSR_OTP_GP_REG
,
188 CSR_OTP_GP_REG_OTP_ACCESS_MODE
);
191 static int iwlcore_get_nvm_type(struct iwl_priv
*priv
, u32 hw_rev
)
196 /* OTP only valid for CP/PP and after */
197 switch (hw_rev
& CSR_HW_REV_TYPE_MSK
) {
198 case CSR_HW_REV_TYPE_NONE
:
199 IWL_ERR(priv
, "Unknown hardware type\n");
201 case CSR_HW_REV_TYPE_5300
:
202 case CSR_HW_REV_TYPE_5350
:
203 case CSR_HW_REV_TYPE_5100
:
204 case CSR_HW_REV_TYPE_5150
:
205 nvm_type
= NVM_DEVICE_TYPE_EEPROM
;
208 otpgp
= iwl_read32(priv
, CSR_OTP_GP_REG
);
209 if (otpgp
& CSR_OTP_GP_REG_DEVICE_SELECT
)
210 nvm_type
= NVM_DEVICE_TYPE_OTP
;
212 nvm_type
= NVM_DEVICE_TYPE_EEPROM
;
218 static int iwl_init_otp_access(struct iwl_priv
*priv
)
222 /* Enable 40MHz radio clock */
223 iwl_write32(priv
, CSR_GP_CNTRL
,
224 iwl_read32(priv
, CSR_GP_CNTRL
) |
225 CSR_GP_CNTRL_REG_FLAG_INIT_DONE
);
227 /* wait for clock to be ready */
228 ret
= iwl_poll_bit(priv
, CSR_GP_CNTRL
,
229 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY
,
230 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY
,
233 IWL_ERR(priv
, "Time out access OTP\n");
235 iwl_set_bits_prph(priv
, APMG_PS_CTRL_REG
,
236 APMG_PS_CTRL_VAL_RESET_REQ
);
238 iwl_clear_bits_prph(priv
, APMG_PS_CTRL_REG
,
239 APMG_PS_CTRL_VAL_RESET_REQ
);
242 * CSR auto clock gate disable bit -
243 * this is only applicable for HW with OTP shadow RAM
245 if (priv
->cfg
->base_params
->shadow_ram_support
)
246 iwl_set_bit(priv
, CSR_DBG_LINK_PWR_MGMT_REG
,
247 CSR_RESET_LINK_PWR_MGMT_DISABLED
);
252 static int iwl_read_otp_word(struct iwl_priv
*priv
, u16 addr
, __le16
*eeprom_data
)
258 iwl_write32(priv
, CSR_EEPROM_REG
,
259 CSR_EEPROM_REG_MSK_ADDR
& (addr
<< 1));
260 ret
= iwl_poll_bit(priv
, CSR_EEPROM_REG
,
261 CSR_EEPROM_REG_READ_VALID_MSK
,
262 CSR_EEPROM_REG_READ_VALID_MSK
,
263 IWL_EEPROM_ACCESS_TIMEOUT
);
265 IWL_ERR(priv
, "Time out reading OTP[%d]\n", addr
);
268 r
= iwl_read32(priv
, CSR_EEPROM_REG
);
269 /* check for ECC errors: */
270 otpgp
= iwl_read32(priv
, CSR_OTP_GP_REG
);
271 if (otpgp
& CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK
) {
272 /* stop in this case */
273 /* set the uncorrectable OTP ECC bit for acknowledgement */
274 iwl_set_bit(priv
, CSR_OTP_GP_REG
,
275 CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK
);
276 IWL_ERR(priv
, "Uncorrectable OTP ECC error, abort OTP read\n");
279 if (otpgp
& CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK
) {
280 /* continue in this case */
281 /* set the correctable OTP ECC bit for acknowledgement */
282 iwl_set_bit(priv
, CSR_OTP_GP_REG
,
283 CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK
);
284 IWL_ERR(priv
, "Correctable OTP ECC error, continue read\n");
286 *eeprom_data
= cpu_to_le16(r
>> 16);
291 * iwl_is_otp_empty: check for empty OTP
293 static bool iwl_is_otp_empty(struct iwl_priv
*priv
)
295 u16 next_link_addr
= 0;
297 bool is_empty
= false;
299 /* locate the beginning of OTP link list */
300 if (!iwl_read_otp_word(priv
, next_link_addr
, &link_value
)) {
302 IWL_ERR(priv
, "OTP is empty\n");
306 IWL_ERR(priv
, "Unable to read first block of OTP list.\n");
315 * iwl_find_otp_image: find EEPROM image in OTP
316 * finding the OTP block that contains the EEPROM image.
317 * the last valid block on the link list (the block _before_ the last block)
318 * is the block we should read and used to configure the device.
319 * If all the available OTP blocks are full, the last block will be the block
320 * we should read and used to configure the device.
321 * only perform this operation if shadow RAM is disabled
323 static int iwl_find_otp_image(struct iwl_priv
*priv
,
326 u16 next_link_addr
= 0, valid_addr
;
327 __le16 link_value
= 0;
330 /* set addressing mode to absolute to traverse the link list */
331 iwl_set_otp_access(priv
, IWL_OTP_ACCESS_ABSOLUTE
);
333 /* checking for empty OTP or error */
334 if (iwl_is_otp_empty(priv
))
338 * start traverse link list
339 * until reach the max number of OTP blocks
340 * different devices have different number of OTP blocks
343 /* save current valid block address
344 * check for more block on the link list
346 valid_addr
= next_link_addr
;
347 next_link_addr
= le16_to_cpu(link_value
) * sizeof(u16
);
348 IWL_DEBUG_EEPROM(priv
, "OTP blocks %d addr 0x%x\n",
349 usedblocks
, next_link_addr
);
350 if (iwl_read_otp_word(priv
, next_link_addr
, &link_value
))
354 * reach the end of link list, return success and
355 * set address point to the starting address
358 *validblockaddr
= valid_addr
;
359 /* skip first 2 bytes (link list pointer) */
360 *validblockaddr
+= 2;
363 /* more in the link list, continue */
365 } while (usedblocks
<= priv
->cfg
->base_params
->max_ll_items
);
367 /* OTP has no valid blocks */
368 IWL_DEBUG_EEPROM(priv
, "OTP has no valid blocks\n");
372 const u8
*iwl_eeprom_query_addr(const struct iwl_priv
*priv
, size_t offset
)
374 return priv
->cfg
->ops
->lib
->eeprom_ops
.query_addr(priv
, offset
);
377 u16
iwl_eeprom_query16(const struct iwl_priv
*priv
, size_t offset
)
381 return (u16
)priv
->eeprom
[offset
] | ((u16
)priv
->eeprom
[offset
+ 1] << 8);
385 * iwl_eeprom_init - read EEPROM contents
387 * Load the EEPROM contents from adapter into priv->eeprom
389 * NOTE: This routine uses the non-debug IO access functions.
391 int iwl_eeprom_init(struct iwl_priv
*priv
, u32 hw_rev
)
394 u32 gp
= iwl_read32(priv
, CSR_EEPROM_GP
);
398 u16 validblockaddr
= 0;
401 priv
->nvm_device_type
= iwlcore_get_nvm_type(priv
, hw_rev
);
402 if (priv
->nvm_device_type
== -ENOENT
)
404 /* allocate eeprom */
405 sz
= priv
->cfg
->base_params
->eeprom_size
;
406 IWL_DEBUG_EEPROM(priv
, "NVM size = %d\n", sz
);
407 priv
->eeprom
= kzalloc(sz
, GFP_KERNEL
);
412 e
= (__le16
*)priv
->eeprom
;
414 priv
->cfg
->ops
->lib
->apm_ops
.init(priv
);
416 ret
= iwl_eeprom_verify_signature(priv
);
418 IWL_ERR(priv
, "EEPROM not found, EEPROM_GP=0x%08x\n", gp
);
423 /* Make sure driver (instead of uCode) is allowed to read EEPROM */
424 ret
= priv
->cfg
->ops
->lib
->eeprom_ops
.acquire_semaphore(priv
);
426 IWL_ERR(priv
, "Failed to acquire EEPROM semaphore.\n");
431 if (priv
->nvm_device_type
== NVM_DEVICE_TYPE_OTP
) {
433 ret
= iwl_init_otp_access(priv
);
435 IWL_ERR(priv
, "Failed to initialize OTP access.\n");
439 iwl_write32(priv
, CSR_EEPROM_GP
,
440 iwl_read32(priv
, CSR_EEPROM_GP
) &
441 ~CSR_EEPROM_GP_IF_OWNER_MSK
);
443 iwl_set_bit(priv
, CSR_OTP_GP_REG
,
444 CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK
|
445 CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK
);
446 /* traversing the linked list if no shadow ram supported */
447 if (!priv
->cfg
->base_params
->shadow_ram_support
) {
448 if (iwl_find_otp_image(priv
, &validblockaddr
)) {
453 for (addr
= validblockaddr
; addr
< validblockaddr
+ sz
;
454 addr
+= sizeof(u16
)) {
457 ret
= iwl_read_otp_word(priv
, addr
, &eeprom_data
);
460 e
[cache_addr
/ 2] = eeprom_data
;
461 cache_addr
+= sizeof(u16
);
464 /* eeprom is an array of 16bit values */
465 for (addr
= 0; addr
< sz
; addr
+= sizeof(u16
)) {
468 iwl_write32(priv
, CSR_EEPROM_REG
,
469 CSR_EEPROM_REG_MSK_ADDR
& (addr
<< 1));
471 ret
= iwl_poll_bit(priv
, CSR_EEPROM_REG
,
472 CSR_EEPROM_REG_READ_VALID_MSK
,
473 CSR_EEPROM_REG_READ_VALID_MSK
,
474 IWL_EEPROM_ACCESS_TIMEOUT
);
476 IWL_ERR(priv
, "Time out reading EEPROM[%d]\n", addr
);
479 r
= iwl_read32(priv
, CSR_EEPROM_REG
);
480 e
[addr
/ 2] = cpu_to_le16(r
>> 16);
484 IWL_DEBUG_EEPROM(priv
, "NVM Type: %s, version: 0x%x\n",
485 (priv
->nvm_device_type
== NVM_DEVICE_TYPE_OTP
)
487 iwl_eeprom_query16(priv
, EEPROM_VERSION
));
491 priv
->cfg
->ops
->lib
->eeprom_ops
.release_semaphore(priv
);
495 iwl_eeprom_free(priv
);
496 /* Reset chip to save power until we load uCode during "up". */
502 void iwl_eeprom_free(struct iwl_priv
*priv
)
508 static void iwl_init_band_reference(const struct iwl_priv
*priv
,
509 int eep_band
, int *eeprom_ch_count
,
510 const struct iwl_eeprom_channel
**eeprom_ch_info
,
511 const u8
**eeprom_ch_index
)
513 u32 offset
= priv
->cfg
->ops
->lib
->
514 eeprom_ops
.regulatory_bands
[eep_band
- 1];
516 case 1: /* 2.4GHz band */
517 *eeprom_ch_count
= ARRAY_SIZE(iwl_eeprom_band_1
);
518 *eeprom_ch_info
= (struct iwl_eeprom_channel
*)
519 iwl_eeprom_query_addr(priv
, offset
);
520 *eeprom_ch_index
= iwl_eeprom_band_1
;
522 case 2: /* 4.9GHz band */
523 *eeprom_ch_count
= ARRAY_SIZE(iwl_eeprom_band_2
);
524 *eeprom_ch_info
= (struct iwl_eeprom_channel
*)
525 iwl_eeprom_query_addr(priv
, offset
);
526 *eeprom_ch_index
= iwl_eeprom_band_2
;
528 case 3: /* 5.2GHz band */
529 *eeprom_ch_count
= ARRAY_SIZE(iwl_eeprom_band_3
);
530 *eeprom_ch_info
= (struct iwl_eeprom_channel
*)
531 iwl_eeprom_query_addr(priv
, offset
);
532 *eeprom_ch_index
= iwl_eeprom_band_3
;
534 case 4: /* 5.5GHz band */
535 *eeprom_ch_count
= ARRAY_SIZE(iwl_eeprom_band_4
);
536 *eeprom_ch_info
= (struct iwl_eeprom_channel
*)
537 iwl_eeprom_query_addr(priv
, offset
);
538 *eeprom_ch_index
= iwl_eeprom_band_4
;
540 case 5: /* 5.7GHz band */
541 *eeprom_ch_count
= ARRAY_SIZE(iwl_eeprom_band_5
);
542 *eeprom_ch_info
= (struct iwl_eeprom_channel
*)
543 iwl_eeprom_query_addr(priv
, offset
);
544 *eeprom_ch_index
= iwl_eeprom_band_5
;
546 case 6: /* 2.4GHz ht40 channels */
547 *eeprom_ch_count
= ARRAY_SIZE(iwl_eeprom_band_6
);
548 *eeprom_ch_info
= (struct iwl_eeprom_channel
*)
549 iwl_eeprom_query_addr(priv
, offset
);
550 *eeprom_ch_index
= iwl_eeprom_band_6
;
552 case 7: /* 5 GHz ht40 channels */
553 *eeprom_ch_count
= ARRAY_SIZE(iwl_eeprom_band_7
);
554 *eeprom_ch_info
= (struct iwl_eeprom_channel
*)
555 iwl_eeprom_query_addr(priv
, offset
);
556 *eeprom_ch_index
= iwl_eeprom_band_7
;
564 #define CHECK_AND_PRINT(x) ((eeprom_ch->flags & EEPROM_CHANNEL_##x) \
567 * iwl_mod_ht40_chan_info - Copy ht40 channel info into driver's priv.
569 * Does not set up a command, or touch hardware.
571 static int iwl_mod_ht40_chan_info(struct iwl_priv
*priv
,
572 enum ieee80211_band band
, u16 channel
,
573 const struct iwl_eeprom_channel
*eeprom_ch
,
574 u8 clear_ht40_extension_channel
)
576 struct iwl_channel_info
*ch_info
;
578 ch_info
= (struct iwl_channel_info
*)
579 iwl_get_channel_info(priv
, band
, channel
);
581 if (!is_channel_valid(ch_info
))
584 IWL_DEBUG_EEPROM(priv
, "HT40 Ch. %d [%sGHz] %s%s%s%s%s(0x%02x %ddBm):"
585 " Ad-Hoc %ssupported\n",
587 is_channel_a_band(ch_info
) ?
589 CHECK_AND_PRINT(IBSS
),
590 CHECK_AND_PRINT(ACTIVE
),
591 CHECK_AND_PRINT(RADAR
),
592 CHECK_AND_PRINT(WIDE
),
593 CHECK_AND_PRINT(DFS
),
595 eeprom_ch
->max_power_avg
,
596 ((eeprom_ch
->flags
& EEPROM_CHANNEL_IBSS
)
597 && !(eeprom_ch
->flags
& EEPROM_CHANNEL_RADAR
)) ?
600 ch_info
->ht40_eeprom
= *eeprom_ch
;
601 ch_info
->ht40_max_power_avg
= eeprom_ch
->max_power_avg
;
602 ch_info
->ht40_flags
= eeprom_ch
->flags
;
603 if (eeprom_ch
->flags
& EEPROM_CHANNEL_VALID
)
604 ch_info
->ht40_extension_channel
&= ~clear_ht40_extension_channel
;
609 #define CHECK_AND_PRINT_I(x) ((eeprom_ch_info[ch].flags & EEPROM_CHANNEL_##x) \
613 * iwl_init_channel_map - Set up driver's info for all possible channels
615 int iwl_init_channel_map(struct iwl_priv
*priv
)
617 int eeprom_ch_count
= 0;
618 const u8
*eeprom_ch_index
= NULL
;
619 const struct iwl_eeprom_channel
*eeprom_ch_info
= NULL
;
621 struct iwl_channel_info
*ch_info
;
623 if (priv
->channel_count
) {
624 IWL_DEBUG_EEPROM(priv
, "Channel map already initialized.\n");
628 IWL_DEBUG_EEPROM(priv
, "Initializing regulatory info from EEPROM\n");
630 priv
->channel_count
=
631 ARRAY_SIZE(iwl_eeprom_band_1
) +
632 ARRAY_SIZE(iwl_eeprom_band_2
) +
633 ARRAY_SIZE(iwl_eeprom_band_3
) +
634 ARRAY_SIZE(iwl_eeprom_band_4
) +
635 ARRAY_SIZE(iwl_eeprom_band_5
);
637 IWL_DEBUG_EEPROM(priv
, "Parsing data for %d channels.\n",
638 priv
->channel_count
);
640 priv
->channel_info
= kzalloc(sizeof(struct iwl_channel_info
) *
641 priv
->channel_count
, GFP_KERNEL
);
642 if (!priv
->channel_info
) {
643 IWL_ERR(priv
, "Could not allocate channel_info\n");
644 priv
->channel_count
= 0;
648 ch_info
= priv
->channel_info
;
650 /* Loop through the 5 EEPROM bands adding them in order to the
651 * channel map we maintain (that contains additional information than
652 * what just in the EEPROM) */
653 for (band
= 1; band
<= 5; band
++) {
655 iwl_init_band_reference(priv
, band
, &eeprom_ch_count
,
656 &eeprom_ch_info
, &eeprom_ch_index
);
658 /* Loop through each band adding each of the channels */
659 for (ch
= 0; ch
< eeprom_ch_count
; ch
++) {
660 ch_info
->channel
= eeprom_ch_index
[ch
];
661 ch_info
->band
= (band
== 1) ? IEEE80211_BAND_2GHZ
:
664 /* permanently store EEPROM's channel regulatory flags
665 * and max power in channel info database. */
666 ch_info
->eeprom
= eeprom_ch_info
[ch
];
668 /* Copy the run-time flags so they are there even on
669 * invalid channels */
670 ch_info
->flags
= eeprom_ch_info
[ch
].flags
;
671 /* First write that ht40 is not enabled, and then enable
673 ch_info
->ht40_extension_channel
=
674 IEEE80211_CHAN_NO_HT40
;
676 if (!(is_channel_valid(ch_info
))) {
677 IWL_DEBUG_EEPROM(priv
,
678 "Ch. %d Flags %x [%sGHz] - "
682 is_channel_a_band(ch_info
) ?
688 /* Initialize regulatory-based run-time data */
689 ch_info
->max_power_avg
= ch_info
->curr_txpow
=
690 eeprom_ch_info
[ch
].max_power_avg
;
691 ch_info
->scan_power
= eeprom_ch_info
[ch
].max_power_avg
;
692 ch_info
->min_power
= 0;
694 IWL_DEBUG_EEPROM(priv
, "Ch. %d [%sGHz] "
695 "%s%s%s%s%s%s(0x%02x %ddBm):"
696 " Ad-Hoc %ssupported\n",
698 is_channel_a_band(ch_info
) ?
700 CHECK_AND_PRINT_I(VALID
),
701 CHECK_AND_PRINT_I(IBSS
),
702 CHECK_AND_PRINT_I(ACTIVE
),
703 CHECK_AND_PRINT_I(RADAR
),
704 CHECK_AND_PRINT_I(WIDE
),
705 CHECK_AND_PRINT_I(DFS
),
706 eeprom_ch_info
[ch
].flags
,
707 eeprom_ch_info
[ch
].max_power_avg
,
708 ((eeprom_ch_info
[ch
].
709 flags
& EEPROM_CHANNEL_IBSS
)
710 && !(eeprom_ch_info
[ch
].
711 flags
& EEPROM_CHANNEL_RADAR
))
718 /* Check if we do have HT40 channels */
719 if (priv
->cfg
->ops
->lib
->eeprom_ops
.regulatory_bands
[5] ==
720 EEPROM_REGULATORY_BAND_NO_HT40
&&
721 priv
->cfg
->ops
->lib
->eeprom_ops
.regulatory_bands
[6] ==
722 EEPROM_REGULATORY_BAND_NO_HT40
)
725 /* Two additional EEPROM bands for 2.4 and 5 GHz HT40 channels */
726 for (band
= 6; band
<= 7; band
++) {
727 enum ieee80211_band ieeeband
;
729 iwl_init_band_reference(priv
, band
, &eeprom_ch_count
,
730 &eeprom_ch_info
, &eeprom_ch_index
);
732 /* EEPROM band 6 is 2.4, band 7 is 5 GHz */
734 (band
== 6) ? IEEE80211_BAND_2GHZ
: IEEE80211_BAND_5GHZ
;
736 /* Loop through each band adding each of the channels */
737 for (ch
= 0; ch
< eeprom_ch_count
; ch
++) {
738 /* Set up driver's info for lower half */
739 iwl_mod_ht40_chan_info(priv
, ieeeband
,
742 IEEE80211_CHAN_NO_HT40PLUS
);
744 /* Set up driver's info for upper half */
745 iwl_mod_ht40_chan_info(priv
, ieeeband
,
746 eeprom_ch_index
[ch
] + 4,
748 IEEE80211_CHAN_NO_HT40MINUS
);
752 /* for newer device (6000 series and up)
753 * EEPROM contain enhanced tx power information
754 * driver need to process addition information
755 * to determine the max channel tx power limits
757 if (priv
->cfg
->ops
->lib
->eeprom_ops
.update_enhanced_txpower
)
758 priv
->cfg
->ops
->lib
->eeprom_ops
.update_enhanced_txpower(priv
);
764 * iwl_free_channel_map - undo allocations in iwl_init_channel_map
766 void iwl_free_channel_map(struct iwl_priv
*priv
)
768 kfree(priv
->channel_info
);
769 priv
->channel_count
= 0;
773 * iwl_get_channel_info - Find driver's private channel info
775 * Based on band and channel number.
777 const struct iwl_channel_info
*iwl_get_channel_info(const struct iwl_priv
*priv
,
778 enum ieee80211_band band
, u16 channel
)
783 case IEEE80211_BAND_5GHZ
:
784 for (i
= 14; i
< priv
->channel_count
; i
++) {
785 if (priv
->channel_info
[i
].channel
== channel
)
786 return &priv
->channel_info
[i
];
789 case IEEE80211_BAND_2GHZ
:
790 if (channel
>= 1 && channel
<= 14)
791 return &priv
->channel_info
[channel
- 1];