?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
iwlagn: fix tx power initialization
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / wireless / iwlwifi / iwl-agn.c
bloba4ec524f4655d2f161089b09ee70cb17b3a9fb97
1 /******************************************************************************
2 *
3 * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
30 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
31
32 #include <linux/kernel.h>
33 #include <linux/module.h>
34 #include <linux/init.h>
35 #include <linux/pci.h>
36 #include <linux/pci-aspm.h>
37 #include <linux/slab.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/delay.h>
40 #include <linux/sched.h>
41 #include <linux/skbuff.h>
42 #include <linux/netdevice.h>
43 #include <linux/wireless.h>
44 #include <linux/firmware.h>
45 #include <linux/etherdevice.h>
46 #include <linux/if_arp.h>
47
48 #include <net/mac80211.h>
49
50 #include <asm/div64.h>
51
52 #define DRV_NAME "iwlagn"
53
54 #include "iwl-eeprom.h"
55 #include "iwl-dev.h"
56 #include "iwl-core.h"
57 #include "iwl-io.h"
58 #include "iwl-helpers.h"
59 #include "iwl-sta.h"
60 #include "iwl-agn-calib.h"
61 #include "iwl-agn.h"
62
63
64 /******************************************************************************
65 *
66 * module boiler plate
67 *
68 ******************************************************************************/
69
70 /*
71 * module name, copyright, version, etc.
72 */
73 #define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux"
74
75 #ifdef CONFIG_IWLWIFI_DEBUG
76 #define VD "d"
77 #else
78 #define VD
79 #endif
80
81 #define DRV_VERSION IWLWIFI_VERSION VD
82
83
84 MODULE_DESCRIPTION(DRV_DESCRIPTION);
85 MODULE_VERSION(DRV_VERSION);
86 MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
87 MODULE_LICENSE("GPL");
88
89 static int iwlagn_ant_coupling;
90 static bool iwlagn_bt_ch_announce = 1;
91
92 void iwl_update_chain_flags(struct iwl_priv *priv)
93 {
94 struct iwl_rxon_context *ctx;
95
96 if (priv->cfg->ops->hcmd->set_rxon_chain) {
97 for_each_context(priv, ctx) {
98 priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
99 if (ctx->active.rx_chain != ctx->staging.rx_chain)
100 iwlcore_commit_rxon(priv, ctx);
101 }
102 }
103 }
104
105 static void iwl_clear_free_frames(struct iwl_priv *priv)
106 {
107 struct list_head *element;
108
109 IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
110 priv->frames_count);
111
112 while (!list_empty(&priv->free_frames)) {
113 element = priv->free_frames.next;
114 list_del(element);
115 kfree(list_entry(element, struct iwl_frame, list));
116 priv->frames_count--;
117 }
118
119 if (priv->frames_count) {
120 IWL_WARN(priv, "%d frames still in use. Did we lose one?\n",
121 priv->frames_count);
122 priv->frames_count = 0;
123 }
124 }
125
126 static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv)
127 {
128 struct iwl_frame *frame;
129 struct list_head *element;
130 if (list_empty(&priv->free_frames)) {
131 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
132 if (!frame) {
133 IWL_ERR(priv, "Could not allocate frame!\n");
134 return NULL;
135 }
136
137 priv->frames_count++;
138 return frame;
139 }
140
141 element = priv->free_frames.next;
142 list_del(element);
143 return list_entry(element, struct iwl_frame, list);
144 }
145
146 static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame)
147 {
148 memset(frame, 0, sizeof(*frame));
149 list_add(&frame->list, &priv->free_frames);
150 }
151
152 static u32 iwl_fill_beacon_frame(struct iwl_priv *priv,
153 struct ieee80211_hdr *hdr,
154 int left)
155 {
156 lockdep_assert_held(&priv->mutex);
157
158 if (!priv->beacon_skb)
159 return 0;
160
161 if (priv->beacon_skb->len > left)
162 return 0;
163
164 memcpy(hdr, priv->beacon_skb->data, priv->beacon_skb->len);
165
166 return priv->beacon_skb->len;
167 }
168
169 /* Parse the beacon frame to find the TIM element and set tim_idx & tim_size */
170 static void iwl_set_beacon_tim(struct iwl_priv *priv,
171 struct iwl_tx_beacon_cmd *tx_beacon_cmd,
172 u8 *beacon, u32 frame_size)
173 {
174 u16 tim_idx;
175 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)beacon;
176
177 /*
178 * The index is relative to frame start but we start looking at the
179 * variable-length part of the beacon.
180 */
181 tim_idx = mgmt->u.beacon.variable - beacon;
182
183 /* Parse variable-length elements of beacon to find WLAN_EID_TIM */
184 while ((tim_idx < (frame_size - 2)) &&
185 (beacon[tim_idx] != WLAN_EID_TIM))
186 tim_idx += beacon[tim_idx+1] + 2;
187
188 /* If TIM field was found, set variables */
189 if ((tim_idx < (frame_size - 1)) && (beacon[tim_idx] == WLAN_EID_TIM)) {
190 tx_beacon_cmd->tim_idx = cpu_to_le16(tim_idx);
191 tx_beacon_cmd->tim_size = beacon[tim_idx+1];
192 } else
193 IWL_WARN(priv, "Unable to find TIM Element in beacon\n");
194 }
195
196 static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv,
197 struct iwl_frame *frame)
198 {
199 struct iwl_tx_beacon_cmd *tx_beacon_cmd;
200 u32 frame_size;
201 u32 rate_flags;
202 u32 rate;
203 /*
204 * We have to set up the TX command, the TX Beacon command, and the
205 * beacon contents.
206 */
207
208 lockdep_assert_held(&priv->mutex);
209
210 if (!priv->beacon_ctx) {
211 IWL_ERR(priv, "trying to build beacon w/o beacon context!\n");
212 return 0;
213 }
214
215 /* Initialize memory */
216 tx_beacon_cmd = &frame->u.beacon;
217 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
218
219 /* Set up TX beacon contents */
220 frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame,
221 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
222 if (WARN_ON_ONCE(frame_size > MAX_MPDU_SIZE))
223 return 0;
224 if (!frame_size)
225 return 0;
226
227 /* Set up TX command fields */
228 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
229 tx_beacon_cmd->tx.sta_id = priv->beacon_ctx->bcast_sta_id;
230 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
231 tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK |
232 TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK;
233
234 /* Set up TX beacon command fields */
235 iwl_set_beacon_tim(priv, tx_beacon_cmd, (u8 *)tx_beacon_cmd->frame,
236 frame_size);
237
238 /* Set up packet rate and flags */
239 rate = iwl_rate_get_lowest_plcp(priv, priv->beacon_ctx);
240 priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant,
241 priv->hw_params.valid_tx_ant);
242 rate_flags = iwl_ant_idx_to_flags(priv->mgmt_tx_ant);
243 if ((rate >= IWL_FIRST_CCK_RATE) && (rate <= IWL_LAST_CCK_RATE))
244 rate_flags |= RATE_MCS_CCK_MSK;
245 tx_beacon_cmd->tx.rate_n_flags = iwl_hw_set_rate_n_flags(rate,
246 rate_flags);
247
248 return sizeof(*tx_beacon_cmd) + frame_size;
249 }
250
251 int iwlagn_send_beacon_cmd(struct iwl_priv *priv)
252 {
253 struct iwl_frame *frame;
254 unsigned int frame_size;
255 int rc;
256 struct iwl_host_cmd cmd = {
257 .id = REPLY_TX_BEACON,
258 .flags = CMD_SIZE_HUGE,
259 };
260
261 frame = iwl_get_free_frame(priv);
262 if (!frame) {
263 IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
264 "command.\n");
265 return -ENOMEM;
266 }
267
268 frame_size = iwl_hw_get_beacon_cmd(priv, frame);
269 if (!frame_size) {
270 IWL_ERR(priv, "Error configuring the beacon command\n");
271 iwl_free_frame(priv, frame);
272 return -EINVAL;
273 }
274
275 cmd.len = frame_size;
276 cmd.data = &frame->u.cmd[0];
277
278 rc = iwl_send_cmd_sync(priv, &cmd);
279
280 iwl_free_frame(priv, frame);
281
282 return rc;
283 }
284
285 static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
286 {
287 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
288
289 dma_addr_t addr = get_unaligned_le32(&tb->lo);
290 if (sizeof(dma_addr_t) > sizeof(u32))
291 addr |=
292 ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
293
294 return addr;
295 }
296
297 static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
298 {
299 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
300
301 return le16_to_cpu(tb->hi_n_len) >> 4;
302 }
303
304 static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
305 dma_addr_t addr, u16 len)
306 {
307 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
308 u16 hi_n_len = len << 4;
309
310 put_unaligned_le32(addr, &tb->lo);
311 if (sizeof(dma_addr_t) > sizeof(u32))
312 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
313
314 tb->hi_n_len = cpu_to_le16(hi_n_len);
315
316 tfd->num_tbs = idx + 1;
317 }
318
319 static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
320 {
321 return tfd->num_tbs & 0x1f;
322 }
323
324 /**
325 * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
326 * @priv - driver private data
327 * @txq - tx queue
328 *
329 * Does NOT advance any TFD circular buffer read/write indexes
330 * Does NOT free the TFD itself (which is within circular buffer)
331 */
332 void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
333 {
334 struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds;
335 struct iwl_tfd *tfd;
336 struct pci_dev *dev = priv->pci_dev;
337 int index = txq->q.read_ptr;
338 int i;
339 int num_tbs;
340
341 tfd = &tfd_tmp[index];
342
343 /* Sanity check on number of chunks */
344 num_tbs = iwl_tfd_get_num_tbs(tfd);
345
346 if (num_tbs >= IWL_NUM_OF_TBS) {
347 IWL_ERR(priv, "Too many chunks: %i\n", num_tbs);
348 /* @todo issue fatal error, it is quite serious situation */
349 return;
350 }
351
352 /* Unmap tx_cmd */
353 if (num_tbs)
354 pci_unmap_single(dev,
355 dma_unmap_addr(&txq->meta[index], mapping),
356 dma_unmap_len(&txq->meta[index], len),
357 PCI_DMA_BIDIRECTIONAL);
358
359 /* Unmap chunks, if any. */
360 for (i = 1; i < num_tbs; i++)
361 pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i),
362 iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE);
363
364 /* free SKB */
365 if (txq->txb) {
366 struct sk_buff *skb;
367
368 skb = txq->txb[txq->q.read_ptr].skb;
369
370 /* can be called from irqs-disabled context */
371 if (skb) {
372 dev_kfree_skb_any(skb);
373 txq->txb[txq->q.read_ptr].skb = NULL;
374 }
375 }
376 }
377
378 int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
379 struct iwl_tx_queue *txq,
380 dma_addr_t addr, u16 len,
381 u8 reset, u8 pad)
382 {
383 struct iwl_queue *q;
384 struct iwl_tfd *tfd, *tfd_tmp;
385 u32 num_tbs;
386
387 q = &txq->q;
388 tfd_tmp = (struct iwl_tfd *)txq->tfds;
389 tfd = &tfd_tmp[q->write_ptr];
390
391 if (reset)
392 memset(tfd, 0, sizeof(*tfd));
393
394 num_tbs = iwl_tfd_get_num_tbs(tfd);
395
396 /* Each TFD can point to a maximum 20 Tx buffers */
397 if (num_tbs >= IWL_NUM_OF_TBS) {
398 IWL_ERR(priv, "Error can not send more than %d chunks\n",
399 IWL_NUM_OF_TBS);
400 return -EINVAL;
401 }
402
403 if (WARN_ON(addr & ~DMA_BIT_MASK(36)))
404 return -EINVAL;
405
406 if (unlikely(addr & ~IWL_TX_DMA_MASK))
407 IWL_ERR(priv, "Unaligned address = %llx\n",
408 (unsigned long long)addr);
409
410 iwl_tfd_set_tb(tfd, num_tbs, addr, len);
411
412 return 0;
413 }
414
415 /*
416 * Tell nic where to find circular buffer of Tx Frame Descriptors for
417 * given Tx queue, and enable the DMA channel used for that queue.
418 *
419 * supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
420 * channels supported in hardware.
421 */
422 int iwl_hw_tx_queue_init(struct iwl_priv *priv,
423 struct iwl_tx_queue *txq)
424 {
425 int txq_id = txq->q.id;
426
427 /* Circular buffer (TFD queue in DRAM) physical base address */
428 iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
429 txq->q.dma_addr >> 8);
430
431 return 0;
432 }
433
434 static void iwl_bg_beacon_update(struct work_struct *work)
435 {
436 struct iwl_priv *priv =
437 container_of(work, struct iwl_priv, beacon_update);
438 struct sk_buff *beacon;
439
440 mutex_lock(&priv->mutex);
441 if (!priv->beacon_ctx) {
442 IWL_ERR(priv, "updating beacon w/o beacon context!\n");
443 goto out;
444 }
445
446 if (priv->beacon_ctx->vif->type != NL80211_IFTYPE_AP) {
447 /*
448 * The ucode will send beacon notifications even in
449 * IBSS mode, but we don't want to process them. But
450 * we need to defer the type check to here due to
451 * requiring locking around the beacon_ctx access.
452 */
453 goto out;
454 }
455
456 /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
457 beacon = ieee80211_beacon_get(priv->hw, priv->beacon_ctx->vif);
458 if (!beacon) {
459 IWL_ERR(priv, "update beacon failed -- keeping old\n");
460 goto out;
461 }
462
463 /* new beacon skb is allocated every time; dispose previous.*/
464 dev_kfree_skb(priv->beacon_skb);
465
466 priv->beacon_skb = beacon;
467
468 iwlagn_send_beacon_cmd(priv);
469 out:
470 mutex_unlock(&priv->mutex);
471 }
472
473 static void iwl_bg_bt_runtime_config(struct work_struct *work)
474 {
475 struct iwl_priv *priv =
476 container_of(work, struct iwl_priv, bt_runtime_config);
477
478 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
479 return;
480
481 /* dont send host command if rf-kill is on */
482 if (!iwl_is_ready_rf(priv))
483 return;
484 priv->cfg->ops->hcmd->send_bt_config(priv);
485 }
486
487 static void iwl_bg_bt_full_concurrency(struct work_struct *work)
488 {
489 struct iwl_priv *priv =
490 container_of(work, struct iwl_priv, bt_full_concurrency);
491 struct iwl_rxon_context *ctx;
492
493 mutex_lock(&priv->mutex);
494
495 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
496 goto out;
497
498 /* dont send host command if rf-kill is on */
499 if (!iwl_is_ready_rf(priv))
500 goto out;
501
502 IWL_DEBUG_INFO(priv, "BT coex in %s mode\n",
503 priv->bt_full_concurrent ?
504 "full concurrency" : "3-wire");
505
506 /*
507 * LQ & RXON updated cmds must be sent before BT Config cmd
508 * to avoid 3-wire collisions
509 */
510 for_each_context(priv, ctx) {
511 if (priv->cfg->ops->hcmd->set_rxon_chain)
512 priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
513 iwlcore_commit_rxon(priv, ctx);
514 }
515
516 priv->cfg->ops->hcmd->send_bt_config(priv);
517 out:
518 mutex_unlock(&priv->mutex);
519 }
520
521 /**
522 * iwl_bg_statistics_periodic - Timer callback to queue statistics
523 *
524 * This callback is provided in order to send a statistics request.
525 *
526 * This timer function is continually reset to execute within
527 * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
528 * was received. We need to ensure we receive the statistics in order
529 * to update the temperature used for calibrating the TXPOWER.
530 */
531 static void iwl_bg_statistics_periodic(unsigned long data)
532 {
533 struct iwl_priv *priv = (struct iwl_priv *)data;
534
535 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
536 return;
537
538 /* dont send host command if rf-kill is on */
539 if (!iwl_is_ready_rf(priv))
540 return;
541
542 iwl_send_statistics_request(priv, CMD_ASYNC, false);
543 }
544
545
546 static void iwl_print_cont_event_trace(struct iwl_priv *priv, u32 base,
547 u32 start_idx, u32 num_events,
548 u32 mode)
549 {
550 u32 i;
551 u32 ptr; /* SRAM byte address of log data */
552 u32 ev, time, data; /* event log data */
553 unsigned long reg_flags;
554
555 if (mode == 0)
556 ptr = base + (4 * sizeof(u32)) + (start_idx * 2 * sizeof(u32));
557 else
558 ptr = base + (4 * sizeof(u32)) + (start_idx * 3 * sizeof(u32));
559
560 /* Make sure device is powered up for SRAM reads */
561 spin_lock_irqsave(&priv->reg_lock, reg_flags);
562 if (iwl_grab_nic_access(priv)) {
563 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
564 return;
565 }
566
567 /* Set starting address; reads will auto-increment */
568 iwl_write32(priv, HBUS_TARG_MEM_RADDR, ptr);
569 rmb();
570
571 /*
572 * "time" is actually "data" for mode 0 (no timestamp).
573 * place event id # at far right for easier visual parsing.
574 */
575 for (i = 0; i < num_events; i++) {
576 ev = iwl_read32(priv, HBUS_TARG_MEM_RDAT);
577 time = iwl_read32(priv, HBUS_TARG_MEM_RDAT);
578 if (mode == 0) {
579 trace_iwlwifi_dev_ucode_cont_event(priv,
580 0, time, ev);
581 } else {
582 data = iwl_read32(priv, HBUS_TARG_MEM_RDAT);
583 trace_iwlwifi_dev_ucode_cont_event(priv,
584 time, data, ev);
585 }
586 }
587 /* Allow device to power down */
588 iwl_release_nic_access(priv);
589 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
590 }
591
592 static void iwl_continuous_event_trace(struct iwl_priv *priv)
593 {
594 u32 capacity; /* event log capacity in # entries */
595 u32 base; /* SRAM byte address of event log header */
596 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
597 u32 num_wraps; /* # times uCode wrapped to top of log */
598 u32 next_entry; /* index of next entry to be written by uCode */
599
600 base = priv->device_pointers.error_event_table;
601 if (priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
602 capacity = iwl_read_targ_mem(priv, base);
603 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
604 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
605 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
606 } else
607 return;
608
609 if (num_wraps == priv->event_log.num_wraps) {
610 iwl_print_cont_event_trace(priv,
611 base, priv->event_log.next_entry,
612 next_entry - priv->event_log.next_entry,
613 mode);
614 priv->event_log.non_wraps_count++;
615 } else {
616 if ((num_wraps - priv->event_log.num_wraps) > 1)
617 priv->event_log.wraps_more_count++;
618 else
619 priv->event_log.wraps_once_count++;
620 trace_iwlwifi_dev_ucode_wrap_event(priv,
621 num_wraps - priv->event_log.num_wraps,
622 next_entry, priv->event_log.next_entry);
623 if (next_entry < priv->event_log.next_entry) {
624 iwl_print_cont_event_trace(priv, base,
625 priv->event_log.next_entry,
626 capacity - priv->event_log.next_entry,
627 mode);
628
629 iwl_print_cont_event_trace(priv, base, 0,
630 next_entry, mode);
631 } else {
632 iwl_print_cont_event_trace(priv, base,
633 next_entry, capacity - next_entry,
634 mode);
635
636 iwl_print_cont_event_trace(priv, base, 0,
637 next_entry, mode);
638 }
639 }
640 priv->event_log.num_wraps = num_wraps;
641 priv->event_log.next_entry = next_entry;
642 }
643
644 /**
645 * iwl_bg_ucode_trace - Timer callback to log ucode event
646 *
647 * The timer is continually set to execute every
648 * UCODE_TRACE_PERIOD milliseconds after the last timer expired
649 * this function is to perform continuous uCode event logging operation
650 * if enabled
651 */
652 static void iwl_bg_ucode_trace(unsigned long data)
653 {
654 struct iwl_priv *priv = (struct iwl_priv *)data;
655
656 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
657 return;
658
659 if (priv->event_log.ucode_trace) {
660 iwl_continuous_event_trace(priv);
661 /* Reschedule the timer to occur in UCODE_TRACE_PERIOD */
662 mod_timer(&priv->ucode_trace,
663 jiffies + msecs_to_jiffies(UCODE_TRACE_PERIOD));
664 }
665 }
666
667 static void iwl_bg_tx_flush(struct work_struct *work)
668 {
669 struct iwl_priv *priv =
670 container_of(work, struct iwl_priv, tx_flush);
671
672 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
673 return;
674
675 /* do nothing if rf-kill is on */
676 if (!iwl_is_ready_rf(priv))
677 return;
678
679 if (priv->cfg->ops->lib->txfifo_flush) {
680 IWL_DEBUG_INFO(priv, "device request: flush all tx frames\n");
681 iwlagn_dev_txfifo_flush(priv, IWL_DROP_ALL);
682 }
683 }
684
685 /**
686 * iwl_rx_handle - Main entry function for receiving responses from uCode
687 *
688 * Uses the priv->rx_handlers callback function array to invoke
689 * the appropriate handlers, including command responses,
690 * frame-received notifications, and other notifications.
691 */
692 static void iwl_rx_handle(struct iwl_priv *priv)
693 {
694 struct iwl_rx_mem_buffer *rxb;
695 struct iwl_rx_packet *pkt;
696 struct iwl_rx_queue *rxq = &priv->rxq;
697 u32 r, i;
698 int reclaim;
699 unsigned long flags;
700 u8 fill_rx = 0;
701 u32 count = 8;
702 int total_empty;
703
704 /* uCode's read index (stored in shared DRAM) indicates the last Rx
705 * buffer that the driver may process (last buffer filled by ucode). */
706 r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
707 i = rxq->read;
708
709 /* Rx interrupt, but nothing sent from uCode */
710 if (i == r)
711 IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
712
713 /* calculate total frames need to be restock after handling RX */
714 total_empty = r - rxq->write_actual;
715 if (total_empty < 0)
716 total_empty += RX_QUEUE_SIZE;
717
718 if (total_empty > (RX_QUEUE_SIZE / 2))
719 fill_rx = 1;
720
721 while (i != r) {
722 int len;
723
724 rxb = rxq->queue[i];
725
726 /* If an RXB doesn't have a Rx queue slot associated with it,
727 * then a bug has been introduced in the queue refilling
728 * routines -- catch it here */
729 if (WARN_ON(rxb == NULL)) {
730 i = (i + 1) & RX_QUEUE_MASK;
731 continue;
732 }
733
734 rxq->queue[i] = NULL;
735
736 pci_unmap_page(priv->pci_dev, rxb->page_dma,
737 PAGE_SIZE << priv->hw_params.rx_page_order,
738 PCI_DMA_FROMDEVICE);
739 pkt = rxb_addr(rxb);
740
741 len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
742 len += sizeof(u32); /* account for status word */
743 trace_iwlwifi_dev_rx(priv, pkt, len);
744
745 /* Reclaim a command buffer only if this packet is a response
746 * to a (driver-originated) command.
747 * If the packet (e.g. Rx frame) originated from uCode,
748 * there is no command buffer to reclaim.
749 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
750 * but apparently a few don't get set; catch them here. */
751 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
752 (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
753 (pkt->hdr.cmd != REPLY_RX) &&
754 (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
755 (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
756 (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
757 (pkt->hdr.cmd != REPLY_TX);
758
759 /*
760 * Do the notification wait before RX handlers so
761 * even if the RX handler consumes the RXB we have
762 * access to it in the notification wait entry.
763 */
764 if (!list_empty(&priv->_agn.notif_waits)) {
765 struct iwl_notification_wait *w;
766
767 spin_lock(&priv->_agn.notif_wait_lock);
768 list_for_each_entry(w, &priv->_agn.notif_waits, list) {
769 if (w->cmd == pkt->hdr.cmd) {
770 w->triggered = true;
771 if (w->fn)
772 w->fn(priv, pkt, w->fn_data);
773 }
774 }
775 spin_unlock(&priv->_agn.notif_wait_lock);
776
777 wake_up_all(&priv->_agn.notif_waitq);
778 }
779
780 /* Based on type of command response or notification,
781 * handle those that need handling via function in
782 * rx_handlers table. See iwl_setup_rx_handlers() */
783 if (priv->rx_handlers[pkt->hdr.cmd]) {
784 IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r,
785 i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
786 priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
787 priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
788 } else {
789 /* No handling needed */
790 IWL_DEBUG_RX(priv,
791 "r %d i %d No handler needed for %s, 0x%02x\n",
792 r, i, get_cmd_string(pkt->hdr.cmd),
793 pkt->hdr.cmd);
794 }
795
796 /*
797 * XXX: After here, we should always check rxb->page
798 * against NULL before touching it or its virtual
799 * memory (pkt). Because some rx_handler might have
800 * already taken or freed the pages.
801 */
802
803 if (reclaim) {
804 /* Invoke any callbacks, transfer the buffer to caller,
805 * and fire off the (possibly) blocking iwl_send_cmd()
806 * as we reclaim the driver command queue */
807 if (rxb->page)
808 iwl_tx_cmd_complete(priv, rxb);
809 else
810 IWL_WARN(priv, "Claim null rxb?\n");
811 }
812
813 /* Reuse the page if possible. For notification packets and
814 * SKBs that fail to Rx correctly, add them back into the
815 * rx_free list for reuse later. */
816 spin_lock_irqsave(&rxq->lock, flags);
817 if (rxb->page != NULL) {
818 rxb->page_dma = pci_map_page(priv->pci_dev, rxb->page,
819 0, PAGE_SIZE << priv->hw_params.rx_page_order,
820 PCI_DMA_FROMDEVICE);
821 list_add_tail(&rxb->list, &rxq->rx_free);
822 rxq->free_count++;
823 } else
824 list_add_tail(&rxb->list, &rxq->rx_used);
825
826 spin_unlock_irqrestore(&rxq->lock, flags);
827
828 i = (i + 1) & RX_QUEUE_MASK;
829 /* If there are a lot of unused frames,
830 * restock the Rx queue so ucode wont assert. */
831 if (fill_rx) {
832 count++;
833 if (count >= 8) {
834 rxq->read = i;
835 iwlagn_rx_replenish_now(priv);
836 count = 0;
837 }
838 }
839 }
840
841 /* Backtrack one entry */
842 rxq->read = i;
843 if (fill_rx)
844 iwlagn_rx_replenish_now(priv);
845 else
846 iwlagn_rx_queue_restock(priv);
847 }
848
849 /* tasklet for iwlagn interrupt */
850 static void iwl_irq_tasklet(struct iwl_priv *priv)
851 {
852 u32 inta = 0;
853 u32 handled = 0;
854 unsigned long flags;
855 u32 i;
856 #ifdef CONFIG_IWLWIFI_DEBUG
857 u32 inta_mask;
858 #endif
859
860 spin_lock_irqsave(&priv->lock, flags);
861
862 /* Ack/clear/reset pending uCode interrupts.
863 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
864 */
865 /* There is a hardware bug in the interrupt mask function that some
866 * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
867 * they are disabled in the CSR_INT_MASK register. Furthermore the
868 * ICT interrupt handling mechanism has another bug that might cause
869 * these unmasked interrupts fail to be detected. We workaround the
870 * hardware bugs here by ACKing all the possible interrupts so that
871 * interrupt coalescing can still be achieved.
872 */
873 iwl_write32(priv, CSR_INT, priv->_agn.inta | ~priv->inta_mask);
874
875 inta = priv->_agn.inta;
876
877 #ifdef CONFIG_IWLWIFI_DEBUG
878 if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
879 /* just for debug */
880 inta_mask = iwl_read32(priv, CSR_INT_MASK);
881 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ",
882 inta, inta_mask);
883 }
884 #endif
885
886 spin_unlock_irqrestore(&priv->lock, flags);
887
888 /* saved interrupt in inta variable now we can reset priv->_agn.inta */
889 priv->_agn.inta = 0;
890
891 /* Now service all interrupt bits discovered above. */
892 if (inta & CSR_INT_BIT_HW_ERR) {
893 IWL_ERR(priv, "Hardware error detected. Restarting.\n");
894
895 /* Tell the device to stop sending interrupts */
896 iwl_disable_interrupts(priv);
897
898 priv->isr_stats.hw++;
899 iwl_irq_handle_error(priv);
900
901 handled |= CSR_INT_BIT_HW_ERR;
902
903 return;
904 }
905
906 #ifdef CONFIG_IWLWIFI_DEBUG
907 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
908 /* NIC fires this, but we don't use it, redundant with WAKEUP */
909 if (inta & CSR_INT_BIT_SCD) {
910 IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
911 "the frame/frames.\n");
912 priv->isr_stats.sch++;
913 }
914
915 /* Alive notification via Rx interrupt will do the real work */
916 if (inta & CSR_INT_BIT_ALIVE) {
917 IWL_DEBUG_ISR(priv, "Alive interrupt\n");
918 priv->isr_stats.alive++;
919 }
920 }
921 #endif
922 /* Safely ignore these bits for debug checks below */
923 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
924
925 /* HW RF KILL switch toggled */
926 if (inta & CSR_INT_BIT_RF_KILL) {
927 int hw_rf_kill = 0;
928 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
929 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
930 hw_rf_kill = 1;
931
932 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
933 hw_rf_kill ? "disable radio" : "enable radio");
934
935 priv->isr_stats.rfkill++;
936
937 /* driver only loads ucode once setting the interface up.
938 * the driver allows loading the ucode even if the radio
939 * is killed. Hence update the killswitch state here. The
940 * rfkill handler will care about restarting if needed.
941 */
942 if (!test_bit(STATUS_ALIVE, &priv->status)) {
943 if (hw_rf_kill)
944 set_bit(STATUS_RF_KILL_HW, &priv->status);
945 else
946 clear_bit(STATUS_RF_KILL_HW, &priv->status);
947 wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
948 }
949
950 handled |= CSR_INT_BIT_RF_KILL;
951 }
952
953 /* Chip got too hot and stopped itself */
954 if (inta & CSR_INT_BIT_CT_KILL) {
955 IWL_ERR(priv, "Microcode CT kill error detected.\n");
956 priv->isr_stats.ctkill++;
957 handled |= CSR_INT_BIT_CT_KILL;
958 }
959
960 /* Error detected by uCode */
961 if (inta & CSR_INT_BIT_SW_ERR) {
962 IWL_ERR(priv, "Microcode SW error detected. "
963 " Restarting 0x%X.\n", inta);
964 priv->isr_stats.sw++;
965 iwl_irq_handle_error(priv);
966 handled |= CSR_INT_BIT_SW_ERR;
967 }
968
969 /* uCode wakes up after power-down sleep */
970 if (inta & CSR_INT_BIT_WAKEUP) {
971 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
972 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
973 for (i = 0; i < priv->hw_params.max_txq_num; i++)
974 iwl_txq_update_write_ptr(priv, &priv->txq[i]);
975
976 priv->isr_stats.wakeup++;
977
978 handled |= CSR_INT_BIT_WAKEUP;
979 }
980
981 /* All uCode command responses, including Tx command responses,
982 * Rx "responses" (frame-received notification), and other
983 * notifications from uCode come through here*/
984 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
985 CSR_INT_BIT_RX_PERIODIC)) {
986 IWL_DEBUG_ISR(priv, "Rx interrupt\n");
987 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
988 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
989 iwl_write32(priv, CSR_FH_INT_STATUS,
990 CSR_FH_INT_RX_MASK);
991 }
992 if (inta & CSR_INT_BIT_RX_PERIODIC) {
993 handled |= CSR_INT_BIT_RX_PERIODIC;
994 iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC);
995 }
996 /* Sending RX interrupt require many steps to be done in the
997 * the device:
998 * 1- write interrupt to current index in ICT table.
999 * 2- dma RX frame.
1000 * 3- update RX shared data to indicate last write index.
1001 * 4- send interrupt.
1002 * This could lead to RX race, driver could receive RX interrupt
1003 * but the shared data changes does not reflect this;
1004 * periodic interrupt will detect any dangling Rx activity.
1005 */
1006
1007 /* Disable periodic interrupt; we use it as just a one-shot. */
1008 iwl_write8(priv, CSR_INT_PERIODIC_REG,
1009 CSR_INT_PERIODIC_DIS);
1010 iwl_rx_handle(priv);
1011
1012 /*
1013 * Enable periodic interrupt in 8 msec only if we received
1014 * real RX interrupt (instead of just periodic int), to catch
1015 * any dangling Rx interrupt. If it was just the periodic
1016 * interrupt, there was no dangling Rx activity, and no need
1017 * to extend the periodic interrupt; one-shot is enough.
1018 */
1019 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
1020 iwl_write8(priv, CSR_INT_PERIODIC_REG,
1021 CSR_INT_PERIODIC_ENA);
1022
1023 priv->isr_stats.rx++;
1024 }
1025
1026 /* This "Tx" DMA channel is used only for loading uCode */
1027 if (inta & CSR_INT_BIT_FH_TX) {
1028 iwl_write32(priv, CSR_FH_INT_STATUS, CSR_FH_INT_TX_MASK);
1029 IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
1030 priv->isr_stats.tx++;
1031 handled |= CSR_INT_BIT_FH_TX;
1032 /* Wake up uCode load routine, now that load is complete */
1033 priv->ucode_write_complete = 1;
1034 wake_up_interruptible(&priv->wait_command_queue);
1035 }
1036
1037 if (inta & ~handled) {
1038 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1039 priv->isr_stats.unhandled++;
1040 }
1041
1042 if (inta & ~(priv->inta_mask)) {
1043 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
1044 inta & ~priv->inta_mask);
1045 }
1046
1047 /* Re-enable all interrupts */
1048 /* only Re-enable if disabled by irq */
1049 if (test_bit(STATUS_INT_ENABLED, &priv->status))
1050 iwl_enable_interrupts(priv);
1051 /* Re-enable RF_KILL if it occurred */
1052 else if (handled & CSR_INT_BIT_RF_KILL)
1053 iwl_enable_rfkill_int(priv);
1054 }
1055
1056 /*****************************************************************************
1057 *
1058 * sysfs attributes
1059 *
1060 *****************************************************************************/
1061
1062 #ifdef CONFIG_IWLWIFI_DEBUG
1063
1064 /*
1065 * The following adds a new attribute to the sysfs representation
1066 * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
1067 * used for controlling the debug level.
1068 *
1069 * See the level definitions in iwl for details.
1070 *
1071 * The debug_level being managed using sysfs below is a per device debug
1072 * level that is used instead of the global debug level if it (the per
1073 * device debug level) is set.
1074 */
1075 static ssize_t show_debug_level(struct device *d,
1076 struct device_attribute *attr, char *buf)
1077 {
1078 struct iwl_priv *priv = dev_get_drvdata(d);
1079 return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv));
1080 }
1081 static ssize_t store_debug_level(struct device *d,
1082 struct device_attribute *attr,
1083 const char *buf, size_t count)
1084 {
1085 struct iwl_priv *priv = dev_get_drvdata(d);
1086 unsigned long val;
1087 int ret;
1088
1089 ret = strict_strtoul(buf, 0, &val);
1090 if (ret)
1091 IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf);
1092 else {
1093 priv->debug_level = val;
1094 if (iwl_alloc_traffic_mem(priv))
1095 IWL_ERR(priv,
1096 "Not enough memory to generate traffic log\n");
1097 }
1098 return strnlen(buf, count);
1099 }
1100
1101 static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
1102 show_debug_level, store_debug_level);
1103
1104
1105 #endif /* CONFIG_IWLWIFI_DEBUG */
1106
1107
1108 static ssize_t show_temperature(struct device *d,
1109 struct device_attribute *attr, char *buf)
1110 {
1111 struct iwl_priv *priv = dev_get_drvdata(d);
1112
1113 if (!iwl_is_alive(priv))
1114 return -EAGAIN;
1115
1116 return sprintf(buf, "%d\n", priv->temperature);
1117 }
1118
1119 static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
1120
1121 static ssize_t show_tx_power(struct device *d,
1122 struct device_attribute *attr, char *buf)
1123 {
1124 struct iwl_priv *priv = dev_get_drvdata(d);
1125
1126 if (!iwl_is_ready_rf(priv))
1127 return sprintf(buf, "off\n");
1128 else
1129 return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
1130 }
1131
1132 static ssize_t store_tx_power(struct device *d,
1133 struct device_attribute *attr,
1134 const char *buf, size_t count)
1135 {
1136 struct iwl_priv *priv = dev_get_drvdata(d);
1137 unsigned long val;
1138 int ret;
1139
1140 ret = strict_strtoul(buf, 10, &val);
1141 if (ret)
1142 IWL_INFO(priv, "%s is not in decimal form.\n", buf);
1143 else {
1144 ret = iwl_set_tx_power(priv, val, false);
1145 if (ret)
1146 IWL_ERR(priv, "failed setting tx power (0x%d).\n",
1147 ret);
1148 else
1149 ret = count;
1150 }
1151 return ret;
1152 }
1153
1154 static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
1155
1156 static struct attribute *iwl_sysfs_entries[] = {
1157 &dev_attr_temperature.attr,
1158 &dev_attr_tx_power.attr,
1159 #ifdef CONFIG_IWLWIFI_DEBUG
1160 &dev_attr_debug_level.attr,
1161 #endif
1162 NULL
1163 };
1164
1165 static struct attribute_group iwl_attribute_group = {
1166 .name = NULL, /* put in device directory */
1167 .attrs = iwl_sysfs_entries,
1168 };
1169
1170 /******************************************************************************
1171 *
1172 * uCode download functions
1173 *
1174 ******************************************************************************/
1175
1176 static void iwl_free_fw_desc(struct pci_dev *pci_dev, struct fw_desc *desc)
1177 {
1178 if (desc->v_addr)
1179 dma_free_coherent(&pci_dev->dev, desc->len,
1180 desc->v_addr, desc->p_addr);
1181 desc->v_addr = NULL;
1182 desc->len = 0;
1183 }
1184
1185 static void iwl_free_fw_img(struct pci_dev *pci_dev, struct fw_img *img)
1186 {
1187 iwl_free_fw_desc(pci_dev, &img->code);
1188 iwl_free_fw_desc(pci_dev, &img->data);
1189 }
1190
1191 static int iwl_alloc_fw_desc(struct pci_dev *pci_dev, struct fw_desc *desc,
1192 const void *data, size_t len)
1193 {
1194 if (!len) {
1195 desc->v_addr = NULL;
1196 return -EINVAL;
1197 }
1198
1199 desc->v_addr = dma_alloc_coherent(&pci_dev->dev, len,
1200 &desc->p_addr, GFP_KERNEL);
1201 if (!desc->v_addr)
1202 return -ENOMEM;
1203 desc->len = len;
1204 memcpy(desc->v_addr, data, len);
1205 return 0;
1206 }
1207
1208 static void iwl_dealloc_ucode_pci(struct iwl_priv *priv)
1209 {
1210 iwl_free_fw_img(priv->pci_dev, &priv->ucode_rt);
1211 iwl_free_fw_img(priv->pci_dev, &priv->ucode_init);
1212 }
1213
1214 struct iwlagn_ucode_capabilities {
1215 u32 max_probe_length;
1216 u32 standard_phy_calibration_size;
1217 u32 flags;
1218 };
1219
1220 static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context);
1221 static int iwl_mac_setup_register(struct iwl_priv *priv,
1222 struct iwlagn_ucode_capabilities *capa);
1223
1224 #define UCODE_EXPERIMENTAL_INDEX 100
1225 #define UCODE_EXPERIMENTAL_TAG "exp"
1226
1227 static int __must_check iwl_request_firmware(struct iwl_priv *priv, bool first)
1228 {
1229 const char *name_pre = priv->cfg->fw_name_pre;
1230 char tag[8];
1231
1232 if (first) {
1233 #ifdef CONFIG_IWLWIFI_DEBUG_EXPERIMENTAL_UCODE
1234 priv->fw_index = UCODE_EXPERIMENTAL_INDEX;
1235 strcpy(tag, UCODE_EXPERIMENTAL_TAG);
1236 } else if (priv->fw_index == UCODE_EXPERIMENTAL_INDEX) {
1237 #endif
1238 priv->fw_index = priv->cfg->ucode_api_max;
1239 sprintf(tag, "%d", priv->fw_index);
1240 } else {
1241 priv->fw_index--;
1242 sprintf(tag, "%d", priv->fw_index);
1243 }
1244
1245 if (priv->fw_index < priv->cfg->ucode_api_min) {
1246 IWL_ERR(priv, "no suitable firmware found!\n");
1247 return -ENOENT;
1248 }
1249
1250 sprintf(priv->firmware_name, "%s%s%s", name_pre, tag, ".ucode");
1251
1252 IWL_DEBUG_INFO(priv, "attempting to load firmware %s'%s'\n",
1253 (priv->fw_index == UCODE_EXPERIMENTAL_INDEX)
1254 ? "EXPERIMENTAL " : "",
1255 priv->firmware_name);
1256
1257 return request_firmware_nowait(THIS_MODULE, 1, priv->firmware_name,
1258 &priv->pci_dev->dev, GFP_KERNEL, priv,
1259 iwl_ucode_callback);
1260 }
1261
1262 struct iwlagn_firmware_pieces {
1263 const void *inst, *data, *init, *init_data;
1264 size_t inst_size, data_size, init_size, init_data_size;
1265
1266 u32 build;
1267
1268 u32 init_evtlog_ptr, init_evtlog_size, init_errlog_ptr;
1269 u32 inst_evtlog_ptr, inst_evtlog_size, inst_errlog_ptr;
1270 };
1271
1272 static int iwlagn_load_legacy_firmware(struct iwl_priv *priv,
1273 const struct firmware *ucode_raw,
1274 struct iwlagn_firmware_pieces *pieces)
1275 {
1276 struct iwl_ucode_header *ucode = (void *)ucode_raw->data;
1277 u32 api_ver, hdr_size;
1278 const u8 *src;
1279
1280 priv->ucode_ver = le32_to_cpu(ucode->ver);
1281 api_ver = IWL_UCODE_API(priv->ucode_ver);
1282
1283 switch (api_ver) {
1284 default:
1285 hdr_size = 28;
1286 if (ucode_raw->size < hdr_size) {
1287 IWL_ERR(priv, "File size too small!\n");
1288 return -EINVAL;
1289 }
1290 pieces->build = le32_to_cpu(ucode->u.v2.build);
1291 pieces->inst_size = le32_to_cpu(ucode->u.v2.inst_size);
1292 pieces->data_size = le32_to_cpu(ucode->u.v2.data_size);
1293 pieces->init_size = le32_to_cpu(ucode->u.v2.init_size);
1294 pieces->init_data_size = le32_to_cpu(ucode->u.v2.init_data_size);
1295 src = ucode->u.v2.data;
1296 break;
1297 case 0:
1298 case 1:
1299 case 2:
1300 hdr_size = 24;
1301 if (ucode_raw->size < hdr_size) {
1302 IWL_ERR(priv, "File size too small!\n");
1303 return -EINVAL;
1304 }
1305 pieces->build = 0;
1306 pieces->inst_size = le32_to_cpu(ucode->u.v1.inst_size);
1307 pieces->data_size = le32_to_cpu(ucode->u.v1.data_size);
1308 pieces->init_size = le32_to_cpu(ucode->u.v1.init_size);
1309 pieces->init_data_size = le32_to_cpu(ucode->u.v1.init_data_size);
1310 src = ucode->u.v1.data;
1311 break;
1312 }
1313
1314 /* Verify size of file vs. image size info in file's header */
1315 if (ucode_raw->size != hdr_size + pieces->inst_size +
1316 pieces->data_size + pieces->init_size +
1317 pieces->init_data_size) {
1318
1319 IWL_ERR(priv,
1320 "uCode file size %d does not match expected size\n",
1321 (int)ucode_raw->size);
1322 return -EINVAL;
1323 }
1324
1325 pieces->inst = src;
1326 src += pieces->inst_size;
1327 pieces->data = src;
1328 src += pieces->data_size;
1329 pieces->init = src;
1330 src += pieces->init_size;
1331 pieces->init_data = src;
1332 src += pieces->init_data_size;
1333
1334 return 0;
1335 }
1336
1337 static int iwlagn_wanted_ucode_alternative = 1;
1338
1339 static int iwlagn_load_firmware(struct iwl_priv *priv,
1340 const struct firmware *ucode_raw,
1341 struct iwlagn_firmware_pieces *pieces,
1342 struct iwlagn_ucode_capabilities *capa)
1343 {
1344 struct iwl_tlv_ucode_header *ucode = (void *)ucode_raw->data;
1345 struct iwl_ucode_tlv *tlv;
1346 size_t len = ucode_raw->size;
1347 const u8 *data;
1348 int wanted_alternative = iwlagn_wanted_ucode_alternative, tmp;
1349 u64 alternatives;
1350 u32 tlv_len;
1351 enum iwl_ucode_tlv_type tlv_type;
1352 const u8 *tlv_data;
1353
1354 if (len < sizeof(*ucode)) {
1355 IWL_ERR(priv, "uCode has invalid length: %zd\n", len);
1356 return -EINVAL;
1357 }
1358
1359 if (ucode->magic != cpu_to_le32(IWL_TLV_UCODE_MAGIC)) {
1360 IWL_ERR(priv, "invalid uCode magic: 0X%x\n",
1361 le32_to_cpu(ucode->magic));
1362 return -EINVAL;
1363 }
1364
1365 /*
1366 * Check which alternatives are present, and "downgrade"
1367 * when the chosen alternative is not present, warning
1368 * the user when that happens. Some files may not have
1369 * any alternatives, so don't warn in that case.
1370 */
1371 alternatives = le64_to_cpu(ucode->alternatives);
1372 tmp = wanted_alternative;
1373 if (wanted_alternative > 63)
1374 wanted_alternative = 63;
1375 while (wanted_alternative && !(alternatives & BIT(wanted_alternative)))
1376 wanted_alternative--;
1377 if (wanted_alternative && wanted_alternative != tmp)
1378 IWL_WARN(priv,
1379 "uCode alternative %d not available, choosing %d\n",
1380 tmp, wanted_alternative);
1381
1382 priv->ucode_ver = le32_to_cpu(ucode->ver);
1383 pieces->build = le32_to_cpu(ucode->build);
1384 data = ucode->data;
1385
1386 len -= sizeof(*ucode);
1387
1388 while (len >= sizeof(*tlv)) {
1389 u16 tlv_alt;
1390
1391 len -= sizeof(*tlv);
1392 tlv = (void *)data;
1393
1394 tlv_len = le32_to_cpu(tlv->length);
1395 tlv_type = le16_to_cpu(tlv->type);
1396 tlv_alt = le16_to_cpu(tlv->alternative);
1397 tlv_data = tlv->data;
1398
1399 if (len < tlv_len) {
1400 IWL_ERR(priv, "invalid TLV len: %zd/%u\n",
1401 len, tlv_len);
1402 return -EINVAL;
1403 }
1404 len -= ALIGN(tlv_len, 4);
1405 data += sizeof(*tlv) + ALIGN(tlv_len, 4);
1406
1407 /*
1408 * Alternative 0 is always valid.
1409 *
1410 * Skip alternative TLVs that are not selected.
1411 */
1412 if (tlv_alt != 0 && tlv_alt != wanted_alternative)
1413 continue;
1414
1415 switch (tlv_type) {
1416 case IWL_UCODE_TLV_INST:
1417 pieces->inst = tlv_data;
1418 pieces->inst_size = tlv_len;
1419 break;
1420 case IWL_UCODE_TLV_DATA:
1421 pieces->data = tlv_data;
1422 pieces->data_size = tlv_len;
1423 break;
1424 case IWL_UCODE_TLV_INIT:
1425 pieces->init = tlv_data;
1426 pieces->init_size = tlv_len;
1427 break;
1428 case IWL_UCODE_TLV_INIT_DATA:
1429 pieces->init_data = tlv_data;
1430 pieces->init_data_size = tlv_len;
1431 break;
1432 case IWL_UCODE_TLV_BOOT:
1433 IWL_ERR(priv, "Found unexpected BOOT ucode\n");
1434 break;
1435 case IWL_UCODE_TLV_PROBE_MAX_LEN:
1436 if (tlv_len != sizeof(u32))
1437 goto invalid_tlv_len;
1438 capa->max_probe_length =
1439 le32_to_cpup((__le32 *)tlv_data);
1440 break;
1441 case IWL_UCODE_TLV_PAN:
1442 if (tlv_len)
1443 goto invalid_tlv_len;
1444 capa->flags |= IWL_UCODE_TLV_FLAGS_PAN;
1445 break;
1446 case IWL_UCODE_TLV_FLAGS:
1447 /* must be at least one u32 */
1448 if (tlv_len < sizeof(u32))
1449 goto invalid_tlv_len;
1450 /* and a proper number of u32s */
1451 if (tlv_len % sizeof(u32))
1452 goto invalid_tlv_len;
1453 /*
1454 * This driver only reads the first u32 as
1455 * right now no more features are defined,
1456 * if that changes then either the driver
1457 * will not work with the new firmware, or
1458 * it'll not take advantage of new features.
1459 */
1460 capa->flags = le32_to_cpup((__le32 *)tlv_data);
1461 break;
1462 case IWL_UCODE_TLV_INIT_EVTLOG_PTR:
1463 if (tlv_len != sizeof(u32))
1464 goto invalid_tlv_len;
1465 pieces->init_evtlog_ptr =
1466 le32_to_cpup((__le32 *)tlv_data);
1467 break;
1468 case IWL_UCODE_TLV_INIT_EVTLOG_SIZE:
1469 if (tlv_len != sizeof(u32))
1470 goto invalid_tlv_len;
1471 pieces->init_evtlog_size =
1472 le32_to_cpup((__le32 *)tlv_data);
1473 break;
1474 case IWL_UCODE_TLV_INIT_ERRLOG_PTR:
1475 if (tlv_len != sizeof(u32))
1476 goto invalid_tlv_len;
1477 pieces->init_errlog_ptr =
1478 le32_to_cpup((__le32 *)tlv_data);
1479 break;
1480 case IWL_UCODE_TLV_RUNT_EVTLOG_PTR:
1481 if (tlv_len != sizeof(u32))
1482 goto invalid_tlv_len;
1483 pieces->inst_evtlog_ptr =
1484 le32_to_cpup((__le32 *)tlv_data);
1485 break;
1486 case IWL_UCODE_TLV_RUNT_EVTLOG_SIZE:
1487 if (tlv_len != sizeof(u32))
1488 goto invalid_tlv_len;
1489 pieces->inst_evtlog_size =
1490 le32_to_cpup((__le32 *)tlv_data);
1491 break;
1492 case IWL_UCODE_TLV_RUNT_ERRLOG_PTR:
1493 if (tlv_len != sizeof(u32))
1494 goto invalid_tlv_len;
1495 pieces->inst_errlog_ptr =
1496 le32_to_cpup((__le32 *)tlv_data);
1497 break;
1498 case IWL_UCODE_TLV_ENHANCE_SENS_TBL:
1499 if (tlv_len)
1500 goto invalid_tlv_len;
1501 priv->enhance_sensitivity_table = true;
1502 break;
1503 case IWL_UCODE_TLV_PHY_CALIBRATION_SIZE:
1504 if (tlv_len != sizeof(u32))
1505 goto invalid_tlv_len;
1506 capa->standard_phy_calibration_size =
1507 le32_to_cpup((__le32 *)tlv_data);
1508 break;
1509 default:
1510 IWL_DEBUG_INFO(priv, "unknown TLV: %d\n", tlv_type);
1511 break;
1512 }
1513 }
1514
1515 if (len) {
1516 IWL_ERR(priv, "invalid TLV after parsing: %zd\n", len);
1517 iwl_print_hex_dump(priv, IWL_DL_FW, (u8 *)data, len);
1518 return -EINVAL;
1519 }
1520
1521 return 0;
1522
1523 invalid_tlv_len:
1524 IWL_ERR(priv, "TLV %d has invalid size: %u\n", tlv_type, tlv_len);
1525 iwl_print_hex_dump(priv, IWL_DL_FW, tlv_data, tlv_len);
1526
1527 return -EINVAL;
1528 }
1529
1530 /**
1531 * iwl_ucode_callback - callback when firmware was loaded
1532 *
1533 * If loaded successfully, copies the firmware into buffers
1534 * for the card to fetch (via DMA).
1535 */
1536 static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context)
1537 {
1538 struct iwl_priv *priv = context;
1539 struct iwl_ucode_header *ucode;
1540 int err;
1541 struct iwlagn_firmware_pieces pieces;
1542 const unsigned int api_max = priv->cfg->ucode_api_max;
1543 const unsigned int api_min = priv->cfg->ucode_api_min;
1544 u32 api_ver;
1545 char buildstr[25];
1546 u32 build;
1547 struct iwlagn_ucode_capabilities ucode_capa = {
1548 .max_probe_length = 200,
1549 .standard_phy_calibration_size =
1550 IWL_DEFAULT_STANDARD_PHY_CALIBRATE_TBL_SIZE,
1551 };
1552
1553 memset(&pieces, 0, sizeof(pieces));
1554
1555 if (!ucode_raw) {
1556 if (priv->fw_index <= priv->cfg->ucode_api_max)
1557 IWL_ERR(priv,
1558 "request for firmware file '%s' failed.\n",
1559 priv->firmware_name);
1560 goto try_again;
1561 }
1562
1563 IWL_DEBUG_INFO(priv, "Loaded firmware file '%s' (%zd bytes).\n",
1564 priv->firmware_name, ucode_raw->size);
1565
1566 /* Make sure that we got at least the API version number */
1567 if (ucode_raw->size < 4) {
1568 IWL_ERR(priv, "File size way too small!\n");
1569 goto try_again;
1570 }
1571
1572 /* Data from ucode file: header followed by uCode images */
1573 ucode = (struct iwl_ucode_header *)ucode_raw->data;
1574
1575 if (ucode->ver)
1576 err = iwlagn_load_legacy_firmware(priv, ucode_raw, &pieces);
1577 else
1578 err = iwlagn_load_firmware(priv, ucode_raw, &pieces,
1579 &ucode_capa);
1580
1581 if (err)
1582 goto try_again;
1583
1584 api_ver = IWL_UCODE_API(priv->ucode_ver);
1585 build = pieces.build;
1586
1587 /*
1588 * api_ver should match the api version forming part of the
1589 * firmware filename ... but we don't check for that and only rely
1590 * on the API version read from firmware header from here on forward
1591 */
1592 /* no api version check required for experimental uCode */
1593 if (priv->fw_index != UCODE_EXPERIMENTAL_INDEX) {
1594 if (api_ver < api_min || api_ver > api_max) {
1595 IWL_ERR(priv,
1596 "Driver unable to support your firmware API. "
1597 "Driver supports v%u, firmware is v%u.\n",
1598 api_max, api_ver);
1599 goto try_again;
1600 }
1601
1602 if (api_ver != api_max)
1603 IWL_ERR(priv,
1604 "Firmware has old API version. Expected v%u, "
1605 "got v%u. New firmware can be obtained "
1606 "from http://www.intellinuxwireless.org.\n",
1607 api_max, api_ver);
1608 }
1609
1610 if (build)
1611 sprintf(buildstr, " build %u%s", build,
1612 (priv->fw_index == UCODE_EXPERIMENTAL_INDEX)
1613 ? " (EXP)" : "");
1614 else
1615 buildstr[0] = '\0';
1616
1617 IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u%s\n",
1618 IWL_UCODE_MAJOR(priv->ucode_ver),
1619 IWL_UCODE_MINOR(priv->ucode_ver),
1620 IWL_UCODE_API(priv->ucode_ver),
1621 IWL_UCODE_SERIAL(priv->ucode_ver),
1622 buildstr);
1623
1624 snprintf(priv->hw->wiphy->fw_version,
1625 sizeof(priv->hw->wiphy->fw_version),
1626 "%u.%u.%u.%u%s",
1627 IWL_UCODE_MAJOR(priv->ucode_ver),
1628 IWL_UCODE_MINOR(priv->ucode_ver),
1629 IWL_UCODE_API(priv->ucode_ver),
1630 IWL_UCODE_SERIAL(priv->ucode_ver),
1631 buildstr);
1632
1633 /*
1634 * For any of the failures below (before allocating pci memory)
1635 * we will try to load a version with a smaller API -- maybe the
1636 * user just got a corrupted version of the latest API.
1637 */
1638
1639 IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
1640 priv->ucode_ver);
1641 IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %Zd\n",
1642 pieces.inst_size);
1643 IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %Zd\n",
1644 pieces.data_size);
1645 IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %Zd\n",
1646 pieces.init_size);
1647 IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %Zd\n",
1648 pieces.init_data_size);
1649
1650 /* Verify that uCode images will fit in card's SRAM */
1651 if (pieces.inst_size > priv->hw_params.max_inst_size) {
1652 IWL_ERR(priv, "uCode instr len %Zd too large to fit in\n",
1653 pieces.inst_size);
1654 goto try_again;
1655 }
1656
1657 if (pieces.data_size > priv->hw_params.max_data_size) {
1658 IWL_ERR(priv, "uCode data len %Zd too large to fit in\n",
1659 pieces.data_size);
1660 goto try_again;
1661 }
1662
1663 if (pieces.init_size > priv->hw_params.max_inst_size) {
1664 IWL_ERR(priv, "uCode init instr len %Zd too large to fit in\n",
1665 pieces.init_size);
1666 goto try_again;
1667 }
1668
1669 if (pieces.init_data_size > priv->hw_params.max_data_size) {
1670 IWL_ERR(priv, "uCode init data len %Zd too large to fit in\n",
1671 pieces.init_data_size);
1672 goto try_again;
1673 }
1674
1675 /* Allocate ucode buffers for card's bus-master loading ... */
1676
1677 /* Runtime instructions and 2 copies of data:
1678 * 1) unmodified from disk
1679 * 2) backup cache for save/restore during power-downs */
1680 if (iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_rt.code,
1681 pieces.inst, pieces.inst_size))
1682 goto err_pci_alloc;
1683 if (iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_rt.data,
1684 pieces.data, pieces.data_size))
1685 goto err_pci_alloc;
1686
1687 /* Initialization instructions and data */
1688 if (pieces.init_size && pieces.init_data_size) {
1689 if (iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init.code,
1690 pieces.init, pieces.init_size))
1691 goto err_pci_alloc;
1692 if (iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init.data,
1693 pieces.init_data, pieces.init_data_size))
1694 goto err_pci_alloc;
1695 }
1696
1697 /* Now that we can no longer fail, copy information */
1698
1699 /*
1700 * The (size - 16) / 12 formula is based on the information recorded
1701 * for each event, which is of mode 1 (including timestamp) for all
1702 * new microcodes that include this information.
1703 */
1704 priv->_agn.init_evtlog_ptr = pieces.init_evtlog_ptr;
1705 if (pieces.init_evtlog_size)
1706 priv->_agn.init_evtlog_size = (pieces.init_evtlog_size - 16)/12;
1707 else
1708 priv->_agn.init_evtlog_size =
1709 priv->cfg->base_params->max_event_log_size;
1710 priv->_agn.init_errlog_ptr = pieces.init_errlog_ptr;
1711 priv->_agn.inst_evtlog_ptr = pieces.inst_evtlog_ptr;
1712 if (pieces.inst_evtlog_size)
1713 priv->_agn.inst_evtlog_size = (pieces.inst_evtlog_size - 16)/12;
1714 else
1715 priv->_agn.inst_evtlog_size =
1716 priv->cfg->base_params->max_event_log_size;
1717 priv->_agn.inst_errlog_ptr = pieces.inst_errlog_ptr;
1718
1719 if (ucode_capa.flags & IWL_UCODE_TLV_FLAGS_PAN) {
1720 priv->valid_contexts |= BIT(IWL_RXON_CTX_PAN);
1721 priv->sta_key_max_num = STA_KEY_MAX_NUM_PAN;
1722 } else
1723 priv->sta_key_max_num = STA_KEY_MAX_NUM;
1724
1725 if (priv->valid_contexts != BIT(IWL_RXON_CTX_BSS))
1726 priv->cmd_queue = IWL_IPAN_CMD_QUEUE_NUM;
1727 else
1728 priv->cmd_queue = IWL_DEFAULT_CMD_QUEUE_NUM;
1729
1730 /*
1731 * figure out the offset of chain noise reset and gain commands
1732 * base on the size of standard phy calibration commands table size
1733 */
1734 if (ucode_capa.standard_phy_calibration_size >
1735 IWL_MAX_PHY_CALIBRATE_TBL_SIZE)
1736 ucode_capa.standard_phy_calibration_size =
1737 IWL_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE;
1738
1739 priv->_agn.phy_calib_chain_noise_reset_cmd =
1740 ucode_capa.standard_phy_calibration_size;
1741 priv->_agn.phy_calib_chain_noise_gain_cmd =
1742 ucode_capa.standard_phy_calibration_size + 1;
1743
1744 /**************************************************
1745 * This is still part of probe() in a sense...
1746 *
1747 * 9. Setup and register with mac80211 and debugfs
1748 **************************************************/
1749 err = iwl_mac_setup_register(priv, &ucode_capa);
1750 if (err)
1751 goto out_unbind;
1752
1753 err = iwl_dbgfs_register(priv, DRV_NAME);
1754 if (err)
1755 IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
1756
1757 err = sysfs_create_group(&priv->pci_dev->dev.kobj,
1758 &iwl_attribute_group);
1759 if (err) {
1760 IWL_ERR(priv, "failed to create sysfs device attributes\n");
1761 goto out_unbind;
1762 }
1763
1764 /* We have our copies now, allow OS release its copies */
1765 release_firmware(ucode_raw);
1766 complete(&priv->_agn.firmware_loading_complete);
1767 return;
1768
1769 try_again:
1770 /* try next, if any */
1771 if (iwl_request_firmware(priv, false))
1772 goto out_unbind;
1773 release_firmware(ucode_raw);
1774 return;
1775
1776 err_pci_alloc:
1777 IWL_ERR(priv, "failed to allocate pci memory\n");
1778 iwl_dealloc_ucode_pci(priv);
1779 out_unbind:
1780 complete(&priv->_agn.firmware_loading_complete);
1781 device_release_driver(&priv->pci_dev->dev);
1782 release_firmware(ucode_raw);
1783 }
1784
1785 static const char *desc_lookup_text[] = {
1786 "OK",
1787 "FAIL",
1788 "BAD_PARAM",
1789 "BAD_CHECKSUM",
1790 "NMI_INTERRUPT_WDG",
1791 "SYSASSERT",
1792 "FATAL_ERROR",
1793 "BAD_COMMAND",
1794 "HW_ERROR_TUNE_LOCK",
1795 "HW_ERROR_TEMPERATURE",
1796 "ILLEGAL_CHAN_FREQ",
1797 "VCC_NOT_STABLE",
1798 "FH_ERROR",
1799 "NMI_INTERRUPT_HOST",
1800 "NMI_INTERRUPT_ACTION_PT",
1801 "NMI_INTERRUPT_UNKNOWN",
1802 "UCODE_VERSION_MISMATCH",
1803 "HW_ERROR_ABS_LOCK",
1804 "HW_ERROR_CAL_LOCK_FAIL",
1805 "NMI_INTERRUPT_INST_ACTION_PT",
1806 "NMI_INTERRUPT_DATA_ACTION_PT",
1807 "NMI_TRM_HW_ER",
1808 "NMI_INTERRUPT_TRM",
1809 "NMI_INTERRUPT_BREAK_POINT"
1810 "DEBUG_0",
1811 "DEBUG_1",
1812 "DEBUG_2",
1813 "DEBUG_3",
1814 };
1815
1816 static struct { char *name; u8 num; } advanced_lookup[] = {
1817 { "NMI_INTERRUPT_WDG", 0x34 },
1818 { "SYSASSERT", 0x35 },
1819 { "UCODE_VERSION_MISMATCH", 0x37 },
1820 { "BAD_COMMAND", 0x38 },
1821 { "NMI_INTERRUPT_DATA_ACTION_PT", 0x3C },
1822 { "FATAL_ERROR", 0x3D },
1823 { "NMI_TRM_HW_ERR", 0x46 },
1824 { "NMI_INTERRUPT_TRM", 0x4C },
1825 { "NMI_INTERRUPT_BREAK_POINT", 0x54 },
1826 { "NMI_INTERRUPT_WDG_RXF_FULL", 0x5C },
1827 { "NMI_INTERRUPT_WDG_NO_RBD_RXF_FULL", 0x64 },
1828 { "NMI_INTERRUPT_HOST", 0x66 },
1829 { "NMI_INTERRUPT_ACTION_PT", 0x7C },
1830 { "NMI_INTERRUPT_UNKNOWN", 0x84 },
1831 { "NMI_INTERRUPT_INST_ACTION_PT", 0x86 },
1832 { "ADVANCED_SYSASSERT", 0 },
1833 };
1834
1835 static const char *desc_lookup(u32 num)
1836 {
1837 int i;
1838 int max = ARRAY_SIZE(desc_lookup_text);
1839
1840 if (num < max)
1841 return desc_lookup_text[num];
1842
1843 max = ARRAY_SIZE(advanced_lookup) - 1;
1844 for (i = 0; i < max; i++) {
1845 if (advanced_lookup[i].num == num)
1846 break;;
1847 }
1848 return advanced_lookup[i].name;
1849 }
1850
1851 #define ERROR_START_OFFSET (1 * sizeof(u32))
1852 #define ERROR_ELEM_SIZE (7 * sizeof(u32))
1853
1854 void iwl_dump_nic_error_log(struct iwl_priv *priv)
1855 {
1856 u32 data2, line;
1857 u32 desc, time, count, base, data1;
1858 u32 blink1, blink2, ilink1, ilink2;
1859 u32 pc, hcmd;
1860 struct iwl_error_event_table table;
1861
1862 base = priv->device_pointers.error_event_table;
1863 if (priv->ucode_type == UCODE_SUBTYPE_INIT) {
1864 if (!base)
1865 base = priv->_agn.init_errlog_ptr;
1866 } else {
1867 if (!base)
1868 base = priv->_agn.inst_errlog_ptr;
1869 }
1870
1871 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
1872 IWL_ERR(priv,
1873 "Not valid error log pointer 0x%08X for %s uCode\n",
1874 base,
1875 (priv->ucode_type == UCODE_SUBTYPE_INIT)
1876 ? "Init" : "RT");
1877 return;
1878 }
1879
1880 iwl_read_targ_mem_words(priv, base, &table, sizeof(table));
1881
1882 count = table.valid;
1883
1884 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
1885 IWL_ERR(priv, "Start IWL Error Log Dump:\n");
1886 IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
1887 priv->status, count);
1888 }
1889
1890 desc = table.error_id;
1891 priv->isr_stats.err_code = desc;
1892 pc = table.pc;
1893 blink1 = table.blink1;
1894 blink2 = table.blink2;
1895 ilink1 = table.ilink1;
1896 ilink2 = table.ilink2;
1897 data1 = table.data1;
1898 data2 = table.data2;
1899 line = table.line;
1900 time = table.tsf_low;
1901 hcmd = table.hcmd;
1902
1903 trace_iwlwifi_dev_ucode_error(priv, desc, time, data1, data2, line,
1904 blink1, blink2, ilink1, ilink2);
1905
1906 IWL_ERR(priv, "Desc Time "
1907 "data1 data2 line\n");
1908 IWL_ERR(priv, "%-28s (0x%04X) %010u 0x%08X 0x%08X %u\n",
1909 desc_lookup(desc), desc, time, data1, data2, line);
1910 IWL_ERR(priv, "pc blink1 blink2 ilink1 ilink2 hcmd\n");
1911 IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X 0x%05X 0x%05X\n",
1912 pc, blink1, blink2, ilink1, ilink2, hcmd);
1913 }
1914
1915 #define EVENT_START_OFFSET (4 * sizeof(u32))
1916
1917 /**
1918 * iwl_print_event_log - Dump error event log to syslog
1919 *
1920 */
1921 static int iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
1922 u32 num_events, u32 mode,
1923 int pos, char **buf, size_t bufsz)
1924 {
1925 u32 i;
1926 u32 base; /* SRAM byte address of event log header */
1927 u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
1928 u32 ptr; /* SRAM byte address of log data */
1929 u32 ev, time, data; /* event log data */
1930 unsigned long reg_flags;
1931
1932 if (num_events == 0)
1933 return pos;
1934
1935 base = priv->device_pointers.log_event_table;
1936 if (priv->ucode_type == UCODE_SUBTYPE_INIT) {
1937 if (!base)
1938 base = priv->_agn.init_evtlog_ptr;
1939 } else {
1940 if (!base)
1941 base = priv->_agn.inst_evtlog_ptr;
1942 }
1943
1944 if (mode == 0)
1945 event_size = 2 * sizeof(u32);
1946 else
1947 event_size = 3 * sizeof(u32);
1948
1949 ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
1950
1951 /* Make sure device is powered up for SRAM reads */
1952 spin_lock_irqsave(&priv->reg_lock, reg_flags);
1953 iwl_grab_nic_access(priv);
1954
1955 /* Set starting address; reads will auto-increment */
1956 iwl_write32(priv, HBUS_TARG_MEM_RADDR, ptr);
1957 rmb();
1958
1959 /* "time" is actually "data" for mode 0 (no timestamp).
1960 * place event id # at far right for easier visual parsing. */
1961 for (i = 0; i < num_events; i++) {
1962 ev = iwl_read32(priv, HBUS_TARG_MEM_RDAT);
1963 time = iwl_read32(priv, HBUS_TARG_MEM_RDAT);
1964 if (mode == 0) {
1965 /* data, ev */
1966 if (bufsz) {
1967 pos += scnprintf(*buf + pos, bufsz - pos,
1968 "EVT_LOG:0x%08x:%04u\n",
1969 time, ev);
1970 } else {
1971 trace_iwlwifi_dev_ucode_event(priv, 0,
1972 time, ev);
1973 IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n",
1974 time, ev);
1975 }
1976 } else {
1977 data = iwl_read32(priv, HBUS_TARG_MEM_RDAT);
1978 if (bufsz) {
1979 pos += scnprintf(*buf + pos, bufsz - pos,
1980 "EVT_LOGT:%010u:0x%08x:%04u\n",
1981 time, data, ev);
1982 } else {
1983 IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n",
1984 time, data, ev);
1985 trace_iwlwifi_dev_ucode_event(priv, time,
1986 data, ev);
1987 }
1988 }
1989 }
1990
1991 /* Allow device to power down */
1992 iwl_release_nic_access(priv);
1993 spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
1994 return pos;
1995 }
1996
1997 /**
1998 * iwl_print_last_event_logs - Dump the newest # of event log to syslog
1999 */
2000 static int iwl_print_last_event_logs(struct iwl_priv *priv, u32 capacity,
2001 u32 num_wraps, u32 next_entry,
2002 u32 size, u32 mode,
2003 int pos, char **buf, size_t bufsz)
2004 {
2005 /*
2006 * display the newest DEFAULT_LOG_ENTRIES entries
2007 * i.e the entries just before the next ont that uCode would fill.
2008 */
2009 if (num_wraps) {
2010 if (next_entry < size) {
2011 pos = iwl_print_event_log(priv,
2012 capacity - (size - next_entry),
2013 size - next_entry, mode,
2014 pos, buf, bufsz);
2015 pos = iwl_print_event_log(priv, 0,
2016 next_entry, mode,
2017 pos, buf, bufsz);
2018 } else
2019 pos = iwl_print_event_log(priv, next_entry - size,
2020 size, mode, pos, buf, bufsz);
2021 } else {
2022 if (next_entry < size) {
2023 pos = iwl_print_event_log(priv, 0, next_entry,
2024 mode, pos, buf, bufsz);
2025 } else {
2026 pos = iwl_print_event_log(priv, next_entry - size,
2027 size, mode, pos, buf, bufsz);
2028 }
2029 }
2030 return pos;
2031 }
2032
2033 #define DEFAULT_DUMP_EVENT_LOG_ENTRIES (20)
2034
2035 int iwl_dump_nic_event_log(struct iwl_priv *priv, bool full_log,
2036 char **buf, bool display)
2037 {
2038 u32 base; /* SRAM byte address of event log header */
2039 u32 capacity; /* event log capacity in # entries */
2040 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
2041 u32 num_wraps; /* # times uCode wrapped to top of log */
2042 u32 next_entry; /* index of next entry to be written by uCode */
2043 u32 size; /* # entries that we'll print */
2044 u32 logsize;
2045 int pos = 0;
2046 size_t bufsz = 0;
2047
2048 base = priv->device_pointers.log_event_table;
2049 if (priv->ucode_type == UCODE_SUBTYPE_INIT) {
2050 logsize = priv->_agn.init_evtlog_size;
2051 if (!base)
2052 base = priv->_agn.init_evtlog_ptr;
2053 } else {
2054 logsize = priv->_agn.inst_evtlog_size;
2055 if (!base)
2056 base = priv->_agn.inst_evtlog_ptr;
2057 }
2058
2059 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
2060 IWL_ERR(priv,
2061 "Invalid event log pointer 0x%08X for %s uCode\n",
2062 base,
2063 (priv->ucode_type == UCODE_SUBTYPE_INIT)
2064 ? "Init" : "RT");
2065 return -EINVAL;
2066 }
2067
2068 /* event log header */
2069 capacity = iwl_read_targ_mem(priv, base);
2070 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
2071 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
2072 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
2073
2074 if (capacity > logsize) {
2075 IWL_ERR(priv, "Log capacity %d is bogus, limit to %d entries\n",
2076 capacity, logsize);
2077 capacity = logsize;
2078 }
2079
2080 if (next_entry > logsize) {
2081 IWL_ERR(priv, "Log write index %d is bogus, limit to %d\n",
2082 next_entry, logsize);
2083 next_entry = logsize;
2084 }
2085
2086 size = num_wraps ? capacity : next_entry;
2087
2088 /* bail out if nothing in log */
2089 if (size == 0) {
2090 IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
2091 return pos;
2092 }
2093
2094 /* enable/disable bt channel inhibition */
2095 priv->bt_ch_announce = iwlagn_bt_ch_announce;
2096
2097 #ifdef CONFIG_IWLWIFI_DEBUG
2098 if (!(iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) && !full_log)
2099 size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
2100 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
2101 #else
2102 size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
2103 ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
2104 #endif
2105 IWL_ERR(priv, "Start IWL Event Log Dump: display last %u entries\n",
2106 size);
2107
2108 #ifdef CONFIG_IWLWIFI_DEBUG
2109 if (display) {
2110 if (full_log)
2111 bufsz = capacity * 48;
2112 else
2113 bufsz = size * 48;
2114 *buf = kmalloc(bufsz, GFP_KERNEL);
2115 if (!*buf)
2116 return -ENOMEM;
2117 }
2118 if ((iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) || full_log) {
2119 /*
2120 * if uCode has wrapped back to top of log,
2121 * start at the oldest entry,
2122 * i.e the next one that uCode would fill.
2123 */
2124 if (num_wraps)
2125 pos = iwl_print_event_log(priv, next_entry,
2126 capacity - next_entry, mode,
2127 pos, buf, bufsz);
2128 /* (then/else) start at top of log */
2129 pos = iwl_print_event_log(priv, 0,
2130 next_entry, mode, pos, buf, bufsz);
2131 } else
2132 pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
2133 next_entry, size, mode,
2134 pos, buf, bufsz);
2135 #else
2136 pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
2137 next_entry, size, mode,
2138 pos, buf, bufsz);
2139 #endif
2140 return pos;
2141 }
2142
2143 static void iwl_rf_kill_ct_config(struct iwl_priv *priv)
2144 {
2145 struct iwl_ct_kill_config cmd;
2146 struct iwl_ct_kill_throttling_config adv_cmd;
2147 unsigned long flags;
2148 int ret = 0;
2149
2150 spin_lock_irqsave(&priv->lock, flags);
2151 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
2152 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
2153 spin_unlock_irqrestore(&priv->lock, flags);
2154 priv->thermal_throttle.ct_kill_toggle = false;
2155
2156 if (priv->cfg->base_params->support_ct_kill_exit) {
2157 adv_cmd.critical_temperature_enter =
2158 cpu_to_le32(priv->hw_params.ct_kill_threshold);
2159 adv_cmd.critical_temperature_exit =
2160 cpu_to_le32(priv->hw_params.ct_kill_exit_threshold);
2161
2162 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
2163 sizeof(adv_cmd), &adv_cmd);
2164 if (ret)
2165 IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
2166 else
2167 IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
2168 "succeeded, "
2169 "critical temperature enter is %d,"
2170 "exit is %d\n",
2171 priv->hw_params.ct_kill_threshold,
2172 priv->hw_params.ct_kill_exit_threshold);
2173 } else {
2174 cmd.critical_temperature_R =
2175 cpu_to_le32(priv->hw_params.ct_kill_threshold);
2176
2177 ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
2178 sizeof(cmd), &cmd);
2179 if (ret)
2180 IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
2181 else
2182 IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
2183 "succeeded, "
2184 "critical temperature is %d\n",
2185 priv->hw_params.ct_kill_threshold);
2186 }
2187 }
2188
2189 static int iwlagn_send_calib_cfg_rt(struct iwl_priv *priv, u32 cfg)
2190 {
2191 struct iwl_calib_cfg_cmd calib_cfg_cmd;
2192 struct iwl_host_cmd cmd = {
2193 .id = CALIBRATION_CFG_CMD,
2194 .len = sizeof(struct iwl_calib_cfg_cmd),
2195 .data = &calib_cfg_cmd,
2196 };
2197
2198 memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd));
2199 calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL;
2200 calib_cfg_cmd.ucd_calib_cfg.once.start = cpu_to_le32(cfg);
2201
2202 return iwl_send_cmd(priv, &cmd);
2203 }
2204
2205
2206 /**
2207 * iwl_alive_start - called after REPLY_ALIVE notification received
2208 * from protocol/runtime uCode (initialization uCode's
2209 * Alive gets handled by iwl_init_alive_start()).
2210 */
2211 static int iwl_alive_start(struct iwl_priv *priv)
2212 {
2213 int ret = 0;
2214 struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
2215
2216 iwl_reset_ict(priv);
2217
2218 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
2219
2220 /* After the ALIVE response, we can send host commands to the uCode */
2221 set_bit(STATUS_ALIVE, &priv->status);
2222
2223 /* Enable watchdog to monitor the driver tx queues */
2224 iwl_setup_watchdog(priv);
2225
2226 if (iwl_is_rfkill(priv))
2227 return -ERFKILL;
2228
2229 /* download priority table before any calibration request */
2230 if (priv->cfg->bt_params &&
2231 priv->cfg->bt_params->advanced_bt_coexist) {
2232 /* Configure Bluetooth device coexistence support */
2233 priv->bt_valid = IWLAGN_BT_ALL_VALID_MSK;
2234 priv->kill_ack_mask = IWLAGN_BT_KILL_ACK_MASK_DEFAULT;
2235 priv->kill_cts_mask = IWLAGN_BT_KILL_CTS_MASK_DEFAULT;
2236 priv->cfg->ops->hcmd->send_bt_config(priv);
2237 priv->bt_valid = IWLAGN_BT_VALID_ENABLE_FLAGS;
2238 iwlagn_send_prio_tbl(priv);
2239
2240 /* FIXME: w/a to force change uCode BT state machine */
2241 ret = iwlagn_send_bt_env(priv, IWL_BT_COEX_ENV_OPEN,
2242 BT_COEX_PRIO_TBL_EVT_INIT_CALIB2);
2243 if (ret)
2244 return ret;
2245 ret = iwlagn_send_bt_env(priv, IWL_BT_COEX_ENV_CLOSE,
2246 BT_COEX_PRIO_TBL_EVT_INIT_CALIB2);
2247 if (ret)
2248 return ret;
2249 }
2250 if (priv->hw_params.calib_rt_cfg)
2251 iwlagn_send_calib_cfg_rt(priv, priv->hw_params.calib_rt_cfg);
2252
2253 ieee80211_wake_queues(priv->hw);
2254
2255 priv->active_rate = IWL_RATES_MASK;
2256
2257 /* Configure Tx antenna selection based on H/W config */
2258 if (priv->cfg->ops->hcmd->set_tx_ant)
2259 priv->cfg->ops->hcmd->set_tx_ant(priv, priv->cfg->valid_tx_ant);
2260
2261 if (iwl_is_associated_ctx(ctx)) {
2262 struct iwl_rxon_cmd *active_rxon =
2263 (struct iwl_rxon_cmd *)&ctx->active;
2264 /* apply any changes in staging */
2265 ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
2266 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2267 } else {
2268 struct iwl_rxon_context *tmp;
2269 /* Initialize our rx_config data */
2270 for_each_context(priv, tmp)
2271 iwl_connection_init_rx_config(priv, tmp);
2272
2273 if (priv->cfg->ops->hcmd->set_rxon_chain)
2274 priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
2275 }
2276
2277 if (!priv->cfg->bt_params || (priv->cfg->bt_params &&
2278 !priv->cfg->bt_params->advanced_bt_coexist)) {
2279 /*
2280 * default is 2-wire BT coexexistence support
2281 */
2282 priv->cfg->ops->hcmd->send_bt_config(priv);
2283 }
2284
2285 iwl_reset_run_time_calib(priv);
2286
2287 set_bit(STATUS_READY, &priv->status);
2288
2289 /* Configure the adapter for unassociated operation */
2290 ret = iwlcore_commit_rxon(priv, ctx);
2291 if (ret)
2292 return ret;
2293
2294 /* At this point, the NIC is initialized and operational */
2295 iwl_rf_kill_ct_config(priv);
2296
2297 IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
2298
2299 return iwl_power_update_mode(priv, true);
2300 }
2301
2302 static void iwl_cancel_deferred_work(struct iwl_priv *priv);
2303
2304 static void __iwl_down(struct iwl_priv *priv)
2305 {
2306 int exit_pending;
2307
2308 IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
2309
2310 iwl_scan_cancel_timeout(priv, 200);
2311
2312 exit_pending = test_and_set_bit(STATUS_EXIT_PENDING, &priv->status);
2313
2314 /* Stop TX queues watchdog. We need to have STATUS_EXIT_PENDING bit set
2315 * to prevent rearm timer */
2316 del_timer_sync(&priv->watchdog);
2317
2318 iwl_clear_ucode_stations(priv, NULL);
2319 iwl_dealloc_bcast_stations(priv);
2320 iwl_clear_driver_stations(priv);
2321
2322 /* reset BT coex data */
2323 priv->bt_status = 0;
2324 if (priv->cfg->bt_params)
2325 priv->bt_traffic_load =
2326 priv->cfg->bt_params->bt_init_traffic_load;
2327 else
2328 priv->bt_traffic_load = 0;
2329 priv->bt_full_concurrent = false;
2330 priv->bt_ci_compliance = 0;
2331
2332 /* Wipe out the EXIT_PENDING status bit if we are not actually
2333 * exiting the module */
2334 if (!exit_pending)
2335 clear_bit(STATUS_EXIT_PENDING, &priv->status);
2336
2337 if (priv->mac80211_registered)
2338 ieee80211_stop_queues(priv->hw);
2339
2340 /* Clear out all status bits but a few that are stable across reset */
2341 priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
2342 STATUS_RF_KILL_HW |
2343 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
2344 STATUS_GEO_CONFIGURED |
2345 test_bit(STATUS_FW_ERROR, &priv->status) <<
2346 STATUS_FW_ERROR |
2347 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
2348 STATUS_EXIT_PENDING;
2349
2350 iwlagn_stop_device(priv);
2351
2352 dev_kfree_skb(priv->beacon_skb);
2353 priv->beacon_skb = NULL;
2354
2355 /* clear out any free frames */
2356 iwl_clear_free_frames(priv);
2357 }
2358
2359 static void iwl_down(struct iwl_priv *priv)
2360 {
2361 mutex_lock(&priv->mutex);
2362 __iwl_down(priv);
2363 mutex_unlock(&priv->mutex);
2364
2365 iwl_cancel_deferred_work(priv);
2366 }
2367
2368 #define HW_READY_TIMEOUT (50)
2369
2370 /* Note: returns poll_bit return value, which is >= 0 if success */
2371 static int iwl_set_hw_ready(struct iwl_priv *priv)
2372 {
2373 int ret;
2374
2375 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
2376 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
2377
2378 /* See if we got it */
2379 ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
2380 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
2381 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
2382 HW_READY_TIMEOUT);
2383
2384 IWL_DEBUG_INFO(priv, "hardware%s ready\n", ret < 0 ? " not" : "");
2385 return ret;
2386 }
2387
2388 /* Note: returns standard 0/-ERROR code */
2389 int iwl_prepare_card_hw(struct iwl_priv *priv)
2390 {
2391 int ret;
2392
2393 IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter\n");
2394
2395 ret = iwl_set_hw_ready(priv);
2396 if (ret >= 0)
2397 return 0;
2398
2399 /* If HW is not ready, prepare the conditions to check again */
2400 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
2401 CSR_HW_IF_CONFIG_REG_PREPARE);
2402
2403 ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
2404 ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
2405 CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
2406
2407 if (ret < 0)
2408 return ret;
2409
2410 /* HW should be ready by now, check again. */
2411 ret = iwl_set_hw_ready(priv);
2412 if (ret >= 0)
2413 return 0;
2414 return ret;
2415 }
2416
2417 #define MAX_HW_RESTARTS 5
2418
2419 static int __iwl_up(struct iwl_priv *priv)
2420 {
2421 struct iwl_rxon_context *ctx;
2422 int ret;
2423
2424 lockdep_assert_held(&priv->mutex);
2425
2426 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
2427 IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
2428 return -EIO;
2429 }
2430
2431 for_each_context(priv, ctx) {
2432 ret = iwlagn_alloc_bcast_station(priv, ctx);
2433 if (ret) {
2434 iwl_dealloc_bcast_stations(priv);
2435 return ret;
2436 }
2437 }
2438
2439 ret = iwlagn_run_init_ucode(priv);
2440 if (ret) {
2441 IWL_ERR(priv, "Failed to run INIT ucode: %d\n", ret);
2442 goto error;
2443 }
2444
2445 ret = iwlagn_load_ucode_wait_alive(priv,
2446 &priv->ucode_rt,
2447 UCODE_SUBTYPE_REGULAR,
2448 UCODE_SUBTYPE_REGULAR_NEW);
2449 if (ret) {
2450 IWL_ERR(priv, "Failed to start RT ucode: %d\n", ret);
2451 goto error;
2452 }
2453
2454 ret = iwl_alive_start(priv);
2455 if (ret)
2456 goto error;
2457 return 0;
2458
2459 error:
2460 set_bit(STATUS_EXIT_PENDING, &priv->status);
2461 __iwl_down(priv);
2462 clear_bit(STATUS_EXIT_PENDING, &priv->status);
2463
2464 IWL_ERR(priv, "Unable to initialize device.\n");
2465 return ret;
2466 }
2467
2468
2469 /*****************************************************************************
2470 *
2471 * Workqueue callbacks
2472 *
2473 *****************************************************************************/
2474
2475 static void iwl_bg_run_time_calib_work(struct work_struct *work)
2476 {
2477 struct iwl_priv *priv = container_of(work, struct iwl_priv,
2478 run_time_calib_work);
2479
2480 mutex_lock(&priv->mutex);
2481
2482 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
2483 test_bit(STATUS_SCANNING, &priv->status)) {
2484 mutex_unlock(&priv->mutex);
2485 return;
2486 }
2487
2488 if (priv->start_calib) {
2489 iwl_chain_noise_calibration(priv);
2490 iwl_sensitivity_calibration(priv);
2491 }
2492
2493 mutex_unlock(&priv->mutex);
2494 }
2495
2496 static void iwl_bg_restart(struct work_struct *data)
2497 {
2498 struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
2499
2500 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2501 return;
2502
2503 if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
2504 struct iwl_rxon_context *ctx;
2505 bool bt_full_concurrent;
2506 u8 bt_ci_compliance;
2507 u8 bt_load;
2508 u8 bt_status;
2509
2510 mutex_lock(&priv->mutex);
2511 for_each_context(priv, ctx)
2512 ctx->vif = NULL;
2513 priv->is_open = 0;
2514
2515 /*
2516 * __iwl_down() will clear the BT status variables,
2517 * which is correct, but when we restart we really
2518 * want to keep them so restore them afterwards.
2519 *
2520 * The restart process will later pick them up and
2521 * re-configure the hw when we reconfigure the BT
2522 * command.
2523 */
2524 bt_full_concurrent = priv->bt_full_concurrent;
2525 bt_ci_compliance = priv->bt_ci_compliance;
2526 bt_load = priv->bt_traffic_load;
2527 bt_status = priv->bt_status;
2528
2529 __iwl_down(priv);
2530
2531 priv->bt_full_concurrent = bt_full_concurrent;
2532 priv->bt_ci_compliance = bt_ci_compliance;
2533 priv->bt_traffic_load = bt_load;
2534 priv->bt_status = bt_status;
2535
2536 mutex_unlock(&priv->mutex);
2537 iwl_cancel_deferred_work(priv);
2538 ieee80211_restart_hw(priv->hw);
2539 } else {
2540 WARN_ON(1);
2541 }
2542 }
2543
2544 static void iwl_bg_rx_replenish(struct work_struct *data)
2545 {
2546 struct iwl_priv *priv =
2547 container_of(data, struct iwl_priv, rx_replenish);
2548
2549 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2550 return;
2551
2552 mutex_lock(&priv->mutex);
2553 iwlagn_rx_replenish(priv);
2554 mutex_unlock(&priv->mutex);
2555 }
2556
2557 static int iwl_mac_offchannel_tx(struct ieee80211_hw *hw, struct sk_buff *skb,
2558 struct ieee80211_channel *chan,
2559 enum nl80211_channel_type channel_type,
2560 unsigned int wait)
2561 {
2562 struct iwl_priv *priv = hw->priv;
2563 int ret;
2564
2565 /* Not supported if we don't have PAN */
2566 if (!(priv->valid_contexts & BIT(IWL_RXON_CTX_PAN))) {
2567 ret = -EOPNOTSUPP;
2568 goto free;
2569 }
2570
2571 /* Not supported on pre-P2P firmware */
2572 if (!(priv->contexts[IWL_RXON_CTX_PAN].interface_modes &
2573 BIT(NL80211_IFTYPE_P2P_CLIENT))) {
2574 ret = -EOPNOTSUPP;
2575 goto free;
2576 }
2577
2578 mutex_lock(&priv->mutex);
2579
2580 if (!priv->contexts[IWL_RXON_CTX_PAN].is_active) {
2581 /*
2582 * If the PAN context is free, use the normal
2583 * way of doing remain-on-channel offload + TX.
2584 */
2585 ret = 1;
2586 goto out;
2587 }
2588
2589 /* TODO: queue up if scanning? */
2590 if (test_bit(STATUS_SCANNING, &priv->status) ||
2591 priv->_agn.offchan_tx_skb) {
2592 ret = -EBUSY;
2593 goto out;
2594 }
2595
2596 /*
2597 * max_scan_ie_len doesn't include the blank SSID or the header,
2598 * so need to add that again here.
2599 */
2600 if (skb->len > hw->wiphy->max_scan_ie_len + 24 + 2) {
2601 ret = -ENOBUFS;
2602 goto out;
2603 }
2604
2605 priv->_agn.offchan_tx_skb = skb;
2606 priv->_agn.offchan_tx_timeout = wait;
2607 priv->_agn.offchan_tx_chan = chan;
2608
2609 ret = iwl_scan_initiate(priv, priv->contexts[IWL_RXON_CTX_PAN].vif,
2610 IWL_SCAN_OFFCH_TX, chan->band);
2611 if (ret)
2612 priv->_agn.offchan_tx_skb = NULL;
2613 out:
2614 mutex_unlock(&priv->mutex);
2615 free:
2616 if (ret < 0)
2617 kfree_skb(skb);
2618
2619 return ret;
2620 }
2621
2622 static int iwl_mac_offchannel_tx_cancel_wait(struct ieee80211_hw *hw)
2623 {
2624 struct iwl_priv *priv = hw->priv;
2625 int ret;
2626
2627 mutex_lock(&priv->mutex);
2628
2629 if (!priv->_agn.offchan_tx_skb) {
2630 ret = -EINVAL;
2631 goto unlock;
2632 }
2633
2634 priv->_agn.offchan_tx_skb = NULL;
2635
2636 ret = iwl_scan_cancel_timeout(priv, 200);
2637 if (ret)
2638 ret = -EIO;
2639 unlock:
2640 mutex_unlock(&priv->mutex);
2641
2642 return ret;
2643 }
2644
2645 /*****************************************************************************
2646 *
2647 * mac80211 entry point functions
2648 *
2649 *****************************************************************************/
2650
2651 /*
2652 * Not a mac80211 entry point function, but it fits in with all the
2653 * other mac80211 functions grouped here.
2654 */
2655 static int iwl_mac_setup_register(struct iwl_priv *priv,
2656 struct iwlagn_ucode_capabilities *capa)
2657 {
2658 int ret;
2659 struct ieee80211_hw *hw = priv->hw;
2660 struct iwl_rxon_context *ctx;
2661
2662 hw->rate_control_algorithm = "iwl-agn-rs";
2663
2664 /* Tell mac80211 our characteristics */
2665 hw->flags = IEEE80211_HW_SIGNAL_DBM |
2666 IEEE80211_HW_AMPDU_AGGREGATION |
2667 IEEE80211_HW_NEED_DTIM_PERIOD |
2668 IEEE80211_HW_SPECTRUM_MGMT |
2669 IEEE80211_HW_REPORTS_TX_ACK_STATUS;
2670
2671 hw->max_tx_aggregation_subframes = LINK_QUAL_AGG_FRAME_LIMIT_DEF;
2672
2673 hw->flags |= IEEE80211_HW_SUPPORTS_PS |
2674 IEEE80211_HW_SUPPORTS_DYNAMIC_PS;
2675
2676 if (priv->cfg->sku & IWL_SKU_N)
2677 hw->flags |= IEEE80211_HW_SUPPORTS_DYNAMIC_SMPS |
2678 IEEE80211_HW_SUPPORTS_STATIC_SMPS;
2679
2680 if (capa->flags & IWL_UCODE_TLV_FLAGS_MFP)
2681 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
2682
2683 hw->sta_data_size = sizeof(struct iwl_station_priv);
2684 hw->vif_data_size = sizeof(struct iwl_vif_priv);
2685
2686 for_each_context(priv, ctx) {
2687 hw->wiphy->interface_modes |= ctx->interface_modes;
2688 hw->wiphy->interface_modes |= ctx->exclusive_interface_modes;
2689 }
2690
2691 hw->wiphy->max_remain_on_channel_duration = 1000;
2692
2693 hw->wiphy->flags |= WIPHY_FLAG_CUSTOM_REGULATORY |
2694 WIPHY_FLAG_DISABLE_BEACON_HINTS |
2695 WIPHY_FLAG_IBSS_RSN;
2696
2697 /*
2698 * For now, disable PS by default because it affects
2699 * RX performance significantly.
2700 */
2701 hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
2702
2703 hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX;
2704 /* we create the 802.11 header and a zero-length SSID element */
2705 hw->wiphy->max_scan_ie_len = capa->max_probe_length - 24 - 2;
2706
2707 /* Default value; 4 EDCA QOS priorities */
2708 hw->queues = 4;
2709
2710 hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL;
2711
2712 if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
2713 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
2714 &priv->bands[IEEE80211_BAND_2GHZ];
2715 if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
2716 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
2717 &priv->bands[IEEE80211_BAND_5GHZ];
2718
2719 iwl_leds_init(priv);
2720
2721 ret = ieee80211_register_hw(priv->hw);
2722 if (ret) {
2723 IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
2724 return ret;
2725 }
2726 priv->mac80211_registered = 1;
2727
2728 return 0;
2729 }
2730
2731
2732 static int iwlagn_mac_start(struct ieee80211_hw *hw)
2733 {
2734 struct iwl_priv *priv = hw->priv;
2735 int ret;
2736
2737 IWL_DEBUG_MAC80211(priv, "enter\n");
2738
2739 /* we should be verifying the device is ready to be opened */
2740 mutex_lock(&priv->mutex);
2741 ret = __iwl_up(priv);
2742 mutex_unlock(&priv->mutex);
2743 if (ret)
2744 return ret;
2745
2746 IWL_DEBUG_INFO(priv, "Start UP work done.\n");
2747
2748 /* Now we should be done, and the READY bit should be set. */
2749 if (WARN_ON(!test_bit(STATUS_READY, &priv->status)))
2750 ret = -EIO;
2751
2752 iwlagn_led_enable(priv);
2753
2754 priv->is_open = 1;
2755 IWL_DEBUG_MAC80211(priv, "leave\n");
2756 return 0;
2757 }
2758
2759 static void iwlagn_mac_stop(struct ieee80211_hw *hw)
2760 {
2761 struct iwl_priv *priv = hw->priv;
2762
2763 IWL_DEBUG_MAC80211(priv, "enter\n");
2764
2765 if (!priv->is_open)
2766 return;
2767
2768 priv->is_open = 0;
2769
2770 iwl_down(priv);
2771
2772 flush_workqueue(priv->workqueue);
2773
2774 /* User space software may expect getting rfkill changes
2775 * even if interface is down */
2776 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
2777 iwl_enable_rfkill_int(priv);
2778
2779 IWL_DEBUG_MAC80211(priv, "leave\n");
2780 }
2781
2782 static void iwlagn_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
2783 {
2784 struct iwl_priv *priv = hw->priv;
2785
2786 IWL_DEBUG_MACDUMP(priv, "enter\n");
2787
2788 IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
2789 ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
2790
2791 if (iwlagn_tx_skb(priv, skb))
2792 dev_kfree_skb_any(skb);
2793
2794 IWL_DEBUG_MACDUMP(priv, "leave\n");
2795 }
2796
2797 static void iwlagn_mac_update_tkip_key(struct ieee80211_hw *hw,
2798 struct ieee80211_vif *vif,
2799 struct ieee80211_key_conf *keyconf,
2800 struct ieee80211_sta *sta,
2801 u32 iv32, u16 *phase1key)
2802 {
2803 struct iwl_priv *priv = hw->priv;
2804 struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
2805
2806 IWL_DEBUG_MAC80211(priv, "enter\n");
2807
2808 iwl_update_tkip_key(priv, vif_priv->ctx, keyconf, sta,
2809 iv32, phase1key);
2810
2811 IWL_DEBUG_MAC80211(priv, "leave\n");
2812 }
2813
2814 static int iwlagn_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
2815 struct ieee80211_vif *vif,
2816 struct ieee80211_sta *sta,
2817 struct ieee80211_key_conf *key)
2818 {
2819 struct iwl_priv *priv = hw->priv;
2820 struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
2821 struct iwl_rxon_context *ctx = vif_priv->ctx;
2822 int ret;
2823 u8 sta_id;
2824 bool is_default_wep_key = false;
2825
2826 IWL_DEBUG_MAC80211(priv, "enter\n");
2827
2828 if (priv->cfg->mod_params->sw_crypto) {
2829 IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
2830 return -EOPNOTSUPP;
2831 }
2832
2833 /*
2834 * To support IBSS RSN, don't program group keys in IBSS, the
2835 * hardware will then not attempt to decrypt the frames.
2836 */
2837 if (vif->type == NL80211_IFTYPE_ADHOC &&
2838 !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE))
2839 return -EOPNOTSUPP;
2840
2841 sta_id = iwl_sta_id_or_broadcast(priv, vif_priv->ctx, sta);
2842 if (sta_id == IWL_INVALID_STATION)
2843 return -EINVAL;
2844
2845 mutex_lock(&priv->mutex);
2846 iwl_scan_cancel_timeout(priv, 100);
2847
2848 /*
2849 * If we are getting WEP group key and we didn't receive any key mapping
2850 * so far, we are in legacy wep mode (group key only), otherwise we are
2851 * in 1X mode.
2852 * In legacy wep mode, we use another host command to the uCode.
2853 */
2854 if ((key->cipher == WLAN_CIPHER_SUITE_WEP40 ||
2855 key->cipher == WLAN_CIPHER_SUITE_WEP104) &&
2856 !sta) {
2857 if (cmd == SET_KEY)
2858 is_default_wep_key = !ctx->key_mapping_keys;
2859 else
2860 is_default_wep_key =
2861 (key->hw_key_idx == HW_KEY_DEFAULT);
2862 }
2863
2864 switch (cmd) {
2865 case SET_KEY:
2866 if (is_default_wep_key)
2867 ret = iwl_set_default_wep_key(priv, vif_priv->ctx, key);
2868 else
2869 ret = iwl_set_dynamic_key(priv, vif_priv->ctx,
2870 key, sta_id);
2871
2872 IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
2873 break;
2874 case DISABLE_KEY:
2875 if (is_default_wep_key)
2876 ret = iwl_remove_default_wep_key(priv, ctx, key);
2877 else
2878 ret = iwl_remove_dynamic_key(priv, ctx, key, sta_id);
2879
2880 IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
2881 break;
2882 default:
2883 ret = -EINVAL;
2884 }
2885
2886 mutex_unlock(&priv->mutex);
2887 IWL_DEBUG_MAC80211(priv, "leave\n");
2888
2889 return ret;
2890 }
2891
2892 static int iwlagn_mac_ampdu_action(struct ieee80211_hw *hw,
2893 struct ieee80211_vif *vif,
2894 enum ieee80211_ampdu_mlme_action action,
2895 struct ieee80211_sta *sta, u16 tid, u16 *ssn,
2896 u8 buf_size)
2897 {
2898 struct iwl_priv *priv = hw->priv;
2899 int ret = -EINVAL;
2900 struct iwl_station_priv *sta_priv = (void *) sta->drv_priv;
2901
2902 IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n",
2903 sta->addr, tid);
2904
2905 if (!(priv->cfg->sku & IWL_SKU_N))
2906 return -EACCES;
2907
2908 mutex_lock(&priv->mutex);
2909
2910 switch (action) {
2911 case IEEE80211_AMPDU_RX_START:
2912 IWL_DEBUG_HT(priv, "start Rx\n");
2913 ret = iwl_sta_rx_agg_start(priv, sta, tid, *ssn);
2914 break;
2915 case IEEE80211_AMPDU_RX_STOP:
2916 IWL_DEBUG_HT(priv, "stop Rx\n");
2917 ret = iwl_sta_rx_agg_stop(priv, sta, tid);
2918 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2919 ret = 0;
2920 break;
2921 case IEEE80211_AMPDU_TX_START:
2922 IWL_DEBUG_HT(priv, "start Tx\n");
2923 ret = iwlagn_tx_agg_start(priv, vif, sta, tid, ssn);
2924 if (ret == 0) {
2925 priv->_agn.agg_tids_count++;
2926 IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
2927 priv->_agn.agg_tids_count);
2928 }
2929 break;
2930 case IEEE80211_AMPDU_TX_STOP:
2931 IWL_DEBUG_HT(priv, "stop Tx\n");
2932 ret = iwlagn_tx_agg_stop(priv, vif, sta, tid);
2933 if ((ret == 0) && (priv->_agn.agg_tids_count > 0)) {
2934 priv->_agn.agg_tids_count--;
2935 IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
2936 priv->_agn.agg_tids_count);
2937 }
2938 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2939 ret = 0;
2940 if (priv->cfg->ht_params &&
2941 priv->cfg->ht_params->use_rts_for_aggregation) {
2942 struct iwl_station_priv *sta_priv =
2943 (void *) sta->drv_priv;
2944 /*
2945 * switch off RTS/CTS if it was previously enabled
2946 */
2947
2948 sta_priv->lq_sta.lq.general_params.flags &=
2949 ~LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK;
2950 iwl_send_lq_cmd(priv, iwl_rxon_ctx_from_vif(vif),
2951 &sta_priv->lq_sta.lq, CMD_ASYNC, false);
2952 }
2953 break;
2954 case IEEE80211_AMPDU_TX_OPERATIONAL:
2955 buf_size = min_t(int, buf_size, LINK_QUAL_AGG_FRAME_LIMIT_DEF);
2956
2957 iwlagn_txq_agg_queue_setup(priv, sta, tid, buf_size);
2958
2959 /*
2960 * If the limit is 0, then it wasn't initialised yet,
2961 * use the default. We can do that since we take the
2962 * minimum below, and we don't want to go above our
2963 * default due to hardware restrictions.
2964 */
2965 if (sta_priv->max_agg_bufsize == 0)
2966 sta_priv->max_agg_bufsize =
2967 LINK_QUAL_AGG_FRAME_LIMIT_DEF;
2968
2969 /*
2970 * Even though in theory the peer could have different
2971 * aggregation reorder buffer sizes for different sessions,
2972 * our ucode doesn't allow for that and has a global limit
2973 * for each station. Therefore, use the minimum of all the
2974 * aggregation sessions and our default value.
2975 */
2976 sta_priv->max_agg_bufsize =
2977 min(sta_priv->max_agg_bufsize, buf_size);
2978
2979 if (priv->cfg->ht_params &&
2980 priv->cfg->ht_params->use_rts_for_aggregation) {
2981 /*
2982 * switch to RTS/CTS if it is the prefer protection
2983 * method for HT traffic
2984 */
2985
2986 sta_priv->lq_sta.lq.general_params.flags |=
2987 LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK;
2988 }
2989
2990 sta_priv->lq_sta.lq.agg_params.agg_frame_cnt_limit =
2991 sta_priv->max_agg_bufsize;
2992
2993 iwl_send_lq_cmd(priv, iwl_rxon_ctx_from_vif(vif),
2994 &sta_priv->lq_sta.lq, CMD_ASYNC, false);
2995 ret = 0;
2996 break;
2997 }
2998 mutex_unlock(&priv->mutex);
2999
3000 return ret;
3001 }
3002
3003 static int iwlagn_mac_sta_add(struct ieee80211_hw *hw,
3004 struct ieee80211_vif *vif,
3005 struct ieee80211_sta *sta)
3006 {
3007 struct iwl_priv *priv = hw->priv;
3008 struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
3009 struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
3010 bool is_ap = vif->type == NL80211_IFTYPE_STATION;
3011 int ret;
3012 u8 sta_id;
3013
3014 IWL_DEBUG_INFO(priv, "received request to add station %pM\n",
3015 sta->addr);
3016 mutex_lock(&priv->mutex);
3017 IWL_DEBUG_INFO(priv, "proceeding to add station %pM\n",
3018 sta->addr);
3019 sta_priv->common.sta_id = IWL_INVALID_STATION;
3020
3021 atomic_set(&sta_priv->pending_frames, 0);
3022 if (vif->type == NL80211_IFTYPE_AP)
3023 sta_priv->client = true;
3024
3025 ret = iwl_add_station_common(priv, vif_priv->ctx, sta->addr,
3026 is_ap, sta, &sta_id);
3027 if (ret) {
3028 IWL_ERR(priv, "Unable to add station %pM (%d)\n",
3029 sta->addr, ret);
3030 /* Should we return success if return code is EEXIST ? */
3031 mutex_unlock(&priv->mutex);
3032 return ret;
3033 }
3034
3035 sta_priv->common.sta_id = sta_id;
3036
3037 /* Initialize rate scaling */
3038 IWL_DEBUG_INFO(priv, "Initializing rate scaling for station %pM\n",
3039 sta->addr);
3040 iwl_rs_rate_init(priv, sta, sta_id);
3041 mutex_unlock(&priv->mutex);
3042
3043 return 0;
3044 }
3045
3046 static void iwlagn_mac_channel_switch(struct ieee80211_hw *hw,
3047 struct ieee80211_channel_switch *ch_switch)
3048 {
3049 struct iwl_priv *priv = hw->priv;
3050 const struct iwl_channel_info *ch_info;
3051 struct ieee80211_conf *conf = &hw->conf;
3052 struct ieee80211_channel *channel = ch_switch->channel;
3053 struct iwl_ht_config *ht_conf = &priv->current_ht_config;
3054 /*
3055 * MULTI-FIXME
3056 * When we add support for multiple interfaces, we need to
3057 * revisit this. The channel switch command in the device
3058 * only affects the BSS context, but what does that really
3059 * mean? And what if we get a CSA on the second interface?
3060 * This needs a lot of work.
3061 */
3062 struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
3063 u16 ch;
3064 unsigned long flags = 0;
3065
3066 IWL_DEBUG_MAC80211(priv, "enter\n");
3067
3068 mutex_lock(&priv->mutex);
3069
3070 if (iwl_is_rfkill(priv))
3071 goto out;
3072
3073 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
3074 test_bit(STATUS_SCANNING, &priv->status))
3075 goto out;
3076
3077 if (!iwl_is_associated_ctx(ctx))
3078 goto out;
3079
3080 /* channel switch in progress */
3081 if (priv->switch_rxon.switch_in_progress == true)
3082 goto out;
3083
3084 if (priv->cfg->ops->lib->set_channel_switch) {
3085
3086 ch = channel->hw_value;
3087 if (le16_to_cpu(ctx->active.channel) != ch) {
3088 ch_info = iwl_get_channel_info(priv,
3089 channel->band,
3090 ch);
3091 if (!is_channel_valid(ch_info)) {
3092 IWL_DEBUG_MAC80211(priv, "invalid channel\n");
3093 goto out;
3094 }
3095 spin_lock_irqsave(&priv->lock, flags);
3096
3097 priv->current_ht_config.smps = conf->smps_mode;
3098
3099 /* Configure HT40 channels */
3100 ctx->ht.enabled = conf_is_ht(conf);
3101 if (ctx->ht.enabled) {
3102 if (conf_is_ht40_minus(conf)) {
3103 ctx->ht.extension_chan_offset =
3104 IEEE80211_HT_PARAM_CHA_SEC_BELOW;
3105 ctx->ht.is_40mhz = true;
3106 } else if (conf_is_ht40_plus(conf)) {
3107 ctx->ht.extension_chan_offset =
3108 IEEE80211_HT_PARAM_CHA_SEC_ABOVE;
3109 ctx->ht.is_40mhz = true;
3110 } else {
3111 ctx->ht.extension_chan_offset =
3112 IEEE80211_HT_PARAM_CHA_SEC_NONE;
3113 ctx->ht.is_40mhz = false;
3114 }
3115 } else
3116 ctx->ht.is_40mhz = false;
3117
3118 if ((le16_to_cpu(ctx->staging.channel) != ch))
3119 ctx->staging.flags = 0;
3120
3121 iwl_set_rxon_channel(priv, channel, ctx);
3122 iwl_set_rxon_ht(priv, ht_conf);
3123 iwl_set_flags_for_band(priv, ctx, channel->band,
3124 ctx->vif);
3125 spin_unlock_irqrestore(&priv->lock, flags);
3126
3127 iwl_set_rate(priv);
3128 /*
3129 * at this point, staging_rxon has the
3130 * configuration for channel switch
3131 */
3132 if (priv->cfg->ops->lib->set_channel_switch(priv,
3133 ch_switch))
3134 priv->switch_rxon.switch_in_progress = false;
3135 }
3136 }
3137 out:
3138 mutex_unlock(&priv->mutex);
3139 if (!priv->switch_rxon.switch_in_progress)
3140 ieee80211_chswitch_done(ctx->vif, false);
3141 IWL_DEBUG_MAC80211(priv, "leave\n");
3142 }
3143
3144 static void iwlagn_configure_filter(struct ieee80211_hw *hw,
3145 unsigned int changed_flags,
3146 unsigned int *total_flags,
3147 u64 multicast)
3148 {
3149 struct iwl_priv *priv = hw->priv;
3150 __le32 filter_or = 0, filter_nand = 0;
3151 struct iwl_rxon_context *ctx;
3152
3153 #define CHK(test, flag) do { \
3154 if (*total_flags & (test)) \
3155 filter_or |= (flag); \
3156 else \
3157 filter_nand |= (flag); \
3158 } while (0)
3159
3160 IWL_DEBUG_MAC80211(priv, "Enter: changed: 0x%x, total: 0x%x\n",
3161 changed_flags, *total_flags);
3162
3163 CHK(FIF_OTHER_BSS | FIF_PROMISC_IN_BSS, RXON_FILTER_PROMISC_MSK);
3164 /* Setting _just_ RXON_FILTER_CTL2HOST_MSK causes FH errors */
3165 CHK(FIF_CONTROL, RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_PROMISC_MSK);
3166 CHK(FIF_BCN_PRBRESP_PROMISC, RXON_FILTER_BCON_AWARE_MSK);
3167
3168 #undef CHK
3169
3170 mutex_lock(&priv->mutex);
3171
3172 for_each_context(priv, ctx) {
3173 ctx->staging.filter_flags &= ~filter_nand;
3174 ctx->staging.filter_flags |= filter_or;
3175
3176 /*
3177 * Not committing directly because hardware can perform a scan,
3178 * but we'll eventually commit the filter flags change anyway.
3179 */
3180 }
3181
3182 mutex_unlock(&priv->mutex);
3183
3184 /*
3185 * Receiving all multicast frames is always enabled by the
3186 * default flags setup in iwl_connection_init_rx_config()
3187 * since we currently do not support programming multicast
3188 * filters into the device.
3189 */
3190 *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS |
3191 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
3192 }
3193
3194 static void iwlagn_mac_flush(struct ieee80211_hw *hw, bool drop)
3195 {
3196 struct iwl_priv *priv = hw->priv;
3197
3198 mutex_lock(&priv->mutex);
3199 IWL_DEBUG_MAC80211(priv, "enter\n");
3200
3201 /* do not support "flush" */
3202 if (!priv->cfg->ops->lib->txfifo_flush)
3203 goto done;
3204
3205 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
3206 IWL_DEBUG_TX(priv, "Aborting flush due to device shutdown\n");
3207 goto done;
3208 }
3209 if (iwl_is_rfkill(priv)) {
3210 IWL_DEBUG_TX(priv, "Aborting flush due to RF Kill\n");
3211 goto done;
3212 }
3213
3214 /*
3215 * mac80211 will not push any more frames for transmit
3216 * until the flush is completed
3217 */
3218 if (drop) {
3219 IWL_DEBUG_MAC80211(priv, "send flush command\n");
3220 if (priv->cfg->ops->lib->txfifo_flush(priv, IWL_DROP_ALL)) {
3221 IWL_ERR(priv, "flush request fail\n");
3222 goto done;
3223 }
3224 }
3225 IWL_DEBUG_MAC80211(priv, "wait transmit/flush all frames\n");
3226 iwlagn_wait_tx_queue_empty(priv);
3227 done:
3228 mutex_unlock(&priv->mutex);
3229 IWL_DEBUG_MAC80211(priv, "leave\n");
3230 }
3231
3232 static void iwlagn_disable_roc(struct iwl_priv *priv)
3233 {
3234 struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_PAN];
3235 struct ieee80211_channel *chan = ACCESS_ONCE(priv->hw->conf.channel);
3236
3237 lockdep_assert_held(&priv->mutex);
3238
3239 if (!ctx->is_active)
3240 return;
3241
3242 ctx->staging.dev_type = RXON_DEV_TYPE_2STA;
3243 ctx->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
3244 iwl_set_rxon_channel(priv, chan, ctx);
3245 iwl_set_flags_for_band(priv, ctx, chan->band, NULL);
3246
3247 priv->_agn.hw_roc_channel = NULL;
3248
3249 iwlcore_commit_rxon(priv, ctx);
3250
3251 ctx->is_active = false;
3252 }
3253
3254 static void iwlagn_bg_roc_done(struct work_struct *work)
3255 {
3256 struct iwl_priv *priv = container_of(work, struct iwl_priv,
3257 _agn.hw_roc_work.work);
3258
3259 mutex_lock(&priv->mutex);
3260 ieee80211_remain_on_channel_expired(priv->hw);
3261 iwlagn_disable_roc(priv);
3262 mutex_unlock(&priv->mutex);
3263 }
3264
3265 static int iwl_mac_remain_on_channel(struct ieee80211_hw *hw,
3266 struct ieee80211_channel *channel,
3267 enum nl80211_channel_type channel_type,
3268 int duration)
3269 {
3270 struct iwl_priv *priv = hw->priv;
3271 int err = 0;
3272
3273 if (!(priv->valid_contexts & BIT(IWL_RXON_CTX_PAN)))
3274 return -EOPNOTSUPP;
3275
3276 if (!(priv->contexts[IWL_RXON_CTX_PAN].interface_modes &
3277 BIT(NL80211_IFTYPE_P2P_CLIENT)))
3278 return -EOPNOTSUPP;
3279
3280 mutex_lock(&priv->mutex);
3281
3282 if (priv->contexts[IWL_RXON_CTX_PAN].is_active ||
3283 test_bit(STATUS_SCAN_HW, &priv->status)) {
3284 err = -EBUSY;
3285 goto out;
3286 }
3287
3288 priv->contexts[IWL_RXON_CTX_PAN].is_active = true;
3289 priv->_agn.hw_roc_channel = channel;
3290 priv->_agn.hw_roc_chantype = channel_type;
3291 priv->_agn.hw_roc_duration = DIV_ROUND_UP(duration * 1000, 1024);
3292 iwlcore_commit_rxon(priv, &priv->contexts[IWL_RXON_CTX_PAN]);
3293 queue_delayed_work(priv->workqueue, &priv->_agn.hw_roc_work,
3294 msecs_to_jiffies(duration + 20));
3295
3296 msleep(IWL_MIN_SLOT_TIME); /* TU is almost ms */
3297 ieee80211_ready_on_channel(priv->hw);
3298
3299 out:
3300 mutex_unlock(&priv->mutex);
3301
3302 return err;
3303 }
3304
3305 static int iwl_mac_cancel_remain_on_channel(struct ieee80211_hw *hw)
3306 {
3307 struct iwl_priv *priv = hw->priv;
3308
3309 if (!(priv->valid_contexts & BIT(IWL_RXON_CTX_PAN)))
3310 return -EOPNOTSUPP;
3311
3312 cancel_delayed_work_sync(&priv->_agn.hw_roc_work);
3313
3314 mutex_lock(&priv->mutex);
3315 iwlagn_disable_roc(priv);
3316 mutex_unlock(&priv->mutex);
3317
3318 return 0;
3319 }
3320
3321 /*****************************************************************************
3322 *
3323 * driver setup and teardown
3324 *
3325 *****************************************************************************/
3326
3327 static void iwl_setup_deferred_work(struct iwl_priv *priv)
3328 {
3329 priv->workqueue = create_singlethread_workqueue(DRV_NAME);
3330
3331 init_waitqueue_head(&priv->wait_command_queue);
3332
3333 INIT_WORK(&priv->restart, iwl_bg_restart);
3334 INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish);
3335 INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update);
3336 INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work);
3337 INIT_WORK(&priv->tx_flush, iwl_bg_tx_flush);
3338 INIT_WORK(&priv->bt_full_concurrency, iwl_bg_bt_full_concurrency);
3339 INIT_WORK(&priv->bt_runtime_config, iwl_bg_bt_runtime_config);
3340 INIT_DELAYED_WORK(&priv->_agn.hw_roc_work, iwlagn_bg_roc_done);
3341
3342 iwl_setup_scan_deferred_work(priv);
3343
3344 if (priv->cfg->ops->lib->setup_deferred_work)
3345 priv->cfg->ops->lib->setup_deferred_work(priv);
3346
3347 init_timer(&priv->statistics_periodic);
3348 priv->statistics_periodic.data = (unsigned long)priv;
3349 priv->statistics_periodic.function = iwl_bg_statistics_periodic;
3350
3351 init_timer(&priv->ucode_trace);
3352 priv->ucode_trace.data = (unsigned long)priv;
3353 priv->ucode_trace.function = iwl_bg_ucode_trace;
3354
3355 init_timer(&priv->watchdog);
3356 priv->watchdog.data = (unsigned long)priv;
3357 priv->watchdog.function = iwl_bg_watchdog;
3358
3359 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
3360 iwl_irq_tasklet, (unsigned long)priv);
3361 }
3362
3363 static void iwl_cancel_deferred_work(struct iwl_priv *priv)
3364 {
3365 if (priv->cfg->ops->lib->cancel_deferred_work)
3366 priv->cfg->ops->lib->cancel_deferred_work(priv);
3367
3368 cancel_work_sync(&priv->run_time_calib_work);
3369 cancel_work_sync(&priv->beacon_update);
3370
3371 iwl_cancel_scan_deferred_work(priv);
3372
3373 cancel_work_sync(&priv->bt_full_concurrency);
3374 cancel_work_sync(&priv->bt_runtime_config);
3375
3376 del_timer_sync(&priv->statistics_periodic);
3377 del_timer_sync(&priv->ucode_trace);
3378 }
3379
3380 static void iwl_init_hw_rates(struct iwl_priv *priv,
3381 struct ieee80211_rate *rates)
3382 {
3383 int i;
3384
3385 for (i = 0; i < IWL_RATE_COUNT_LEGACY; i++) {
3386 rates[i].bitrate = iwl_rates[i].ieee * 5;
3387 rates[i].hw_value = i; /* Rate scaling will work on indexes */
3388 rates[i].hw_value_short = i;
3389 rates[i].flags = 0;
3390 if ((i >= IWL_FIRST_CCK_RATE) && (i <= IWL_LAST_CCK_RATE)) {
3391 /*
3392 * If CCK != 1M then set short preamble rate flag.
3393 */
3394 rates[i].flags |=
3395 (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
3396 0 : IEEE80211_RATE_SHORT_PREAMBLE;
3397 }
3398 }
3399 }
3400
3401 static int iwl_init_drv(struct iwl_priv *priv)
3402 {
3403 int ret;
3404
3405 spin_lock_init(&priv->sta_lock);
3406 spin_lock_init(&priv->hcmd_lock);
3407
3408 INIT_LIST_HEAD(&priv->free_frames);
3409
3410 mutex_init(&priv->mutex);
3411
3412 priv->ieee_channels = NULL;
3413 priv->ieee_rates = NULL;
3414 priv->band = IEEE80211_BAND_2GHZ;
3415
3416 priv->iw_mode = NL80211_IFTYPE_STATION;
3417 priv->current_ht_config.smps = IEEE80211_SMPS_STATIC;
3418 priv->missed_beacon_threshold = IWL_MISSED_BEACON_THRESHOLD_DEF;
3419 priv->_agn.agg_tids_count = 0;
3420
3421 /* initialize force reset */
3422 priv->force_reset[IWL_RF_RESET].reset_duration =
3423 IWL_DELAY_NEXT_FORCE_RF_RESET;
3424 priv->force_reset[IWL_FW_RESET].reset_duration =
3425 IWL_DELAY_NEXT_FORCE_FW_RELOAD;
3426
3427 priv->rx_statistics_jiffies = jiffies;
3428
3429 /* Choose which receivers/antennas to use */
3430 if (priv->cfg->ops->hcmd->set_rxon_chain)
3431 priv->cfg->ops->hcmd->set_rxon_chain(priv,
3432 &priv->contexts[IWL_RXON_CTX_BSS]);
3433
3434 iwl_init_scan_params(priv);
3435
3436 /* init bt coex */
3437 if (priv->cfg->bt_params &&
3438 priv->cfg->bt_params->advanced_bt_coexist) {
3439 priv->kill_ack_mask = IWLAGN_BT_KILL_ACK_MASK_DEFAULT;
3440 priv->kill_cts_mask = IWLAGN_BT_KILL_CTS_MASK_DEFAULT;
3441 priv->bt_valid = IWLAGN_BT_ALL_VALID_MSK;
3442 priv->bt_on_thresh = BT_ON_THRESHOLD_DEF;
3443 priv->bt_duration = BT_DURATION_LIMIT_DEF;
3444 priv->dynamic_frag_thresh = BT_FRAG_THRESHOLD_DEF;
3445 }
3446
3447 ret = iwl_init_channel_map(priv);
3448 if (ret) {
3449 IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
3450 goto err;
3451 }
3452
3453 ret = iwlcore_init_geos(priv);
3454 if (ret) {
3455 IWL_ERR(priv, "initializing geos failed: %d\n", ret);
3456 goto err_free_channel_map;
3457 }
3458 iwl_init_hw_rates(priv, priv->ieee_rates);
3459
3460 return 0;
3461
3462 err_free_channel_map:
3463 iwl_free_channel_map(priv);
3464 err:
3465 return ret;
3466 }
3467
3468 static void iwl_uninit_drv(struct iwl_priv *priv)
3469 {
3470 iwl_calib_free_results(priv);
3471 iwlcore_free_geos(priv);
3472 iwl_free_channel_map(priv);
3473 kfree(priv->scan_cmd);
3474 }
3475
3476 struct ieee80211_ops iwlagn_hw_ops = {
3477 .tx = iwlagn_mac_tx,
3478 .start = iwlagn_mac_start,
3479 .stop = iwlagn_mac_stop,
3480 .add_interface = iwl_mac_add_interface,
3481 .remove_interface = iwl_mac_remove_interface,
3482 .change_interface = iwl_mac_change_interface,
3483 .config = iwlagn_mac_config,
3484 .configure_filter = iwlagn_configure_filter,
3485 .set_key = iwlagn_mac_set_key,
3486 .update_tkip_key = iwlagn_mac_update_tkip_key,
3487 .conf_tx = iwl_mac_conf_tx,
3488 .bss_info_changed = iwlagn_bss_info_changed,
3489 .ampdu_action = iwlagn_mac_ampdu_action,
3490 .hw_scan = iwl_mac_hw_scan,
3491 .sta_notify = iwlagn_mac_sta_notify,
3492 .sta_add = iwlagn_mac_sta_add,
3493 .sta_remove = iwl_mac_sta_remove,
3494 .channel_switch = iwlagn_mac_channel_switch,
3495 .flush = iwlagn_mac_flush,
3496 .tx_last_beacon = iwl_mac_tx_last_beacon,
3497 .remain_on_channel = iwl_mac_remain_on_channel,
3498 .cancel_remain_on_channel = iwl_mac_cancel_remain_on_channel,
3499 .offchannel_tx = iwl_mac_offchannel_tx,
3500 .offchannel_tx_cancel_wait = iwl_mac_offchannel_tx_cancel_wait,
3501 };
3502
3503 static u32 iwl_hw_detect(struct iwl_priv *priv)
3504 {
3505 u8 rev_id;
3506
3507 pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &rev_id);
3508 IWL_DEBUG_INFO(priv, "HW Revision ID = 0x%X\n", rev_id);
3509 return iwl_read32(priv, CSR_HW_REV);
3510 }
3511
3512 static int iwl_set_hw_params(struct iwl_priv *priv)
3513 {
3514 priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
3515 priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
3516 if (priv->cfg->mod_params->amsdu_size_8K)
3517 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_8K);
3518 else
3519 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_4K);
3520
3521 priv->hw_params.max_beacon_itrvl = IWL_MAX_UCODE_BEACON_INTERVAL;
3522
3523 if (priv->cfg->mod_params->disable_11n)
3524 priv->cfg->sku &= ~IWL_SKU_N;
3525
3526 /* Device-specific setup */
3527 return priv->cfg->ops->lib->set_hw_params(priv);
3528 }
3529
3530 static const u8 iwlagn_bss_ac_to_fifo[] = {
3531 IWL_TX_FIFO_VO,
3532 IWL_TX_FIFO_VI,
3533 IWL_TX_FIFO_BE,
3534 IWL_TX_FIFO_BK,
3535 };
3536
3537 static const u8 iwlagn_bss_ac_to_queue[] = {
3538 0, 1, 2, 3,
3539 };
3540
3541 static const u8 iwlagn_pan_ac_to_fifo[] = {
3542 IWL_TX_FIFO_VO_IPAN,
3543 IWL_TX_FIFO_VI_IPAN,
3544 IWL_TX_FIFO_BE_IPAN,
3545 IWL_TX_FIFO_BK_IPAN,
3546 };
3547
3548 static const u8 iwlagn_pan_ac_to_queue[] = {
3549 7, 6, 5, 4,
3550 };
3551
3552 /* This function both allocates and initializes hw and priv. */
3553 static struct ieee80211_hw *iwl_alloc_all(struct iwl_cfg *cfg)
3554 {
3555 struct iwl_priv *priv;
3556 /* mac80211 allocates memory for this device instance, including
3557 * space for this driver's private structure */
3558 struct ieee80211_hw *hw;
3559
3560 hw = ieee80211_alloc_hw(sizeof(struct iwl_priv), &iwlagn_hw_ops);
3561 if (hw == NULL) {
3562 pr_err("%s: Can not allocate network device\n",
3563 cfg->name);
3564 goto out;
3565 }
3566
3567 priv = hw->priv;
3568 priv->hw = hw;
3569
3570 out:
3571 return hw;
3572 }
3573
3574 static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3575 {
3576 int err = 0, i;
3577 struct iwl_priv *priv;
3578 struct ieee80211_hw *hw;
3579 struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
3580 unsigned long flags;
3581 u16 pci_cmd, num_mac;
3582 u32 hw_rev;
3583
3584 /************************
3585 * 1. Allocating HW data
3586 ************************/
3587
3588 hw = iwl_alloc_all(cfg);
3589 if (!hw) {
3590 err = -ENOMEM;
3591 goto out;
3592 }
3593 priv = hw->priv;
3594 /* At this point both hw and priv are allocated. */
3595
3596 priv->ucode_type = UCODE_SUBTYPE_NONE_LOADED;
3597
3598 /*
3599 * The default context is always valid,
3600 * more may be discovered when firmware
3601 * is loaded.
3602 */
3603 priv->valid_contexts = BIT(IWL_RXON_CTX_BSS);
3604
3605 for (i = 0; i < NUM_IWL_RXON_CTX; i++)
3606 priv->contexts[i].ctxid = i;
3607
3608 priv->contexts[IWL_RXON_CTX_BSS].always_active = true;
3609 priv->contexts[IWL_RXON_CTX_BSS].is_active = true;
3610 priv->contexts[IWL_RXON_CTX_BSS].rxon_cmd = REPLY_RXON;
3611 priv->contexts[IWL_RXON_CTX_BSS].rxon_timing_cmd = REPLY_RXON_TIMING;
3612 priv->contexts[IWL_RXON_CTX_BSS].rxon_assoc_cmd = REPLY_RXON_ASSOC;
3613 priv->contexts[IWL_RXON_CTX_BSS].qos_cmd = REPLY_QOS_PARAM;
3614 priv->contexts[IWL_RXON_CTX_BSS].ap_sta_id = IWL_AP_ID;
3615 priv->contexts[IWL_RXON_CTX_BSS].wep_key_cmd = REPLY_WEPKEY;
3616 priv->contexts[IWL_RXON_CTX_BSS].ac_to_fifo = iwlagn_bss_ac_to_fifo;
3617 priv->contexts[IWL_RXON_CTX_BSS].ac_to_queue = iwlagn_bss_ac_to_queue;
3618 priv->contexts[IWL_RXON_CTX_BSS].exclusive_interface_modes =
3619 BIT(NL80211_IFTYPE_ADHOC);
3620 priv->contexts[IWL_RXON_CTX_BSS].interface_modes =
3621 BIT(NL80211_IFTYPE_STATION);
3622 priv->contexts[IWL_RXON_CTX_BSS].ap_devtype = RXON_DEV_TYPE_AP;
3623 priv->contexts[IWL_RXON_CTX_BSS].ibss_devtype = RXON_DEV_TYPE_IBSS;
3624 priv->contexts[IWL_RXON_CTX_BSS].station_devtype = RXON_DEV_TYPE_ESS;
3625 priv->contexts[IWL_RXON_CTX_BSS].unused_devtype = RXON_DEV_TYPE_ESS;
3626
3627 priv->contexts[IWL_RXON_CTX_PAN].rxon_cmd = REPLY_WIPAN_RXON;
3628 priv->contexts[IWL_RXON_CTX_PAN].rxon_timing_cmd = REPLY_WIPAN_RXON_TIMING;
3629 priv->contexts[IWL_RXON_CTX_PAN].rxon_assoc_cmd = REPLY_WIPAN_RXON_ASSOC;
3630 priv->contexts[IWL_RXON_CTX_PAN].qos_cmd = REPLY_WIPAN_QOS_PARAM;
3631 priv->contexts[IWL_RXON_CTX_PAN].ap_sta_id = IWL_AP_ID_PAN;
3632 priv->contexts[IWL_RXON_CTX_PAN].wep_key_cmd = REPLY_WIPAN_WEPKEY;
3633 priv->contexts[IWL_RXON_CTX_PAN].bcast_sta_id = IWLAGN_PAN_BCAST_ID;
3634 priv->contexts[IWL_RXON_CTX_PAN].station_flags = STA_FLG_PAN_STATION;
3635 priv->contexts[IWL_RXON_CTX_PAN].ac_to_fifo = iwlagn_pan_ac_to_fifo;
3636 priv->contexts[IWL_RXON_CTX_PAN].ac_to_queue = iwlagn_pan_ac_to_queue;
3637 priv->contexts[IWL_RXON_CTX_PAN].mcast_queue = IWL_IPAN_MCAST_QUEUE;
3638 priv->contexts[IWL_RXON_CTX_PAN].interface_modes =
3639 BIT(NL80211_IFTYPE_STATION) | BIT(NL80211_IFTYPE_AP);
3640 #ifdef CONFIG_IWL_P2P
3641 priv->contexts[IWL_RXON_CTX_PAN].interface_modes |=
3642 BIT(NL80211_IFTYPE_P2P_CLIENT) | BIT(NL80211_IFTYPE_P2P_GO);
3643 #endif
3644 priv->contexts[IWL_RXON_CTX_PAN].ap_devtype = RXON_DEV_TYPE_CP;
3645 priv->contexts[IWL_RXON_CTX_PAN].station_devtype = RXON_DEV_TYPE_2STA;
3646 priv->contexts[IWL_RXON_CTX_PAN].unused_devtype = RXON_DEV_TYPE_P2P;
3647
3648 BUILD_BUG_ON(NUM_IWL_RXON_CTX != 2);
3649
3650 SET_IEEE80211_DEV(hw, &pdev->dev);
3651
3652 IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
3653 priv->cfg = cfg;
3654 priv->pci_dev = pdev;
3655 priv->inta_mask = CSR_INI_SET_MASK;
3656
3657 /* is antenna coupling more than 35dB ? */
3658 priv->bt_ant_couple_ok =
3659 (iwlagn_ant_coupling > IWL_BT_ANTENNA_COUPLING_THRESHOLD) ?
3660 true : false;
3661
3662 /* enable/disable bt channel inhibition */
3663 priv->bt_ch_announce = iwlagn_bt_ch_announce;
3664 IWL_DEBUG_INFO(priv, "BT channel inhibition is %s\n",
3665 (priv->bt_ch_announce) ? "On" : "Off");
3666
3667 if (iwl_alloc_traffic_mem(priv))
3668 IWL_ERR(priv, "Not enough memory to generate traffic log\n");
3669
3670 /**************************
3671 * 2. Initializing PCI bus
3672 **************************/
3673 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
3674 PCIE_LINK_STATE_CLKPM);
3675
3676 if (pci_enable_device(pdev)) {
3677 err = -ENODEV;
3678 goto out_ieee80211_free_hw;
3679 }
3680
3681 pci_set_master(pdev);
3682
3683 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
3684 if (!err)
3685 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
3686 if (err) {
3687 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3688 if (!err)
3689 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
3690 /* both attempts failed: */
3691 if (err) {
3692 IWL_WARN(priv, "No suitable DMA available.\n");
3693 goto out_pci_disable_device;
3694 }
3695 }
3696
3697 err = pci_request_regions(pdev, DRV_NAME);
3698 if (err)
3699 goto out_pci_disable_device;
3700
3701 pci_set_drvdata(pdev, priv);
3702
3703
3704 /***********************
3705 * 3. Read REV register
3706 ***********************/
3707 priv->hw_base = pci_iomap(pdev, 0, 0);
3708 if (!priv->hw_base) {
3709 err = -ENODEV;
3710 goto out_pci_release_regions;
3711 }
3712
3713 IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
3714 (unsigned long long) pci_resource_len(pdev, 0));
3715 IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
3716
3717 /* these spin locks will be used in apm_ops.init and EEPROM access
3718 * we should init now
3719 */
3720 spin_lock_init(&priv->reg_lock);
3721 spin_lock_init(&priv->lock);
3722
3723 /*
3724 * stop and reset the on-board processor just in case it is in a
3725 * strange state ... like being left stranded by a primary kernel
3726 * and this is now the kdump kernel trying to start up
3727 */
3728 iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
3729
3730 hw_rev = iwl_hw_detect(priv);
3731 IWL_INFO(priv, "Detected %s, REV=0x%X\n",
3732 priv->cfg->name, hw_rev);
3733
3734 /* We disable the RETRY_TIMEOUT register (0x41) to keep
3735 * PCI Tx retries from interfering with C3 CPU state */
3736 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
3737
3738 if (iwl_prepare_card_hw(priv)) {
3739 IWL_WARN(priv, "Failed, HW not ready\n");
3740 goto out_iounmap;
3741 }
3742
3743 /*****************
3744 * 4. Read EEPROM
3745 *****************/
3746 /* Read the EEPROM */
3747 err = iwl_eeprom_init(priv, hw_rev);
3748 if (err) {
3749 IWL_ERR(priv, "Unable to init EEPROM\n");
3750 goto out_iounmap;
3751 }
3752 err = iwl_eeprom_check_version(priv);
3753 if (err)
3754 goto out_free_eeprom;
3755
3756 err = iwl_eeprom_check_sku(priv);
3757 if (err)
3758 goto out_free_eeprom;
3759
3760 /* extract MAC Address */
3761 iwl_eeprom_get_mac(priv, priv->addresses[0].addr);
3762 IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->addresses[0].addr);
3763 priv->hw->wiphy->addresses = priv->addresses;
3764 priv->hw->wiphy->n_addresses = 1;
3765 num_mac = iwl_eeprom_query16(priv, EEPROM_NUM_MAC_ADDRESS);
3766 if (num_mac > 1) {
3767 memcpy(priv->addresses[1].addr, priv->addresses[0].addr,
3768 ETH_ALEN);
3769 priv->addresses[1].addr[5]++;
3770 priv->hw->wiphy->n_addresses++;
3771 }
3772
3773 /************************
3774 * 5. Setup HW constants
3775 ************************/
3776 if (iwl_set_hw_params(priv)) {
3777 IWL_ERR(priv, "failed to set hw parameters\n");
3778 goto out_free_eeprom;
3779 }
3780
3781 /*******************
3782 * 6. Setup priv
3783 *******************/
3784
3785 err = iwl_init_drv(priv);
3786 if (err)
3787 goto out_free_eeprom;
3788 /* At this point both hw and priv are initialized. */
3789
3790 /********************
3791 * 7. Setup services
3792 ********************/
3793 spin_lock_irqsave(&priv->lock, flags);
3794 iwl_disable_interrupts(priv);
3795 spin_unlock_irqrestore(&priv->lock, flags);
3796
3797 pci_enable_msi(priv->pci_dev);
3798
3799 iwl_alloc_isr_ict(priv);
3800
3801 err = request_irq(priv->pci_dev->irq, iwl_isr_ict,
3802 IRQF_SHARED, DRV_NAME, priv);
3803 if (err) {
3804 IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
3805 goto out_disable_msi;
3806 }
3807
3808 iwl_setup_deferred_work(priv);
3809 iwl_setup_rx_handlers(priv);
3810
3811 /*********************************************
3812 * 8. Enable interrupts and read RFKILL state
3813 *********************************************/
3814
3815 /* enable rfkill interrupt: hw bug w/a */
3816 pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd);
3817 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
3818 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
3819 pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd);
3820 }
3821
3822 iwl_enable_rfkill_int(priv);
3823
3824 /* If platform's RF_KILL switch is NOT set to KILL */
3825 if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
3826 clear_bit(STATUS_RF_KILL_HW, &priv->status);
3827 else
3828 set_bit(STATUS_RF_KILL_HW, &priv->status);
3829
3830 wiphy_rfkill_set_hw_state(priv->hw->wiphy,
3831 test_bit(STATUS_RF_KILL_HW, &priv->status));
3832
3833 iwl_power_initialize(priv);
3834 iwl_tt_initialize(priv);
3835
3836 init_completion(&priv->_agn.firmware_loading_complete);
3837
3838 err = iwl_request_firmware(priv, true);
3839 if (err)
3840 goto out_destroy_workqueue;
3841
3842 return 0;
3843
3844 out_destroy_workqueue:
3845 destroy_workqueue(priv->workqueue);
3846 priv->workqueue = NULL;
3847 free_irq(priv->pci_dev->irq, priv);
3848 iwl_free_isr_ict(priv);
3849 out_disable_msi:
3850 pci_disable_msi(priv->pci_dev);
3851 iwl_uninit_drv(priv);
3852 out_free_eeprom:
3853 iwl_eeprom_free(priv);
3854 out_iounmap:
3855 pci_iounmap(pdev, priv->hw_base);
3856 out_pci_release_regions:
3857 pci_set_drvdata(pdev, NULL);
3858 pci_release_regions(pdev);
3859 out_pci_disable_device:
3860 pci_disable_device(pdev);
3861 out_ieee80211_free_hw:
3862 iwl_free_traffic_mem(priv);
3863 ieee80211_free_hw(priv->hw);
3864 out:
3865 return err;
3866 }
3867
3868 static void __devexit iwl_pci_remove(struct pci_dev *pdev)
3869 {
3870 struct iwl_priv *priv = pci_get_drvdata(pdev);
3871 unsigned long flags;
3872
3873 if (!priv)
3874 return;
3875
3876 wait_for_completion(&priv->_agn.firmware_loading_complete);
3877
3878 IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
3879
3880 iwl_dbgfs_unregister(priv);
3881 sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
3882
3883 /* ieee80211_unregister_hw call wil cause iwl_mac_stop to
3884 * to be called and iwl_down since we are removing the device
3885 * we need to set STATUS_EXIT_PENDING bit.
3886 */
3887 set_bit(STATUS_EXIT_PENDING, &priv->status);
3888
3889 iwl_leds_exit(priv);
3890
3891 if (priv->mac80211_registered) {
3892 ieee80211_unregister_hw(priv->hw);
3893 priv->mac80211_registered = 0;
3894 }
3895
3896 /* Reset to low power before unloading driver. */
3897 iwl_apm_stop(priv);
3898
3899 iwl_tt_exit(priv);
3900
3901 /* make sure we flush any pending irq or
3902 * tasklet for the driver
3903 */
3904 spin_lock_irqsave(&priv->lock, flags);
3905 iwl_disable_interrupts(priv);
3906 spin_unlock_irqrestore(&priv->lock, flags);
3907
3908 iwl_synchronize_irq(priv);
3909
3910 iwl_dealloc_ucode_pci(priv);
3911
3912 if (priv->rxq.bd)
3913 iwlagn_rx_queue_free(priv, &priv->rxq);
3914 iwlagn_hw_txq_ctx_free(priv);
3915
3916 iwl_eeprom_free(priv);
3917
3918
3919 /*netif_stop_queue(dev); */
3920 flush_workqueue(priv->workqueue);
3921
3922 /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes
3923 * priv->workqueue... so we can't take down the workqueue
3924 * until now... */
3925 destroy_workqueue(priv->workqueue);
3926 priv->workqueue = NULL;
3927 iwl_free_traffic_mem(priv);
3928
3929 free_irq(priv->pci_dev->irq, priv);
3930 pci_disable_msi(priv->pci_dev);
3931 pci_iounmap(pdev, priv->hw_base);
3932 pci_release_regions(pdev);
3933 pci_disable_device(pdev);
3934 pci_set_drvdata(pdev, NULL);
3935
3936 iwl_uninit_drv(priv);
3937
3938 iwl_free_isr_ict(priv);
3939
3940 dev_kfree_skb(priv->beacon_skb);
3941
3942 ieee80211_free_hw(priv->hw);
3943 }
3944
3945
3946 /*****************************************************************************
3947 *
3948 * driver and module entry point
3949 *
3950 *****************************************************************************/
3951
3952 /* Hardware specific file defines the PCI IDs table for that hardware module */
3953 static DEFINE_PCI_DEVICE_TABLE(iwl_hw_card_ids) = {
3954 {IWL_PCI_DEVICE(0x4232, 0x1201, iwl5100_agn_cfg)}, /* Mini Card */
3955 {IWL_PCI_DEVICE(0x4232, 0x1301, iwl5100_agn_cfg)}, /* Half Mini Card */
3956 {IWL_PCI_DEVICE(0x4232, 0x1204, iwl5100_agn_cfg)}, /* Mini Card */
3957 {IWL_PCI_DEVICE(0x4232, 0x1304, iwl5100_agn_cfg)}, /* Half Mini Card */
3958 {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bgn_cfg)}, /* Mini Card */
3959 {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bgn_cfg)}, /* Half Mini Card */
3960 {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)}, /* Mini Card */
3961 {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)}, /* Half Mini Card */
3962 {IWL_PCI_DEVICE(0x4232, 0x1221, iwl5100_agn_cfg)}, /* Mini Card */
3963 {IWL_PCI_DEVICE(0x4232, 0x1321, iwl5100_agn_cfg)}, /* Half Mini Card */
3964 {IWL_PCI_DEVICE(0x4232, 0x1224, iwl5100_agn_cfg)}, /* Mini Card */
3965 {IWL_PCI_DEVICE(0x4232, 0x1324, iwl5100_agn_cfg)}, /* Half Mini Card */
3966 {IWL_PCI_DEVICE(0x4232, 0x1225, iwl5100_bgn_cfg)}, /* Mini Card */
3967 {IWL_PCI_DEVICE(0x4232, 0x1325, iwl5100_bgn_cfg)}, /* Half Mini Card */
3968 {IWL_PCI_DEVICE(0x4232, 0x1226, iwl5100_abg_cfg)}, /* Mini Card */
3969 {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)}, /* Half Mini Card */
3970 {IWL_PCI_DEVICE(0x4237, 0x1211, iwl5100_agn_cfg)}, /* Mini Card */
3971 {IWL_PCI_DEVICE(0x4237, 0x1311, iwl5100_agn_cfg)}, /* Half Mini Card */
3972 {IWL_PCI_DEVICE(0x4237, 0x1214, iwl5100_agn_cfg)}, /* Mini Card */
3973 {IWL_PCI_DEVICE(0x4237, 0x1314, iwl5100_agn_cfg)}, /* Half Mini Card */
3974 {IWL_PCI_DEVICE(0x4237, 0x1215, iwl5100_bgn_cfg)}, /* Mini Card */
3975 {IWL_PCI_DEVICE(0x4237, 0x1315, iwl5100_bgn_cfg)}, /* Half Mini Card */
3976 {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)}, /* Mini Card */
3977 {IWL_PCI_DEVICE(0x4237, 0x1316, iwl5100_abg_cfg)}, /* Half Mini Card */
3978
3979 /* 5300 Series WiFi */
3980 {IWL_PCI_DEVICE(0x4235, 0x1021, iwl5300_agn_cfg)}, /* Mini Card */
3981 {IWL_PCI_DEVICE(0x4235, 0x1121, iwl5300_agn_cfg)}, /* Half Mini Card */
3982 {IWL_PCI_DEVICE(0x4235, 0x1024, iwl5300_agn_cfg)}, /* Mini Card */
3983 {IWL_PCI_DEVICE(0x4235, 0x1124, iwl5300_agn_cfg)}, /* Half Mini Card */
3984 {IWL_PCI_DEVICE(0x4235, 0x1001, iwl5300_agn_cfg)}, /* Mini Card */
3985 {IWL_PCI_DEVICE(0x4235, 0x1101, iwl5300_agn_cfg)}, /* Half Mini Card */
3986 {IWL_PCI_DEVICE(0x4235, 0x1004, iwl5300_agn_cfg)}, /* Mini Card */
3987 {IWL_PCI_DEVICE(0x4235, 0x1104, iwl5300_agn_cfg)}, /* Half Mini Card */
3988 {IWL_PCI_DEVICE(0x4236, 0x1011, iwl5300_agn_cfg)}, /* Mini Card */
3989 {IWL_PCI_DEVICE(0x4236, 0x1111, iwl5300_agn_cfg)}, /* Half Mini Card */
3990 {IWL_PCI_DEVICE(0x4236, 0x1014, iwl5300_agn_cfg)}, /* Mini Card */
3991 {IWL_PCI_DEVICE(0x4236, 0x1114, iwl5300_agn_cfg)}, /* Half Mini Card */
3992
3993 /* 5350 Series WiFi/WiMax */
3994 {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)}, /* Mini Card */
3995 {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)}, /* Mini Card */
3996 {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)}, /* Mini Card */
3997
3998 /* 5150 Series Wifi/WiMax */
3999 {IWL_PCI_DEVICE(0x423C, 0x1201, iwl5150_agn_cfg)}, /* Mini Card */
4000 {IWL_PCI_DEVICE(0x423C, 0x1301, iwl5150_agn_cfg)}, /* Half Mini Card */
4001 {IWL_PCI_DEVICE(0x423C, 0x1206, iwl5150_abg_cfg)}, /* Mini Card */
4002 {IWL_PCI_DEVICE(0x423C, 0x1306, iwl5150_abg_cfg)}, /* Half Mini Card */
4003 {IWL_PCI_DEVICE(0x423C, 0x1221, iwl5150_agn_cfg)}, /* Mini Card */
4004 {IWL_PCI_DEVICE(0x423C, 0x1321, iwl5150_agn_cfg)}, /* Half Mini Card */
4005
4006 {IWL_PCI_DEVICE(0x423D, 0x1211, iwl5150_agn_cfg)}, /* Mini Card */
4007 {IWL_PCI_DEVICE(0x423D, 0x1311, iwl5150_agn_cfg)}, /* Half Mini Card */
4008 {IWL_PCI_DEVICE(0x423D, 0x1216, iwl5150_abg_cfg)}, /* Mini Card */
4009 {IWL_PCI_DEVICE(0x423D, 0x1316, iwl5150_abg_cfg)}, /* Half Mini Card */
4010
4011 /* 6x00 Series */
4012 {IWL_PCI_DEVICE(0x422B, 0x1101, iwl6000_3agn_cfg)},
4013 {IWL_PCI_DEVICE(0x422B, 0x1121, iwl6000_3agn_cfg)},
4014 {IWL_PCI_DEVICE(0x422C, 0x1301, iwl6000i_2agn_cfg)},
4015 {IWL_PCI_DEVICE(0x422C, 0x1306, iwl6000i_2abg_cfg)},
4016 {IWL_PCI_DEVICE(0x422C, 0x1307, iwl6000i_2bg_cfg)},
4017 {IWL_PCI_DEVICE(0x422C, 0x1321, iwl6000i_2agn_cfg)},
4018 {IWL_PCI_DEVICE(0x422C, 0x1326, iwl6000i_2abg_cfg)},
4019 {IWL_PCI_DEVICE(0x4238, 0x1111, iwl6000_3agn_cfg)},
4020 {IWL_PCI_DEVICE(0x4239, 0x1311, iwl6000i_2agn_cfg)},
4021 {IWL_PCI_DEVICE(0x4239, 0x1316, iwl6000i_2abg_cfg)},
4022
4023 /* 6x05 Series */
4024 {IWL_PCI_DEVICE(0x0082, 0x1301, iwl6005_2agn_cfg)},
4025 {IWL_PCI_DEVICE(0x0082, 0x1306, iwl6005_2abg_cfg)},
4026 {IWL_PCI_DEVICE(0x0082, 0x1307, iwl6005_2bg_cfg)},
4027 {IWL_PCI_DEVICE(0x0082, 0x1321, iwl6005_2agn_cfg)},
4028 {IWL_PCI_DEVICE(0x0082, 0x1326, iwl6005_2abg_cfg)},
4029 {IWL_PCI_DEVICE(0x0085, 0x1311, iwl6005_2agn_cfg)},
4030 {IWL_PCI_DEVICE(0x0085, 0x1316, iwl6005_2abg_cfg)},
4031
4032 /* 6x30 Series */
4033 {IWL_PCI_DEVICE(0x008A, 0x5305, iwl1030_bgn_cfg)},
4034 {IWL_PCI_DEVICE(0x008A, 0x5307, iwl1030_bg_cfg)},
4035 {IWL_PCI_DEVICE(0x008A, 0x5325, iwl1030_bgn_cfg)},
4036 {IWL_PCI_DEVICE(0x008A, 0x5327, iwl1030_bg_cfg)},
4037 {IWL_PCI_DEVICE(0x008B, 0x5315, iwl1030_bgn_cfg)},
4038 {IWL_PCI_DEVICE(0x008B, 0x5317, iwl1030_bg_cfg)},
4039 {IWL_PCI_DEVICE(0x0090, 0x5211, iwl6030_2agn_cfg)},
4040 {IWL_PCI_DEVICE(0x0090, 0x5215, iwl6030_2bgn_cfg)},
4041 {IWL_PCI_DEVICE(0x0090, 0x5216, iwl6030_2abg_cfg)},
4042 {IWL_PCI_DEVICE(0x0091, 0x5201, iwl6030_2agn_cfg)},
4043 {IWL_PCI_DEVICE(0x0091, 0x5205, iwl6030_2bgn_cfg)},
4044 {IWL_PCI_DEVICE(0x0091, 0x5206, iwl6030_2abg_cfg)},
4045 {IWL_PCI_DEVICE(0x0091, 0x5207, iwl6030_2bg_cfg)},
4046 {IWL_PCI_DEVICE(0x0091, 0x5221, iwl6030_2agn_cfg)},
4047 {IWL_PCI_DEVICE(0x0091, 0x5225, iwl6030_2bgn_cfg)},
4048 {IWL_PCI_DEVICE(0x0091, 0x5226, iwl6030_2abg_cfg)},
4049
4050 /* 6x50 WiFi/WiMax Series */
4051 {IWL_PCI_DEVICE(0x0087, 0x1301, iwl6050_2agn_cfg)},
4052 {IWL_PCI_DEVICE(0x0087, 0x1306, iwl6050_2abg_cfg)},
4053 {IWL_PCI_DEVICE(0x0087, 0x1321, iwl6050_2agn_cfg)},
4054 {IWL_PCI_DEVICE(0x0087, 0x1326, iwl6050_2abg_cfg)},
4055 {IWL_PCI_DEVICE(0x0089, 0x1311, iwl6050_2agn_cfg)},
4056 {IWL_PCI_DEVICE(0x0089, 0x1316, iwl6050_2abg_cfg)},
4057
4058 /* 6150 WiFi/WiMax Series */
4059 {IWL_PCI_DEVICE(0x0885, 0x1305, iwl6150_bgn_cfg)},
4060 {IWL_PCI_DEVICE(0x0885, 0x1306, iwl6150_bgn_cfg)},
4061 {IWL_PCI_DEVICE(0x0885, 0x1325, iwl6150_bgn_cfg)},
4062 {IWL_PCI_DEVICE(0x0885, 0x1326, iwl6150_bgn_cfg)},
4063 {IWL_PCI_DEVICE(0x0886, 0x1315, iwl6150_bgn_cfg)},
4064 {IWL_PCI_DEVICE(0x0886, 0x1316, iwl6150_bgn_cfg)},
4065
4066 /* 1000 Series WiFi */
4067 {IWL_PCI_DEVICE(0x0083, 0x1205, iwl1000_bgn_cfg)},
4068 {IWL_PCI_DEVICE(0x0083, 0x1305, iwl1000_bgn_cfg)},
4069 {IWL_PCI_DEVICE(0x0083, 0x1225, iwl1000_bgn_cfg)},
4070 {IWL_PCI_DEVICE(0x0083, 0x1325, iwl1000_bgn_cfg)},
4071 {IWL_PCI_DEVICE(0x0084, 0x1215, iwl1000_bgn_cfg)},
4072 {IWL_PCI_DEVICE(0x0084, 0x1315, iwl1000_bgn_cfg)},
4073 {IWL_PCI_DEVICE(0x0083, 0x1206, iwl1000_bg_cfg)},
4074 {IWL_PCI_DEVICE(0x0083, 0x1306, iwl1000_bg_cfg)},
4075 {IWL_PCI_DEVICE(0x0083, 0x1226, iwl1000_bg_cfg)},
4076 {IWL_PCI_DEVICE(0x0083, 0x1326, iwl1000_bg_cfg)},
4077 {IWL_PCI_DEVICE(0x0084, 0x1216, iwl1000_bg_cfg)},
4078 {IWL_PCI_DEVICE(0x0084, 0x1316, iwl1000_bg_cfg)},
4079
4080 /* 100 Series WiFi */
4081 {IWL_PCI_DEVICE(0x08AE, 0x1005, iwl100_bgn_cfg)},
4082 {IWL_PCI_DEVICE(0x08AE, 0x1007, iwl100_bg_cfg)},
4083 {IWL_PCI_DEVICE(0x08AF, 0x1015, iwl100_bgn_cfg)},
4084 {IWL_PCI_DEVICE(0x08AF, 0x1017, iwl100_bg_cfg)},
4085 {IWL_PCI_DEVICE(0x08AE, 0x1025, iwl100_bgn_cfg)},
4086 {IWL_PCI_DEVICE(0x08AE, 0x1027, iwl100_bg_cfg)},
4087
4088 /* 130 Series WiFi */
4089 {IWL_PCI_DEVICE(0x0896, 0x5005, iwl130_bgn_cfg)},
4090 {IWL_PCI_DEVICE(0x0896, 0x5007, iwl130_bg_cfg)},
4091 {IWL_PCI_DEVICE(0x0897, 0x5015, iwl130_bgn_cfg)},
4092 {IWL_PCI_DEVICE(0x0897, 0x5017, iwl130_bg_cfg)},
4093 {IWL_PCI_DEVICE(0x0896, 0x5025, iwl130_bgn_cfg)},
4094 {IWL_PCI_DEVICE(0x0896, 0x5027, iwl130_bg_cfg)},
4095
4096 /* 2x00 Series */
4097 {IWL_PCI_DEVICE(0x0890, 0x4022, iwl2000_2bgn_cfg)},
4098 {IWL_PCI_DEVICE(0x0891, 0x4222, iwl2000_2bgn_cfg)},
4099 {IWL_PCI_DEVICE(0x0890, 0x4422, iwl2000_2bgn_cfg)},
4100 {IWL_PCI_DEVICE(0x0890, 0x4026, iwl2000_2bg_cfg)},
4101 {IWL_PCI_DEVICE(0x0891, 0x4226, iwl2000_2bg_cfg)},
4102 {IWL_PCI_DEVICE(0x0890, 0x4426, iwl2000_2bg_cfg)},
4103
4104 /* 2x30 Series */
4105 {IWL_PCI_DEVICE(0x0887, 0x4062, iwl2030_2bgn_cfg)},
4106 {IWL_PCI_DEVICE(0x0888, 0x4262, iwl2030_2bgn_cfg)},
4107 {IWL_PCI_DEVICE(0x0887, 0x4462, iwl2030_2bgn_cfg)},
4108 {IWL_PCI_DEVICE(0x0887, 0x4066, iwl2030_2bg_cfg)},
4109 {IWL_PCI_DEVICE(0x0888, 0x4266, iwl2030_2bg_cfg)},
4110 {IWL_PCI_DEVICE(0x0887, 0x4466, iwl2030_2bg_cfg)},
4111
4112 /* 6x35 Series */
4113 {IWL_PCI_DEVICE(0x088E, 0x4060, iwl6035_2agn_cfg)},
4114 {IWL_PCI_DEVICE(0x088F, 0x4260, iwl6035_2agn_cfg)},
4115 {IWL_PCI_DEVICE(0x088E, 0x4460, iwl6035_2agn_cfg)},
4116 {IWL_PCI_DEVICE(0x088E, 0x4064, iwl6035_2abg_cfg)},
4117 {IWL_PCI_DEVICE(0x088F, 0x4264, iwl6035_2abg_cfg)},
4118 {IWL_PCI_DEVICE(0x088E, 0x4464, iwl6035_2abg_cfg)},
4119 {IWL_PCI_DEVICE(0x088E, 0x4066, iwl6035_2bg_cfg)},
4120 {IWL_PCI_DEVICE(0x088F, 0x4266, iwl6035_2bg_cfg)},
4121 {IWL_PCI_DEVICE(0x088E, 0x4466, iwl6035_2bg_cfg)},
4122
4123 /* 200 Series */
4124 {IWL_PCI_DEVICE(0x0894, 0x0022, iwl200_bgn_cfg)},
4125 {IWL_PCI_DEVICE(0x0895, 0x0222, iwl200_bgn_cfg)},
4126 {IWL_PCI_DEVICE(0x0894, 0x0422, iwl200_bgn_cfg)},
4127 {IWL_PCI_DEVICE(0x0894, 0x0026, iwl200_bg_cfg)},
4128 {IWL_PCI_DEVICE(0x0895, 0x0226, iwl200_bg_cfg)},
4129 {IWL_PCI_DEVICE(0x0894, 0x0426, iwl200_bg_cfg)},
4130
4131 /* 230 Series */
4132 {IWL_PCI_DEVICE(0x0892, 0x0062, iwl230_bgn_cfg)},
4133 {IWL_PCI_DEVICE(0x0893, 0x0262, iwl230_bgn_cfg)},
4134 {IWL_PCI_DEVICE(0x0892, 0x0462, iwl230_bgn_cfg)},
4135 {IWL_PCI_DEVICE(0x0892, 0x0066, iwl230_bg_cfg)},
4136 {IWL_PCI_DEVICE(0x0893, 0x0266, iwl230_bg_cfg)},
4137 {IWL_PCI_DEVICE(0x0892, 0x0466, iwl230_bg_cfg)},
4138
4139 {0}
4140 };
4141 MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
4142
4143 static struct pci_driver iwl_driver = {
4144 .name = DRV_NAME,
4145 .id_table = iwl_hw_card_ids,
4146 .probe = iwl_pci_probe,
4147 .remove = __devexit_p(iwl_pci_remove),
4148 .driver.pm = IWL_PM_OPS,
4149 };
4150
4151 static int __init iwl_init(void)
4152 {
4153
4154 int ret;
4155 pr_info(DRV_DESCRIPTION ", " DRV_VERSION "\n");
4156 pr_info(DRV_COPYRIGHT "\n");
4157
4158 ret = iwlagn_rate_control_register();
4159 if (ret) {
4160 pr_err("Unable to register rate control algorithm: %d\n", ret);
4161 return ret;
4162 }
4163
4164 ret = pci_register_driver(&iwl_driver);
4165 if (ret) {
4166 pr_err("Unable to initialize PCI module\n");
4167 goto error_register;
4168 }
4169
4170 return ret;
4171
4172 error_register:
4173 iwlagn_rate_control_unregister();
4174 return ret;
4175 }
4176
4177 static void __exit iwl_exit(void)
4178 {
4179 pci_unregister_driver(&iwl_driver);
4180 iwlagn_rate_control_unregister();
4181 }
4182
4183 module_exit(iwl_exit);
4184 module_init(iwl_init);
4185
4186 #ifdef CONFIG_IWLWIFI_DEBUG
4187 module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR);
4188 MODULE_PARM_DESC(debug, "debug output mask");
4189 #endif
4190
4191 module_param_named(swcrypto, iwlagn_mod_params.sw_crypto, int, S_IRUGO);
4192 MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])");
4193 module_param_named(queues_num, iwlagn_mod_params.num_of_queues, int, S_IRUGO);
4194 MODULE_PARM_DESC(queues_num, "number of hw queues.");
4195 module_param_named(11n_disable, iwlagn_mod_params.disable_11n, int, S_IRUGO);
4196 MODULE_PARM_DESC(11n_disable, "disable 11n functionality");
4197 module_param_named(amsdu_size_8K, iwlagn_mod_params.amsdu_size_8K,
4198 int, S_IRUGO);
4199 MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");
4200 module_param_named(fw_restart, iwlagn_mod_params.restart_fw, int, S_IRUGO);
4201 MODULE_PARM_DESC(fw_restart, "restart firmware in case of error");
4202
4203 module_param_named(ucode_alternative, iwlagn_wanted_ucode_alternative, int,
4204 S_IRUGO);
4205 MODULE_PARM_DESC(ucode_alternative,
4206 "specify ucode alternative to use from ucode file");
4207
4208 module_param_named(antenna_coupling, iwlagn_ant_coupling, int, S_IRUGO);
4209 MODULE_PARM_DESC(antenna_coupling,
4210 "specify antenna coupling in dB (defualt: 0 dB)");
4211
4212 module_param_named(bt_ch_inhibition, iwlagn_bt_ch_announce, bool, S_IRUGO);
4213 MODULE_PARM_DESC(bt_ch_inhibition,
4214 "Disable BT channel inhibition (default: enable)");
4215
4216 module_param_named(plcp_check, iwlagn_mod_params.plcp_check, bool, S_IRUGO);
4217 MODULE_PARM_DESC(plcp_check, "Check plcp health (default: 1 [enabled])");
4218
4219 module_param_named(ack_check, iwlagn_mod_params.ack_check, bool, S_IRUGO);
4220 MODULE_PARM_DESC(ack_check, "Check ack health (default: 0 [disabled])");
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree