drivers/serial/sh-sci.h

   1 #include <linux/serial_core.h>
   2 #include <asm/io.h>
   3 #include <asm/gpio.h>
   4
   5 #if defined(CONFIG_H83007) || defined(CONFIG_H83068)
   6 #include <asm/regs306x.h>
   7 #endif
   8 #if defined(CONFIG_H8S2678)
   9 #include <asm/regs267x.h>
  10 #endif
  11
  12 #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
  13     defined(CONFIG_CPU_SUBTYPE_SH7707) || \
  14     defined(CONFIG_CPU_SUBTYPE_SH7708) || \
  15     defined(CONFIG_CPU_SUBTYPE_SH7709)
  16 # define SCPCR  0xA4000116 /* 16 bit SCI and SCIF */
  17 # define SCPDR  0xA4000136 /* 8  bit SCI and SCIF */
  18 # define SCSCR_INIT(port)          0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
  19 #elif defined(CONFIG_CPU_SUBTYPE_SH7705)
  20 # define SCIF0          0xA4400000
  21 # define SCIF2          0xA4410000
  22 # define SCSMR_Ir       0xA44A0000
  23 # define IRDA_SCIF      SCIF0
  24 # define SCPCR 0xA4000116
  25 # define SCPDR 0xA4000136
  26
  27 /* Set the clock source,
  28  * SCIF2 (0xA4410000) -> External clock, SCK pin used as clock input
  29  * SCIF0 (0xA4400000) -> Internal clock, SCK pin as serial clock output
  30  */
  31 # define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0
  32 #elif defined(CONFIG_CPU_SUBTYPE_SH7720) || \
  33       defined(CONFIG_CPU_SUBTYPE_SH7721)
  34 # define SCSCR_INIT(port)  0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */
  35 #define SCIF_ORER    0x0200   /* overrun error bit */
  36 #elif defined(CONFIG_SH_RTS7751R2D)
  37 # define SCSPTR1 0xFFE0001C /* 8 bit SCIF */
  38 # define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
  39 # define SCIF_ORER 0x0001   /* overrun error bit */
  40 # define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
  41 #elif defined(CONFIG_CPU_SUBTYPE_SH7750)  || \
  42       defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
  43       defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
  44       defined(CONFIG_CPU_SUBTYPE_SH7091)  || \
  45       defined(CONFIG_CPU_SUBTYPE_SH7751)  || \
  46       defined(CONFIG_CPU_SUBTYPE_SH7751R)
  47 # define SCSPTR1 0xffe0001c /* 8  bit SCI */
  48 # define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
  49 # define SCIF_ORER 0x0001   /* overrun error bit */
  50 # define SCSCR_INIT(port) (((port)->type == PORT_SCI) ? \
  51         0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \
  52         0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ )
  53 #elif defined(CONFIG_CPU_SUBTYPE_SH7760)
  54 # define SCSPTR0 0xfe600024 /* 16 bit SCIF */
  55 # define SCSPTR1 0xfe610024 /* 16 bit SCIF */
  56 # define SCSPTR2 0xfe620024 /* 16 bit SCIF */
  57 # define SCIF_ORER 0x0001  /* overrun error bit */
  58 # define SCSCR_INIT(port)          0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
  59 #elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
  60 # define SCSPTR0 0xA4400000       /* 16 bit SCIF */
  61 # define SCIF_ORER 0x0001   /* overrun error bit */
  62 # define PACR 0xa4050100
  63 # define PBCR 0xa4050102
  64 # define SCSCR_INIT(port)          0x3B
  65 #elif defined(CONFIG_CPU_SUBTYPE_SH7343)
  66 # define SCSPTR0 0xffe00010     /* 16 bit SCIF */
  67 # define SCSPTR1 0xffe10010     /* 16 bit SCIF */
  68 # define SCSPTR2 0xffe20010     /* 16 bit SCIF */
  69 # define SCSPTR3 0xffe30010     /* 16 bit SCIF */
  70 # define SCSCR_INIT(port) 0x32  /* TIE=0,RIE=0,TE=1,RE=1,REIE=0,CKE=1 */
  71 #elif defined(CONFIG_CPU_SUBTYPE_SH7722)
  72 # define PADR                   0xA4050120
  73 # define PSDR                   0xA405013e
  74 # define PWDR                   0xA4050166
  75 # define PSCR                   0xA405011E
  76 # define SCIF_ORER              0x0001  /* overrun error bit */
  77 # define SCSCR_INIT(port)       0x0038  /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
  78 #elif defined(CONFIG_CPU_SUBTYPE_SH7366)
  79 # define SCPDR0                 0xA405013E      /* 16 bit SCIF0 PSDR */
  80 # define SCSPTR0                SCPDR0
  81 # define SCIF_ORER              0x0001  /* overrun error bit */
  82 # define SCSCR_INIT(port)       0x0038  /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
  83 #elif defined(CONFIG_CPU_SUBTYPE_SH7723)
  84 # define SCSPTR0                0xa4050160
  85 # define SCSPTR1                0xa405013e
  86 # define SCSPTR2                0xa4050160
  87 # define SCSPTR3                0xa405013e
  88 # define SCSPTR4                0xa4050128
  89 # define SCSPTR5                0xa4050128
  90 # define SCIF_ORER              0x0001  /* overrun error bit */
  91 # define SCSCR_INIT(port)       0x0038  /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
  92 #elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
  93 # define SCSPTR2 0xffe80020 /* 16 bit SCIF */
  94 # define SCIF_ORER 0x0001   /* overrun error bit */
  95 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
  96 #elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
  97 # define SCIF_BASE_ADDR    0x01030000
  98 # define SCIF_ADDR_SH5     PHYS_PERIPHERAL_BLOCK+SCIF_BASE_ADDR
  99 # define SCIF_PTR2_OFFS    0x0000020
 100 # define SCIF_LSR2_OFFS    0x0000024
 101 # define SCSPTR2           ((port->mapbase)+SCIF_PTR2_OFFS) /* 16 bit SCIF */
 102 # define SCLSR2            ((port->mapbase)+SCIF_LSR2_OFFS) /* 16 bit SCIF */
 103 # define SCSCR_INIT(port)  0x38         /* TIE=0,RIE=0, TE=1,RE=1,REIE=1 */
 104 #elif defined(CONFIG_H83007) || defined(CONFIG_H83068)
 105 # define SCSCR_INIT(port)          0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
 106 # define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
 107 #elif defined(CONFIG_H8S2678)
 108 # define SCSCR_INIT(port)          0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
 109 # define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
 110 #elif defined(CONFIG_CPU_SUBTYPE_SH7763)
 111 # define SCSPTR0 0xffe00024 /* 16 bit SCIF */
 112 # define SCSPTR1 0xffe08024 /* 16 bit SCIF */
 113 # define SCSPTR2 0xffe10020 /* 16 bit SCIF/IRDA */
 114 # define SCIF_ORER 0x0001  /* overrun error bit */
 115 # define SCSCR_INIT(port)       0x38    /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
 116 #elif defined(CONFIG_CPU_SUBTYPE_SH7770)
 117 # define SCSPTR0 0xff923020 /* 16 bit SCIF */
 118 # define SCSPTR1 0xff924020 /* 16 bit SCIF */
 119 # define SCSPTR2 0xff925020 /* 16 bit SCIF */
 120 # define SCIF_ORER 0x0001  /* overrun error bit */
 121 # define SCSCR_INIT(port)       0x3c /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,cke=2 */
 122 #elif defined(CONFIG_CPU_SUBTYPE_SH7780)
 123 # define SCSPTR0        0xffe00024      /* 16 bit SCIF */
 124 # define SCSPTR1        0xffe10024      /* 16 bit SCIF */
 125 # define SCIF_ORER      0x0001          /* Overrun error bit */
 126 # define SCSCR_INIT(port)       0x3a    /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
 127 #elif defined(CONFIG_CPU_SUBTYPE_SH7785)
 128 # define SCSPTR0        0xffea0024      /* 16 bit SCIF */
 129 # define SCSPTR1        0xffeb0024      /* 16 bit SCIF */
 130 # define SCSPTR2        0xffec0024      /* 16 bit SCIF */
 131 # define SCSPTR3        0xffed0024      /* 16 bit SCIF */
 132 # define SCSPTR4        0xffee0024      /* 16 bit SCIF */
 133 # define SCSPTR5        0xffef0024      /* 16 bit SCIF */
 134 # define SCIF_OPER      0x0001          /* Overrun error bit */
 135 # define SCSCR_INIT(port)       0x3a    /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
 136 #elif defined(CONFIG_CPU_SUBTYPE_SH7203) || \
 137       defined(CONFIG_CPU_SUBTYPE_SH7206) || \
 138       defined(CONFIG_CPU_SUBTYPE_SH7263)
 139 # define SCSPTR0 0xfffe8020 /* 16 bit SCIF */
 140 # define SCSPTR1 0xfffe8820 /* 16 bit SCIF */
 141 # define SCSPTR2 0xfffe9020 /* 16 bit SCIF */
 142 # define SCSPTR3 0xfffe9820 /* 16 bit SCIF */
 143 # define SCSCR_INIT(port)       0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
 144 #elif defined(CONFIG_CPU_SUBTYPE_SH7619)
 145 # define SCSPTR0 0xf8400020 /* 16 bit SCIF */
 146 # define SCSPTR1 0xf8410020 /* 16 bit SCIF */
 147 # define SCSPTR2 0xf8420020 /* 16 bit SCIF */
 148 # define SCIF_ORER 0x0001  /* overrun error bit */
 149 # define SCSCR_INIT(port)       0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
 150 #elif defined(CONFIG_CPU_SUBTYPE_SHX3)
 151 # define SCSPTR0 0xffc30020             /* 16 bit SCIF */
 152 # define SCSPTR1 0xffc40020             /* 16 bit SCIF */
 153 # define SCSPTR2 0xffc50020             /* 16 bit SCIF */
 154 # define SCSPTR3 0xffc60020             /* 16 bit SCIF */
 155 # define SCIF_ORER 0x0001               /* Overrun error bit */
 156 # define SCSCR_INIT(port)       0x38    /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
 157 #else
 158 # error CPU subtype not defined
 159 #endif
 160
 161 /* SCSCR */
 162 #define SCI_CTRL_FLAGS_TIE  0x80 /* all */
 163 #define SCI_CTRL_FLAGS_RIE  0x40 /* all */
 164 #define SCI_CTRL_FLAGS_TE   0x20 /* all */
 165 #define SCI_CTRL_FLAGS_RE   0x10 /* all */
 166 #if defined(CONFIG_CPU_SUBTYPE_SH7750)  || \
 167     defined(CONFIG_CPU_SUBTYPE_SH7091)  || \
 168     defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
 169     defined(CONFIG_CPU_SUBTYPE_SH7722)  || \
 170     defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
 171     defined(CONFIG_CPU_SUBTYPE_SH7751)  || \
 172     defined(CONFIG_CPU_SUBTYPE_SH7751R) || \
 173     defined(CONFIG_CPU_SUBTYPE_SH7763)  || \
 174     defined(CONFIG_CPU_SUBTYPE_SH7780)  || \
 175     defined(CONFIG_CPU_SUBTYPE_SH7785)  || \
 176     defined(CONFIG_CPU_SUBTYPE_SHX3)
 177 #define SCI_CTRL_FLAGS_REIE 0x08 /* 7750 SCIF */
 178 #else
 179 #define SCI_CTRL_FLAGS_REIE 0
 180 #endif
 181 /*      SCI_CTRL_FLAGS_MPIE 0x08  * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 182 /*      SCI_CTRL_FLAGS_TEIE 0x04  * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 183 /*      SCI_CTRL_FLAGS_CKE1 0x02  * all */
 184 /*      SCI_CTRL_FLAGS_CKE0 0x01  * 7707 SCI/SCIF, 7708 SCI, 7709 SCI/SCIF, 7750 SCI */
 185
 186 /* SCxSR SCI */
 187 #define SCI_TDRE  0x80 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 188 #define SCI_RDRF  0x40 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 189 #define SCI_ORER  0x20 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 190 #define SCI_FER   0x10 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 191 #define SCI_PER   0x08 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 192 #define SCI_TEND  0x04 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 193 /*      SCI_MPB   0x02  * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 194 /*      SCI_MPBT  0x01  * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 195
 196 #define SCI_ERRORS ( SCI_PER | SCI_FER | SCI_ORER)
 197
 198 /* SCxSR SCIF */
 199 #define SCIF_ER    0x0080 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
 200 #define SCIF_TEND  0x0040 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
 201 #define SCIF_TDFE  0x0020 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
 202 #define SCIF_BRK   0x0010 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
 203 #define SCIF_FER   0x0008 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
 204 #define SCIF_PER   0x0004 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
 205 #define SCIF_RDF   0x0002 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
 206 #define SCIF_DR    0x0001 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
 207
 208 #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
 209     defined(CONFIG_CPU_SUBTYPE_SH7720) || \
 210     defined(CONFIG_CPU_SUBTYPE_SH7721)
 211 # define SCIF_ORER    0x0200
 212 # define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER)
 213 # define SCIF_RFDC_MASK 0x007f
 214 # define SCIF_TXROOM_MAX 64
 215 #elif defined(CONFIG_CPU_SUBTYPE_SH7763)
 216 # define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK )
 217 # define SCIF_RFDC_MASK 0x007f
 218 # define SCIF_TXROOM_MAX 64
 219 /* SH7763 SCIF2 support */
 220 # define SCIF2_RFDC_MASK 0x001f
 221 # define SCIF2_TXROOM_MAX 16
 222 #else
 223 # define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
 224 # define SCIF_RFDC_MASK 0x001f
 225 # define SCIF_TXROOM_MAX 16
 226 #endif
 227
 228 #define SCxSR_TEND(port)        (((port)->type == PORT_SCI) ? SCI_TEND   : SCIF_TEND)
 229 #define SCxSR_ERRORS(port)      (((port)->type == PORT_SCI) ? SCI_ERRORS : SCIF_ERRORS)
 230 #define SCxSR_RDxF(port)        (((port)->type == PORT_SCI) ? SCI_RDRF   : SCIF_RDF)
 231 #define SCxSR_TDxE(port)        (((port)->type == PORT_SCI) ? SCI_TDRE   : SCIF_TDFE)
 232 #define SCxSR_FER(port)         (((port)->type == PORT_SCI) ? SCI_FER    : SCIF_FER)
 233 #define SCxSR_PER(port)         (((port)->type == PORT_SCI) ? SCI_PER    : SCIF_PER)
 234 #define SCxSR_BRK(port)         (((port)->type == PORT_SCI) ? 0x00       : SCIF_BRK)
 235
 236 #if defined(CONFIG_CPU_SUBTYPE_SH7705)
 237 # define SCxSR_ORER(port)       (((port)->type == PORT_SCI) ? SCI_ORER : SCIF_ORER)
 238 #else
 239 # define SCxSR_ORER(port)       (((port)->type == PORT_SCI) ? SCI_ORER : 0x0000)
 240 #endif
 241
 242 #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
 243     defined(CONFIG_CPU_SUBTYPE_SH7720) || \
 244     defined(CONFIG_CPU_SUBTYPE_SH7721)
 245 # define SCxSR_RDxF_CLEAR(port)  (sci_in(port, SCxSR) & 0xfffc)
 246 # define SCxSR_ERROR_CLEAR(port) (sci_in(port, SCxSR) & 0xfd73)
 247 # define SCxSR_TDxE_CLEAR(port)  (sci_in(port, SCxSR) & 0xffdf)
 248 # define SCxSR_BREAK_CLEAR(port) (sci_in(port, SCxSR) & 0xffe3)
 249 #else
 250 # define SCxSR_RDxF_CLEAR(port)  (((port)->type == PORT_SCI) ? 0xbc : 0x00fc)
 251 # define SCxSR_ERROR_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x0073)
 252 # define SCxSR_TDxE_CLEAR(port)  (((port)->type == PORT_SCI) ? 0x78 : 0x00df)
 253 # define SCxSR_BREAK_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x00e3)
 254 #endif
 255
 256 /* SCFCR */
 257 #define SCFCR_RFRST 0x0002
 258 #define SCFCR_TFRST 0x0004
 259 #define SCFCR_TCRST 0x4000
 260 #define SCFCR_MCE   0x0008
 261
 262 #define SCI_MAJOR               204
 263 #define SCI_MINOR_START         8
 264
 265 /* Generic serial flags */
 266 #define SCI_RX_THROTTLE         0x0000001
 267
 268 #define SCI_MAGIC 0xbabeface
 269
 270 /*
 271  * Events are used to schedule things to happen at timer-interrupt
 272  * time, instead of at rs interrupt time.
 273  */
 274 #define SCI_EVENT_WRITE_WAKEUP  0
 275
 276 #define SCI_IN(size, offset)                                    \
 277   if ((size) == 8) {                                            \
 278     return ioread8(port->membase + (offset));                   \
 279   } else {                                                      \
 280     return ioread16(port->membase + (offset));                  \
 281   }
 282 #define SCI_OUT(size, offset, value)                            \
 283   if ((size) == 8) {                                            \
 284     iowrite8(value, port->membase + (offset));                  \
 285   } else if ((size) == 16) {                                    \
 286     iowrite16(value, port->membase + (offset));                 \
 287   }
 288
 289 #define CPU_SCIx_FNS(name, sci_offset, sci_size, scif_offset, scif_size)\
 290   static inline unsigned int sci_##name##_in(struct uart_port *port)    \
 291   {                                                                     \
 292     if (port->type == PORT_SCIF) {                                      \
 293       SCI_IN(scif_size, scif_offset)                                    \
 294     } else {    /* PORT_SCI or PORT_SCIFA */                            \
 295       SCI_IN(sci_size, sci_offset);                                     \
 296     }                                                                   \
 297   }                                                                     \
 298   static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \
 299   {                                                                     \
 300     if (port->type == PORT_SCIF) {                                      \
 301       SCI_OUT(scif_size, scif_offset, value)                            \
 302     } else {    /* PORT_SCI or PORT_SCIFA */                            \
 303       SCI_OUT(sci_size, sci_offset, value);                             \
 304     }                                                                   \
 305   }
 306
 307 #define CPU_SCIF_FNS(name, scif_offset, scif_size)                              \
 308   static inline unsigned int sci_##name##_in(struct uart_port *port)    \
 309   {                                                                     \
 310     SCI_IN(scif_size, scif_offset);                                     \
 311   }                                                                     \
 312   static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \
 313   {                                                                     \
 314     SCI_OUT(scif_size, scif_offset, value);                             \
 315   }
 316
 317 #define CPU_SCI_FNS(name, sci_offset, sci_size)                         \
 318   static inline unsigned int sci_##name##_in(struct uart_port* port)    \
 319   {                                                                     \
 320     SCI_IN(sci_size, sci_offset);                                       \
 321   }                                                                     \
 322   static inline void sci_##name##_out(struct uart_port* port, unsigned int value) \
 323   {                                                                     \
 324     SCI_OUT(sci_size, sci_offset, value);                               \
 325   }
 326
 327 #ifdef CONFIG_CPU_SH3
 328 #if defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
 329 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
 330                                 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
 331                                  h8_sci_offset, h8_sci_size) \
 332   CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size)
 333 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
 334           CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
 335 #elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
 336       defined(CONFIG_CPU_SUBTYPE_SH7720) || \
 337       defined(CONFIG_CPU_SUBTYPE_SH7721)
 338 #define SCIF_FNS(name, scif_offset, scif_size) \
 339   CPU_SCIF_FNS(name, scif_offset, scif_size)
 340 #else
 341 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
 342                  sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
 343                  h8_sci_offset, h8_sci_size) \
 344   CPU_SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh3_scif_offset, sh3_scif_size)
 345 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
 346   CPU_SCIF_FNS(name, sh3_scif_offset, sh3_scif_size)
 347 #endif
 348 #elif defined(__H8300H__) || defined(__H8300S__)
 349 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
 350                  sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
 351                  h8_sci_offset, h8_sci_size) \
 352   CPU_SCI_FNS(name, h8_sci_offset, h8_sci_size)
 353 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size)
 354 #elif defined(CONFIG_CPU_SUBTYPE_SH7723)
 355         #define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scif_offset, sh4_scif_size) \
 356                 CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scif_offset, sh4_scif_size)
 357         #define SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) \
 358                 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
 359 #else
 360 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
 361                  sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
 362                  h8_sci_offset, h8_sci_size) \
 363   CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size)
 364 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
 365   CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
 366 #endif
 367
 368 #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
 369     defined(CONFIG_CPU_SUBTYPE_SH7720) || \
 370     defined(CONFIG_CPU_SUBTYPE_SH7721)
 371
 372 SCIF_FNS(SCSMR,  0x00, 16)
 373 SCIF_FNS(SCBRR,  0x04,  8)
 374 SCIF_FNS(SCSCR,  0x08, 16)
 375 SCIF_FNS(SCTDSR, 0x0c,  8)
 376 SCIF_FNS(SCFER,  0x10, 16)
 377 SCIF_FNS(SCxSR,  0x14, 16)
 378 SCIF_FNS(SCFCR,  0x18, 16)
 379 SCIF_FNS(SCFDR,  0x1c, 16)
 380 SCIF_FNS(SCxTDR, 0x20,  8)
 381 SCIF_FNS(SCxRDR, 0x24,  8)
 382 SCIF_FNS(SCLSR,  0x24, 16)
 383 #elif defined(CONFIG_CPU_SUBTYPE_SH7723)
 384 SCIx_FNS(SCSMR,  0x00, 16, 0x00, 16)
 385 SCIx_FNS(SCBRR,  0x04,  8, 0x04,  8)
 386 SCIx_FNS(SCSCR,  0x08, 16, 0x08, 16)
 387 SCIx_FNS(SCxTDR, 0x20,  8, 0x0c,  8)
 388 SCIx_FNS(SCxSR,  0x14, 16, 0x10, 16)
 389 SCIx_FNS(SCxRDR, 0x24,  8, 0x14,  8)
 390 SCIF_FNS(SCTDSR, 0x0c,  8)
 391 SCIF_FNS(SCFER,  0x10, 16)
 392 SCIF_FNS(SCFCR,  0x18, 16)
 393 SCIF_FNS(SCFDR,  0x1c, 16)
 394 SCIF_FNS(SCLSR,  0x24, 16)
 395 #else
 396 /*      reg      SCI/SH3   SCI/SH4  SCIF/SH3   SCIF/SH4  SCI/H8*/
 397 /*      name     off  sz   off  sz   off  sz   off  sz   off  sz*/
 398 SCIx_FNS(SCSMR,  0x00,  8, 0x00,  8, 0x00,  8, 0x00, 16, 0x00,  8)
 399 SCIx_FNS(SCBRR,  0x02,  8, 0x04,  8, 0x02,  8, 0x04,  8, 0x01,  8)
 400 SCIx_FNS(SCSCR,  0x04,  8, 0x08,  8, 0x04,  8, 0x08, 16, 0x02,  8)
 401 SCIx_FNS(SCxTDR, 0x06,  8, 0x0c,  8, 0x06,  8, 0x0C,  8, 0x03,  8)
 402 SCIx_FNS(SCxSR,  0x08,  8, 0x10,  8, 0x08, 16, 0x10, 16, 0x04,  8)
 403 SCIx_FNS(SCxRDR, 0x0a,  8, 0x14,  8, 0x0A,  8, 0x14,  8, 0x05,  8)
 404 SCIF_FNS(SCFCR,                      0x0c,  8, 0x18, 16)
 405 #if defined(CONFIG_CPU_SUBTYPE_SH7760) || \
 406     defined(CONFIG_CPU_SUBTYPE_SH7780) || \
 407     defined(CONFIG_CPU_SUBTYPE_SH7785)
 408 SCIF_FNS(SCFDR,                      0x0e, 16, 0x1C, 16)
 409 SCIF_FNS(SCTFDR,                     0x0e, 16, 0x1C, 16)
 410 SCIF_FNS(SCRFDR,                     0x0e, 16, 0x20, 16)
 411 SCIF_FNS(SCSPTR,                        0,  0, 0x24, 16)
 412 SCIF_FNS(SCLSR,                         0,  0, 0x28, 16)
 413 #elif defined(CONFIG_CPU_SUBTYPE_SH7763)
 414 SCIF_FNS(SCFDR,                         0,  0, 0x1C, 16)
 415 SCIF_FNS(SCSPTR2,                       0,  0, 0x20, 16)
 416 SCIF_FNS(SCLSR2,                        0,  0, 0x24, 16)
 417 SCIF_FNS(SCTFDR,                     0x0e, 16, 0x1C, 16)
 418 SCIF_FNS(SCRFDR,                     0x0e, 16, 0x20, 16)
 419 SCIF_FNS(SCSPTR,                        0,  0, 0x24, 16)
 420 SCIF_FNS(SCLSR,                         0,  0, 0x28, 16)
 421 #else
 422 SCIF_FNS(SCFDR,                      0x0e, 16, 0x1C, 16)
 423 #if defined(CONFIG_CPU_SUBTYPE_SH7722)
 424 SCIF_FNS(SCSPTR,                        0,  0, 0, 0)
 425 #else
 426 SCIF_FNS(SCSPTR,                        0,  0, 0x20, 16)
 427 #endif
 428 SCIF_FNS(SCLSR,                         0,  0, 0x24, 16)
 429 #endif
 430 #endif
 431 #define sci_in(port, reg) sci_##reg##_in(port)
 432 #define sci_out(port, reg, value) sci_##reg##_out(port, value)
 433
 434 /* H8/300 series SCI pins assignment */
 435 #if defined(__H8300H__) || defined(__H8300S__)
 436 static const struct __attribute__((packed)) {
 437         int port;             /* GPIO port no */
 438         unsigned short rx,tx; /* GPIO bit no */
 439 } h8300_sci_pins[] = {
 440 #if defined(CONFIG_H83007) || defined(CONFIG_H83068)
 441         {    /* SCI0 */
 442                 .port = H8300_GPIO_P9,
 443                 .rx   = H8300_GPIO_B2,
 444                 .tx   = H8300_GPIO_B0,
 445         },
 446         {    /* SCI1 */
 447                 .port = H8300_GPIO_P9,
 448                 .rx   = H8300_GPIO_B3,
 449                 .tx   = H8300_GPIO_B1,
 450         },
 451         {    /* SCI2 */
 452                 .port = H8300_GPIO_PB,
 453                 .rx   = H8300_GPIO_B7,
 454                 .tx   = H8300_GPIO_B6,
 455         }
 456 #elif defined(CONFIG_H8S2678)
 457         {    /* SCI0 */
 458                 .port = H8300_GPIO_P3,
 459                 .rx   = H8300_GPIO_B2,
 460                 .tx   = H8300_GPIO_B0,
 461         },
 462         {    /* SCI1 */
 463                 .port = H8300_GPIO_P3,
 464                 .rx   = H8300_GPIO_B3,
 465                 .tx   = H8300_GPIO_B1,
 466         },
 467         {    /* SCI2 */
 468                 .port = H8300_GPIO_P5,
 469                 .rx   = H8300_GPIO_B1,
 470                 .tx   = H8300_GPIO_B0,
 471         }
 472 #endif
 473 };
 474 #endif
 475
 476 #if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
 477     defined(CONFIG_CPU_SUBTYPE_SH7707) || \
 478     defined(CONFIG_CPU_SUBTYPE_SH7708) || \
 479     defined(CONFIG_CPU_SUBTYPE_SH7709)
 480 static inline int sci_rxd_in(struct uart_port *port)
 481 {
 482         if (port->mapbase == 0xfffffe80)
 483                 return ctrl_inb(SCPDR)&0x01 ? 1 : 0; /* SCI */
 484         if (port->mapbase == 0xa4000150)
 485                 return ctrl_inb(SCPDR)&0x10 ? 1 : 0; /* SCIF */
 486         if (port->mapbase == 0xa4000140)
 487                 return ctrl_inb(SCPDR)&0x04 ? 1 : 0; /* IRDA */
 488         return 1;
 489 }
 490 #elif defined(CONFIG_CPU_SUBTYPE_SH7705)
 491 static inline int sci_rxd_in(struct uart_port *port)
 492 {
 493         if (port->mapbase == SCIF0)
 494                 return ctrl_inb(SCPDR)&0x04 ? 1 : 0; /* IRDA */
 495         if (port->mapbase == SCIF2)
 496                 return ctrl_inb(SCPDR)&0x10 ? 1 : 0; /* SCIF */
 497         return 1;
 498 }
 499 #elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
 500 static inline int sci_rxd_in(struct uart_port *port)
 501 {
 502           return sci_in(port,SCxSR)&0x0010 ? 1 : 0;
 503 }
 504 static inline void set_sh771x_scif_pfc(struct uart_port *port)
 505 {
 506         if (port->mapbase == 0xA4400000){
 507                 ctrl_outw(ctrl_inw(PACR)&0xffc0,PACR);
 508                 ctrl_outw(ctrl_inw(PBCR)&0x0fff,PBCR);
 509                 return;
 510         }
 511         if (port->mapbase == 0xA4410000){
 512                 ctrl_outw(ctrl_inw(PBCR)&0xf003,PBCR);
 513                 return;
 514         }
 515 }
 516 #elif defined(CONFIG_CPU_SUBTYPE_SH7720) || \
 517       defined(CONFIG_CPU_SUBTYPE_SH7721)
 518 static inline int sci_rxd_in(struct uart_port *port)
 519 {
 520         if (port->mapbase == 0xa4430000)
 521                 return sci_in(port, SCxSR) & 0x0003 ? 1 : 0;
 522         else if (port->mapbase == 0xa4438000)
 523                 return sci_in(port, SCxSR) & 0x0003 ? 1 : 0;
 524         return 1;
 525 }
 526 #elif defined(CONFIG_CPU_SUBTYPE_SH7750)  || \
 527       defined(CONFIG_CPU_SUBTYPE_SH7751)  || \
 528       defined(CONFIG_CPU_SUBTYPE_SH7751R) || \
 529       defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
 530       defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
 531       defined(CONFIG_CPU_SUBTYPE_SH7091)
 532 static inline int sci_rxd_in(struct uart_port *port)
 533 {
 534         if (port->mapbase == 0xffe00000)
 535                 return ctrl_inb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */
 536         if (port->mapbase == 0xffe80000)
 537                 return ctrl_inw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */
 538         return 1;
 539 }
 540 #elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
 541 static inline int sci_rxd_in(struct uart_port *port)
 542 {
 543         if (port->mapbase == 0xffe80000)
 544                 return ctrl_inw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */
 545         return 1;
 546 }
 547 #elif defined(CONFIG_CPU_SUBTYPE_SH7760)
 548 static inline int sci_rxd_in(struct uart_port *port)
 549 {
 550         if (port->mapbase == 0xfe600000)
 551                 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
 552         if (port->mapbase == 0xfe610000)
 553                 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
 554         if (port->mapbase == 0xfe620000)
 555                 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
 556         return 1;
 557 }
 558 #elif defined(CONFIG_CPU_SUBTYPE_SH7343)
 559 static inline int sci_rxd_in(struct uart_port *port)
 560 {
 561         if (port->mapbase == 0xffe00000)
 562                 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
 563         if (port->mapbase == 0xffe10000)
 564                 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
 565         if (port->mapbase == 0xffe20000)
 566                 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
 567         if (port->mapbase == 0xffe30000)
 568                 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
 569         return 1;
 570 }
 571 #elif defined(CONFIG_CPU_SUBTYPE_SH7366)
 572 static inline int sci_rxd_in(struct uart_port *port)
 573 {
 574         if (port->mapbase == 0xffe00000)
 575                 return ctrl_inb(SCPDR0) & 0x0001 ? 1 : 0; /* SCIF0 */
 576         return 1;
 577 }
 578 #elif defined(CONFIG_CPU_SUBTYPE_SH7722)
 579 static inline int sci_rxd_in(struct uart_port *port)
 580 {
 581         if (port->mapbase == 0xffe00000)
 582                 return ctrl_inb(PSDR) & 0x02 ? 1 : 0; /* SCIF0 */
 583         if (port->mapbase == 0xffe10000)
 584                 return ctrl_inb(PADR) & 0x40 ? 1 : 0; /* SCIF1 */
 585         if (port->mapbase == 0xffe20000)
 586                 return ctrl_inb(PWDR) & 0x04 ? 1 : 0; /* SCIF2 */
 587
 588         return 1;
 589 }
 590 #elif defined(CONFIG_CPU_SUBTYPE_SH7723)
 591 static inline int sci_rxd_in(struct uart_port *port)
 592 {
 593         if (port->mapbase == 0xffe00000)
 594                 return ctrl_inb(SCSPTR0) & 0x0008 ? 1 : 0; /* SCIF0 */
 595         if (port->mapbase == 0xffe10000)
 596                 return ctrl_inb(SCSPTR1) & 0x0020 ? 1 : 0; /* SCIF1 */
 597         if (port->mapbase == 0xffe20000)
 598                 return ctrl_inb(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF2 */
 599         if (port->mapbase == 0xa4e30000)
 600                 return ctrl_inb(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF3 */
 601         if (port->mapbase == 0xa4e40000)
 602                 return ctrl_inb(SCSPTR4) & 0x0001 ? 1 : 0; /* SCIF4 */
 603         if (port->mapbase == 0xa4e50000)
 604                 return ctrl_inb(SCSPTR5) & 0x0008 ? 1 : 0; /* SCIF5 */
 605         return 1;
 606 }
 607 #elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
 608 static inline int sci_rxd_in(struct uart_port *port)
 609 {
 610          return sci_in(port, SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */
 611 }
 612 #elif defined(__H8300H__) || defined(__H8300S__)
 613 static inline int sci_rxd_in(struct uart_port *port)
 614 {
 615         int ch = (port->mapbase - SMR0) >> 3;
 616         return (H8300_SCI_DR(ch) & h8300_sci_pins[ch].rx) ? 1 : 0;
 617 }
 618 #elif defined(CONFIG_CPU_SUBTYPE_SH7763)
 619 static inline int sci_rxd_in(struct uart_port *port)
 620 {
 621         if (port->mapbase == 0xffe00000)
 622                 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
 623         if (port->mapbase == 0xffe08000)
 624                 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
 625         if (port->mapbase == 0xffe10000)
 626                 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF/IRDA */
 627
 628         return 1;
 629 }
 630 #elif defined(CONFIG_CPU_SUBTYPE_SH7770)
 631 static inline int sci_rxd_in(struct uart_port *port)
 632 {
 633         if (port->mapbase == 0xff923000)
 634                 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
 635         if (port->mapbase == 0xff924000)
 636                 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
 637         if (port->mapbase == 0xff925000)
 638                 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
 639         return 1;
 640 }
 641 #elif defined(CONFIG_CPU_SUBTYPE_SH7780)
 642 static inline int sci_rxd_in(struct uart_port *port)
 643 {
 644         if (port->mapbase == 0xffe00000)
 645                 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
 646         if (port->mapbase == 0xffe10000)
 647                 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
 648         return 1;
 649 }
 650 #elif defined(CONFIG_CPU_SUBTYPE_SH7785)
 651 static inline int sci_rxd_in(struct uart_port *port)
 652 {
 653         if (port->mapbase == 0xffea0000)
 654                 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
 655         if (port->mapbase == 0xffeb0000)
 656                 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
 657         if (port->mapbase == 0xffec0000)
 658                 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
 659         if (port->mapbase == 0xffed0000)
 660                 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
 661         if (port->mapbase == 0xffee0000)
 662                 return ctrl_inw(SCSPTR4) & 0x0001 ? 1 : 0; /* SCIF */
 663         if (port->mapbase == 0xffef0000)
 664                 return ctrl_inw(SCSPTR5) & 0x0001 ? 1 : 0; /* SCIF */
 665         return 1;
 666 }
 667 #elif defined(CONFIG_CPU_SUBTYPE_SH7203) || \
 668       defined(CONFIG_CPU_SUBTYPE_SH7206) || \
 669       defined(CONFIG_CPU_SUBTYPE_SH7263)
 670 static inline int sci_rxd_in(struct uart_port *port)
 671 {
 672         if (port->mapbase == 0xfffe8000)
 673                 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
 674         if (port->mapbase == 0xfffe8800)
 675                 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
 676         if (port->mapbase == 0xfffe9000)
 677                 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
 678         if (port->mapbase == 0xfffe9800)
 679                 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
 680         return 1;
 681 }
 682 #elif defined(CONFIG_CPU_SUBTYPE_SH7619)
 683 static inline int sci_rxd_in(struct uart_port *port)
 684 {
 685         if (port->mapbase == 0xf8400000)
 686                 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
 687         if (port->mapbase == 0xf8410000)
 688                 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
 689         if (port->mapbase == 0xf8420000)
 690                 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
 691         return 1;
 692 }
 693 #elif defined(CONFIG_CPU_SUBTYPE_SHX3)
 694 static inline int sci_rxd_in(struct uart_port *port)
 695 {
 696         if (port->mapbase == 0xffc30000)
 697                 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
 698         if (port->mapbase == 0xffc40000)
 699                 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
 700         if (port->mapbase == 0xffc50000)
 701                 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
 702         if (port->mapbase == 0xffc60000)
 703                 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
 704         return 1;
 705 }
 706 #endif
 707
 708 /*
 709  * Values for the BitRate Register (SCBRR)
 710  *
 711  * The values are actually divisors for a frequency which can
 712  * be internal to the SH3 (14.7456MHz) or derived from an external
 713  * clock source.  This driver assumes the internal clock is used;
 714  * to support using an external clock source, config options or
 715  * possibly command-line options would need to be added.
 716  *
 717  * Also, to support speeds below 2400 (why?) the lower 2 bits of
 718  * the SCSMR register would also need to be set to non-zero values.
 719  *
 720  * -- Greg Banks 27Feb2000
 721  *
 722  * Answer: The SCBRR register is only eight bits, and the value in
 723  * it gets larger with lower baud rates. At around 2400 (depending on
 724  * the peripherial module clock) you run out of bits. However the
 725  * lower two bits of SCSMR allow the module clock to be divided down,
 726  * scaling the value which is needed in SCBRR.
 727  *
 728  * -- Stuart Menefy - 23 May 2000
 729  *
 730  * I meant, why would anyone bother with bitrates below 2400.
 731  *
 732  * -- Greg Banks - 7Jul2000
 733  *
 734  * You "speedist"!  How will I use my 110bps ASR-33 teletype with paper
 735  * tape reader as a console!
 736  *
 737  * -- Mitch Davis - 15 Jul 2000
 738  */
 739
 740 #if defined(CONFIG_CPU_SUBTYPE_SH7780) || \
 741     defined(CONFIG_CPU_SUBTYPE_SH7785)
 742 #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1)
 743 #elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
 744       defined(CONFIG_CPU_SUBTYPE_SH7720) || \
 745       defined(CONFIG_CPU_SUBTYPE_SH7721)
 746 #define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
 747 #elif defined(CONFIG_CPU_SUBTYPE_SH7723)
 748 static inline int scbrr_calc(struct uart_port *port, int bps, int clk)
 749 {
 750         if (port->type == PORT_SCIF)
 751                 return (clk+16*bps)/(32*bps)-1;
 752         else
 753                 return ((clk*2)+16*bps)/(16*bps)-1;
 754 }
 755 #define SCBRR_VALUE(bps, clk) scbrr_calc(port, bps, clk)
 756 #elif defined(__H8300H__) || defined(__H8300S__)
 757 #define SCBRR_VALUE(bps, clk) (((clk*1000/32)/bps)-1)
 758 #else /* Generic SH */
 759 #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1)
 760 #endif