2 * linux/drivers/char/8250_pci.c
4 * Probe module for 8250/16550-type PCI serial ports.
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
8 * Copyright (C) 2001 Russell King, All Rights Reserved.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License.
14 #include <linux/module.h>
15 #include <linux/init.h>
16 #include <linux/pci.h>
17 #include <linux/string.h>
18 #include <linux/kernel.h>
19 #include <linux/slab.h>
20 #include <linux/delay.h>
21 #include <linux/tty.h>
22 #include <linux/serial_core.h>
23 #include <linux/8250_pci.h>
24 #include <linux/bitops.h>
26 #include <asm/byteorder.h>
31 #undef SERIAL_DEBUG_PCI
34 * init function returns:
35 * > 0 - number of ports
36 * = 0 - use board->num_ports
39 struct pci_serial_quirk
{
44 int (*init
)(struct pci_dev
*dev
);
45 int (*setup
)(struct serial_private
*, struct pciserial_board
*,
46 struct uart_port
*, int);
47 void (*exit
)(struct pci_dev
*dev
);
50 #define PCI_NUM_BAR_RESOURCES 6
52 struct serial_private
{
55 void __iomem
*remapped_bar
[PCI_NUM_BAR_RESOURCES
];
56 struct pci_serial_quirk
*quirk
;
60 static void moan_device(const char *str
, struct pci_dev
*dev
)
62 printk(KERN_WARNING
"%s: %s\n"
63 KERN_WARNING
"Please send the output of lspci -vv, this\n"
64 KERN_WARNING
"message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
65 KERN_WARNING
"manufacturer and name of serial board or\n"
66 KERN_WARNING
"modem board to rmk+serial@arm.linux.org.uk.\n",
67 pci_name(dev
), str
, dev
->vendor
, dev
->device
,
68 dev
->subsystem_vendor
, dev
->subsystem_device
);
72 setup_port(struct serial_private
*priv
, struct uart_port
*port
,
73 int bar
, int offset
, int regshift
)
75 struct pci_dev
*dev
= priv
->dev
;
76 unsigned long base
, len
;
78 if (bar
>= PCI_NUM_BAR_RESOURCES
)
81 base
= pci_resource_start(dev
, bar
);
83 if (pci_resource_flags(dev
, bar
) & IORESOURCE_MEM
) {
84 len
= pci_resource_len(dev
, bar
);
86 if (!priv
->remapped_bar
[bar
])
87 priv
->remapped_bar
[bar
] = ioremap_nocache(base
, len
);
88 if (!priv
->remapped_bar
[bar
])
91 port
->iotype
= UPIO_MEM
;
93 port
->mapbase
= base
+ offset
;
94 port
->membase
= priv
->remapped_bar
[bar
] + offset
;
95 port
->regshift
= regshift
;
97 port
->iotype
= UPIO_PORT
;
98 port
->iobase
= base
+ offset
;
100 port
->membase
= NULL
;
107 * ADDI-DATA GmbH communication cards <info@addi-data.com>
109 static int addidata_apci7800_setup(struct serial_private
*priv
,
110 struct pciserial_board
*board
,
111 struct uart_port
*port
, int idx
)
113 unsigned int bar
= 0, offset
= board
->first_offset
;
114 bar
= FL_GET_BASE(board
->flags
);
117 offset
+= idx
* board
->uart_offset
;
118 } else if ((idx
>= 2) && (idx
< 4)) {
120 offset
+= ((idx
- 2) * board
->uart_offset
);
121 } else if ((idx
>= 4) && (idx
< 6)) {
123 offset
+= ((idx
- 4) * board
->uart_offset
);
124 } else if (idx
>= 6) {
126 offset
+= ((idx
- 6) * board
->uart_offset
);
129 return setup_port(priv
, port
, bar
, offset
, board
->reg_shift
);
133 * AFAVLAB uses a different mixture of BARs and offsets
134 * Not that ugly ;) -- HW
137 afavlab_setup(struct serial_private
*priv
, struct pciserial_board
*board
,
138 struct uart_port
*port
, int idx
)
140 unsigned int bar
, offset
= board
->first_offset
;
142 bar
= FL_GET_BASE(board
->flags
);
147 offset
+= (idx
- 4) * board
->uart_offset
;
150 return setup_port(priv
, port
, bar
, offset
, board
->reg_shift
);
154 * HP's Remote Management Console. The Diva chip came in several
155 * different versions. N-class, L2000 and A500 have two Diva chips, each
156 * with 3 UARTs (the third UART on the second chip is unused). Superdome
157 * and Keystone have one Diva chip with 3 UARTs. Some later machines have
158 * one Diva chip, but it has been expanded to 5 UARTs.
160 static int pci_hp_diva_init(struct pci_dev
*dev
)
164 switch (dev
->subsystem_device
) {
165 case PCI_DEVICE_ID_HP_DIVA_TOSCA1
:
166 case PCI_DEVICE_ID_HP_DIVA_HALFDOME
:
167 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE
:
168 case PCI_DEVICE_ID_HP_DIVA_EVEREST
:
171 case PCI_DEVICE_ID_HP_DIVA_TOSCA2
:
174 case PCI_DEVICE_ID_HP_DIVA_MAESTRO
:
177 case PCI_DEVICE_ID_HP_DIVA_POWERBAR
:
178 case PCI_DEVICE_ID_HP_DIVA_HURRICANE
:
187 * HP's Diva chip puts the 4th/5th serial port further out, and
188 * some serial ports are supposed to be hidden on certain models.
191 pci_hp_diva_setup(struct serial_private
*priv
, struct pciserial_board
*board
,
192 struct uart_port
*port
, int idx
)
194 unsigned int offset
= board
->first_offset
;
195 unsigned int bar
= FL_GET_BASE(board
->flags
);
197 switch (priv
->dev
->subsystem_device
) {
198 case PCI_DEVICE_ID_HP_DIVA_MAESTRO
:
202 case PCI_DEVICE_ID_HP_DIVA_EVEREST
:
212 offset
+= idx
* board
->uart_offset
;
214 return setup_port(priv
, port
, bar
, offset
, board
->reg_shift
);
218 * Added for EKF Intel i960 serial boards
220 static int pci_inteli960ni_init(struct pci_dev
*dev
)
222 unsigned long oldval
;
224 if (!(dev
->subsystem_device
& 0x1000))
227 /* is firmware started? */
228 pci_read_config_dword(dev
, 0x44, (void *)&oldval
);
229 if (oldval
== 0x00001000L
) { /* RESET value */
230 printk(KERN_DEBUG
"Local i960 firmware missing");
237 * Some PCI serial cards using the PLX 9050 PCI interface chip require
238 * that the card interrupt be explicitly enabled or disabled. This
239 * seems to be mainly needed on card using the PLX which also use I/O
242 static int pci_plx9050_init(struct pci_dev
*dev
)
247 if ((pci_resource_flags(dev
, 0) & IORESOURCE_MEM
) == 0) {
248 moan_device("no memory in bar 0", dev
);
253 if (dev
->vendor
== PCI_VENDOR_ID_PANACOM
||
254 dev
->subsystem_vendor
== PCI_SUBVENDOR_ID_EXSYS
)
257 if ((dev
->vendor
== PCI_VENDOR_ID_PLX
) &&
258 (dev
->device
== PCI_DEVICE_ID_PLX_ROMULUS
))
260 * As the megawolf cards have the int pins active
261 * high, and have 2 UART chips, both ints must be
262 * enabled on the 9050. Also, the UARTS are set in
263 * 16450 mode by default, so we have to enable the
264 * 16C950 'enhanced' mode so that we can use the
269 * enable/disable interrupts
271 p
= ioremap_nocache(pci_resource_start(dev
, 0), 0x80);
274 writel(irq_config
, p
+ 0x4c);
277 * Read the register back to ensure that it took effect.
285 static void __devexit
pci_plx9050_exit(struct pci_dev
*dev
)
289 if ((pci_resource_flags(dev
, 0) & IORESOURCE_MEM
) == 0)
295 p
= ioremap_nocache(pci_resource_start(dev
, 0), 0x80);
300 * Read the register back to ensure that it took effect.
307 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
309 sbs_setup(struct serial_private
*priv
, struct pciserial_board
*board
,
310 struct uart_port
*port
, int idx
)
312 unsigned int bar
, offset
= board
->first_offset
;
317 /* first four channels map to 0, 0x100, 0x200, 0x300 */
318 offset
+= idx
* board
->uart_offset
;
319 } else if (idx
< 8) {
320 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
321 offset
+= idx
* board
->uart_offset
+ 0xC00;
322 } else /* we have only 8 ports on PMC-OCTALPRO */
325 return setup_port(priv
, port
, bar
, offset
, board
->reg_shift
);
329 * This does initialization for PMC OCTALPRO cards:
330 * maps the device memory, resets the UARTs (needed, bc
331 * if the module is removed and inserted again, the card
332 * is in the sleep mode) and enables global interrupt.
335 /* global control register offset for SBS PMC-OctalPro */
336 #define OCT_REG_CR_OFF 0x500
338 static int sbs_init(struct pci_dev
*dev
)
342 p
= ioremap_nocache(pci_resource_start(dev
, 0),
343 pci_resource_len(dev
, 0));
347 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
348 writeb(0x10, p
+ OCT_REG_CR_OFF
);
350 writeb(0x0, p
+ OCT_REG_CR_OFF
);
352 /* Set bit-2 (INTENABLE) of Control Register */
353 writeb(0x4, p
+ OCT_REG_CR_OFF
);
360 * Disables the global interrupt of PMC-OctalPro
363 static void __devexit
sbs_exit(struct pci_dev
*dev
)
367 p
= ioremap_nocache(pci_resource_start(dev
, 0),
368 pci_resource_len(dev
, 0));
369 /* FIXME: What if resource_len < OCT_REG_CR_OFF */
371 writeb(0, p
+ OCT_REG_CR_OFF
);
376 * SIIG serial cards have an PCI interface chip which also controls
377 * the UART clocking frequency. Each UART can be clocked independently
378 * (except cards equiped with 4 UARTs) and initial clocking settings
379 * are stored in the EEPROM chip. It can cause problems because this
380 * version of serial driver doesn't support differently clocked UART's
381 * on single PCI card. To prevent this, initialization functions set
382 * high frequency clocking for all UART's on given card. It is safe (I
383 * hope) because it doesn't touch EEPROM settings to prevent conflicts
384 * with other OSes (like M$ DOS).
386 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
388 * There is two family of SIIG serial cards with different PCI
389 * interface chip and different configuration methods:
390 * - 10x cards have control registers in IO and/or memory space;
391 * - 20x cards have control registers in standard PCI configuration space.
393 * Note: all 10x cards have PCI device ids 0x10..
394 * all 20x cards have PCI device ids 0x20..
396 * There are also Quartet Serial cards which use Oxford Semiconductor
397 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
399 * Note: some SIIG cards are probed by the parport_serial object.
402 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
403 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
405 static int pci_siig10x_init(struct pci_dev
*dev
)
410 switch (dev
->device
& 0xfff8) {
411 case PCI_DEVICE_ID_SIIG_1S_10x
: /* 1S */
414 case PCI_DEVICE_ID_SIIG_2S_10x
: /* 2S, 2S1P */
417 default: /* 1S1P, 4S */
422 p
= ioremap_nocache(pci_resource_start(dev
, 0), 0x80);
426 writew(readw(p
+ 0x28) & data
, p
+ 0x28);
432 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
433 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
435 static int pci_siig20x_init(struct pci_dev
*dev
)
439 /* Change clock frequency for the first UART. */
440 pci_read_config_byte(dev
, 0x6f, &data
);
441 pci_write_config_byte(dev
, 0x6f, data
& 0xef);
443 /* If this card has 2 UART, we have to do the same with second UART. */
444 if (((dev
->device
& 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x
) ||
445 ((dev
->device
& 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x
)) {
446 pci_read_config_byte(dev
, 0x73, &data
);
447 pci_write_config_byte(dev
, 0x73, data
& 0xef);
452 static int pci_siig_init(struct pci_dev
*dev
)
454 unsigned int type
= dev
->device
& 0xff00;
457 return pci_siig10x_init(dev
);
458 else if (type
== 0x2000)
459 return pci_siig20x_init(dev
);
461 moan_device("Unknown SIIG card", dev
);
465 static int pci_siig_setup(struct serial_private
*priv
,
466 struct pciserial_board
*board
,
467 struct uart_port
*port
, int idx
)
469 unsigned int bar
= FL_GET_BASE(board
->flags
) + idx
, offset
= 0;
473 offset
= (idx
- 4) * 8;
476 return setup_port(priv
, port
, bar
, offset
, 0);
480 * Timedia has an explosion of boards, and to avoid the PCI table from
481 * growing *huge*, we use this function to collapse some 70 entries
482 * in the PCI table into one, for sanity's and compactness's sake.
484 static const unsigned short timedia_single_port
[] = {
485 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
488 static const unsigned short timedia_dual_port
[] = {
489 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
490 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
491 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
492 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
496 static const unsigned short timedia_quad_port
[] = {
497 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
498 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
499 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
503 static const unsigned short timedia_eight_port
[] = {
504 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
505 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
508 static const struct timedia_struct
{
510 const unsigned short *ids
;
512 { 1, timedia_single_port
},
513 { 2, timedia_dual_port
},
514 { 4, timedia_quad_port
},
515 { 8, timedia_eight_port
}
518 static int pci_timedia_init(struct pci_dev
*dev
)
520 const unsigned short *ids
;
523 for (i
= 0; i
< ARRAY_SIZE(timedia_data
); i
++) {
524 ids
= timedia_data
[i
].ids
;
525 for (j
= 0; ids
[j
]; j
++)
526 if (dev
->subsystem_device
== ids
[j
])
527 return timedia_data
[i
].num
;
533 * Timedia/SUNIX uses a mixture of BARs and offsets
534 * Ugh, this is ugly as all hell --- TYT
537 pci_timedia_setup(struct serial_private
*priv
, struct pciserial_board
*board
,
538 struct uart_port
*port
, int idx
)
540 unsigned int bar
= 0, offset
= board
->first_offset
;
547 offset
= board
->uart_offset
;
554 offset
= board
->uart_offset
;
563 return setup_port(priv
, port
, bar
, offset
, board
->reg_shift
);
567 * Some Titan cards are also a little weird
570 titan_400l_800l_setup(struct serial_private
*priv
,
571 struct pciserial_board
*board
,
572 struct uart_port
*port
, int idx
)
574 unsigned int bar
, offset
= board
->first_offset
;
585 offset
= (idx
- 2) * board
->uart_offset
;
588 return setup_port(priv
, port
, bar
, offset
, board
->reg_shift
);
591 static int pci_xircom_init(struct pci_dev
*dev
)
597 static int pci_netmos_init(struct pci_dev
*dev
)
599 /* subdevice 0x00PS means <P> parallel, <S> serial */
600 unsigned int num_serial
= dev
->subsystem_device
& 0xf;
608 * ITE support by Niels de Vos <niels.devos@wincor-nixdorf.com>
610 * These chips are available with optionally one parallel port and up to
611 * two serial ports. Unfortunately they all have the same product id.
613 * Basic configuration is done over a region of 32 I/O ports. The base
614 * ioport is called INTA or INTC, depending on docs/other drivers.
616 * The region of the 32 I/O ports is configured in POSIO0R...
620 #define ITE_887x_MISCR 0x9c
621 #define ITE_887x_INTCBAR 0x78
622 #define ITE_887x_UARTBAR 0x7c
623 #define ITE_887x_PS0BAR 0x10
624 #define ITE_887x_POSIO0 0x60
627 #define ITE_887x_IOSIZE 32
628 /* I/O space size (bits 26-24; 8 bytes = 011b) */
629 #define ITE_887x_POSIO_IOSIZE_8 (3 << 24)
630 /* I/O space size (bits 26-24; 32 bytes = 101b) */
631 #define ITE_887x_POSIO_IOSIZE_32 (5 << 24)
632 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
633 #define ITE_887x_POSIO_SPEED (3 << 29)
634 /* enable IO_Space bit */
635 #define ITE_887x_POSIO_ENABLE (1 << 31)
637 static int pci_ite887x_init(struct pci_dev
*dev
)
639 /* inta_addr are the configuration addresses of the ITE */
640 static const short inta_addr
[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
643 struct resource
*iobase
= NULL
;
644 u32 miscr
, uartbar
, ioport
;
646 /* search for the base-ioport */
648 while (inta_addr
[i
] && iobase
== NULL
) {
649 iobase
= request_region(inta_addr
[i
], ITE_887x_IOSIZE
,
651 if (iobase
!= NULL
) {
652 /* write POSIO0R - speed | size | ioport */
653 pci_write_config_dword(dev
, ITE_887x_POSIO0
,
654 ITE_887x_POSIO_ENABLE
| ITE_887x_POSIO_SPEED
|
655 ITE_887x_POSIO_IOSIZE_32
| inta_addr
[i
]);
656 /* write INTCBAR - ioport */
657 pci_write_config_dword(dev
, ITE_887x_INTCBAR
,
659 ret
= inb(inta_addr
[i
]);
661 /* ioport connected */
664 release_region(iobase
->start
, ITE_887x_IOSIZE
);
671 printk(KERN_ERR
"ite887x: could not find iobase\n");
675 /* start of undocumented type checking (see parport_pc.c) */
676 type
= inb(iobase
->start
+ 0x18) & 0x0f;
679 case 0x2: /* ITE8871 (1P) */
680 case 0xa: /* ITE8875 (1P) */
683 case 0xe: /* ITE8872 (2S1P) */
686 case 0x6: /* ITE8873 (1S) */
689 case 0x8: /* ITE8874 (2S) */
693 moan_device("Unknown ITE887x", dev
);
697 /* configure all serial ports */
698 for (i
= 0; i
< ret
; i
++) {
699 /* read the I/O port from the device */
700 pci_read_config_dword(dev
, ITE_887x_PS0BAR
+ (0x4 * (i
+ 1)),
702 ioport
&= 0x0000FF00; /* the actual base address */
703 pci_write_config_dword(dev
, ITE_887x_POSIO0
+ (0x4 * (i
+ 1)),
704 ITE_887x_POSIO_ENABLE
| ITE_887x_POSIO_SPEED
|
705 ITE_887x_POSIO_IOSIZE_8
| ioport
);
707 /* write the ioport to the UARTBAR */
708 pci_read_config_dword(dev
, ITE_887x_UARTBAR
, &uartbar
);
709 uartbar
&= ~(0xffff << (16 * i
)); /* clear half the reg */
710 uartbar
|= (ioport
<< (16 * i
)); /* set the ioport */
711 pci_write_config_dword(dev
, ITE_887x_UARTBAR
, uartbar
);
713 /* get current config */
714 pci_read_config_dword(dev
, ITE_887x_MISCR
, &miscr
);
715 /* disable interrupts (UARTx_Routing[3:0]) */
716 miscr
&= ~(0xf << (12 - 4 * i
));
717 /* activate the UART (UARTx_En) */
718 miscr
|= 1 << (23 - i
);
719 /* write new config with activated UART */
720 pci_write_config_dword(dev
, ITE_887x_MISCR
, miscr
);
724 /* the device has no UARTs if we get here */
725 release_region(iobase
->start
, ITE_887x_IOSIZE
);
731 static void __devexit
pci_ite887x_exit(struct pci_dev
*dev
)
734 /* the ioport is bit 0-15 in POSIO0R */
735 pci_read_config_dword(dev
, ITE_887x_POSIO0
, &ioport
);
737 release_region(ioport
, ITE_887x_IOSIZE
);
741 pci_default_setup(struct serial_private
*priv
, struct pciserial_board
*board
,
742 struct uart_port
*port
, int idx
)
744 unsigned int bar
, offset
= board
->first_offset
, maxnr
;
746 bar
= FL_GET_BASE(board
->flags
);
747 if (board
->flags
& FL_BASE_BARS
)
750 offset
+= idx
* board
->uart_offset
;
752 maxnr
= (pci_resource_len(priv
->dev
, bar
) - board
->first_offset
) >>
753 (board
->reg_shift
+ 3);
755 if (board
->flags
& FL_REGION_SZ_CAP
&& idx
>= maxnr
)
758 return setup_port(priv
, port
, bar
, offset
, board
->reg_shift
);
761 static int skip_tx_en_setup(struct serial_private
*priv
,
762 const struct pciserial_board
*board
,
763 struct uart_port
*port
, int idx
)
765 port
->flags
|= UPF_NO_TXEN_TEST
;
766 printk(KERN_DEBUG
"serial8250: skipping TxEn test for device "
767 "[%04x:%04x] subsystem [%04x:%04x]\n",
770 priv
->dev
->subsystem_vendor
,
771 priv
->dev
->subsystem_device
);
773 return pci_default_setup(priv
, board
, port
, idx
);
776 /* This should be in linux/pci_ids.h */
777 #define PCI_VENDOR_ID_SBSMODULARIO 0x124B
778 #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
779 #define PCI_DEVICE_ID_OCTPRO 0x0001
780 #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
781 #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
782 #define PCI_SUBDEVICE_ID_POCTAL232 0x0308
783 #define PCI_SUBDEVICE_ID_POCTAL422 0x0408
784 #define PCI_VENDOR_ID_ADVANTECH 0x13fe
785 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
787 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */
788 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
791 * Master list of serial port init/setup/exit quirks.
792 * This does not describe the general nature of the port.
793 * (ie, baud base, number and location of ports, etc)
795 * This list is ordered alphabetically by vendor then device.
796 * Specific entries must come before more generic entries.
798 static struct pci_serial_quirk pci_serial_quirks
[] __refdata
= {
800 * ADDI-DATA GmbH communication cards <info@addi-data.com>
803 .vendor
= PCI_VENDOR_ID_ADDIDATA_OLD
,
804 .device
= PCI_DEVICE_ID_ADDIDATA_APCI7800
,
805 .subvendor
= PCI_ANY_ID
,
806 .subdevice
= PCI_ANY_ID
,
807 .setup
= addidata_apci7800_setup
,
810 * AFAVLAB cards - these may be called via parport_serial
811 * It is not clear whether this applies to all products.
814 .vendor
= PCI_VENDOR_ID_AFAVLAB
,
815 .device
= PCI_ANY_ID
,
816 .subvendor
= PCI_ANY_ID
,
817 .subdevice
= PCI_ANY_ID
,
818 .setup
= afavlab_setup
,
824 .vendor
= PCI_VENDOR_ID_HP
,
825 .device
= PCI_DEVICE_ID_HP_DIVA
,
826 .subvendor
= PCI_ANY_ID
,
827 .subdevice
= PCI_ANY_ID
,
828 .init
= pci_hp_diva_init
,
829 .setup
= pci_hp_diva_setup
,
835 .vendor
= PCI_VENDOR_ID_INTEL
,
836 .device
= PCI_DEVICE_ID_INTEL_80960_RP
,
838 .subdevice
= PCI_ANY_ID
,
839 .init
= pci_inteli960ni_init
,
840 .setup
= pci_default_setup
,
843 .vendor
= PCI_VENDOR_ID_INTEL
,
844 .device
= PCI_DEVICE_ID_INTEL_8257X_SOL
,
845 .subvendor
= PCI_ANY_ID
,
846 .subdevice
= PCI_ANY_ID
,
847 .setup
= skip_tx_en_setup
,
850 .vendor
= PCI_VENDOR_ID_INTEL
,
851 .device
= PCI_DEVICE_ID_INTEL_82573L_SOL
,
852 .subvendor
= PCI_ANY_ID
,
853 .subdevice
= PCI_ANY_ID
,
854 .setup
= skip_tx_en_setup
,
857 .vendor
= PCI_VENDOR_ID_INTEL
,
858 .device
= PCI_DEVICE_ID_INTEL_82573E_SOL
,
859 .subvendor
= PCI_ANY_ID
,
860 .subdevice
= PCI_ANY_ID
,
861 .setup
= skip_tx_en_setup
,
867 .vendor
= PCI_VENDOR_ID_ITE
,
868 .device
= PCI_DEVICE_ID_ITE_8872
,
869 .subvendor
= PCI_ANY_ID
,
870 .subdevice
= PCI_ANY_ID
,
871 .init
= pci_ite887x_init
,
872 .setup
= pci_default_setup
,
873 .exit
= __devexit_p(pci_ite887x_exit
),
879 .vendor
= PCI_VENDOR_ID_PANACOM
,
880 .device
= PCI_DEVICE_ID_PANACOM_QUADMODEM
,
881 .subvendor
= PCI_ANY_ID
,
882 .subdevice
= PCI_ANY_ID
,
883 .init
= pci_plx9050_init
,
884 .setup
= pci_default_setup
,
885 .exit
= __devexit_p(pci_plx9050_exit
),
888 .vendor
= PCI_VENDOR_ID_PANACOM
,
889 .device
= PCI_DEVICE_ID_PANACOM_DUALMODEM
,
890 .subvendor
= PCI_ANY_ID
,
891 .subdevice
= PCI_ANY_ID
,
892 .init
= pci_plx9050_init
,
893 .setup
= pci_default_setup
,
894 .exit
= __devexit_p(pci_plx9050_exit
),
900 .vendor
= PCI_VENDOR_ID_PLX
,
901 .device
= PCI_DEVICE_ID_PLX_9030
,
902 .subvendor
= PCI_SUBVENDOR_ID_PERLE
,
903 .subdevice
= PCI_ANY_ID
,
904 .setup
= pci_default_setup
,
907 .vendor
= PCI_VENDOR_ID_PLX
,
908 .device
= PCI_DEVICE_ID_PLX_9050
,
909 .subvendor
= PCI_SUBVENDOR_ID_EXSYS
,
910 .subdevice
= PCI_SUBDEVICE_ID_EXSYS_4055
,
911 .init
= pci_plx9050_init
,
912 .setup
= pci_default_setup
,
913 .exit
= __devexit_p(pci_plx9050_exit
),
916 .vendor
= PCI_VENDOR_ID_PLX
,
917 .device
= PCI_DEVICE_ID_PLX_9050
,
918 .subvendor
= PCI_SUBVENDOR_ID_KEYSPAN
,
919 .subdevice
= PCI_SUBDEVICE_ID_KEYSPAN_SX2
,
920 .init
= pci_plx9050_init
,
921 .setup
= pci_default_setup
,
922 .exit
= __devexit_p(pci_plx9050_exit
),
925 .vendor
= PCI_VENDOR_ID_PLX
,
926 .device
= PCI_DEVICE_ID_PLX_9050
,
927 .subvendor
= PCI_VENDOR_ID_PLX
,
928 .subdevice
= PCI_SUBDEVICE_ID_UNKNOWN_0x1584
,
929 .init
= pci_plx9050_init
,
930 .setup
= pci_default_setup
,
931 .exit
= __devexit_p(pci_plx9050_exit
),
934 .vendor
= PCI_VENDOR_ID_PLX
,
935 .device
= PCI_DEVICE_ID_PLX_ROMULUS
,
936 .subvendor
= PCI_VENDOR_ID_PLX
,
937 .subdevice
= PCI_DEVICE_ID_PLX_ROMULUS
,
938 .init
= pci_plx9050_init
,
939 .setup
= pci_default_setup
,
940 .exit
= __devexit_p(pci_plx9050_exit
),
943 * SBS Technologies, Inc., PMC-OCTALPRO 232
946 .vendor
= PCI_VENDOR_ID_SBSMODULARIO
,
947 .device
= PCI_DEVICE_ID_OCTPRO
,
948 .subvendor
= PCI_SUBVENDOR_ID_SBSMODULARIO
,
949 .subdevice
= PCI_SUBDEVICE_ID_OCTPRO232
,
952 .exit
= __devexit_p(sbs_exit
),
955 * SBS Technologies, Inc., PMC-OCTALPRO 422
958 .vendor
= PCI_VENDOR_ID_SBSMODULARIO
,
959 .device
= PCI_DEVICE_ID_OCTPRO
,
960 .subvendor
= PCI_SUBVENDOR_ID_SBSMODULARIO
,
961 .subdevice
= PCI_SUBDEVICE_ID_OCTPRO422
,
964 .exit
= __devexit_p(sbs_exit
),
967 * SBS Technologies, Inc., P-Octal 232
970 .vendor
= PCI_VENDOR_ID_SBSMODULARIO
,
971 .device
= PCI_DEVICE_ID_OCTPRO
,
972 .subvendor
= PCI_SUBVENDOR_ID_SBSMODULARIO
,
973 .subdevice
= PCI_SUBDEVICE_ID_POCTAL232
,
976 .exit
= __devexit_p(sbs_exit
),
979 * SBS Technologies, Inc., P-Octal 422
982 .vendor
= PCI_VENDOR_ID_SBSMODULARIO
,
983 .device
= PCI_DEVICE_ID_OCTPRO
,
984 .subvendor
= PCI_SUBVENDOR_ID_SBSMODULARIO
,
985 .subdevice
= PCI_SUBDEVICE_ID_POCTAL422
,
988 .exit
= __devexit_p(sbs_exit
),
991 * SIIG cards - these may be called via parport_serial
994 .vendor
= PCI_VENDOR_ID_SIIG
,
995 .device
= PCI_ANY_ID
,
996 .subvendor
= PCI_ANY_ID
,
997 .subdevice
= PCI_ANY_ID
,
998 .init
= pci_siig_init
,
999 .setup
= pci_siig_setup
,
1005 .vendor
= PCI_VENDOR_ID_TITAN
,
1006 .device
= PCI_DEVICE_ID_TITAN_400L
,
1007 .subvendor
= PCI_ANY_ID
,
1008 .subdevice
= PCI_ANY_ID
,
1009 .setup
= titan_400l_800l_setup
,
1012 .vendor
= PCI_VENDOR_ID_TITAN
,
1013 .device
= PCI_DEVICE_ID_TITAN_800L
,
1014 .subvendor
= PCI_ANY_ID
,
1015 .subdevice
= PCI_ANY_ID
,
1016 .setup
= titan_400l_800l_setup
,
1022 .vendor
= PCI_VENDOR_ID_TIMEDIA
,
1023 .device
= PCI_DEVICE_ID_TIMEDIA_1889
,
1024 .subvendor
= PCI_VENDOR_ID_TIMEDIA
,
1025 .subdevice
= PCI_ANY_ID
,
1026 .init
= pci_timedia_init
,
1027 .setup
= pci_timedia_setup
,
1030 .vendor
= PCI_VENDOR_ID_TIMEDIA
,
1031 .device
= PCI_ANY_ID
,
1032 .subvendor
= PCI_ANY_ID
,
1033 .subdevice
= PCI_ANY_ID
,
1034 .setup
= pci_timedia_setup
,
1040 .vendor
= PCI_VENDOR_ID_XIRCOM
,
1041 .device
= PCI_DEVICE_ID_XIRCOM_X3201_MDM
,
1042 .subvendor
= PCI_ANY_ID
,
1043 .subdevice
= PCI_ANY_ID
,
1044 .init
= pci_xircom_init
,
1045 .setup
= pci_default_setup
,
1048 * Netmos cards - these may be called via parport_serial
1051 .vendor
= PCI_VENDOR_ID_NETMOS
,
1052 .device
= PCI_ANY_ID
,
1053 .subvendor
= PCI_ANY_ID
,
1054 .subdevice
= PCI_ANY_ID
,
1055 .init
= pci_netmos_init
,
1056 .setup
= pci_default_setup
,
1059 * Default "match everything" terminator entry
1062 .vendor
= PCI_ANY_ID
,
1063 .device
= PCI_ANY_ID
,
1064 .subvendor
= PCI_ANY_ID
,
1065 .subdevice
= PCI_ANY_ID
,
1066 .setup
= pci_default_setup
,
1070 static inline int quirk_id_matches(u32 quirk_id
, u32 dev_id
)
1072 return quirk_id
== PCI_ANY_ID
|| quirk_id
== dev_id
;
1075 static struct pci_serial_quirk
*find_quirk(struct pci_dev
*dev
)
1077 struct pci_serial_quirk
*quirk
;
1079 for (quirk
= pci_serial_quirks
; ; quirk
++)
1080 if (quirk_id_matches(quirk
->vendor
, dev
->vendor
) &&
1081 quirk_id_matches(quirk
->device
, dev
->device
) &&
1082 quirk_id_matches(quirk
->subvendor
, dev
->subsystem_vendor
) &&
1083 quirk_id_matches(quirk
->subdevice
, dev
->subsystem_device
))
1088 static inline int get_pci_irq(struct pci_dev
*dev
,
1089 struct pciserial_board
*board
)
1091 if (board
->flags
& FL_NOIRQ
)
1098 * This is the configuration table for all of the PCI serial boards
1099 * which we support. It is directly indexed by the pci_board_num_t enum
1100 * value, which is encoded in the pci_device_id PCI probe table's
1101 * driver_data member.
1103 * The makeup of these names are:
1104 * pbn_bn{_bt}_n_baud{_offsetinhex}
1106 * bn = PCI BAR number
1107 * bt = Index using PCI BARs
1108 * n = number of serial ports
1110 * offsetinhex = offset for each sequential port (in hex)
1112 * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
1114 * Please note: in theory if n = 1, _bt infix should make no difference.
1115 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
1117 enum pci_board_num_t
{
1137 pbn_b0_2_1843200_200
,
1138 pbn_b0_4_1843200_200
,
1139 pbn_b0_8_1843200_200
,
1202 * Board-specific versions.
1210 pbn_oxsemi_1_4000000
,
1211 pbn_oxsemi_2_4000000
,
1212 pbn_oxsemi_4_4000000
,
1213 pbn_oxsemi_8_4000000
,
1227 * uart_offset - the space between channels
1228 * reg_shift - describes how the UART registers are mapped
1229 * to PCI memory by the card.
1230 * For example IER register on SBS, Inc. PMC-OctPro is located at
1231 * offset 0x10 from the UART base, while UART_IER is defined as 1
1232 * in include/linux/serial_reg.h,
1233 * see first lines of serial_in() and serial_out() in 8250.c
1236 static struct pciserial_board pci_boards
[] __devinitdata
= {
1240 .base_baud
= 115200,
1243 [pbn_b0_1_115200
] = {
1246 .base_baud
= 115200,
1249 [pbn_b0_2_115200
] = {
1252 .base_baud
= 115200,
1255 [pbn_b0_4_115200
] = {
1258 .base_baud
= 115200,
1261 [pbn_b0_5_115200
] = {
1264 .base_baud
= 115200,
1267 [pbn_b0_8_115200
] = {
1270 .base_baud
= 115200,
1273 [pbn_b0_1_921600
] = {
1276 .base_baud
= 921600,
1279 [pbn_b0_2_921600
] = {
1282 .base_baud
= 921600,
1285 [pbn_b0_4_921600
] = {
1288 .base_baud
= 921600,
1292 [pbn_b0_2_1130000
] = {
1295 .base_baud
= 1130000,
1299 [pbn_b0_4_1152000
] = {
1302 .base_baud
= 1152000,
1306 [pbn_b0_2_1843200
] = {
1309 .base_baud
= 1843200,
1312 [pbn_b0_4_1843200
] = {
1315 .base_baud
= 1843200,
1319 [pbn_b0_2_1843200_200
] = {
1322 .base_baud
= 1843200,
1323 .uart_offset
= 0x200,
1325 [pbn_b0_4_1843200_200
] = {
1328 .base_baud
= 1843200,
1329 .uart_offset
= 0x200,
1331 [pbn_b0_8_1843200_200
] = {
1334 .base_baud
= 1843200,
1335 .uart_offset
= 0x200,
1337 [pbn_b0_1_4000000
] = {
1340 .base_baud
= 4000000,
1344 [pbn_b0_bt_1_115200
] = {
1345 .flags
= FL_BASE0
|FL_BASE_BARS
,
1347 .base_baud
= 115200,
1350 [pbn_b0_bt_2_115200
] = {
1351 .flags
= FL_BASE0
|FL_BASE_BARS
,
1353 .base_baud
= 115200,
1356 [pbn_b0_bt_8_115200
] = {
1357 .flags
= FL_BASE0
|FL_BASE_BARS
,
1359 .base_baud
= 115200,
1363 [pbn_b0_bt_1_460800
] = {
1364 .flags
= FL_BASE0
|FL_BASE_BARS
,
1366 .base_baud
= 460800,
1369 [pbn_b0_bt_2_460800
] = {
1370 .flags
= FL_BASE0
|FL_BASE_BARS
,
1372 .base_baud
= 460800,
1375 [pbn_b0_bt_4_460800
] = {
1376 .flags
= FL_BASE0
|FL_BASE_BARS
,
1378 .base_baud
= 460800,
1382 [pbn_b0_bt_1_921600
] = {
1383 .flags
= FL_BASE0
|FL_BASE_BARS
,
1385 .base_baud
= 921600,
1388 [pbn_b0_bt_2_921600
] = {
1389 .flags
= FL_BASE0
|FL_BASE_BARS
,
1391 .base_baud
= 921600,
1394 [pbn_b0_bt_4_921600
] = {
1395 .flags
= FL_BASE0
|FL_BASE_BARS
,
1397 .base_baud
= 921600,
1400 [pbn_b0_bt_8_921600
] = {
1401 .flags
= FL_BASE0
|FL_BASE_BARS
,
1403 .base_baud
= 921600,
1407 [pbn_b1_1_115200
] = {
1410 .base_baud
= 115200,
1413 [pbn_b1_2_115200
] = {
1416 .base_baud
= 115200,
1419 [pbn_b1_4_115200
] = {
1422 .base_baud
= 115200,
1425 [pbn_b1_8_115200
] = {
1428 .base_baud
= 115200,
1432 [pbn_b1_1_921600
] = {
1435 .base_baud
= 921600,
1438 [pbn_b1_2_921600
] = {
1441 .base_baud
= 921600,
1444 [pbn_b1_4_921600
] = {
1447 .base_baud
= 921600,
1450 [pbn_b1_8_921600
] = {
1453 .base_baud
= 921600,
1456 [pbn_b1_2_1250000
] = {
1459 .base_baud
= 1250000,
1463 [pbn_b1_bt_1_115200
] = {
1464 .flags
= FL_BASE1
|FL_BASE_BARS
,
1466 .base_baud
= 115200,
1470 [pbn_b1_bt_2_921600
] = {
1471 .flags
= FL_BASE1
|FL_BASE_BARS
,
1473 .base_baud
= 921600,
1477 [pbn_b1_1_1382400
] = {
1480 .base_baud
= 1382400,
1483 [pbn_b1_2_1382400
] = {
1486 .base_baud
= 1382400,
1489 [pbn_b1_4_1382400
] = {
1492 .base_baud
= 1382400,
1495 [pbn_b1_8_1382400
] = {
1498 .base_baud
= 1382400,
1502 [pbn_b2_1_115200
] = {
1505 .base_baud
= 115200,
1508 [pbn_b2_2_115200
] = {
1511 .base_baud
= 115200,
1514 [pbn_b2_4_115200
] = {
1517 .base_baud
= 115200,
1520 [pbn_b2_8_115200
] = {
1523 .base_baud
= 115200,
1527 [pbn_b2_1_460800
] = {
1530 .base_baud
= 460800,
1533 [pbn_b2_4_460800
] = {
1536 .base_baud
= 460800,
1539 [pbn_b2_8_460800
] = {
1542 .base_baud
= 460800,
1545 [pbn_b2_16_460800
] = {
1548 .base_baud
= 460800,
1552 [pbn_b2_1_921600
] = {
1555 .base_baud
= 921600,
1558 [pbn_b2_4_921600
] = {
1561 .base_baud
= 921600,
1564 [pbn_b2_8_921600
] = {
1567 .base_baud
= 921600,
1571 [pbn_b2_bt_1_115200
] = {
1572 .flags
= FL_BASE2
|FL_BASE_BARS
,
1574 .base_baud
= 115200,
1577 [pbn_b2_bt_2_115200
] = {
1578 .flags
= FL_BASE2
|FL_BASE_BARS
,
1580 .base_baud
= 115200,
1583 [pbn_b2_bt_4_115200
] = {
1584 .flags
= FL_BASE2
|FL_BASE_BARS
,
1586 .base_baud
= 115200,
1590 [pbn_b2_bt_2_921600
] = {
1591 .flags
= FL_BASE2
|FL_BASE_BARS
,
1593 .base_baud
= 921600,
1596 [pbn_b2_bt_4_921600
] = {
1597 .flags
= FL_BASE2
|FL_BASE_BARS
,
1599 .base_baud
= 921600,
1603 [pbn_b3_2_115200
] = {
1606 .base_baud
= 115200,
1609 [pbn_b3_4_115200
] = {
1612 .base_baud
= 115200,
1615 [pbn_b3_8_115200
] = {
1618 .base_baud
= 115200,
1623 * Entries following this are board-specific.
1632 .base_baud
= 921600,
1633 .uart_offset
= 0x400,
1637 .flags
= FL_BASE2
|FL_BASE_BARS
,
1639 .base_baud
= 921600,
1640 .uart_offset
= 0x400,
1644 .flags
= FL_BASE2
|FL_BASE_BARS
,
1646 .base_baud
= 921600,
1647 .uart_offset
= 0x400,
1651 [pbn_exsys_4055
] = {
1654 .base_baud
= 115200,
1658 /* I think this entry is broken - the first_offset looks wrong --rmk */
1659 [pbn_plx_romulus
] = {
1662 .base_baud
= 921600,
1663 .uart_offset
= 8 << 2,
1665 .first_offset
= 0x03,
1669 * This board uses the size of PCI Base region 0 to
1670 * signal now many ports are available
1673 .flags
= FL_BASE0
|FL_REGION_SZ_CAP
,
1675 .base_baud
= 115200,
1678 [pbn_oxsemi_1_4000000
] = {
1681 .base_baud
= 4000000,
1682 .uart_offset
= 0x200,
1683 .first_offset
= 0x1000,
1685 [pbn_oxsemi_2_4000000
] = {
1688 .base_baud
= 4000000,
1689 .uart_offset
= 0x200,
1690 .first_offset
= 0x1000,
1692 [pbn_oxsemi_4_4000000
] = {
1695 .base_baud
= 4000000,
1696 .uart_offset
= 0x200,
1697 .first_offset
= 0x1000,
1699 [pbn_oxsemi_8_4000000
] = {
1702 .base_baud
= 4000000,
1703 .uart_offset
= 0x200,
1704 .first_offset
= 0x1000,
1709 * EKF addition for i960 Boards form EKF with serial port.
1712 [pbn_intel_i960
] = {
1715 .base_baud
= 921600,
1716 .uart_offset
= 8 << 2,
1718 .first_offset
= 0x10000,
1721 .flags
= FL_BASE0
|FL_NOIRQ
,
1723 .base_baud
= 458333,
1726 .first_offset
= 0x20178,
1730 * Computone - uses IOMEM.
1732 [pbn_computone_4
] = {
1735 .base_baud
= 921600,
1736 .uart_offset
= 0x40,
1738 .first_offset
= 0x200,
1740 [pbn_computone_6
] = {
1743 .base_baud
= 921600,
1744 .uart_offset
= 0x40,
1746 .first_offset
= 0x200,
1748 [pbn_computone_8
] = {
1751 .base_baud
= 921600,
1752 .uart_offset
= 0x40,
1754 .first_offset
= 0x200,
1759 .base_baud
= 460800,
1764 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
1765 * Only basic 16550A support.
1766 * XR17C15[24] are not tested, but they should work.
1768 [pbn_exar_XR17C152
] = {
1771 .base_baud
= 921600,
1772 .uart_offset
= 0x200,
1774 [pbn_exar_XR17C154
] = {
1777 .base_baud
= 921600,
1778 .uart_offset
= 0x200,
1780 [pbn_exar_XR17C158
] = {
1783 .base_baud
= 921600,
1784 .uart_offset
= 0x200,
1787 * PA Semi PWRficient PA6T-1682M on-chip UART
1789 [pbn_pasemi_1682M
] = {
1792 .base_baud
= 8333333,
1796 static const struct pci_device_id softmodem_blacklist
[] = {
1797 { PCI_VDEVICE(AL
, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
1801 * Given a complete unknown PCI device, try to use some heuristics to
1802 * guess what the configuration might be, based on the pitiful PCI
1803 * serial specs. Returns 0 on success, 1 on failure.
1805 static int __devinit
1806 serial_pci_guess_board(struct pci_dev
*dev
, struct pciserial_board
*board
)
1808 const struct pci_device_id
*blacklist
;
1809 int num_iomem
, num_port
, first_port
= -1, i
;
1812 * If it is not a communications device or the programming
1813 * interface is greater than 6, give up.
1815 * (Should we try to make guesses for multiport serial devices
1818 if ((((dev
->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL
) &&
1819 ((dev
->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM
)) ||
1820 (dev
->class & 0xff) > 6)
1824 * Do not access blacklisted devices that are known not to
1825 * feature serial ports.
1827 for (blacklist
= softmodem_blacklist
;
1828 blacklist
< softmodem_blacklist
+ ARRAY_SIZE(softmodem_blacklist
);
1830 if (dev
->vendor
== blacklist
->vendor
&&
1831 dev
->device
== blacklist
->device
)
1835 num_iomem
= num_port
= 0;
1836 for (i
= 0; i
< PCI_NUM_BAR_RESOURCES
; i
++) {
1837 if (pci_resource_flags(dev
, i
) & IORESOURCE_IO
) {
1839 if (first_port
== -1)
1842 if (pci_resource_flags(dev
, i
) & IORESOURCE_MEM
)
1847 * If there is 1 or 0 iomem regions, and exactly one port,
1848 * use it. We guess the number of ports based on the IO
1851 if (num_iomem
<= 1 && num_port
== 1) {
1852 board
->flags
= first_port
;
1853 board
->num_ports
= pci_resource_len(dev
, first_port
) / 8;
1858 * Now guess if we've got a board which indexes by BARs.
1859 * Each IO BAR should be 8 bytes, and they should follow
1864 for (i
= 0; i
< PCI_NUM_BAR_RESOURCES
; i
++) {
1865 if (pci_resource_flags(dev
, i
) & IORESOURCE_IO
&&
1866 pci_resource_len(dev
, i
) == 8 &&
1867 (first_port
== -1 || (first_port
+ num_port
) == i
)) {
1869 if (first_port
== -1)
1875 board
->flags
= first_port
| FL_BASE_BARS
;
1876 board
->num_ports
= num_port
;
1884 serial_pci_matches(struct pciserial_board
*board
,
1885 struct pciserial_board
*guessed
)
1888 board
->num_ports
== guessed
->num_ports
&&
1889 board
->base_baud
== guessed
->base_baud
&&
1890 board
->uart_offset
== guessed
->uart_offset
&&
1891 board
->reg_shift
== guessed
->reg_shift
&&
1892 board
->first_offset
== guessed
->first_offset
;
1896 * Oxford Semiconductor Inc.
1897 * Check that device is part of the Tornado range of devices, then determine
1898 * the number of ports available on the device.
1900 static int pci_oxsemi_tornado_init(struct pci_dev
*dev
, struct pciserial_board
*board
)
1903 unsigned long deviceID
;
1904 unsigned int number_uarts
;
1906 /* OxSemi Tornado devices are all 0xCxxx */
1907 if (dev
->vendor
== PCI_VENDOR_ID_OXSEMI
&&
1908 (dev
->device
& 0xF000) != 0xC000)
1911 p
= pci_iomap(dev
, 0, 5);
1915 deviceID
= ioread32(p
);
1916 /* Tornado device */
1917 if (deviceID
== 0x07000200) {
1918 number_uarts
= ioread8(p
+ 4);
1919 board
->num_ports
= number_uarts
;
1921 "%d ports detected on Oxford PCI Express device\n",
1924 pci_iounmap(dev
, p
);
1928 struct serial_private
*
1929 pciserial_init_ports(struct pci_dev
*dev
, struct pciserial_board
*board
)
1931 struct uart_port serial_port
;
1932 struct serial_private
*priv
;
1933 struct pci_serial_quirk
*quirk
;
1934 int rc
, nr_ports
, i
;
1937 * Find number of ports on board
1939 if (dev
->vendor
== PCI_VENDOR_ID_OXSEMI
||
1940 dev
->vendor
== PCI_VENDOR_ID_MAINPINE
)
1941 pci_oxsemi_tornado_init(dev
, board
);
1943 nr_ports
= board
->num_ports
;
1946 * Find an init and setup quirks.
1948 quirk
= find_quirk(dev
);
1951 * Run the new-style initialization function.
1952 * The initialization function returns:
1954 * 0 - use board->num_ports
1955 * >0 - number of ports
1958 rc
= quirk
->init(dev
);
1967 priv
= kzalloc(sizeof(struct serial_private
) +
1968 sizeof(unsigned int) * nr_ports
,
1971 priv
= ERR_PTR(-ENOMEM
);
1976 priv
->quirk
= quirk
;
1978 memset(&serial_port
, 0, sizeof(struct uart_port
));
1979 serial_port
.flags
= UPF_SKIP_TEST
| UPF_BOOT_AUTOCONF
| UPF_SHARE_IRQ
;
1980 serial_port
.uartclk
= board
->base_baud
* 16;
1981 serial_port
.irq
= get_pci_irq(dev
, board
);
1982 serial_port
.dev
= &dev
->dev
;
1984 for (i
= 0; i
< nr_ports
; i
++) {
1985 if (quirk
->setup(priv
, board
, &serial_port
, i
))
1988 #ifdef SERIAL_DEBUG_PCI
1989 printk(KERN_DEBUG
"Setup PCI port: port %x, irq %d, type %d\n",
1990 serial_port
.iobase
, serial_port
.irq
, serial_port
.iotype
);
1993 priv
->line
[i
] = serial8250_register_port(&serial_port
);
1994 if (priv
->line
[i
] < 0) {
1995 printk(KERN_WARNING
"Couldn't register serial port %s: %d\n", pci_name(dev
), priv
->line
[i
]);
2008 EXPORT_SYMBOL_GPL(pciserial_init_ports
);
2010 void pciserial_remove_ports(struct serial_private
*priv
)
2012 struct pci_serial_quirk
*quirk
;
2015 for (i
= 0; i
< priv
->nr
; i
++)
2016 serial8250_unregister_port(priv
->line
[i
]);
2018 for (i
= 0; i
< PCI_NUM_BAR_RESOURCES
; i
++) {
2019 if (priv
->remapped_bar
[i
])
2020 iounmap(priv
->remapped_bar
[i
]);
2021 priv
->remapped_bar
[i
] = NULL
;
2025 * Find the exit quirks.
2027 quirk
= find_quirk(priv
->dev
);
2029 quirk
->exit(priv
->dev
);
2033 EXPORT_SYMBOL_GPL(pciserial_remove_ports
);
2035 void pciserial_suspend_ports(struct serial_private
*priv
)
2039 for (i
= 0; i
< priv
->nr
; i
++)
2040 if (priv
->line
[i
] >= 0)
2041 serial8250_suspend_port(priv
->line
[i
]);
2043 EXPORT_SYMBOL_GPL(pciserial_suspend_ports
);
2045 void pciserial_resume_ports(struct serial_private
*priv
)
2050 * Ensure that the board is correctly configured.
2052 if (priv
->quirk
->init
)
2053 priv
->quirk
->init(priv
->dev
);
2055 for (i
= 0; i
< priv
->nr
; i
++)
2056 if (priv
->line
[i
] >= 0)
2057 serial8250_resume_port(priv
->line
[i
]);
2059 EXPORT_SYMBOL_GPL(pciserial_resume_ports
);
2062 * Probe one serial board. Unfortunately, there is no rhyme nor reason
2063 * to the arrangement of serial ports on a PCI card.
2065 static int __devinit
2066 pciserial_init_one(struct pci_dev
*dev
, const struct pci_device_id
*ent
)
2068 struct serial_private
*priv
;
2069 struct pciserial_board
*board
, tmp
;
2072 if (ent
->driver_data
>= ARRAY_SIZE(pci_boards
)) {
2073 printk(KERN_ERR
"pci_init_one: invalid driver_data: %ld\n",
2078 board
= &pci_boards
[ent
->driver_data
];
2080 rc
= pci_enable_device(dev
);
2084 if (ent
->driver_data
== pbn_default
) {
2086 * Use a copy of the pci_board entry for this;
2087 * avoid changing entries in the table.
2089 memcpy(&tmp
, board
, sizeof(struct pciserial_board
));
2093 * We matched one of our class entries. Try to
2094 * determine the parameters of this board.
2096 rc
= serial_pci_guess_board(dev
, board
);
2101 * We matched an explicit entry. If we are able to
2102 * detect this boards settings with our heuristic,
2103 * then we no longer need this entry.
2105 memcpy(&tmp
, &pci_boards
[pbn_default
],
2106 sizeof(struct pciserial_board
));
2107 rc
= serial_pci_guess_board(dev
, &tmp
);
2108 if (rc
== 0 && serial_pci_matches(board
, &tmp
))
2109 moan_device("Redundant entry in serial pci_table.",
2113 priv
= pciserial_init_ports(dev
, board
);
2114 if (!IS_ERR(priv
)) {
2115 pci_set_drvdata(dev
, priv
);
2122 pci_disable_device(dev
);
2126 static void __devexit
pciserial_remove_one(struct pci_dev
*dev
)
2128 struct serial_private
*priv
= pci_get_drvdata(dev
);
2130 pci_set_drvdata(dev
, NULL
);
2132 pciserial_remove_ports(priv
);
2134 pci_disable_device(dev
);
2138 static int pciserial_suspend_one(struct pci_dev
*dev
, pm_message_t state
)
2140 struct serial_private
*priv
= pci_get_drvdata(dev
);
2143 pciserial_suspend_ports(priv
);
2145 pci_save_state(dev
);
2146 pci_set_power_state(dev
, pci_choose_state(dev
, state
));
2150 static int pciserial_resume_one(struct pci_dev
*dev
)
2153 struct serial_private
*priv
= pci_get_drvdata(dev
);
2155 pci_set_power_state(dev
, PCI_D0
);
2156 pci_restore_state(dev
);
2160 * The device may have been disabled. Re-enable it.
2162 err
= pci_enable_device(dev
);
2163 /* FIXME: We cannot simply error out here */
2165 printk(KERN_ERR
"pciserial: Unable to re-enable ports, trying to continue.\n");
2166 pciserial_resume_ports(priv
);
2172 static struct pci_device_id serial_pci_tbl
[] = {
2173 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
2174 { PCI_VENDOR_ID_ADVANTECH
, PCI_DEVICE_ID_ADVANTECH_PCI3620
,
2175 PCI_DEVICE_ID_ADVANTECH_PCI3620
, 0x0001, 0, 0,
2177 { PCI_VENDOR_ID_V3
, PCI_DEVICE_ID_V3_V960
,
2178 PCI_SUBVENDOR_ID_CONNECT_TECH
,
2179 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232
, 0, 0,
2181 { PCI_VENDOR_ID_V3
, PCI_DEVICE_ID_V3_V960
,
2182 PCI_SUBVENDOR_ID_CONNECT_TECH
,
2183 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232
, 0, 0,
2185 { PCI_VENDOR_ID_V3
, PCI_DEVICE_ID_V3_V960
,
2186 PCI_SUBVENDOR_ID_CONNECT_TECH
,
2187 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232
, 0, 0,
2189 { PCI_VENDOR_ID_V3
, PCI_DEVICE_ID_V3_V351
,
2190 PCI_SUBVENDOR_ID_CONNECT_TECH
,
2191 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232
, 0, 0,
2193 { PCI_VENDOR_ID_V3
, PCI_DEVICE_ID_V3_V351
,
2194 PCI_SUBVENDOR_ID_CONNECT_TECH
,
2195 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232
, 0, 0,
2197 { PCI_VENDOR_ID_V3
, PCI_DEVICE_ID_V3_V351
,
2198 PCI_SUBVENDOR_ID_CONNECT_TECH
,
2199 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232
, 0, 0,
2201 { PCI_VENDOR_ID_V3
, PCI_DEVICE_ID_V3_V351
,
2202 PCI_SUBVENDOR_ID_CONNECT_TECH
,
2203 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485
, 0, 0,
2205 { PCI_VENDOR_ID_V3
, PCI_DEVICE_ID_V3_V351
,
2206 PCI_SUBVENDOR_ID_CONNECT_TECH
,
2207 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4
, 0, 0,
2209 { PCI_VENDOR_ID_V3
, PCI_DEVICE_ID_V3_V351
,
2210 PCI_SUBVENDOR_ID_CONNECT_TECH
,
2211 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485
, 0, 0,
2213 { PCI_VENDOR_ID_V3
, PCI_DEVICE_ID_V3_V351
,
2214 PCI_SUBVENDOR_ID_CONNECT_TECH
,
2215 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2
, 0, 0,
2217 { PCI_VENDOR_ID_V3
, PCI_DEVICE_ID_V3_V351
,
2218 PCI_SUBVENDOR_ID_CONNECT_TECH
,
2219 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485
, 0, 0,
2221 { PCI_VENDOR_ID_V3
, PCI_DEVICE_ID_V3_V351
,
2222 PCI_SUBVENDOR_ID_CONNECT_TECH
,
2223 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6
, 0, 0,
2225 { PCI_VENDOR_ID_V3
, PCI_DEVICE_ID_V3_V351
,
2226 PCI_SUBVENDOR_ID_CONNECT_TECH
,
2227 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1
, 0, 0,
2229 { PCI_VENDOR_ID_V3
, PCI_DEVICE_ID_V3_V351
,
2230 PCI_SUBVENDOR_ID_CONNECT_TECH
,
2231 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1
, 0, 0,
2233 { PCI_VENDOR_ID_V3
, PCI_DEVICE_ID_V3_V351
,
2234 PCI_SUBVENDOR_ID_CONNECT_TECH
,
2235 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ
, 0, 0,
2237 { PCI_VENDOR_ID_OXSEMI
, PCI_DEVICE_ID_OXSEMI_16PCI954
,
2238 PCI_SUBVENDOR_ID_CONNECT_TECH
,
2239 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2
, 0, 0,
2241 { PCI_VENDOR_ID_OXSEMI
, PCI_DEVICE_ID_OXSEMI_16PCI954
,
2242 PCI_SUBVENDOR_ID_CONNECT_TECH
,
2243 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4
, 0, 0,
2245 { PCI_VENDOR_ID_OXSEMI
, PCI_DEVICE_ID_OXSEMI_16PCI954
,
2246 PCI_VENDOR_ID_AFAVLAB
,
2247 PCI_SUBDEVICE_ID_AFAVLAB_P061
, 0, 0,
2249 { PCI_VENDOR_ID_EXAR
, PCI_DEVICE_ID_EXAR_XR17C152
,
2250 PCI_SUBVENDOR_ID_CONNECT_TECH
,
2251 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232
, 0, 0,
2252 pbn_b0_2_1843200_200
},
2253 { PCI_VENDOR_ID_EXAR
, PCI_DEVICE_ID_EXAR_XR17C154
,
2254 PCI_SUBVENDOR_ID_CONNECT_TECH
,
2255 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232
, 0, 0,
2256 pbn_b0_4_1843200_200
},
2257 { PCI_VENDOR_ID_EXAR
, PCI_DEVICE_ID_EXAR_XR17C158
,
2258 PCI_SUBVENDOR_ID_CONNECT_TECH
,
2259 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232
, 0, 0,
2260 pbn_b0_8_1843200_200
},
2261 { PCI_VENDOR_ID_EXAR
, PCI_DEVICE_ID_EXAR_XR17C152
,
2262 PCI_SUBVENDOR_ID_CONNECT_TECH
,
2263 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1
, 0, 0,
2264 pbn_b0_2_1843200_200
},
2265 { PCI_VENDOR_ID_EXAR
, PCI_DEVICE_ID_EXAR_XR17C154
,
2266 PCI_SUBVENDOR_ID_CONNECT_TECH
,
2267 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2
, 0, 0,
2268 pbn_b0_4_1843200_200
},
2269 { PCI_VENDOR_ID_EXAR
, PCI_DEVICE_ID_EXAR_XR17C158
,
2270 PCI_SUBVENDOR_ID_CONNECT_TECH
,
2271 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4
, 0, 0,
2272 pbn_b0_8_1843200_200
},
2273 { PCI_VENDOR_ID_EXAR
, PCI_DEVICE_ID_EXAR_XR17C152
,
2274 PCI_SUBVENDOR_ID_CONNECT_TECH
,
2275 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2
, 0, 0,
2276 pbn_b0_2_1843200_200
},
2277 { PCI_VENDOR_ID_EXAR
, PCI_DEVICE_ID_EXAR_XR17C154
,
2278 PCI_SUBVENDOR_ID_CONNECT_TECH
,
2279 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4
, 0, 0,
2280 pbn_b0_4_1843200_200
},
2281 { PCI_VENDOR_ID_EXAR
, PCI_DEVICE_ID_EXAR_XR17C158
,
2282 PCI_SUBVENDOR_ID_CONNECT_TECH
,
2283 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8
, 0, 0,
2284 pbn_b0_8_1843200_200
},
2285 { PCI_VENDOR_ID_EXAR
, PCI_DEVICE_ID_EXAR_XR17C152
,
2286 PCI_SUBVENDOR_ID_CONNECT_TECH
,
2287 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485
, 0, 0,
2288 pbn_b0_2_1843200_200
},
2289 { PCI_VENDOR_ID_EXAR
, PCI_DEVICE_ID_EXAR_XR17C154
,
2290 PCI_SUBVENDOR_ID_CONNECT_TECH
,
2291 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485
, 0, 0,
2292 pbn_b0_4_1843200_200
},
2293 { PCI_VENDOR_ID_EXAR
, PCI_DEVICE_ID_EXAR_XR17C158
,
2294 PCI_SUBVENDOR_ID_CONNECT_TECH
,
2295 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485
, 0, 0,
2296 pbn_b0_8_1843200_200
},
2298 { PCI_VENDOR_ID_SEALEVEL
, PCI_DEVICE_ID_SEALEVEL_U530
,
2299 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2300 pbn_b2_bt_1_115200
},
2301 { PCI_VENDOR_ID_SEALEVEL
, PCI_DEVICE_ID_SEALEVEL_UCOMM2
,
2302 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2303 pbn_b2_bt_2_115200
},
2304 { PCI_VENDOR_ID_SEALEVEL
, PCI_DEVICE_ID_SEALEVEL_UCOMM422
,
2305 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2306 pbn_b2_bt_4_115200
},
2307 { PCI_VENDOR_ID_SEALEVEL
, PCI_DEVICE_ID_SEALEVEL_UCOMM232
,
2308 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2309 pbn_b2_bt_2_115200
},
2310 { PCI_VENDOR_ID_SEALEVEL
, PCI_DEVICE_ID_SEALEVEL_COMM4
,
2311 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2312 pbn_b2_bt_4_115200
},
2313 { PCI_VENDOR_ID_SEALEVEL
, PCI_DEVICE_ID_SEALEVEL_COMM8
,
2314 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2316 { PCI_VENDOR_ID_SEALEVEL
, PCI_DEVICE_ID_SEALEVEL_7803
,
2317 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2319 { PCI_VENDOR_ID_SEALEVEL
, PCI_DEVICE_ID_SEALEVEL_UCOMM8
,
2320 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2323 { PCI_VENDOR_ID_PLX
, PCI_DEVICE_ID_PLX_GTEK_SERIAL2
,
2324 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2325 pbn_b2_bt_2_115200
},
2326 { PCI_VENDOR_ID_PLX
, PCI_DEVICE_ID_PLX_SPCOM200
,
2327 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2328 pbn_b2_bt_2_921600
},
2330 * VScom SPCOM800, from sl@s.pl
2332 { PCI_VENDOR_ID_PLX
, PCI_DEVICE_ID_PLX_SPCOM800
,
2333 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2335 { PCI_VENDOR_ID_PLX
, PCI_DEVICE_ID_PLX_1077
,
2336 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2338 /* Unknown card - subdevice 0x1584 */
2339 { PCI_VENDOR_ID_PLX
, PCI_DEVICE_ID_PLX_9050
,
2341 PCI_SUBDEVICE_ID_UNKNOWN_0x1584
, 0, 0,
2343 { PCI_VENDOR_ID_PLX
, PCI_DEVICE_ID_PLX_9050
,
2344 PCI_SUBVENDOR_ID_KEYSPAN
,
2345 PCI_SUBDEVICE_ID_KEYSPAN_SX2
, 0, 0,
2347 { PCI_VENDOR_ID_PANACOM
, PCI_DEVICE_ID_PANACOM_QUADMODEM
,
2348 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2350 { PCI_VENDOR_ID_PANACOM
, PCI_DEVICE_ID_PANACOM_DUALMODEM
,
2351 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2353 { PCI_VENDOR_ID_PLX
, PCI_DEVICE_ID_PLX_9030
,
2354 PCI_VENDOR_ID_ESDGMBH
,
2355 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4
, 0, 0,
2357 { PCI_VENDOR_ID_PLX
, PCI_DEVICE_ID_PLX_9050
,
2358 PCI_SUBVENDOR_ID_CHASE_PCIFAST
,
2359 PCI_SUBDEVICE_ID_CHASE_PCIFAST4
, 0, 0,
2361 { PCI_VENDOR_ID_PLX
, PCI_DEVICE_ID_PLX_9050
,
2362 PCI_SUBVENDOR_ID_CHASE_PCIFAST
,
2363 PCI_SUBDEVICE_ID_CHASE_PCIFAST8
, 0, 0,
2365 { PCI_VENDOR_ID_PLX
, PCI_DEVICE_ID_PLX_9050
,
2366 PCI_SUBVENDOR_ID_CHASE_PCIFAST
,
2367 PCI_SUBDEVICE_ID_CHASE_PCIFAST16
, 0, 0,
2369 { PCI_VENDOR_ID_PLX
, PCI_DEVICE_ID_PLX_9050
,
2370 PCI_SUBVENDOR_ID_CHASE_PCIFAST
,
2371 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC
, 0, 0,
2373 { PCI_VENDOR_ID_PLX
, PCI_DEVICE_ID_PLX_9050
,
2374 PCI_SUBVENDOR_ID_CHASE_PCIRAS
,
2375 PCI_SUBDEVICE_ID_CHASE_PCIRAS4
, 0, 0,
2377 { PCI_VENDOR_ID_PLX
, PCI_DEVICE_ID_PLX_9050
,
2378 PCI_SUBVENDOR_ID_CHASE_PCIRAS
,
2379 PCI_SUBDEVICE_ID_CHASE_PCIRAS8
, 0, 0,
2381 { PCI_VENDOR_ID_PLX
, PCI_DEVICE_ID_PLX_9050
,
2382 PCI_SUBVENDOR_ID_EXSYS
,
2383 PCI_SUBDEVICE_ID_EXSYS_4055
, 0, 0,
2386 * Megawolf Romulus PCI Serial Card, from Mike Hudson
2389 { PCI_VENDOR_ID_PLX
, PCI_DEVICE_ID_PLX_ROMULUS
,
2390 0x10b5, 0x106a, 0, 0,
2392 { PCI_VENDOR_ID_QUATECH
, PCI_DEVICE_ID_QUATECH_QSC100
,
2393 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2395 { PCI_VENDOR_ID_QUATECH
, PCI_DEVICE_ID_QUATECH_DSC100
,
2396 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2398 { PCI_VENDOR_ID_QUATECH
, PCI_DEVICE_ID_QUATECH_ESC100D
,
2399 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2401 { PCI_VENDOR_ID_QUATECH
, PCI_DEVICE_ID_QUATECH_ESC100M
,
2402 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2404 { PCI_VENDOR_ID_SPECIALIX
, PCI_DEVICE_ID_OXSEMI_16PCI954
,
2405 PCI_VENDOR_ID_SPECIALIX
, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4
,
2408 { PCI_VENDOR_ID_OXSEMI
, PCI_DEVICE_ID_OXSEMI_16PCI954
,
2409 PCI_SUBVENDOR_ID_SIIG
, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL
,
2414 * The below card is a little controversial since it is the
2415 * subject of a PCI vendor/device ID clash. (See
2416 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
2417 * For now just used the hex ID 0x950a.
2419 { PCI_VENDOR_ID_OXSEMI
, 0x950a,
2420 PCI_SUBVENDOR_ID_SIIG
, PCI_SUBDEVICE_ID_SIIG_DUAL_SERIAL
, 0, 0,
2422 { PCI_VENDOR_ID_OXSEMI
, 0x950a,
2423 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2425 { PCI_VENDOR_ID_OXSEMI
, PCI_DEVICE_ID_OXSEMI_16PCI954
,
2426 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2428 { PCI_VENDOR_ID_OXSEMI
, PCI_DEVICE_ID_OXSEMI_16PCI952
,
2429 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2430 pbn_b0_bt_2_921600
},
2433 * Oxford Semiconductor Inc. Tornado PCI express device range.
2435 { PCI_VENDOR_ID_OXSEMI
, 0xc101, /* OXPCIe952 1 Legacy UART */
2436 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2438 { PCI_VENDOR_ID_OXSEMI
, 0xc105, /* OXPCIe952 1 Legacy UART */
2439 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2441 { PCI_VENDOR_ID_OXSEMI
, 0xc11b, /* OXPCIe952 1 Native UART */
2442 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2443 pbn_oxsemi_1_4000000
},
2444 { PCI_VENDOR_ID_OXSEMI
, 0xc11f, /* OXPCIe952 1 Native UART */
2445 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2446 pbn_oxsemi_1_4000000
},
2447 { PCI_VENDOR_ID_OXSEMI
, 0xc120, /* OXPCIe952 1 Legacy UART */
2448 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2450 { PCI_VENDOR_ID_OXSEMI
, 0xc124, /* OXPCIe952 1 Legacy UART */
2451 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2453 { PCI_VENDOR_ID_OXSEMI
, 0xc138, /* OXPCIe952 1 Native UART */
2454 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2455 pbn_oxsemi_1_4000000
},
2456 { PCI_VENDOR_ID_OXSEMI
, 0xc13d, /* OXPCIe952 1 Native UART */
2457 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2458 pbn_oxsemi_1_4000000
},
2459 { PCI_VENDOR_ID_OXSEMI
, 0xc140, /* OXPCIe952 1 Legacy UART */
2460 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2462 { PCI_VENDOR_ID_OXSEMI
, 0xc141, /* OXPCIe952 1 Legacy UART */
2463 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2465 { PCI_VENDOR_ID_OXSEMI
, 0xc144, /* OXPCIe952 1 Legacy UART */
2466 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2468 { PCI_VENDOR_ID_OXSEMI
, 0xc145, /* OXPCIe952 1 Legacy UART */
2469 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2471 { PCI_VENDOR_ID_OXSEMI
, 0xc158, /* OXPCIe952 2 Native UART */
2472 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2473 pbn_oxsemi_2_4000000
},
2474 { PCI_VENDOR_ID_OXSEMI
, 0xc15d, /* OXPCIe952 2 Native UART */
2475 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2476 pbn_oxsemi_2_4000000
},
2477 { PCI_VENDOR_ID_OXSEMI
, 0xc208, /* OXPCIe954 4 Native UART */
2478 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2479 pbn_oxsemi_4_4000000
},
2480 { PCI_VENDOR_ID_OXSEMI
, 0xc20d, /* OXPCIe954 4 Native UART */
2481 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2482 pbn_oxsemi_4_4000000
},
2483 { PCI_VENDOR_ID_OXSEMI
, 0xc308, /* OXPCIe958 8 Native UART */
2484 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2485 pbn_oxsemi_8_4000000
},
2486 { PCI_VENDOR_ID_OXSEMI
, 0xc30d, /* OXPCIe958 8 Native UART */
2487 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2488 pbn_oxsemi_8_4000000
},
2489 { PCI_VENDOR_ID_OXSEMI
, 0xc40b, /* OXPCIe200 1 Native UART */
2490 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2491 pbn_oxsemi_1_4000000
},
2492 { PCI_VENDOR_ID_OXSEMI
, 0xc40f, /* OXPCIe200 1 Native UART */
2493 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2494 pbn_oxsemi_1_4000000
},
2495 { PCI_VENDOR_ID_OXSEMI
, 0xc41b, /* OXPCIe200 1 Native UART */
2496 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2497 pbn_oxsemi_1_4000000
},
2498 { PCI_VENDOR_ID_OXSEMI
, 0xc41f, /* OXPCIe200 1 Native UART */
2499 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2500 pbn_oxsemi_1_4000000
},
2501 { PCI_VENDOR_ID_OXSEMI
, 0xc42b, /* OXPCIe200 1 Native UART */
2502 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2503 pbn_oxsemi_1_4000000
},
2504 { PCI_VENDOR_ID_OXSEMI
, 0xc42f, /* OXPCIe200 1 Native UART */
2505 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2506 pbn_oxsemi_1_4000000
},
2507 { PCI_VENDOR_ID_OXSEMI
, 0xc43b, /* OXPCIe200 1 Native UART */
2508 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2509 pbn_oxsemi_1_4000000
},
2510 { PCI_VENDOR_ID_OXSEMI
, 0xc43f, /* OXPCIe200 1 Native UART */
2511 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2512 pbn_oxsemi_1_4000000
},
2513 { PCI_VENDOR_ID_OXSEMI
, 0xc44b, /* OXPCIe200 1 Native UART */
2514 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2515 pbn_oxsemi_1_4000000
},
2516 { PCI_VENDOR_ID_OXSEMI
, 0xc44f, /* OXPCIe200 1 Native UART */
2517 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2518 pbn_oxsemi_1_4000000
},
2519 { PCI_VENDOR_ID_OXSEMI
, 0xc45b, /* OXPCIe200 1 Native UART */
2520 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2521 pbn_oxsemi_1_4000000
},
2522 { PCI_VENDOR_ID_OXSEMI
, 0xc45f, /* OXPCIe200 1 Native UART */
2523 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2524 pbn_oxsemi_1_4000000
},
2525 { PCI_VENDOR_ID_OXSEMI
, 0xc46b, /* OXPCIe200 1 Native UART */
2526 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2527 pbn_oxsemi_1_4000000
},
2528 { PCI_VENDOR_ID_OXSEMI
, 0xc46f, /* OXPCIe200 1 Native UART */
2529 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2530 pbn_oxsemi_1_4000000
},
2531 { PCI_VENDOR_ID_OXSEMI
, 0xc47b, /* OXPCIe200 1 Native UART */
2532 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2533 pbn_oxsemi_1_4000000
},
2534 { PCI_VENDOR_ID_OXSEMI
, 0xc47f, /* OXPCIe200 1 Native UART */
2535 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2536 pbn_oxsemi_1_4000000
},
2537 { PCI_VENDOR_ID_OXSEMI
, 0xc48b, /* OXPCIe200 1 Native UART */
2538 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2539 pbn_oxsemi_1_4000000
},
2540 { PCI_VENDOR_ID_OXSEMI
, 0xc48f, /* OXPCIe200 1 Native UART */
2541 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2542 pbn_oxsemi_1_4000000
},
2543 { PCI_VENDOR_ID_OXSEMI
, 0xc49b, /* OXPCIe200 1 Native UART */
2544 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2545 pbn_oxsemi_1_4000000
},
2546 { PCI_VENDOR_ID_OXSEMI
, 0xc49f, /* OXPCIe200 1 Native UART */
2547 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2548 pbn_oxsemi_1_4000000
},
2549 { PCI_VENDOR_ID_OXSEMI
, 0xc4ab, /* OXPCIe200 1 Native UART */
2550 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2551 pbn_oxsemi_1_4000000
},
2552 { PCI_VENDOR_ID_OXSEMI
, 0xc4af, /* OXPCIe200 1 Native UART */
2553 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2554 pbn_oxsemi_1_4000000
},
2555 { PCI_VENDOR_ID_OXSEMI
, 0xc4bb, /* OXPCIe200 1 Native UART */
2556 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2557 pbn_oxsemi_1_4000000
},
2558 { PCI_VENDOR_ID_OXSEMI
, 0xc4bf, /* OXPCIe200 1 Native UART */
2559 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2560 pbn_oxsemi_1_4000000
},
2561 { PCI_VENDOR_ID_OXSEMI
, 0xc4cb, /* OXPCIe200 1 Native UART */
2562 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2563 pbn_oxsemi_1_4000000
},
2564 { PCI_VENDOR_ID_OXSEMI
, 0xc4cf, /* OXPCIe200 1 Native UART */
2565 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2566 pbn_oxsemi_1_4000000
},
2568 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
2570 { PCI_VENDOR_ID_MAINPINE
, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
2571 PCI_VENDOR_ID_MAINPINE
, 0x4001, 0, 0,
2572 pbn_oxsemi_1_4000000
},
2573 { PCI_VENDOR_ID_MAINPINE
, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
2574 PCI_VENDOR_ID_MAINPINE
, 0x4002, 0, 0,
2575 pbn_oxsemi_2_4000000
},
2576 { PCI_VENDOR_ID_MAINPINE
, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
2577 PCI_VENDOR_ID_MAINPINE
, 0x4004, 0, 0,
2578 pbn_oxsemi_4_4000000
},
2579 { PCI_VENDOR_ID_MAINPINE
, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
2580 PCI_VENDOR_ID_MAINPINE
, 0x4008, 0, 0,
2581 pbn_oxsemi_8_4000000
},
2583 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
2584 * from skokodyn@yahoo.com
2586 { PCI_VENDOR_ID_SBSMODULARIO
, PCI_DEVICE_ID_OCTPRO
,
2587 PCI_SUBVENDOR_ID_SBSMODULARIO
, PCI_SUBDEVICE_ID_OCTPRO232
, 0, 0,
2589 { PCI_VENDOR_ID_SBSMODULARIO
, PCI_DEVICE_ID_OCTPRO
,
2590 PCI_SUBVENDOR_ID_SBSMODULARIO
, PCI_SUBDEVICE_ID_OCTPRO422
, 0, 0,
2592 { PCI_VENDOR_ID_SBSMODULARIO
, PCI_DEVICE_ID_OCTPRO
,
2593 PCI_SUBVENDOR_ID_SBSMODULARIO
, PCI_SUBDEVICE_ID_POCTAL232
, 0, 0,
2595 { PCI_VENDOR_ID_SBSMODULARIO
, PCI_DEVICE_ID_OCTPRO
,
2596 PCI_SUBVENDOR_ID_SBSMODULARIO
, PCI_SUBDEVICE_ID_POCTAL422
, 0, 0,
2600 * Digitan DS560-558, from jimd@esoft.com
2602 { PCI_VENDOR_ID_ATT
, PCI_DEVICE_ID_ATT_VENUS_MODEM
,
2603 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2607 * Titan Electronic cards
2608 * The 400L and 800L have a custom setup quirk.
2610 { PCI_VENDOR_ID_TITAN
, PCI_DEVICE_ID_TITAN_100
,
2611 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2613 { PCI_VENDOR_ID_TITAN
, PCI_DEVICE_ID_TITAN_200
,
2614 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2616 { PCI_VENDOR_ID_TITAN
, PCI_DEVICE_ID_TITAN_400
,
2617 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2619 { PCI_VENDOR_ID_TITAN
, PCI_DEVICE_ID_TITAN_800B
,
2620 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2622 { PCI_VENDOR_ID_TITAN
, PCI_DEVICE_ID_TITAN_100L
,
2623 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2625 { PCI_VENDOR_ID_TITAN
, PCI_DEVICE_ID_TITAN_200L
,
2626 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2627 pbn_b1_bt_2_921600
},
2628 { PCI_VENDOR_ID_TITAN
, PCI_DEVICE_ID_TITAN_400L
,
2629 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2630 pbn_b0_bt_4_921600
},
2631 { PCI_VENDOR_ID_TITAN
, PCI_DEVICE_ID_TITAN_800L
,
2632 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2633 pbn_b0_bt_8_921600
},
2635 { PCI_VENDOR_ID_SIIG
, PCI_DEVICE_ID_SIIG_1S_10x_550
,
2636 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2638 { PCI_VENDOR_ID_SIIG
, PCI_DEVICE_ID_SIIG_1S_10x_650
,
2639 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2641 { PCI_VENDOR_ID_SIIG
, PCI_DEVICE_ID_SIIG_1S_10x_850
,
2642 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2644 { PCI_VENDOR_ID_SIIG
, PCI_DEVICE_ID_SIIG_2S_10x_550
,
2645 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2646 pbn_b2_bt_2_921600
},
2647 { PCI_VENDOR_ID_SIIG
, PCI_DEVICE_ID_SIIG_2S_10x_650
,
2648 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2649 pbn_b2_bt_2_921600
},
2650 { PCI_VENDOR_ID_SIIG
, PCI_DEVICE_ID_SIIG_2S_10x_850
,
2651 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2652 pbn_b2_bt_2_921600
},
2653 { PCI_VENDOR_ID_SIIG
, PCI_DEVICE_ID_SIIG_4S_10x_550
,
2654 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2655 pbn_b2_bt_4_921600
},
2656 { PCI_VENDOR_ID_SIIG
, PCI_DEVICE_ID_SIIG_4S_10x_650
,
2657 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2658 pbn_b2_bt_4_921600
},
2659 { PCI_VENDOR_ID_SIIG
, PCI_DEVICE_ID_SIIG_4S_10x_850
,
2660 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2661 pbn_b2_bt_4_921600
},
2662 { PCI_VENDOR_ID_SIIG
, PCI_DEVICE_ID_SIIG_1S_20x_550
,
2663 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2665 { PCI_VENDOR_ID_SIIG
, PCI_DEVICE_ID_SIIG_1S_20x_650
,
2666 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2668 { PCI_VENDOR_ID_SIIG
, PCI_DEVICE_ID_SIIG_1S_20x_850
,
2669 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2671 { PCI_VENDOR_ID_SIIG
, PCI_DEVICE_ID_SIIG_2S_20x_550
,
2672 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2673 pbn_b0_bt_2_921600
},
2674 { PCI_VENDOR_ID_SIIG
, PCI_DEVICE_ID_SIIG_2S_20x_650
,
2675 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2676 pbn_b0_bt_2_921600
},
2677 { PCI_VENDOR_ID_SIIG
, PCI_DEVICE_ID_SIIG_2S_20x_850
,
2678 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2679 pbn_b0_bt_2_921600
},
2680 { PCI_VENDOR_ID_SIIG
, PCI_DEVICE_ID_SIIG_4S_20x_550
,
2681 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2682 pbn_b0_bt_4_921600
},
2683 { PCI_VENDOR_ID_SIIG
, PCI_DEVICE_ID_SIIG_4S_20x_650
,
2684 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2685 pbn_b0_bt_4_921600
},
2686 { PCI_VENDOR_ID_SIIG
, PCI_DEVICE_ID_SIIG_4S_20x_850
,
2687 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2688 pbn_b0_bt_4_921600
},
2689 { PCI_VENDOR_ID_SIIG
, PCI_DEVICE_ID_SIIG_8S_20x_550
,
2690 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2691 pbn_b0_bt_8_921600
},
2692 { PCI_VENDOR_ID_SIIG
, PCI_DEVICE_ID_SIIG_8S_20x_650
,
2693 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2694 pbn_b0_bt_8_921600
},
2695 { PCI_VENDOR_ID_SIIG
, PCI_DEVICE_ID_SIIG_8S_20x_850
,
2696 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2697 pbn_b0_bt_8_921600
},
2700 * Computone devices submitted by Doug McNash dmcnash@computone.com
2702 { PCI_VENDOR_ID_COMPUTONE
, PCI_DEVICE_ID_COMPUTONE_PG
,
2703 PCI_SUBVENDOR_ID_COMPUTONE
, PCI_SUBDEVICE_ID_COMPUTONE_PG4
,
2704 0, 0, pbn_computone_4
},
2705 { PCI_VENDOR_ID_COMPUTONE
, PCI_DEVICE_ID_COMPUTONE_PG
,
2706 PCI_SUBVENDOR_ID_COMPUTONE
, PCI_SUBDEVICE_ID_COMPUTONE_PG8
,
2707 0, 0, pbn_computone_8
},
2708 { PCI_VENDOR_ID_COMPUTONE
, PCI_DEVICE_ID_COMPUTONE_PG
,
2709 PCI_SUBVENDOR_ID_COMPUTONE
, PCI_SUBDEVICE_ID_COMPUTONE_PG6
,
2710 0, 0, pbn_computone_6
},
2712 { PCI_VENDOR_ID_OXSEMI
, PCI_DEVICE_ID_OXSEMI_16PCI95N
,
2713 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2715 { PCI_VENDOR_ID_TIMEDIA
, PCI_DEVICE_ID_TIMEDIA_1889
,
2716 PCI_VENDOR_ID_TIMEDIA
, PCI_ANY_ID
, 0, 0,
2717 pbn_b0_bt_1_921600
},
2720 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
2722 { PCI_VENDOR_ID_AFAVLAB
, PCI_DEVICE_ID_AFAVLAB_P028
,
2723 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2724 pbn_b0_bt_8_115200
},
2725 { PCI_VENDOR_ID_AFAVLAB
, PCI_DEVICE_ID_AFAVLAB_P030
,
2726 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2727 pbn_b0_bt_8_115200
},
2729 { PCI_VENDOR_ID_LAVA
, PCI_DEVICE_ID_LAVA_DSERIAL
,
2730 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2731 pbn_b0_bt_2_115200
},
2732 { PCI_VENDOR_ID_LAVA
, PCI_DEVICE_ID_LAVA_QUATRO_A
,
2733 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2734 pbn_b0_bt_2_115200
},
2735 { PCI_VENDOR_ID_LAVA
, PCI_DEVICE_ID_LAVA_QUATRO_B
,
2736 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2737 pbn_b0_bt_2_115200
},
2738 { PCI_VENDOR_ID_LAVA
, PCI_DEVICE_ID_LAVA_OCTO_A
,
2739 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2740 pbn_b0_bt_4_460800
},
2741 { PCI_VENDOR_ID_LAVA
, PCI_DEVICE_ID_LAVA_OCTO_B
,
2742 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2743 pbn_b0_bt_4_460800
},
2744 { PCI_VENDOR_ID_LAVA
, PCI_DEVICE_ID_LAVA_PORT_PLUS
,
2745 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2746 pbn_b0_bt_2_460800
},
2747 { PCI_VENDOR_ID_LAVA
, PCI_DEVICE_ID_LAVA_QUAD_A
,
2748 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2749 pbn_b0_bt_2_460800
},
2750 { PCI_VENDOR_ID_LAVA
, PCI_DEVICE_ID_LAVA_QUAD_B
,
2751 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2752 pbn_b0_bt_2_460800
},
2753 { PCI_VENDOR_ID_LAVA
, PCI_DEVICE_ID_LAVA_SSERIAL
,
2754 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2755 pbn_b0_bt_1_115200
},
2756 { PCI_VENDOR_ID_LAVA
, PCI_DEVICE_ID_LAVA_PORT_650
,
2757 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2758 pbn_b0_bt_1_460800
},
2761 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
2762 * Cards are identified by their subsystem vendor IDs, which
2763 * (in hex) match the model number.
2765 * Note that JC140x are RS422/485 cards which require ox950
2766 * ACR = 0x10, and as such are not currently fully supported.
2768 { PCI_VENDOR_ID_KORENIX
, PCI_DEVICE_ID_KORENIX_JETCARDF0
,
2769 0x1204, 0x0004, 0, 0,
2771 { PCI_VENDOR_ID_KORENIX
, PCI_DEVICE_ID_KORENIX_JETCARDF0
,
2772 0x1208, 0x0004, 0, 0,
2774 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
2775 0x1402, 0x0002, 0, 0,
2776 pbn_b0_2_921600 }, */
2777 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
2778 0x1404, 0x0004, 0, 0,
2779 pbn_b0_4_921600 }, */
2780 { PCI_VENDOR_ID_KORENIX
, PCI_DEVICE_ID_KORENIX_JETCARDF1
,
2781 0x1208, 0x0004, 0, 0,
2785 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
2787 { PCI_VENDOR_ID_DELL
, PCI_DEVICE_ID_DELL_RAC4
,
2788 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2792 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
2794 { PCI_VENDOR_ID_DELL
, PCI_DEVICE_ID_DELL_RACIII
,
2795 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2799 * RAStel 2 port modem, gerg@moreton.com.au
2801 { PCI_VENDOR_ID_MORETON
, PCI_DEVICE_ID_RASTEL_2PORT
,
2802 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2803 pbn_b2_bt_2_115200
},
2806 * EKF addition for i960 Boards form EKF with serial port
2808 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_80960_RP
,
2809 0xE4BF, PCI_ANY_ID
, 0, 0,
2813 * Xircom Cardbus/Ethernet combos
2815 { PCI_VENDOR_ID_XIRCOM
, PCI_DEVICE_ID_XIRCOM_X3201_MDM
,
2816 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2819 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
2821 { PCI_VENDOR_ID_XIRCOM
, PCI_DEVICE_ID_XIRCOM_RBM56G
,
2822 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2826 * Untested PCI modems, sent in from various folks...
2830 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
2832 { PCI_VENDOR_ID_ROCKWELL
, 0x1004,
2833 0x1048, 0x1500, 0, 0,
2836 { PCI_VENDOR_ID_SGI
, PCI_DEVICE_ID_SGI_IOC3
,
2843 { PCI_VENDOR_ID_HP
, PCI_DEVICE_ID_HP_DIVA
,
2844 PCI_VENDOR_ID_HP
, PCI_DEVICE_ID_HP_DIVA_RMP3
, 0, 0,
2846 { PCI_VENDOR_ID_HP
, PCI_DEVICE_ID_HP_DIVA
,
2847 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2849 { PCI_VENDOR_ID_HP
, PCI_DEVICE_ID_HP_DIVA_AUX
,
2850 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2853 { PCI_VENDOR_ID_DCI
, PCI_DEVICE_ID_DCI_PCCOM2
,
2854 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2856 { PCI_VENDOR_ID_DCI
, PCI_DEVICE_ID_DCI_PCCOM4
,
2857 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2859 { PCI_VENDOR_ID_DCI
, PCI_DEVICE_ID_DCI_PCCOM8
,
2860 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2864 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
2866 { PCI_VENDOR_ID_EXAR
, PCI_DEVICE_ID_EXAR_XR17C152
,
2867 PCI_ANY_ID
, PCI_ANY_ID
,
2869 0, pbn_exar_XR17C152
},
2870 { PCI_VENDOR_ID_EXAR
, PCI_DEVICE_ID_EXAR_XR17C154
,
2871 PCI_ANY_ID
, PCI_ANY_ID
,
2873 0, pbn_exar_XR17C154
},
2874 { PCI_VENDOR_ID_EXAR
, PCI_DEVICE_ID_EXAR_XR17C158
,
2875 PCI_ANY_ID
, PCI_ANY_ID
,
2877 0, pbn_exar_XR17C158
},
2880 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
2882 { PCI_VENDOR_ID_TOPIC
, PCI_DEVICE_ID_TOPIC_TP560
,
2883 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
2888 { PCI_VENDOR_ID_ITE
, PCI_DEVICE_ID_ITE_8872
,
2889 PCI_ANY_ID
, PCI_ANY_ID
,
2891 pbn_b1_bt_1_115200
},
2896 { PCI_VENDOR_ID_INTASHIELD
, PCI_DEVICE_ID_INTASHIELD_IS200
,
2897 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, /* 135a.0811 */
2902 { PCI_VENDOR_ID_INTASHIELD
, PCI_DEVICE_ID_INTASHIELD_IS400
,
2903 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, /* 135a.0dc0 */
2906 * Perle PCI-RAS cards
2908 { PCI_VENDOR_ID_PLX
, PCI_DEVICE_ID_PLX_9030
,
2909 PCI_SUBVENDOR_ID_PERLE
, PCI_SUBDEVICE_ID_PCI_RAS4
,
2910 0, 0, pbn_b2_4_921600
},
2911 { PCI_VENDOR_ID_PLX
, PCI_DEVICE_ID_PLX_9030
,
2912 PCI_SUBVENDOR_ID_PERLE
, PCI_SUBDEVICE_ID_PCI_RAS8
,
2913 0, 0, pbn_b2_8_921600
},
2916 * Mainpine series cards: Fairly standard layout but fools
2917 * parts of the autodetect in some cases and uses otherwise
2918 * unmatched communications subclasses in the PCI Express case
2921 { /* RockForceDUO */
2922 PCI_VENDOR_ID_MAINPINE
, PCI_DEVICE_ID_MAINPINE_PBRIDGE
,
2923 PCI_VENDOR_ID_MAINPINE
, 0x0200,
2924 0, 0, pbn_b0_2_115200
},
2925 { /* RockForceQUATRO */
2926 PCI_VENDOR_ID_MAINPINE
, PCI_DEVICE_ID_MAINPINE_PBRIDGE
,
2927 PCI_VENDOR_ID_MAINPINE
, 0x0300,
2928 0, 0, pbn_b0_4_115200
},
2929 { /* RockForceDUO+ */
2930 PCI_VENDOR_ID_MAINPINE
, PCI_DEVICE_ID_MAINPINE_PBRIDGE
,
2931 PCI_VENDOR_ID_MAINPINE
, 0x0400,
2932 0, 0, pbn_b0_2_115200
},
2933 { /* RockForceQUATRO+ */
2934 PCI_VENDOR_ID_MAINPINE
, PCI_DEVICE_ID_MAINPINE_PBRIDGE
,
2935 PCI_VENDOR_ID_MAINPINE
, 0x0500,
2936 0, 0, pbn_b0_4_115200
},
2938 PCI_VENDOR_ID_MAINPINE
, PCI_DEVICE_ID_MAINPINE_PBRIDGE
,
2939 PCI_VENDOR_ID_MAINPINE
, 0x0600,
2940 0, 0, pbn_b0_2_115200
},
2942 PCI_VENDOR_ID_MAINPINE
, PCI_DEVICE_ID_MAINPINE_PBRIDGE
,
2943 PCI_VENDOR_ID_MAINPINE
, 0x0700,
2944 0, 0, pbn_b0_4_115200
},
2945 { /* RockForceOCTO+ */
2946 PCI_VENDOR_ID_MAINPINE
, PCI_DEVICE_ID_MAINPINE_PBRIDGE
,
2947 PCI_VENDOR_ID_MAINPINE
, 0x0800,
2948 0, 0, pbn_b0_8_115200
},
2949 { /* RockForceDUO+ */
2950 PCI_VENDOR_ID_MAINPINE
, PCI_DEVICE_ID_MAINPINE_PBRIDGE
,
2951 PCI_VENDOR_ID_MAINPINE
, 0x0C00,
2952 0, 0, pbn_b0_2_115200
},
2953 { /* RockForceQUARTRO+ */
2954 PCI_VENDOR_ID_MAINPINE
, PCI_DEVICE_ID_MAINPINE_PBRIDGE
,
2955 PCI_VENDOR_ID_MAINPINE
, 0x0D00,
2956 0, 0, pbn_b0_4_115200
},
2957 { /* RockForceOCTO+ */
2958 PCI_VENDOR_ID_MAINPINE
, PCI_DEVICE_ID_MAINPINE_PBRIDGE
,
2959 PCI_VENDOR_ID_MAINPINE
, 0x1D00,
2960 0, 0, pbn_b0_8_115200
},
2962 PCI_VENDOR_ID_MAINPINE
, PCI_DEVICE_ID_MAINPINE_PBRIDGE
,
2963 PCI_VENDOR_ID_MAINPINE
, 0x2000,
2964 0, 0, pbn_b0_1_115200
},
2966 PCI_VENDOR_ID_MAINPINE
, PCI_DEVICE_ID_MAINPINE_PBRIDGE
,
2967 PCI_VENDOR_ID_MAINPINE
, 0x2100,
2968 0, 0, pbn_b0_1_115200
},
2970 PCI_VENDOR_ID_MAINPINE
, PCI_DEVICE_ID_MAINPINE_PBRIDGE
,
2971 PCI_VENDOR_ID_MAINPINE
, 0x2200,
2972 0, 0, pbn_b0_2_115200
},
2974 PCI_VENDOR_ID_MAINPINE
, PCI_DEVICE_ID_MAINPINE_PBRIDGE
,
2975 PCI_VENDOR_ID_MAINPINE
, 0x2300,
2976 0, 0, pbn_b0_2_115200
},
2978 PCI_VENDOR_ID_MAINPINE
, PCI_DEVICE_ID_MAINPINE_PBRIDGE
,
2979 PCI_VENDOR_ID_MAINPINE
, 0x2400,
2980 0, 0, pbn_b0_4_115200
},
2982 PCI_VENDOR_ID_MAINPINE
, PCI_DEVICE_ID_MAINPINE_PBRIDGE
,
2983 PCI_VENDOR_ID_MAINPINE
, 0x2500,
2984 0, 0, pbn_b0_4_115200
},
2986 PCI_VENDOR_ID_MAINPINE
, PCI_DEVICE_ID_MAINPINE_PBRIDGE
,
2987 PCI_VENDOR_ID_MAINPINE
, 0x2600,
2988 0, 0, pbn_b0_8_115200
},
2990 PCI_VENDOR_ID_MAINPINE
, PCI_DEVICE_ID_MAINPINE_PBRIDGE
,
2991 PCI_VENDOR_ID_MAINPINE
, 0x2700,
2992 0, 0, pbn_b0_8_115200
},
2993 { /* IQ Express D1 */
2994 PCI_VENDOR_ID_MAINPINE
, PCI_DEVICE_ID_MAINPINE_PBRIDGE
,
2995 PCI_VENDOR_ID_MAINPINE
, 0x3000,
2996 0, 0, pbn_b0_1_115200
},
2997 { /* IQ Express F1 */
2998 PCI_VENDOR_ID_MAINPINE
, PCI_DEVICE_ID_MAINPINE_PBRIDGE
,
2999 PCI_VENDOR_ID_MAINPINE
, 0x3100,
3000 0, 0, pbn_b0_1_115200
},
3001 { /* IQ Express D2 */
3002 PCI_VENDOR_ID_MAINPINE
, PCI_DEVICE_ID_MAINPINE_PBRIDGE
,
3003 PCI_VENDOR_ID_MAINPINE
, 0x3200,
3004 0, 0, pbn_b0_2_115200
},
3005 { /* IQ Express F2 */
3006 PCI_VENDOR_ID_MAINPINE
, PCI_DEVICE_ID_MAINPINE_PBRIDGE
,
3007 PCI_VENDOR_ID_MAINPINE
, 0x3300,
3008 0, 0, pbn_b0_2_115200
},
3009 { /* IQ Express D4 */
3010 PCI_VENDOR_ID_MAINPINE
, PCI_DEVICE_ID_MAINPINE_PBRIDGE
,
3011 PCI_VENDOR_ID_MAINPINE
, 0x3400,
3012 0, 0, pbn_b0_4_115200
},
3013 { /* IQ Express F4 */
3014 PCI_VENDOR_ID_MAINPINE
, PCI_DEVICE_ID_MAINPINE_PBRIDGE
,
3015 PCI_VENDOR_ID_MAINPINE
, 0x3500,
3016 0, 0, pbn_b0_4_115200
},
3017 { /* IQ Express D8 */
3018 PCI_VENDOR_ID_MAINPINE
, PCI_DEVICE_ID_MAINPINE_PBRIDGE
,
3019 PCI_VENDOR_ID_MAINPINE
, 0x3C00,
3020 0, 0, pbn_b0_8_115200
},
3021 { /* IQ Express F8 */
3022 PCI_VENDOR_ID_MAINPINE
, PCI_DEVICE_ID_MAINPINE_PBRIDGE
,
3023 PCI_VENDOR_ID_MAINPINE
, 0x3D00,
3024 0, 0, pbn_b0_8_115200
},
3028 * PA Semi PA6T-1682M on-chip UART
3030 { PCI_VENDOR_ID_PASEMI
, 0xa004,
3031 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
3035 * ADDI-DATA GmbH communication cards <info@addi-data.com>
3037 { PCI_VENDOR_ID_ADDIDATA
,
3038 PCI_DEVICE_ID_ADDIDATA_APCI7500
,
3045 { PCI_VENDOR_ID_ADDIDATA
,
3046 PCI_DEVICE_ID_ADDIDATA_APCI7420
,
3053 { PCI_VENDOR_ID_ADDIDATA
,
3054 PCI_DEVICE_ID_ADDIDATA_APCI7300
,
3061 { PCI_VENDOR_ID_ADDIDATA_OLD
,
3062 PCI_DEVICE_ID_ADDIDATA_APCI7800
,
3069 { PCI_VENDOR_ID_ADDIDATA
,
3070 PCI_DEVICE_ID_ADDIDATA_APCI7500_2
,
3077 { PCI_VENDOR_ID_ADDIDATA
,
3078 PCI_DEVICE_ID_ADDIDATA_APCI7420_2
,
3085 { PCI_VENDOR_ID_ADDIDATA
,
3086 PCI_DEVICE_ID_ADDIDATA_APCI7300_2
,
3093 { PCI_VENDOR_ID_ADDIDATA
,
3094 PCI_DEVICE_ID_ADDIDATA_APCI7500_3
,
3101 { PCI_VENDOR_ID_ADDIDATA
,
3102 PCI_DEVICE_ID_ADDIDATA_APCI7420_3
,
3109 { PCI_VENDOR_ID_ADDIDATA
,
3110 PCI_DEVICE_ID_ADDIDATA_APCI7300_3
,
3117 { PCI_VENDOR_ID_ADDIDATA
,
3118 PCI_DEVICE_ID_ADDIDATA_APCI7800_3
,
3126 * These entries match devices with class COMMUNICATION_SERIAL,
3127 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
3129 { PCI_ANY_ID
, PCI_ANY_ID
,
3130 PCI_ANY_ID
, PCI_ANY_ID
,
3131 PCI_CLASS_COMMUNICATION_SERIAL
<< 8,
3132 0xffff00, pbn_default
},
3133 { PCI_ANY_ID
, PCI_ANY_ID
,
3134 PCI_ANY_ID
, PCI_ANY_ID
,
3135 PCI_CLASS_COMMUNICATION_MODEM
<< 8,
3136 0xffff00, pbn_default
},
3137 { PCI_ANY_ID
, PCI_ANY_ID
,
3138 PCI_ANY_ID
, PCI_ANY_ID
,
3139 PCI_CLASS_COMMUNICATION_MULTISERIAL
<< 8,
3140 0xffff00, pbn_default
},
3144 static struct pci_driver serial_pci_driver
= {
3146 .probe
= pciserial_init_one
,
3147 .remove
= __devexit_p(pciserial_remove_one
),
3149 .suspend
= pciserial_suspend_one
,
3150 .resume
= pciserial_resume_one
,
3152 .id_table
= serial_pci_tbl
,
3155 static int __init
serial8250_pci_init(void)
3157 return pci_register_driver(&serial_pci_driver
);
3160 static void __exit
serial8250_pci_exit(void)
3162 pci_unregister_driver(&serial_pci_driver
);
3165 module_init(serial8250_pci_init
);
3166 module_exit(serial8250_pci_exit
);
3168 MODULE_LICENSE("GPL");
3169 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
3170 MODULE_DEVICE_TABLE(pci
, serial_pci_tbl
);