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thinkpad-acpi: R52 brightness_mode has been confirmed
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / serial / 8250.c
bloba181ccf46281bb4bc2e8a1f818c9f3c53f52a963
1 /*
2 * linux/drivers/char/8250.c
3 *
4 * Driver for 8250/16550-type serial ports
5 *
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
8 * Copyright (C) 2001 Russell King.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * A note about mapbase / membase
16 *
17 * mapbase is the physical address of the IO port.
18 * membase is an 'ioremapped' cookie.
19 */
20
21 #if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
22 #define SUPPORT_SYSRQ
23 #endif
24
25 #include <linux/module.h>
26 #include <linux/moduleparam.h>
27 #include <linux/ioport.h>
28 #include <linux/init.h>
29 #include <linux/console.h>
30 #include <linux/sysrq.h>
31 #include <linux/delay.h>
32 #include <linux/platform_device.h>
33 #include <linux/tty.h>
34 #include <linux/tty_flip.h>
35 #include <linux/serial_reg.h>
36 #include <linux/serial_core.h>
37 #include <linux/serial.h>
38 #include <linux/serial_8250.h>
39 #include <linux/nmi.h>
40 #include <linux/mutex.h>
41
42 #include <asm/io.h>
43 #include <asm/irq.h>
44
45 #include "8250.h"
46
47 #ifdef CONFIG_SPARC
48 #include "suncore.h"
49 #endif
50
51 /*
52 * Configuration:
53 * share_irqs - whether we pass IRQF_SHARED to request_irq(). This option
54 * is unsafe when used on edge-triggered interrupts.
55 */
56 static unsigned int share_irqs = SERIAL8250_SHARE_IRQS;
57
58 static unsigned int nr_uarts = CONFIG_SERIAL_8250_RUNTIME_UARTS;
59
60 static struct uart_driver serial8250_reg;
61
62 static int serial_index(struct uart_port *port)
63 {
64 return (serial8250_reg.minor - 64) + port->line;
65 }
66
67 /*
68 * Debugging.
69 */
70 #if 0
71 #define DEBUG_AUTOCONF(fmt...) printk(fmt)
72 #else
73 #define DEBUG_AUTOCONF(fmt...) do { } while (0)
74 #endif
75
76 #if 0
77 #define DEBUG_INTR(fmt...) printk(fmt)
78 #else
79 #define DEBUG_INTR(fmt...) do { } while (0)
80 #endif
81
82 #define PASS_LIMIT 256
83
84 /*
85 * We default to IRQ0 for the "no irq" hack. Some
86 * machine types want others as well - they're free
87 * to redefine this in their header file.
88 */
89 #define is_real_interrupt(irq) ((irq) != 0)
90
91 #ifdef CONFIG_SERIAL_8250_DETECT_IRQ
92 #define CONFIG_SERIAL_DETECT_IRQ 1
93 #endif
94 #ifdef CONFIG_SERIAL_8250_MANY_PORTS
95 #define CONFIG_SERIAL_MANY_PORTS 1
96 #endif
97
98 /*
99 * HUB6 is always on. This will be removed once the header
100 * files have been cleaned.
101 */
102 #define CONFIG_HUB6 1
103
104 #include <asm/serial.h>
105 /*
106 * SERIAL_PORT_DFNS tells us about built-in ports that have no
107 * standard enumeration mechanism. Platforms that can find all
108 * serial ports via mechanisms like ACPI or PCI need not supply it.
109 */
110 #ifndef SERIAL_PORT_DFNS
111 #define SERIAL_PORT_DFNS
112 #endif
113
114 static const struct old_serial_port old_serial_port[] = {
115 SERIAL_PORT_DFNS /* defined in asm/serial.h */
116 };
117
118 #define UART_NR CONFIG_SERIAL_8250_NR_UARTS
119
120 #ifdef CONFIG_SERIAL_8250_RSA
121
122 #define PORT_RSA_MAX 4
123 static unsigned long probe_rsa[PORT_RSA_MAX];
124 static unsigned int probe_rsa_count;
125 #endif /* CONFIG_SERIAL_8250_RSA */
126
127 struct uart_8250_port {
128 struct uart_port port;
129 struct timer_list timer; /* "no irq" timer */
130 struct list_head list; /* ports on this IRQ */
131 unsigned short capabilities; /* port capabilities */
132 unsigned short bugs; /* port bugs */
133 unsigned int tx_loadsz; /* transmit fifo load size */
134 unsigned char acr;
135 unsigned char ier;
136 unsigned char lcr;
137 unsigned char mcr;
138 unsigned char mcr_mask; /* mask of user bits */
139 unsigned char mcr_force; /* mask of forced bits */
140
141 /*
142 * Some bits in registers are cleared on a read, so they must
143 * be saved whenever the register is read but the bits will not
144 * be immediately processed.
145 */
146 #define LSR_SAVE_FLAGS UART_LSR_BRK_ERROR_BITS
147 unsigned char lsr_saved_flags;
148 #define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA
149 unsigned char msr_saved_flags;
150
151 /*
152 * We provide a per-port pm hook.
153 */
154 void (*pm)(struct uart_port *port,
155 unsigned int state, unsigned int old);
156 };
157
158 struct irq_info {
159 struct hlist_node node;
160 int irq;
161 spinlock_t lock; /* Protects list not the hash */
162 struct list_head *head;
163 };
164
165 #define NR_IRQ_HASH 32 /* Can be adjusted later */
166 static struct hlist_head irq_lists[NR_IRQ_HASH];
167 static DEFINE_MUTEX(hash_mutex); /* Used to walk the hash */
168
169 /*
170 * Here we define the default xmit fifo size used for each type of UART.
171 */
172 static const struct serial8250_config uart_config[] = {
173 [PORT_UNKNOWN] = {
174 .name = "unknown",
175 .fifo_size = 1,
176 .tx_loadsz = 1,
177 },
178 [PORT_8250] = {
179 .name = "8250",
180 .fifo_size = 1,
181 .tx_loadsz = 1,
182 },
183 [PORT_16450] = {
184 .name = "16450",
185 .fifo_size = 1,
186 .tx_loadsz = 1,
187 },
188 [PORT_16550] = {
189 .name = "16550",
190 .fifo_size = 1,
191 .tx_loadsz = 1,
192 },
193 [PORT_16550A] = {
194 .name = "16550A",
195 .fifo_size = 16,
196 .tx_loadsz = 16,
197 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
198 .flags = UART_CAP_FIFO,
199 },
200 [PORT_CIRRUS] = {
201 .name = "Cirrus",
202 .fifo_size = 1,
203 .tx_loadsz = 1,
204 },
205 [PORT_16650] = {
206 .name = "ST16650",
207 .fifo_size = 1,
208 .tx_loadsz = 1,
209 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
210 },
211 [PORT_16650V2] = {
212 .name = "ST16650V2",
213 .fifo_size = 32,
214 .tx_loadsz = 16,
215 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
216 UART_FCR_T_TRIG_00,
217 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
218 },
219 [PORT_16750] = {
220 .name = "TI16750",
221 .fifo_size = 64,
222 .tx_loadsz = 64,
223 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
224 UART_FCR7_64BYTE,
225 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
226 },
227 [PORT_STARTECH] = {
228 .name = "Startech",
229 .fifo_size = 1,
230 .tx_loadsz = 1,
231 },
232 [PORT_16C950] = {
233 .name = "16C950/954",
234 .fifo_size = 128,
235 .tx_loadsz = 128,
236 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
237 .flags = UART_CAP_FIFO,
238 },
239 [PORT_16654] = {
240 .name = "ST16654",
241 .fifo_size = 64,
242 .tx_loadsz = 32,
243 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
244 UART_FCR_T_TRIG_10,
245 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
246 },
247 [PORT_16850] = {
248 .name = "XR16850",
249 .fifo_size = 128,
250 .tx_loadsz = 128,
251 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
252 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
253 },
254 [PORT_RSA] = {
255 .name = "RSA",
256 .fifo_size = 2048,
257 .tx_loadsz = 2048,
258 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
259 .flags = UART_CAP_FIFO,
260 },
261 [PORT_NS16550A] = {
262 .name = "NS16550A",
263 .fifo_size = 16,
264 .tx_loadsz = 16,
265 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
266 .flags = UART_CAP_FIFO | UART_NATSEMI,
267 },
268 [PORT_XSCALE] = {
269 .name = "XScale",
270 .fifo_size = 32,
271 .tx_loadsz = 32,
272 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
273 .flags = UART_CAP_FIFO | UART_CAP_UUE,
274 },
275 [PORT_RM9000] = {
276 .name = "RM9000",
277 .fifo_size = 16,
278 .tx_loadsz = 16,
279 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
280 .flags = UART_CAP_FIFO,
281 },
282 };
283
284 #if defined (CONFIG_SERIAL_8250_AU1X00)
285
286 /* Au1x00 UART hardware has a weird register layout */
287 static const u8 au_io_in_map[] = {
288 [UART_RX] = 0,
289 [UART_IER] = 2,
290 [UART_IIR] = 3,
291 [UART_LCR] = 5,
292 [UART_MCR] = 6,
293 [UART_LSR] = 7,
294 [UART_MSR] = 8,
295 };
296
297 static const u8 au_io_out_map[] = {
298 [UART_TX] = 1,
299 [UART_IER] = 2,
300 [UART_FCR] = 4,
301 [UART_LCR] = 5,
302 [UART_MCR] = 6,
303 };
304
305 /* sane hardware needs no mapping */
306 static inline int map_8250_in_reg(struct uart_8250_port *up, int offset)
307 {
308 if (up->port.iotype != UPIO_AU)
309 return offset;
310 return au_io_in_map[offset];
311 }
312
313 static inline int map_8250_out_reg(struct uart_8250_port *up, int offset)
314 {
315 if (up->port.iotype != UPIO_AU)
316 return offset;
317 return au_io_out_map[offset];
318 }
319
320 #elif defined(CONFIG_SERIAL_8250_RM9K)
321
322 static const u8
323 regmap_in[8] = {
324 [UART_RX] = 0x00,
325 [UART_IER] = 0x0c,
326 [UART_IIR] = 0x14,
327 [UART_LCR] = 0x1c,
328 [UART_MCR] = 0x20,
329 [UART_LSR] = 0x24,
330 [UART_MSR] = 0x28,
331 [UART_SCR] = 0x2c
332 },
333 regmap_out[8] = {
334 [UART_TX] = 0x04,
335 [UART_IER] = 0x0c,
336 [UART_FCR] = 0x18,
337 [UART_LCR] = 0x1c,
338 [UART_MCR] = 0x20,
339 [UART_LSR] = 0x24,
340 [UART_MSR] = 0x28,
341 [UART_SCR] = 0x2c
342 };
343
344 static inline int map_8250_in_reg(struct uart_8250_port *up, int offset)
345 {
346 if (up->port.iotype != UPIO_RM9000)
347 return offset;
348 return regmap_in[offset];
349 }
350
351 static inline int map_8250_out_reg(struct uart_8250_port *up, int offset)
352 {
353 if (up->port.iotype != UPIO_RM9000)
354 return offset;
355 return regmap_out[offset];
356 }
357
358 #else
359
360 /* sane hardware needs no mapping */
361 #define map_8250_in_reg(up, offset) (offset)
362 #define map_8250_out_reg(up, offset) (offset)
363
364 #endif
365
366 static unsigned int serial_in(struct uart_8250_port *up, int offset)
367 {
368 unsigned int tmp;
369 offset = map_8250_in_reg(up, offset) << up->port.regshift;
370
371 switch (up->port.iotype) {
372 case UPIO_HUB6:
373 outb(up->port.hub6 - 1 + offset, up->port.iobase);
374 return inb(up->port.iobase + 1);
375
376 case UPIO_MEM:
377 case UPIO_DWAPB:
378 return readb(up->port.membase + offset);
379
380 case UPIO_RM9000:
381 case UPIO_MEM32:
382 return readl(up->port.membase + offset);
383
384 #ifdef CONFIG_SERIAL_8250_AU1X00
385 case UPIO_AU:
386 return __raw_readl(up->port.membase + offset);
387 #endif
388
389 case UPIO_TSI:
390 if (offset == UART_IIR) {
391 tmp = readl(up->port.membase + (UART_IIR & ~3));
392 return (tmp >> 16) & 0xff; /* UART_IIR % 4 == 2 */
393 } else
394 return readb(up->port.membase + offset);
395
396 default:
397 return inb(up->port.iobase + offset);
398 }
399 }
400
401 static void
402 serial_out(struct uart_8250_port *up, int offset, int value)
403 {
404 /* Save the offset before it's remapped */
405 int save_offset = offset;
406 offset = map_8250_out_reg(up, offset) << up->port.regshift;
407
408 switch (up->port.iotype) {
409 case UPIO_HUB6:
410 outb(up->port.hub6 - 1 + offset, up->port.iobase);
411 outb(value, up->port.iobase + 1);
412 break;
413
414 case UPIO_MEM:
415 writeb(value, up->port.membase + offset);
416 break;
417
418 case UPIO_RM9000:
419 case UPIO_MEM32:
420 writel(value, up->port.membase + offset);
421 break;
422
423 #ifdef CONFIG_SERIAL_8250_AU1X00
424 case UPIO_AU:
425 __raw_writel(value, up->port.membase + offset);
426 break;
427 #endif
428 case UPIO_TSI:
429 if (!((offset == UART_IER) && (value & UART_IER_UUE)))
430 writeb(value, up->port.membase + offset);
431 break;
432
433 case UPIO_DWAPB:
434 /* Save the LCR value so it can be re-written when a
435 * Busy Detect interrupt occurs. */
436 if (save_offset == UART_LCR)
437 up->lcr = value;
438 writeb(value, up->port.membase + offset);
439 /* Read the IER to ensure any interrupt is cleared before
440 * returning from ISR. */
441 if (save_offset == UART_TX || save_offset == UART_IER)
442 value = serial_in(up, UART_IER);
443 break;
444
445 default:
446 outb(value, up->port.iobase + offset);
447 }
448 }
449
450 static void
451 serial_out_sync(struct uart_8250_port *up, int offset, int value)
452 {
453 switch (up->port.iotype) {
454 case UPIO_MEM:
455 case UPIO_MEM32:
456 #ifdef CONFIG_SERIAL_8250_AU1X00
457 case UPIO_AU:
458 #endif
459 case UPIO_DWAPB:
460 serial_out(up, offset, value);
461 serial_in(up, UART_LCR); /* safe, no side-effects */
462 break;
463 default:
464 serial_out(up, offset, value);
465 }
466 }
467
468 /*
469 * We used to support using pause I/O for certain machines. We
470 * haven't supported this for a while, but just in case it's badly
471 * needed for certain old 386 machines, I've left these #define's
472 * in....
473 */
474 #define serial_inp(up, offset) serial_in(up, offset)
475 #define serial_outp(up, offset, value) serial_out(up, offset, value)
476
477 /* Uart divisor latch read */
478 static inline int _serial_dl_read(struct uart_8250_port *up)
479 {
480 return serial_inp(up, UART_DLL) | serial_inp(up, UART_DLM) << 8;
481 }
482
483 /* Uart divisor latch write */
484 static inline void _serial_dl_write(struct uart_8250_port *up, int value)
485 {
486 serial_outp(up, UART_DLL, value & 0xff);
487 serial_outp(up, UART_DLM, value >> 8 & 0xff);
488 }
489
490 #if defined(CONFIG_SERIAL_8250_AU1X00)
491 /* Au1x00 haven't got a standard divisor latch */
492 static int serial_dl_read(struct uart_8250_port *up)
493 {
494 if (up->port.iotype == UPIO_AU)
495 return __raw_readl(up->port.membase + 0x28);
496 else
497 return _serial_dl_read(up);
498 }
499
500 static void serial_dl_write(struct uart_8250_port *up, int value)
501 {
502 if (up->port.iotype == UPIO_AU)
503 __raw_writel(value, up->port.membase + 0x28);
504 else
505 _serial_dl_write(up, value);
506 }
507 #elif defined(CONFIG_SERIAL_8250_RM9K)
508 static int serial_dl_read(struct uart_8250_port *up)
509 {
510 return (up->port.iotype == UPIO_RM9000) ?
511 (((__raw_readl(up->port.membase + 0x10) << 8) |
512 (__raw_readl(up->port.membase + 0x08) & 0xff)) & 0xffff) :
513 _serial_dl_read(up);
514 }
515
516 static void serial_dl_write(struct uart_8250_port *up, int value)
517 {
518 if (up->port.iotype == UPIO_RM9000) {
519 __raw_writel(value, up->port.membase + 0x08);
520 __raw_writel(value >> 8, up->port.membase + 0x10);
521 } else {
522 _serial_dl_write(up, value);
523 }
524 }
525 #else
526 #define serial_dl_read(up) _serial_dl_read(up)
527 #define serial_dl_write(up, value) _serial_dl_write(up, value)
528 #endif
529
530 /*
531 * For the 16C950
532 */
533 static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
534 {
535 serial_out(up, UART_SCR, offset);
536 serial_out(up, UART_ICR, value);
537 }
538
539 static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
540 {
541 unsigned int value;
542
543 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
544 serial_out(up, UART_SCR, offset);
545 value = serial_in(up, UART_ICR);
546 serial_icr_write(up, UART_ACR, up->acr);
547
548 return value;
549 }
550
551 /*
552 * FIFO support.
553 */
554 static void serial8250_clear_fifos(struct uart_8250_port *p)
555 {
556 if (p->capabilities & UART_CAP_FIFO) {
557 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO);
558 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO |
559 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
560 serial_outp(p, UART_FCR, 0);
561 }
562 }
563
564 /*
565 * IER sleep support. UARTs which have EFRs need the "extended
566 * capability" bit enabled. Note that on XR16C850s, we need to
567 * reset LCR to write to IER.
568 */
569 static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
570 {
571 if (p->capabilities & UART_CAP_SLEEP) {
572 if (p->capabilities & UART_CAP_EFR) {
573 serial_outp(p, UART_LCR, 0xBF);
574 serial_outp(p, UART_EFR, UART_EFR_ECB);
575 serial_outp(p, UART_LCR, 0);
576 }
577 serial_outp(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
578 if (p->capabilities & UART_CAP_EFR) {
579 serial_outp(p, UART_LCR, 0xBF);
580 serial_outp(p, UART_EFR, 0);
581 serial_outp(p, UART_LCR, 0);
582 }
583 }
584 }
585
586 #ifdef CONFIG_SERIAL_8250_RSA
587 /*
588 * Attempts to turn on the RSA FIFO. Returns zero on failure.
589 * We set the port uart clock rate if we succeed.
590 */
591 static int __enable_rsa(struct uart_8250_port *up)
592 {
593 unsigned char mode;
594 int result;
595
596 mode = serial_inp(up, UART_RSA_MSR);
597 result = mode & UART_RSA_MSR_FIFO;
598
599 if (!result) {
600 serial_outp(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
601 mode = serial_inp(up, UART_RSA_MSR);
602 result = mode & UART_RSA_MSR_FIFO;
603 }
604
605 if (result)
606 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
607
608 return result;
609 }
610
611 static void enable_rsa(struct uart_8250_port *up)
612 {
613 if (up->port.type == PORT_RSA) {
614 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
615 spin_lock_irq(&up->port.lock);
616 __enable_rsa(up);
617 spin_unlock_irq(&up->port.lock);
618 }
619 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
620 serial_outp(up, UART_RSA_FRR, 0);
621 }
622 }
623
624 /*
625 * Attempts to turn off the RSA FIFO. Returns zero on failure.
626 * It is unknown why interrupts were disabled in here. However,
627 * the caller is expected to preserve this behaviour by grabbing
628 * the spinlock before calling this function.
629 */
630 static void disable_rsa(struct uart_8250_port *up)
631 {
632 unsigned char mode;
633 int result;
634
635 if (up->port.type == PORT_RSA &&
636 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
637 spin_lock_irq(&up->port.lock);
638
639 mode = serial_inp(up, UART_RSA_MSR);
640 result = !(mode & UART_RSA_MSR_FIFO);
641
642 if (!result) {
643 serial_outp(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
644 mode = serial_inp(up, UART_RSA_MSR);
645 result = !(mode & UART_RSA_MSR_FIFO);
646 }
647
648 if (result)
649 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
650 spin_unlock_irq(&up->port.lock);
651 }
652 }
653 #endif /* CONFIG_SERIAL_8250_RSA */
654
655 /*
656 * This is a quickie test to see how big the FIFO is.
657 * It doesn't work at all the time, more's the pity.
658 */
659 static int size_fifo(struct uart_8250_port *up)
660 {
661 unsigned char old_fcr, old_mcr, old_lcr;
662 unsigned short old_dl;
663 int count;
664
665 old_lcr = serial_inp(up, UART_LCR);
666 serial_outp(up, UART_LCR, 0);
667 old_fcr = serial_inp(up, UART_FCR);
668 old_mcr = serial_inp(up, UART_MCR);
669 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO |
670 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
671 serial_outp(up, UART_MCR, UART_MCR_LOOP);
672 serial_outp(up, UART_LCR, UART_LCR_DLAB);
673 old_dl = serial_dl_read(up);
674 serial_dl_write(up, 0x0001);
675 serial_outp(up, UART_LCR, 0x03);
676 for (count = 0; count < 256; count++)
677 serial_outp(up, UART_TX, count);
678 mdelay(20);/* FIXME - schedule_timeout */
679 for (count = 0; (serial_inp(up, UART_LSR) & UART_LSR_DR) &&
680 (count < 256); count++)
681 serial_inp(up, UART_RX);
682 serial_outp(up, UART_FCR, old_fcr);
683 serial_outp(up, UART_MCR, old_mcr);
684 serial_outp(up, UART_LCR, UART_LCR_DLAB);
685 serial_dl_write(up, old_dl);
686 serial_outp(up, UART_LCR, old_lcr);
687
688 return count;
689 }
690
691 /*
692 * Read UART ID using the divisor method - set DLL and DLM to zero
693 * and the revision will be in DLL and device type in DLM. We
694 * preserve the device state across this.
695 */
696 static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
697 {
698 unsigned char old_dll, old_dlm, old_lcr;
699 unsigned int id;
700
701 old_lcr = serial_inp(p, UART_LCR);
702 serial_outp(p, UART_LCR, UART_LCR_DLAB);
703
704 old_dll = serial_inp(p, UART_DLL);
705 old_dlm = serial_inp(p, UART_DLM);
706
707 serial_outp(p, UART_DLL, 0);
708 serial_outp(p, UART_DLM, 0);
709
710 id = serial_inp(p, UART_DLL) | serial_inp(p, UART_DLM) << 8;
711
712 serial_outp(p, UART_DLL, old_dll);
713 serial_outp(p, UART_DLM, old_dlm);
714 serial_outp(p, UART_LCR, old_lcr);
715
716 return id;
717 }
718
719 /*
720 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
721 * When this function is called we know it is at least a StarTech
722 * 16650 V2, but it might be one of several StarTech UARTs, or one of
723 * its clones. (We treat the broken original StarTech 16650 V1 as a
724 * 16550, and why not? Startech doesn't seem to even acknowledge its
725 * existence.)
726 *
727 * What evil have men's minds wrought...
728 */
729 static void autoconfig_has_efr(struct uart_8250_port *up)
730 {
731 unsigned int id1, id2, id3, rev;
732
733 /*
734 * Everything with an EFR has SLEEP
735 */
736 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
737
738 /*
739 * First we check to see if it's an Oxford Semiconductor UART.
740 *
741 * If we have to do this here because some non-National
742 * Semiconductor clone chips lock up if you try writing to the
743 * LSR register (which serial_icr_read does)
744 */
745
746 /*
747 * Check for Oxford Semiconductor 16C950.
748 *
749 * EFR [4] must be set else this test fails.
750 *
751 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
752 * claims that it's needed for 952 dual UART's (which are not
753 * recommended for new designs).
754 */
755 up->acr = 0;
756 serial_out(up, UART_LCR, 0xBF);
757 serial_out(up, UART_EFR, UART_EFR_ECB);
758 serial_out(up, UART_LCR, 0x00);
759 id1 = serial_icr_read(up, UART_ID1);
760 id2 = serial_icr_read(up, UART_ID2);
761 id3 = serial_icr_read(up, UART_ID3);
762 rev = serial_icr_read(up, UART_REV);
763
764 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
765
766 if (id1 == 0x16 && id2 == 0xC9 &&
767 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
768 up->port.type = PORT_16C950;
769
770 /*
771 * Enable work around for the Oxford Semiconductor 952 rev B
772 * chip which causes it to seriously miscalculate baud rates
773 * when DLL is 0.
774 */
775 if (id3 == 0x52 && rev == 0x01)
776 up->bugs |= UART_BUG_QUOT;
777 return;
778 }
779
780 /*
781 * We check for a XR16C850 by setting DLL and DLM to 0, and then
782 * reading back DLL and DLM. The chip type depends on the DLM
783 * value read back:
784 * 0x10 - XR16C850 and the DLL contains the chip revision.
785 * 0x12 - XR16C2850.
786 * 0x14 - XR16C854.
787 */
788 id1 = autoconfig_read_divisor_id(up);
789 DEBUG_AUTOCONF("850id=%04x ", id1);
790
791 id2 = id1 >> 8;
792 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
793 up->port.type = PORT_16850;
794 return;
795 }
796
797 /*
798 * It wasn't an XR16C850.
799 *
800 * We distinguish between the '654 and the '650 by counting
801 * how many bytes are in the FIFO. I'm using this for now,
802 * since that's the technique that was sent to me in the
803 * serial driver update, but I'm not convinced this works.
804 * I've had problems doing this in the past. -TYT
805 */
806 if (size_fifo(up) == 64)
807 up->port.type = PORT_16654;
808 else
809 up->port.type = PORT_16650V2;
810 }
811
812 /*
813 * We detected a chip without a FIFO. Only two fall into
814 * this category - the original 8250 and the 16450. The
815 * 16450 has a scratch register (accessible with LCR=0)
816 */
817 static void autoconfig_8250(struct uart_8250_port *up)
818 {
819 unsigned char scratch, status1, status2;
820
821 up->port.type = PORT_8250;
822
823 scratch = serial_in(up, UART_SCR);
824 serial_outp(up, UART_SCR, 0xa5);
825 status1 = serial_in(up, UART_SCR);
826 serial_outp(up, UART_SCR, 0x5a);
827 status2 = serial_in(up, UART_SCR);
828 serial_outp(up, UART_SCR, scratch);
829
830 if (status1 == 0xa5 && status2 == 0x5a)
831 up->port.type = PORT_16450;
832 }
833
834 static int broken_efr(struct uart_8250_port *up)
835 {
836 /*
837 * Exar ST16C2550 "A2" devices incorrectly detect as
838 * having an EFR, and report an ID of 0x0201. See
839 * http://www.exar.com/info.php?pdf=dan180_oct2004.pdf
840 */
841 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
842 return 1;
843
844 return 0;
845 }
846
847 /*
848 * We know that the chip has FIFOs. Does it have an EFR? The
849 * EFR is located in the same register position as the IIR and
850 * we know the top two bits of the IIR are currently set. The
851 * EFR should contain zero. Try to read the EFR.
852 */
853 static void autoconfig_16550a(struct uart_8250_port *up)
854 {
855 unsigned char status1, status2;
856 unsigned int iersave;
857
858 up->port.type = PORT_16550A;
859 up->capabilities |= UART_CAP_FIFO;
860
861 /*
862 * Check for presence of the EFR when DLAB is set.
863 * Only ST16C650V1 UARTs pass this test.
864 */
865 serial_outp(up, UART_LCR, UART_LCR_DLAB);
866 if (serial_in(up, UART_EFR) == 0) {
867 serial_outp(up, UART_EFR, 0xA8);
868 if (serial_in(up, UART_EFR) != 0) {
869 DEBUG_AUTOCONF("EFRv1 ");
870 up->port.type = PORT_16650;
871 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
872 } else {
873 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
874 }
875 serial_outp(up, UART_EFR, 0);
876 return;
877 }
878
879 /*
880 * Maybe it requires 0xbf to be written to the LCR.
881 * (other ST16C650V2 UARTs, TI16C752A, etc)
882 */
883 serial_outp(up, UART_LCR, 0xBF);
884 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
885 DEBUG_AUTOCONF("EFRv2 ");
886 autoconfig_has_efr(up);
887 return;
888 }
889
890 /*
891 * Check for a National Semiconductor SuperIO chip.
892 * Attempt to switch to bank 2, read the value of the LOOP bit
893 * from EXCR1. Switch back to bank 0, change it in MCR. Then
894 * switch back to bank 2, read it from EXCR1 again and check
895 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
896 */
897 serial_outp(up, UART_LCR, 0);
898 status1 = serial_in(up, UART_MCR);
899 serial_outp(up, UART_LCR, 0xE0);
900 status2 = serial_in(up, 0x02); /* EXCR1 */
901
902 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
903 serial_outp(up, UART_LCR, 0);
904 serial_outp(up, UART_MCR, status1 ^ UART_MCR_LOOP);
905 serial_outp(up, UART_LCR, 0xE0);
906 status2 = serial_in(up, 0x02); /* EXCR1 */
907 serial_outp(up, UART_LCR, 0);
908 serial_outp(up, UART_MCR, status1);
909
910 if ((status2 ^ status1) & UART_MCR_LOOP) {
911 unsigned short quot;
912
913 serial_outp(up, UART_LCR, 0xE0);
914
915 quot = serial_dl_read(up);
916 quot <<= 3;
917
918 status1 = serial_in(up, 0x04); /* EXCR2 */
919 status1 &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
920 status1 |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
921 serial_outp(up, 0x04, status1);
922
923 serial_dl_write(up, quot);
924
925 serial_outp(up, UART_LCR, 0);
926
927 up->port.uartclk = 921600*16;
928 up->port.type = PORT_NS16550A;
929 up->capabilities |= UART_NATSEMI;
930 return;
931 }
932 }
933
934 /*
935 * No EFR. Try to detect a TI16750, which only sets bit 5 of
936 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
937 * Try setting it with and without DLAB set. Cheap clones
938 * set bit 5 without DLAB set.
939 */
940 serial_outp(up, UART_LCR, 0);
941 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
942 status1 = serial_in(up, UART_IIR) >> 5;
943 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
944 serial_outp(up, UART_LCR, UART_LCR_DLAB);
945 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
946 status2 = serial_in(up, UART_IIR) >> 5;
947 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
948 serial_outp(up, UART_LCR, 0);
949
950 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
951
952 if (status1 == 6 && status2 == 7) {
953 up->port.type = PORT_16750;
954 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
955 return;
956 }
957
958 /*
959 * Try writing and reading the UART_IER_UUE bit (b6).
960 * If it works, this is probably one of the Xscale platform's
961 * internal UARTs.
962 * We're going to explicitly set the UUE bit to 0 before
963 * trying to write and read a 1 just to make sure it's not
964 * already a 1 and maybe locked there before we even start start.
965 */
966 iersave = serial_in(up, UART_IER);
967 serial_outp(up, UART_IER, iersave & ~UART_IER_UUE);
968 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
969 /*
970 * OK it's in a known zero state, try writing and reading
971 * without disturbing the current state of the other bits.
972 */
973 serial_outp(up, UART_IER, iersave | UART_IER_UUE);
974 if (serial_in(up, UART_IER) & UART_IER_UUE) {
975 /*
976 * It's an Xscale.
977 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
978 */
979 DEBUG_AUTOCONF("Xscale ");
980 up->port.type = PORT_XSCALE;
981 up->capabilities |= UART_CAP_UUE;
982 return;
983 }
984 } else {
985 /*
986 * If we got here we couldn't force the IER_UUE bit to 0.
987 * Log it and continue.
988 */
989 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
990 }
991 serial_outp(up, UART_IER, iersave);
992 }
993
994 /*
995 * This routine is called by rs_init() to initialize a specific serial
996 * port. It determines what type of UART chip this serial port is
997 * using: 8250, 16450, 16550, 16550A. The important question is
998 * whether or not this UART is a 16550A or not, since this will
999 * determine whether or not we can use its FIFO features or not.
1000 */
1001 static void autoconfig(struct uart_8250_port *up, unsigned int probeflags)
1002 {
1003 unsigned char status1, scratch, scratch2, scratch3;
1004 unsigned char save_lcr, save_mcr;
1005 unsigned long flags;
1006
1007 if (!up->port.iobase && !up->port.mapbase && !up->port.membase)
1008 return;
1009
1010 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04x, 0x%p): ",
1011 serial_index(&up->port), up->port.iobase, up->port.membase);
1012
1013 /*
1014 * We really do need global IRQs disabled here - we're going to
1015 * be frobbing the chips IRQ enable register to see if it exists.
1016 */
1017 spin_lock_irqsave(&up->port.lock, flags);
1018
1019 up->capabilities = 0;
1020 up->bugs = 0;
1021
1022 if (!(up->port.flags & UPF_BUGGY_UART)) {
1023 /*
1024 * Do a simple existence test first; if we fail this,
1025 * there's no point trying anything else.
1026 *
1027 * 0x80 is used as a nonsense port to prevent against
1028 * false positives due to ISA bus float. The
1029 * assumption is that 0x80 is a non-existent port;
1030 * which should be safe since include/asm/io.h also
1031 * makes this assumption.
1032 *
1033 * Note: this is safe as long as MCR bit 4 is clear
1034 * and the device is in "PC" mode.
1035 */
1036 scratch = serial_inp(up, UART_IER);
1037 serial_outp(up, UART_IER, 0);
1038 #ifdef __i386__
1039 outb(0xff, 0x080);
1040 #endif
1041 /*
1042 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1043 * 16C754B) allow only to modify them if an EFR bit is set.
1044 */
1045 scratch2 = serial_inp(up, UART_IER) & 0x0f;
1046 serial_outp(up, UART_IER, 0x0F);
1047 #ifdef __i386__
1048 outb(0, 0x080);
1049 #endif
1050 scratch3 = serial_inp(up, UART_IER) & 0x0f;
1051 serial_outp(up, UART_IER, scratch);
1052 if (scratch2 != 0 || scratch3 != 0x0F) {
1053 /*
1054 * We failed; there's nothing here
1055 */
1056 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1057 scratch2, scratch3);
1058 goto out;
1059 }
1060 }
1061
1062 save_mcr = serial_in(up, UART_MCR);
1063 save_lcr = serial_in(up, UART_LCR);
1064
1065 /*
1066 * Check to see if a UART is really there. Certain broken
1067 * internal modems based on the Rockwell chipset fail this
1068 * test, because they apparently don't implement the loopback
1069 * test mode. So this test is skipped on the COM 1 through
1070 * COM 4 ports. This *should* be safe, since no board
1071 * manufacturer would be stupid enough to design a board
1072 * that conflicts with COM 1-4 --- we hope!
1073 */
1074 if (!(up->port.flags & UPF_SKIP_TEST)) {
1075 serial_outp(up, UART_MCR, UART_MCR_LOOP | 0x0A);
1076 status1 = serial_inp(up, UART_MSR) & 0xF0;
1077 serial_outp(up, UART_MCR, save_mcr);
1078 if (status1 != 0x90) {
1079 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1080 status1);
1081 goto out;
1082 }
1083 }
1084
1085 /*
1086 * We're pretty sure there's a port here. Lets find out what
1087 * type of port it is. The IIR top two bits allows us to find
1088 * out if it's 8250 or 16450, 16550, 16550A or later. This
1089 * determines what we test for next.
1090 *
1091 * We also initialise the EFR (if any) to zero for later. The
1092 * EFR occupies the same register location as the FCR and IIR.
1093 */
1094 serial_outp(up, UART_LCR, 0xBF);
1095 serial_outp(up, UART_EFR, 0);
1096 serial_outp(up, UART_LCR, 0);
1097
1098 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1099 scratch = serial_in(up, UART_IIR) >> 6;
1100
1101 DEBUG_AUTOCONF("iir=%d ", scratch);
1102
1103 switch (scratch) {
1104 case 0:
1105 autoconfig_8250(up);
1106 break;
1107 case 1:
1108 up->port.type = PORT_UNKNOWN;
1109 break;
1110 case 2:
1111 up->port.type = PORT_16550;
1112 break;
1113 case 3:
1114 autoconfig_16550a(up);
1115 break;
1116 }
1117
1118 #ifdef CONFIG_SERIAL_8250_RSA
1119 /*
1120 * Only probe for RSA ports if we got the region.
1121 */
1122 if (up->port.type == PORT_16550A && probeflags & PROBE_RSA) {
1123 int i;
1124
1125 for (i = 0 ; i < probe_rsa_count; ++i) {
1126 if (probe_rsa[i] == up->port.iobase &&
1127 __enable_rsa(up)) {
1128 up->port.type = PORT_RSA;
1129 break;
1130 }
1131 }
1132 }
1133 #endif
1134
1135 #ifdef CONFIG_SERIAL_8250_AU1X00
1136 /* if access method is AU, it is a 16550 with a quirk */
1137 if (up->port.type == PORT_16550A && up->port.iotype == UPIO_AU)
1138 up->bugs |= UART_BUG_NOMSR;
1139 #endif
1140
1141 serial_outp(up, UART_LCR, save_lcr);
1142
1143 if (up->capabilities != uart_config[up->port.type].flags) {
1144 printk(KERN_WARNING
1145 "ttyS%d: detected caps %08x should be %08x\n",
1146 serial_index(&up->port), up->capabilities,
1147 uart_config[up->port.type].flags);
1148 }
1149
1150 up->port.fifosize = uart_config[up->port.type].fifo_size;
1151 up->capabilities = uart_config[up->port.type].flags;
1152 up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
1153
1154 if (up->port.type == PORT_UNKNOWN)
1155 goto out;
1156
1157 /*
1158 * Reset the UART.
1159 */
1160 #ifdef CONFIG_SERIAL_8250_RSA
1161 if (up->port.type == PORT_RSA)
1162 serial_outp(up, UART_RSA_FRR, 0);
1163 #endif
1164 serial_outp(up, UART_MCR, save_mcr);
1165 serial8250_clear_fifos(up);
1166 serial_in(up, UART_RX);
1167 if (up->capabilities & UART_CAP_UUE)
1168 serial_outp(up, UART_IER, UART_IER_UUE);
1169 else
1170 serial_outp(up, UART_IER, 0);
1171
1172 out:
1173 spin_unlock_irqrestore(&up->port.lock, flags);
1174 DEBUG_AUTOCONF("type=%s\n", uart_config[up->port.type].name);
1175 }
1176
1177 static void autoconfig_irq(struct uart_8250_port *up)
1178 {
1179 unsigned char save_mcr, save_ier;
1180 unsigned char save_ICP = 0;
1181 unsigned int ICP = 0;
1182 unsigned long irqs;
1183 int irq;
1184
1185 if (up->port.flags & UPF_FOURPORT) {
1186 ICP = (up->port.iobase & 0xfe0) | 0x1f;
1187 save_ICP = inb_p(ICP);
1188 outb_p(0x80, ICP);
1189 (void) inb_p(ICP);
1190 }
1191
1192 /* forget possible initially masked and pending IRQ */
1193 probe_irq_off(probe_irq_on());
1194 save_mcr = serial_inp(up, UART_MCR);
1195 save_ier = serial_inp(up, UART_IER);
1196 serial_outp(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2);
1197
1198 irqs = probe_irq_on();
1199 serial_outp(up, UART_MCR, 0);
1200 udelay(10);
1201 if (up->port.flags & UPF_FOURPORT) {
1202 serial_outp(up, UART_MCR,
1203 UART_MCR_DTR | UART_MCR_RTS);
1204 } else {
1205 serial_outp(up, UART_MCR,
1206 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1207 }
1208 serial_outp(up, UART_IER, 0x0f); /* enable all intrs */
1209 (void)serial_inp(up, UART_LSR);
1210 (void)serial_inp(up, UART_RX);
1211 (void)serial_inp(up, UART_IIR);
1212 (void)serial_inp(up, UART_MSR);
1213 serial_outp(up, UART_TX, 0xFF);
1214 udelay(20);
1215 irq = probe_irq_off(irqs);
1216
1217 serial_outp(up, UART_MCR, save_mcr);
1218 serial_outp(up, UART_IER, save_ier);
1219
1220 if (up->port.flags & UPF_FOURPORT)
1221 outb_p(save_ICP, ICP);
1222
1223 up->port.irq = (irq > 0) ? irq : 0;
1224 }
1225
1226 static inline void __stop_tx(struct uart_8250_port *p)
1227 {
1228 if (p->ier & UART_IER_THRI) {
1229 p->ier &= ~UART_IER_THRI;
1230 serial_out(p, UART_IER, p->ier);
1231 }
1232 }
1233
1234 static void serial8250_stop_tx(struct uart_port *port)
1235 {
1236 struct uart_8250_port *up = (struct uart_8250_port *)port;
1237
1238 __stop_tx(up);
1239
1240 /*
1241 * We really want to stop the transmitter from sending.
1242 */
1243 if (up->port.type == PORT_16C950) {
1244 up->acr |= UART_ACR_TXDIS;
1245 serial_icr_write(up, UART_ACR, up->acr);
1246 }
1247 }
1248
1249 static void transmit_chars(struct uart_8250_port *up);
1250
1251 static void serial8250_start_tx(struct uart_port *port)
1252 {
1253 struct uart_8250_port *up = (struct uart_8250_port *)port;
1254
1255 if (!(up->ier & UART_IER_THRI)) {
1256 up->ier |= UART_IER_THRI;
1257 serial_out(up, UART_IER, up->ier);
1258
1259 if (up->bugs & UART_BUG_TXEN) {
1260 unsigned char lsr, iir;
1261 lsr = serial_in(up, UART_LSR);
1262 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1263 iir = serial_in(up, UART_IIR) & 0x0f;
1264 if ((up->port.type == PORT_RM9000) ?
1265 (lsr & UART_LSR_THRE &&
1266 (iir == UART_IIR_NO_INT || iir == UART_IIR_THRI)) :
1267 (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT))
1268 transmit_chars(up);
1269 }
1270 }
1271
1272 /*
1273 * Re-enable the transmitter if we disabled it.
1274 */
1275 if (up->port.type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1276 up->acr &= ~UART_ACR_TXDIS;
1277 serial_icr_write(up, UART_ACR, up->acr);
1278 }
1279 }
1280
1281 static void serial8250_stop_rx(struct uart_port *port)
1282 {
1283 struct uart_8250_port *up = (struct uart_8250_port *)port;
1284
1285 up->ier &= ~UART_IER_RLSI;
1286 up->port.read_status_mask &= ~UART_LSR_DR;
1287 serial_out(up, UART_IER, up->ier);
1288 }
1289
1290 static void serial8250_enable_ms(struct uart_port *port)
1291 {
1292 struct uart_8250_port *up = (struct uart_8250_port *)port;
1293
1294 /* no MSR capabilities */
1295 if (up->bugs & UART_BUG_NOMSR)
1296 return;
1297
1298 up->ier |= UART_IER_MSI;
1299 serial_out(up, UART_IER, up->ier);
1300 }
1301
1302 static void
1303 receive_chars(struct uart_8250_port *up, unsigned int *status)
1304 {
1305 struct tty_struct *tty = up->port.info->port.tty;
1306 unsigned char ch, lsr = *status;
1307 int max_count = 256;
1308 char flag;
1309
1310 do {
1311 if (likely(lsr & UART_LSR_DR))
1312 ch = serial_inp(up, UART_RX);
1313 else
1314 /*
1315 * Intel 82571 has a Serial Over Lan device that will
1316 * set UART_LSR_BI without setting UART_LSR_DR when
1317 * it receives a break. To avoid reading from the
1318 * receive buffer without UART_LSR_DR bit set, we
1319 * just force the read character to be 0
1320 */
1321 ch = 0;
1322
1323 flag = TTY_NORMAL;
1324 up->port.icount.rx++;
1325
1326 lsr |= up->lsr_saved_flags;
1327 up->lsr_saved_flags = 0;
1328
1329 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1330 /*
1331 * For statistics only
1332 */
1333 if (lsr & UART_LSR_BI) {
1334 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1335 up->port.icount.brk++;
1336 /*
1337 * We do the SysRQ and SAK checking
1338 * here because otherwise the break
1339 * may get masked by ignore_status_mask
1340 * or read_status_mask.
1341 */
1342 if (uart_handle_break(&up->port))
1343 goto ignore_char;
1344 } else if (lsr & UART_LSR_PE)
1345 up->port.icount.parity++;
1346 else if (lsr & UART_LSR_FE)
1347 up->port.icount.frame++;
1348 if (lsr & UART_LSR_OE)
1349 up->port.icount.overrun++;
1350
1351 /*
1352 * Mask off conditions which should be ignored.
1353 */
1354 lsr &= up->port.read_status_mask;
1355
1356 if (lsr & UART_LSR_BI) {
1357 DEBUG_INTR("handling break....");
1358 flag = TTY_BREAK;
1359 } else if (lsr & UART_LSR_PE)
1360 flag = TTY_PARITY;
1361 else if (lsr & UART_LSR_FE)
1362 flag = TTY_FRAME;
1363 }
1364 if (uart_handle_sysrq_char(&up->port, ch))
1365 goto ignore_char;
1366
1367 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
1368
1369 ignore_char:
1370 lsr = serial_inp(up, UART_LSR);
1371 } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (max_count-- > 0));
1372 spin_unlock(&up->port.lock);
1373 tty_flip_buffer_push(tty);
1374 spin_lock(&up->port.lock);
1375 *status = lsr;
1376 }
1377
1378 static void transmit_chars(struct uart_8250_port *up)
1379 {
1380 struct circ_buf *xmit = &up->port.info->xmit;
1381 int count;
1382
1383 if (up->port.x_char) {
1384 serial_outp(up, UART_TX, up->port.x_char);
1385 up->port.icount.tx++;
1386 up->port.x_char = 0;
1387 return;
1388 }
1389 if (uart_tx_stopped(&up->port)) {
1390 serial8250_stop_tx(&up->port);
1391 return;
1392 }
1393 if (uart_circ_empty(xmit)) {
1394 __stop_tx(up);
1395 return;
1396 }
1397
1398 count = up->tx_loadsz;
1399 do {
1400 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1401 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1402 up->port.icount.tx++;
1403 if (uart_circ_empty(xmit))
1404 break;
1405 } while (--count > 0);
1406
1407 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1408 uart_write_wakeup(&up->port);
1409
1410 DEBUG_INTR("THRE...");
1411
1412 if (uart_circ_empty(xmit))
1413 __stop_tx(up);
1414 }
1415
1416 static unsigned int check_modem_status(struct uart_8250_port *up)
1417 {
1418 unsigned int status = serial_in(up, UART_MSR);
1419
1420 status |= up->msr_saved_flags;
1421 up->msr_saved_flags = 0;
1422 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
1423 up->port.info != NULL) {
1424 if (status & UART_MSR_TERI)
1425 up->port.icount.rng++;
1426 if (status & UART_MSR_DDSR)
1427 up->port.icount.dsr++;
1428 if (status & UART_MSR_DDCD)
1429 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
1430 if (status & UART_MSR_DCTS)
1431 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
1432
1433 wake_up_interruptible(&up->port.info->delta_msr_wait);
1434 }
1435
1436 return status;
1437 }
1438
1439 /*
1440 * This handles the interrupt from one port.
1441 */
1442 static void serial8250_handle_port(struct uart_8250_port *up)
1443 {
1444 unsigned int status;
1445 unsigned long flags;
1446
1447 spin_lock_irqsave(&up->port.lock, flags);
1448
1449 status = serial_inp(up, UART_LSR);
1450
1451 DEBUG_INTR("status = %x...", status);
1452
1453 if (status & (UART_LSR_DR | UART_LSR_BI))
1454 receive_chars(up, &status);
1455 check_modem_status(up);
1456 if (status & UART_LSR_THRE)
1457 transmit_chars(up);
1458
1459 spin_unlock_irqrestore(&up->port.lock, flags);
1460 }
1461
1462 /*
1463 * This is the serial driver's interrupt routine.
1464 *
1465 * Arjan thinks the old way was overly complex, so it got simplified.
1466 * Alan disagrees, saying that need the complexity to handle the weird
1467 * nature of ISA shared interrupts. (This is a special exception.)
1468 *
1469 * In order to handle ISA shared interrupts properly, we need to check
1470 * that all ports have been serviced, and therefore the ISA interrupt
1471 * line has been de-asserted.
1472 *
1473 * This means we need to loop through all ports. checking that they
1474 * don't have an interrupt pending.
1475 */
1476 static irqreturn_t serial8250_interrupt(int irq, void *dev_id)
1477 {
1478 struct irq_info *i = dev_id;
1479 struct list_head *l, *end = NULL;
1480 int pass_counter = 0, handled = 0;
1481
1482 DEBUG_INTR("serial8250_interrupt(%d)...", irq);
1483
1484 spin_lock(&i->lock);
1485
1486 l = i->head;
1487 do {
1488 struct uart_8250_port *up;
1489 unsigned int iir;
1490
1491 up = list_entry(l, struct uart_8250_port, list);
1492
1493 iir = serial_in(up, UART_IIR);
1494 if (!(iir & UART_IIR_NO_INT)) {
1495 serial8250_handle_port(up);
1496
1497 handled = 1;
1498
1499 end = NULL;
1500 } else if (up->port.iotype == UPIO_DWAPB &&
1501 (iir & UART_IIR_BUSY) == UART_IIR_BUSY) {
1502 /* The DesignWare APB UART has an Busy Detect (0x07)
1503 * interrupt meaning an LCR write attempt occured while the
1504 * UART was busy. The interrupt must be cleared by reading
1505 * the UART status register (USR) and the LCR re-written. */
1506 unsigned int status;
1507 status = *(volatile u32 *)up->port.private_data;
1508 serial_out(up, UART_LCR, up->lcr);
1509
1510 handled = 1;
1511
1512 end = NULL;
1513 } else if (end == NULL)
1514 end = l;
1515
1516 l = l->next;
1517
1518 if (l == i->head && pass_counter++ > PASS_LIMIT) {
1519 /* If we hit this, we're dead. */
1520 printk(KERN_ERR "serial8250: too much work for "
1521 "irq%d\n", irq);
1522 break;
1523 }
1524 } while (l != end);
1525
1526 spin_unlock(&i->lock);
1527
1528 DEBUG_INTR("end.\n");
1529
1530 return IRQ_RETVAL(handled);
1531 }
1532
1533 /*
1534 * To support ISA shared interrupts, we need to have one interrupt
1535 * handler that ensures that the IRQ line has been deasserted
1536 * before returning. Failing to do this will result in the IRQ
1537 * line being stuck active, and, since ISA irqs are edge triggered,
1538 * no more IRQs will be seen.
1539 */
1540 static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up)
1541 {
1542 spin_lock_irq(&i->lock);
1543
1544 if (!list_empty(i->head)) {
1545 if (i->head == &up->list)
1546 i->head = i->head->next;
1547 list_del(&up->list);
1548 } else {
1549 BUG_ON(i->head != &up->list);
1550 i->head = NULL;
1551 }
1552 spin_unlock_irq(&i->lock);
1553 /* List empty so throw away the hash node */
1554 if (i->head == NULL) {
1555 hlist_del(&i->node);
1556 kfree(i);
1557 }
1558 }
1559
1560 static int serial_link_irq_chain(struct uart_8250_port *up)
1561 {
1562 struct hlist_head *h;
1563 struct hlist_node *n;
1564 struct irq_info *i;
1565 int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? IRQF_SHARED : 0;
1566
1567 mutex_lock(&hash_mutex);
1568
1569 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1570
1571 hlist_for_each(n, h) {
1572 i = hlist_entry(n, struct irq_info, node);
1573 if (i->irq == up->port.irq)
1574 break;
1575 }
1576
1577 if (n == NULL) {
1578 i = kzalloc(sizeof(struct irq_info), GFP_KERNEL);
1579 if (i == NULL) {
1580 mutex_unlock(&hash_mutex);
1581 return -ENOMEM;
1582 }
1583 spin_lock_init(&i->lock);
1584 i->irq = up->port.irq;
1585 hlist_add_head(&i->node, h);
1586 }
1587 mutex_unlock(&hash_mutex);
1588
1589 spin_lock_irq(&i->lock);
1590
1591 if (i->head) {
1592 list_add(&up->list, i->head);
1593 spin_unlock_irq(&i->lock);
1594
1595 ret = 0;
1596 } else {
1597 INIT_LIST_HEAD(&up->list);
1598 i->head = &up->list;
1599 spin_unlock_irq(&i->lock);
1600
1601 ret = request_irq(up->port.irq, serial8250_interrupt,
1602 irq_flags, "serial", i);
1603 if (ret < 0)
1604 serial_do_unlink(i, up);
1605 }
1606
1607 return ret;
1608 }
1609
1610 static void serial_unlink_irq_chain(struct uart_8250_port *up)
1611 {
1612 struct irq_info *i;
1613 struct hlist_node *n;
1614 struct hlist_head *h;
1615
1616 mutex_lock(&hash_mutex);
1617
1618 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1619
1620 hlist_for_each(n, h) {
1621 i = hlist_entry(n, struct irq_info, node);
1622 if (i->irq == up->port.irq)
1623 break;
1624 }
1625
1626 BUG_ON(n == NULL);
1627 BUG_ON(i->head == NULL);
1628
1629 if (list_empty(i->head))
1630 free_irq(up->port.irq, i);
1631
1632 serial_do_unlink(i, up);
1633 mutex_unlock(&hash_mutex);
1634 }
1635
1636 /* Base timer interval for polling */
1637 static inline int poll_timeout(int timeout)
1638 {
1639 return timeout > 6 ? (timeout / 2 - 2) : 1;
1640 }
1641
1642 /*
1643 * This function is used to handle ports that do not have an
1644 * interrupt. This doesn't work very well for 16450's, but gives
1645 * barely passable results for a 16550A. (Although at the expense
1646 * of much CPU overhead).
1647 */
1648 static void serial8250_timeout(unsigned long data)
1649 {
1650 struct uart_8250_port *up = (struct uart_8250_port *)data;
1651 unsigned int iir;
1652
1653 iir = serial_in(up, UART_IIR);
1654 if (!(iir & UART_IIR_NO_INT))
1655 serial8250_handle_port(up);
1656 mod_timer(&up->timer, jiffies + poll_timeout(up->port.timeout));
1657 }
1658
1659 static void serial8250_backup_timeout(unsigned long data)
1660 {
1661 struct uart_8250_port *up = (struct uart_8250_port *)data;
1662 unsigned int iir, ier = 0, lsr;
1663 unsigned long flags;
1664
1665 /*
1666 * Must disable interrupts or else we risk racing with the interrupt
1667 * based handler.
1668 */
1669 if (is_real_interrupt(up->port.irq)) {
1670 ier = serial_in(up, UART_IER);
1671 serial_out(up, UART_IER, 0);
1672 }
1673
1674 iir = serial_in(up, UART_IIR);
1675
1676 /*
1677 * This should be a safe test for anyone who doesn't trust the
1678 * IIR bits on their UART, but it's specifically designed for
1679 * the "Diva" UART used on the management processor on many HP
1680 * ia64 and parisc boxes.
1681 */
1682 spin_lock_irqsave(&up->port.lock, flags);
1683 lsr = serial_in(up, UART_LSR);
1684 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1685 spin_unlock_irqrestore(&up->port.lock, flags);
1686 if ((iir & UART_IIR_NO_INT) && (up->ier & UART_IER_THRI) &&
1687 (!uart_circ_empty(&up->port.info->xmit) || up->port.x_char) &&
1688 (lsr & UART_LSR_THRE)) {
1689 iir &= ~(UART_IIR_ID | UART_IIR_NO_INT);
1690 iir |= UART_IIR_THRI;
1691 }
1692
1693 if (!(iir & UART_IIR_NO_INT))
1694 serial8250_handle_port(up);
1695
1696 if (is_real_interrupt(up->port.irq))
1697 serial_out(up, UART_IER, ier);
1698
1699 /* Standard timer interval plus 0.2s to keep the port running */
1700 mod_timer(&up->timer,
1701 jiffies + poll_timeout(up->port.timeout) + HZ / 5);
1702 }
1703
1704 static unsigned int serial8250_tx_empty(struct uart_port *port)
1705 {
1706 struct uart_8250_port *up = (struct uart_8250_port *)port;
1707 unsigned long flags;
1708 unsigned int lsr;
1709
1710 spin_lock_irqsave(&up->port.lock, flags);
1711 lsr = serial_in(up, UART_LSR);
1712 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1713 spin_unlock_irqrestore(&up->port.lock, flags);
1714
1715 return lsr & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
1716 }
1717
1718 static unsigned int serial8250_get_mctrl(struct uart_port *port)
1719 {
1720 struct uart_8250_port *up = (struct uart_8250_port *)port;
1721 unsigned int status;
1722 unsigned int ret;
1723
1724 status = check_modem_status(up);
1725
1726 ret = 0;
1727 if (status & UART_MSR_DCD)
1728 ret |= TIOCM_CAR;
1729 if (status & UART_MSR_RI)
1730 ret |= TIOCM_RNG;
1731 if (status & UART_MSR_DSR)
1732 ret |= TIOCM_DSR;
1733 if (status & UART_MSR_CTS)
1734 ret |= TIOCM_CTS;
1735 return ret;
1736 }
1737
1738 static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1739 {
1740 struct uart_8250_port *up = (struct uart_8250_port *)port;
1741 unsigned char mcr = 0;
1742
1743 if (mctrl & TIOCM_RTS)
1744 mcr |= UART_MCR_RTS;
1745 if (mctrl & TIOCM_DTR)
1746 mcr |= UART_MCR_DTR;
1747 if (mctrl & TIOCM_OUT1)
1748 mcr |= UART_MCR_OUT1;
1749 if (mctrl & TIOCM_OUT2)
1750 mcr |= UART_MCR_OUT2;
1751 if (mctrl & TIOCM_LOOP)
1752 mcr |= UART_MCR_LOOP;
1753
1754 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1755
1756 serial_out(up, UART_MCR, mcr);
1757 }
1758
1759 static void serial8250_break_ctl(struct uart_port *port, int break_state)
1760 {
1761 struct uart_8250_port *up = (struct uart_8250_port *)port;
1762 unsigned long flags;
1763
1764 spin_lock_irqsave(&up->port.lock, flags);
1765 if (break_state == -1)
1766 up->lcr |= UART_LCR_SBC;
1767 else
1768 up->lcr &= ~UART_LCR_SBC;
1769 serial_out(up, UART_LCR, up->lcr);
1770 spin_unlock_irqrestore(&up->port.lock, flags);
1771 }
1772
1773 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
1774
1775 /*
1776 * Wait for transmitter & holding register to empty
1777 */
1778 static void wait_for_xmitr(struct uart_8250_port *up, int bits)
1779 {
1780 unsigned int status, tmout = 10000;
1781
1782 /* Wait up to 10ms for the character(s) to be sent. */
1783 do {
1784 status = serial_in(up, UART_LSR);
1785
1786 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
1787
1788 if (--tmout == 0)
1789 break;
1790 udelay(1);
1791 } while ((status & bits) != bits);
1792
1793 /* Wait up to 1s for flow control if necessary */
1794 if (up->port.flags & UPF_CONS_FLOW) {
1795 unsigned int tmout;
1796 for (tmout = 1000000; tmout; tmout--) {
1797 unsigned int msr = serial_in(up, UART_MSR);
1798 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1799 if (msr & UART_MSR_CTS)
1800 break;
1801 udelay(1);
1802 touch_nmi_watchdog();
1803 }
1804 }
1805 }
1806
1807 #ifdef CONFIG_CONSOLE_POLL
1808 /*
1809 * Console polling routines for writing and reading from the uart while
1810 * in an interrupt or debug context.
1811 */
1812
1813 static int serial8250_get_poll_char(struct uart_port *port)
1814 {
1815 struct uart_8250_port *up = (struct uart_8250_port *)port;
1816 unsigned char lsr = serial_inp(up, UART_LSR);
1817
1818 while (!(lsr & UART_LSR_DR))
1819 lsr = serial_inp(up, UART_LSR);
1820
1821 return serial_inp(up, UART_RX);
1822 }
1823
1824
1825 static void serial8250_put_poll_char(struct uart_port *port,
1826 unsigned char c)
1827 {
1828 unsigned int ier;
1829 struct uart_8250_port *up = (struct uart_8250_port *)port;
1830
1831 /*
1832 * First save the IER then disable the interrupts
1833 */
1834 ier = serial_in(up, UART_IER);
1835 if (up->capabilities & UART_CAP_UUE)
1836 serial_out(up, UART_IER, UART_IER_UUE);
1837 else
1838 serial_out(up, UART_IER, 0);
1839
1840 wait_for_xmitr(up, BOTH_EMPTY);
1841 /*
1842 * Send the character out.
1843 * If a LF, also do CR...
1844 */
1845 serial_out(up, UART_TX, c);
1846 if (c == 10) {
1847 wait_for_xmitr(up, BOTH_EMPTY);
1848 serial_out(up, UART_TX, 13);
1849 }
1850
1851 /*
1852 * Finally, wait for transmitter to become empty
1853 * and restore the IER
1854 */
1855 wait_for_xmitr(up, BOTH_EMPTY);
1856 serial_out(up, UART_IER, ier);
1857 }
1858
1859 #endif /* CONFIG_CONSOLE_POLL */
1860
1861 static int serial8250_startup(struct uart_port *port)
1862 {
1863 struct uart_8250_port *up = (struct uart_8250_port *)port;
1864 unsigned long flags;
1865 unsigned char lsr, iir;
1866 int retval;
1867
1868 up->capabilities = uart_config[up->port.type].flags;
1869 up->mcr = 0;
1870
1871 if (up->port.type == PORT_16C950) {
1872 /* Wake up and initialize UART */
1873 up->acr = 0;
1874 serial_outp(up, UART_LCR, 0xBF);
1875 serial_outp(up, UART_EFR, UART_EFR_ECB);
1876 serial_outp(up, UART_IER, 0);
1877 serial_outp(up, UART_LCR, 0);
1878 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
1879 serial_outp(up, UART_LCR, 0xBF);
1880 serial_outp(up, UART_EFR, UART_EFR_ECB);
1881 serial_outp(up, UART_LCR, 0);
1882 }
1883
1884 #ifdef CONFIG_SERIAL_8250_RSA
1885 /*
1886 * If this is an RSA port, see if we can kick it up to the
1887 * higher speed clock.
1888 */
1889 enable_rsa(up);
1890 #endif
1891
1892 /*
1893 * Clear the FIFO buffers and disable them.
1894 * (they will be reenabled in set_termios())
1895 */
1896 serial8250_clear_fifos(up);
1897
1898 /*
1899 * Clear the interrupt registers.
1900 */
1901 (void) serial_inp(up, UART_LSR);
1902 (void) serial_inp(up, UART_RX);
1903 (void) serial_inp(up, UART_IIR);
1904 (void) serial_inp(up, UART_MSR);
1905
1906 /*
1907 * At this point, there's no way the LSR could still be 0xff;
1908 * if it is, then bail out, because there's likely no UART
1909 * here.
1910 */
1911 if (!(up->port.flags & UPF_BUGGY_UART) &&
1912 (serial_inp(up, UART_LSR) == 0xff)) {
1913 printk(KERN_INFO "ttyS%d: LSR safety check engaged!\n",
1914 serial_index(&up->port));
1915 return -ENODEV;
1916 }
1917
1918 /*
1919 * For a XR16C850, we need to set the trigger levels
1920 */
1921 if (up->port.type == PORT_16850) {
1922 unsigned char fctr;
1923
1924 serial_outp(up, UART_LCR, 0xbf);
1925
1926 fctr = serial_inp(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
1927 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_RX);
1928 serial_outp(up, UART_TRG, UART_TRG_96);
1929 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_TX);
1930 serial_outp(up, UART_TRG, UART_TRG_96);
1931
1932 serial_outp(up, UART_LCR, 0);
1933 }
1934
1935 if (is_real_interrupt(up->port.irq)) {
1936 unsigned char iir1;
1937 /*
1938 * Test for UARTs that do not reassert THRE when the
1939 * transmitter is idle and the interrupt has already
1940 * been cleared. Real 16550s should always reassert
1941 * this interrupt whenever the transmitter is idle and
1942 * the interrupt is enabled. Delays are necessary to
1943 * allow register changes to become visible.
1944 */
1945 spin_lock_irqsave(&up->port.lock, flags);
1946 if (up->port.flags & UPF_SHARE_IRQ)
1947 disable_irq_nosync(up->port.irq);
1948
1949 wait_for_xmitr(up, UART_LSR_THRE);
1950 serial_out_sync(up, UART_IER, UART_IER_THRI);
1951 udelay(1); /* allow THRE to set */
1952 iir1 = serial_in(up, UART_IIR);
1953 serial_out(up, UART_IER, 0);
1954 serial_out_sync(up, UART_IER, UART_IER_THRI);
1955 udelay(1); /* allow a working UART time to re-assert THRE */
1956 iir = serial_in(up, UART_IIR);
1957 serial_out(up, UART_IER, 0);
1958
1959 if (up->port.flags & UPF_SHARE_IRQ)
1960 enable_irq(up->port.irq);
1961 spin_unlock_irqrestore(&up->port.lock, flags);
1962
1963 /*
1964 * If the interrupt is not reasserted, setup a timer to
1965 * kick the UART on a regular basis.
1966 */
1967 if (!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) {
1968 up->bugs |= UART_BUG_THRE;
1969 pr_debug("ttyS%d - using backup timer\n",
1970 serial_index(port));
1971 }
1972 }
1973
1974 /*
1975 * The above check will only give an accurate result the first time
1976 * the port is opened so this value needs to be preserved.
1977 */
1978 if (up->bugs & UART_BUG_THRE) {
1979 up->timer.function = serial8250_backup_timeout;
1980 up->timer.data = (unsigned long)up;
1981 mod_timer(&up->timer, jiffies +
1982 poll_timeout(up->port.timeout) + HZ / 5);
1983 }
1984
1985 /*
1986 * If the "interrupt" for this port doesn't correspond with any
1987 * hardware interrupt, we use a timer-based system. The original
1988 * driver used to do this with IRQ0.
1989 */
1990 if (!is_real_interrupt(up->port.irq)) {
1991 up->timer.data = (unsigned long)up;
1992 mod_timer(&up->timer, jiffies + poll_timeout(up->port.timeout));
1993 } else {
1994 retval = serial_link_irq_chain(up);
1995 if (retval)
1996 return retval;
1997 }
1998
1999 /*
2000 * Now, initialize the UART
2001 */
2002 serial_outp(up, UART_LCR, UART_LCR_WLEN8);
2003
2004 spin_lock_irqsave(&up->port.lock, flags);
2005 if (up->port.flags & UPF_FOURPORT) {
2006 if (!is_real_interrupt(up->port.irq))
2007 up->port.mctrl |= TIOCM_OUT1;
2008 } else
2009 /*
2010 * Most PC uarts need OUT2 raised to enable interrupts.
2011 */
2012 if (is_real_interrupt(up->port.irq))
2013 up->port.mctrl |= TIOCM_OUT2;
2014
2015 serial8250_set_mctrl(&up->port, up->port.mctrl);
2016
2017 /* Serial over Lan (SoL) hack:
2018 Intel 8257x Gigabit ethernet chips have a
2019 16550 emulation, to be used for Serial Over Lan.
2020 Those chips take a longer time than a normal
2021 serial device to signalize that a transmission
2022 data was queued. Due to that, the above test generally
2023 fails. One solution would be to delay the reading of
2024 iir. However, this is not reliable, since the timeout
2025 is variable. So, let's just don't test if we receive
2026 TX irq. This way, we'll never enable UART_BUG_TXEN.
2027 */
2028 if (up->port.flags & UPF_NO_TXEN_TEST)
2029 goto dont_test_tx_en;
2030
2031 /*
2032 * Do a quick test to see if we receive an
2033 * interrupt when we enable the TX irq.
2034 */
2035 serial_outp(up, UART_IER, UART_IER_THRI);
2036 lsr = serial_in(up, UART_LSR);
2037 iir = serial_in(up, UART_IIR);
2038 serial_outp(up, UART_IER, 0);
2039
2040 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
2041 if (!(up->bugs & UART_BUG_TXEN)) {
2042 up->bugs |= UART_BUG_TXEN;
2043 pr_debug("ttyS%d - enabling bad tx status workarounds\n",
2044 serial_index(port));
2045 }
2046 } else {
2047 up->bugs &= ~UART_BUG_TXEN;
2048 }
2049
2050 dont_test_tx_en:
2051 spin_unlock_irqrestore(&up->port.lock, flags);
2052
2053 /*
2054 * Clear the interrupt registers again for luck, and clear the
2055 * saved flags to avoid getting false values from polling
2056 * routines or the previous session.
2057 */
2058 serial_inp(up, UART_LSR);
2059 serial_inp(up, UART_RX);
2060 serial_inp(up, UART_IIR);
2061 serial_inp(up, UART_MSR);
2062 up->lsr_saved_flags = 0;
2063 up->msr_saved_flags = 0;
2064
2065 /*
2066 * Finally, enable interrupts. Note: Modem status interrupts
2067 * are set via set_termios(), which will be occurring imminently
2068 * anyway, so we don't enable them here.
2069 */
2070 up->ier = UART_IER_RLSI | UART_IER_RDI;
2071 serial_outp(up, UART_IER, up->ier);
2072
2073 if (up->port.flags & UPF_FOURPORT) {
2074 unsigned int icp;
2075 /*
2076 * Enable interrupts on the AST Fourport board
2077 */
2078 icp = (up->port.iobase & 0xfe0) | 0x01f;
2079 outb_p(0x80, icp);
2080 (void) inb_p(icp);
2081 }
2082
2083 return 0;
2084 }
2085
2086 static void serial8250_shutdown(struct uart_port *port)
2087 {
2088 struct uart_8250_port *up = (struct uart_8250_port *)port;
2089 unsigned long flags;
2090
2091 /*
2092 * Disable interrupts from this port
2093 */
2094 up->ier = 0;
2095 serial_outp(up, UART_IER, 0);
2096
2097 spin_lock_irqsave(&up->port.lock, flags);
2098 if (up->port.flags & UPF_FOURPORT) {
2099 /* reset interrupts on the AST Fourport board */
2100 inb((up->port.iobase & 0xfe0) | 0x1f);
2101 up->port.mctrl |= TIOCM_OUT1;
2102 } else
2103 up->port.mctrl &= ~TIOCM_OUT2;
2104
2105 serial8250_set_mctrl(&up->port, up->port.mctrl);
2106 spin_unlock_irqrestore(&up->port.lock, flags);
2107
2108 /*
2109 * Disable break condition and FIFOs
2110 */
2111 serial_out(up, UART_LCR, serial_inp(up, UART_LCR) & ~UART_LCR_SBC);
2112 serial8250_clear_fifos(up);
2113
2114 #ifdef CONFIG_SERIAL_8250_RSA
2115 /*
2116 * Reset the RSA board back to 115kbps compat mode.
2117 */
2118 disable_rsa(up);
2119 #endif
2120
2121 /*
2122 * Read data port to reset things, and then unlink from
2123 * the IRQ chain.
2124 */
2125 (void) serial_in(up, UART_RX);
2126
2127 del_timer_sync(&up->timer);
2128 up->timer.function = serial8250_timeout;
2129 if (is_real_interrupt(up->port.irq))
2130 serial_unlink_irq_chain(up);
2131 }
2132
2133 static unsigned int serial8250_get_divisor(struct uart_port *port, unsigned int baud)
2134 {
2135 unsigned int quot;
2136
2137 /*
2138 * Handle magic divisors for baud rates above baud_base on
2139 * SMSC SuperIO chips.
2140 */
2141 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2142 baud == (port->uartclk/4))
2143 quot = 0x8001;
2144 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2145 baud == (port->uartclk/8))
2146 quot = 0x8002;
2147 else
2148 quot = uart_get_divisor(port, baud);
2149
2150 return quot;
2151 }
2152
2153 static void
2154 serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2155 struct ktermios *old)
2156 {
2157 struct uart_8250_port *up = (struct uart_8250_port *)port;
2158 unsigned char cval, fcr = 0;
2159 unsigned long flags;
2160 unsigned int baud, quot;
2161
2162 switch (termios->c_cflag & CSIZE) {
2163 case CS5:
2164 cval = UART_LCR_WLEN5;
2165 break;
2166 case CS6:
2167 cval = UART_LCR_WLEN6;
2168 break;
2169 case CS7:
2170 cval = UART_LCR_WLEN7;
2171 break;
2172 default:
2173 case CS8:
2174 cval = UART_LCR_WLEN8;
2175 break;
2176 }
2177
2178 if (termios->c_cflag & CSTOPB)
2179 cval |= UART_LCR_STOP;
2180 if (termios->c_cflag & PARENB)
2181 cval |= UART_LCR_PARITY;
2182 if (!(termios->c_cflag & PARODD))
2183 cval |= UART_LCR_EPAR;
2184 #ifdef CMSPAR
2185 if (termios->c_cflag & CMSPAR)
2186 cval |= UART_LCR_SPAR;
2187 #endif
2188
2189 /*
2190 * Ask the core to calculate the divisor for us.
2191 */
2192 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
2193 quot = serial8250_get_divisor(port, baud);
2194
2195 /*
2196 * Oxford Semi 952 rev B workaround
2197 */
2198 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
2199 quot++;
2200
2201 if (up->capabilities & UART_CAP_FIFO && up->port.fifosize > 1) {
2202 if (baud < 2400)
2203 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1;
2204 else
2205 fcr = uart_config[up->port.type].fcr;
2206 }
2207
2208 /*
2209 * MCR-based auto flow control. When AFE is enabled, RTS will be
2210 * deasserted when the receive FIFO contains more characters than
2211 * the trigger, or the MCR RTS bit is cleared. In the case where
2212 * the remote UART is not using CTS auto flow control, we must
2213 * have sufficient FIFO entries for the latency of the remote
2214 * UART to respond. IOW, at least 32 bytes of FIFO.
2215 */
2216 if (up->capabilities & UART_CAP_AFE && up->port.fifosize >= 32) {
2217 up->mcr &= ~UART_MCR_AFE;
2218 if (termios->c_cflag & CRTSCTS)
2219 up->mcr |= UART_MCR_AFE;
2220 }
2221
2222 /*
2223 * Ok, we're now changing the port state. Do it with
2224 * interrupts disabled.
2225 */
2226 spin_lock_irqsave(&up->port.lock, flags);
2227
2228 /*
2229 * Update the per-port timeout.
2230 */
2231 uart_update_timeout(port, termios->c_cflag, baud);
2232
2233 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2234 if (termios->c_iflag & INPCK)
2235 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2236 if (termios->c_iflag & (BRKINT | PARMRK))
2237 up->port.read_status_mask |= UART_LSR_BI;
2238
2239 /*
2240 * Characteres to ignore
2241 */
2242 up->port.ignore_status_mask = 0;
2243 if (termios->c_iflag & IGNPAR)
2244 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2245 if (termios->c_iflag & IGNBRK) {
2246 up->port.ignore_status_mask |= UART_LSR_BI;
2247 /*
2248 * If we're ignoring parity and break indicators,
2249 * ignore overruns too (for real raw support).
2250 */
2251 if (termios->c_iflag & IGNPAR)
2252 up->port.ignore_status_mask |= UART_LSR_OE;
2253 }
2254
2255 /*
2256 * ignore all characters if CREAD is not set
2257 */
2258 if ((termios->c_cflag & CREAD) == 0)
2259 up->port.ignore_status_mask |= UART_LSR_DR;
2260
2261 /*
2262 * CTS flow control flag and modem status interrupts
2263 */
2264 up->ier &= ~UART_IER_MSI;
2265 if (!(up->bugs & UART_BUG_NOMSR) &&
2266 UART_ENABLE_MS(&up->port, termios->c_cflag))
2267 up->ier |= UART_IER_MSI;
2268 if (up->capabilities & UART_CAP_UUE)
2269 up->ier |= UART_IER_UUE | UART_IER_RTOIE;
2270
2271 serial_out(up, UART_IER, up->ier);
2272
2273 if (up->capabilities & UART_CAP_EFR) {
2274 unsigned char efr = 0;
2275 /*
2276 * TI16C752/Startech hardware flow control. FIXME:
2277 * - TI16C752 requires control thresholds to be set.
2278 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2279 */
2280 if (termios->c_cflag & CRTSCTS)
2281 efr |= UART_EFR_CTS;
2282
2283 serial_outp(up, UART_LCR, 0xBF);
2284 serial_outp(up, UART_EFR, efr);
2285 }
2286
2287 #ifdef CONFIG_ARCH_OMAP
2288 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
2289 if (cpu_is_omap1510() && is_omap_port(up)) {
2290 if (baud == 115200) {
2291 quot = 1;
2292 serial_out(up, UART_OMAP_OSC_12M_SEL, 1);
2293 } else
2294 serial_out(up, UART_OMAP_OSC_12M_SEL, 0);
2295 }
2296 #endif
2297
2298 if (up->capabilities & UART_NATSEMI) {
2299 /* Switch to bank 2 not bank 1, to avoid resetting EXCR2 */
2300 serial_outp(up, UART_LCR, 0xe0);
2301 } else {
2302 serial_outp(up, UART_LCR, cval | UART_LCR_DLAB);/* set DLAB */
2303 }
2304
2305 serial_dl_write(up, quot);
2306
2307 /*
2308 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2309 * is written without DLAB set, this mode will be disabled.
2310 */
2311 if (up->port.type == PORT_16750)
2312 serial_outp(up, UART_FCR, fcr);
2313
2314 serial_outp(up, UART_LCR, cval); /* reset DLAB */
2315 up->lcr = cval; /* Save LCR */
2316 if (up->port.type != PORT_16750) {
2317 if (fcr & UART_FCR_ENABLE_FIFO) {
2318 /* emulated UARTs (Lucent Venus 167x) need two steps */
2319 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
2320 }
2321 serial_outp(up, UART_FCR, fcr); /* set fcr */
2322 }
2323 serial8250_set_mctrl(&up->port, up->port.mctrl);
2324 spin_unlock_irqrestore(&up->port.lock, flags);
2325 /* Don't rewrite B0 */
2326 if (tty_termios_baud_rate(termios))
2327 tty_termios_encode_baud_rate(termios, baud, baud);
2328 }
2329
2330 static void
2331 serial8250_pm(struct uart_port *port, unsigned int state,
2332 unsigned int oldstate)
2333 {
2334 struct uart_8250_port *p = (struct uart_8250_port *)port;
2335
2336 serial8250_set_sleep(p, state != 0);
2337
2338 if (p->pm)
2339 p->pm(port, state, oldstate);
2340 }
2341
2342 static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2343 {
2344 if (pt->port.iotype == UPIO_AU)
2345 return 0x100000;
2346 #ifdef CONFIG_ARCH_OMAP
2347 if (is_omap_port(pt))
2348 return 0x16 << pt->port.regshift;
2349 #endif
2350 return 8 << pt->port.regshift;
2351 }
2352
2353 /*
2354 * Resource handling.
2355 */
2356 static int serial8250_request_std_resource(struct uart_8250_port *up)
2357 {
2358 unsigned int size = serial8250_port_size(up);
2359 int ret = 0;
2360
2361 switch (up->port.iotype) {
2362 case UPIO_AU:
2363 case UPIO_TSI:
2364 case UPIO_MEM32:
2365 case UPIO_MEM:
2366 case UPIO_DWAPB:
2367 if (!up->port.mapbase)
2368 break;
2369
2370 if (!request_mem_region(up->port.mapbase, size, "serial")) {
2371 ret = -EBUSY;
2372 break;
2373 }
2374
2375 if (up->port.flags & UPF_IOREMAP) {
2376 up->port.membase = ioremap_nocache(up->port.mapbase,
2377 size);
2378 if (!up->port.membase) {
2379 release_mem_region(up->port.mapbase, size);
2380 ret = -ENOMEM;
2381 }
2382 }
2383 break;
2384
2385 case UPIO_HUB6:
2386 case UPIO_PORT:
2387 if (!request_region(up->port.iobase, size, "serial"))
2388 ret = -EBUSY;
2389 break;
2390 }
2391 return ret;
2392 }
2393
2394 static void serial8250_release_std_resource(struct uart_8250_port *up)
2395 {
2396 unsigned int size = serial8250_port_size(up);
2397
2398 switch (up->port.iotype) {
2399 case UPIO_AU:
2400 case UPIO_TSI:
2401 case UPIO_MEM32:
2402 case UPIO_MEM:
2403 case UPIO_DWAPB:
2404 if (!up->port.mapbase)
2405 break;
2406
2407 if (up->port.flags & UPF_IOREMAP) {
2408 iounmap(up->port.membase);
2409 up->port.membase = NULL;
2410 }
2411
2412 release_mem_region(up->port.mapbase, size);
2413 break;
2414
2415 case UPIO_HUB6:
2416 case UPIO_PORT:
2417 release_region(up->port.iobase, size);
2418 break;
2419 }
2420 }
2421
2422 static int serial8250_request_rsa_resource(struct uart_8250_port *up)
2423 {
2424 unsigned long start = UART_RSA_BASE << up->port.regshift;
2425 unsigned int size = 8 << up->port.regshift;
2426 int ret = -EINVAL;
2427
2428 switch (up->port.iotype) {
2429 case UPIO_HUB6:
2430 case UPIO_PORT:
2431 start += up->port.iobase;
2432 if (request_region(start, size, "serial-rsa"))
2433 ret = 0;
2434 else
2435 ret = -EBUSY;
2436 break;
2437 }
2438
2439 return ret;
2440 }
2441
2442 static void serial8250_release_rsa_resource(struct uart_8250_port *up)
2443 {
2444 unsigned long offset = UART_RSA_BASE << up->port.regshift;
2445 unsigned int size = 8 << up->port.regshift;
2446
2447 switch (up->port.iotype) {
2448 case UPIO_HUB6:
2449 case UPIO_PORT:
2450 release_region(up->port.iobase + offset, size);
2451 break;
2452 }
2453 }
2454
2455 static void serial8250_release_port(struct uart_port *port)
2456 {
2457 struct uart_8250_port *up = (struct uart_8250_port *)port;
2458
2459 serial8250_release_std_resource(up);
2460 if (up->port.type == PORT_RSA)
2461 serial8250_release_rsa_resource(up);
2462 }
2463
2464 static int serial8250_request_port(struct uart_port *port)
2465 {
2466 struct uart_8250_port *up = (struct uart_8250_port *)port;
2467 int ret = 0;
2468
2469 ret = serial8250_request_std_resource(up);
2470 if (ret == 0 && up->port.type == PORT_RSA) {
2471 ret = serial8250_request_rsa_resource(up);
2472 if (ret < 0)
2473 serial8250_release_std_resource(up);
2474 }
2475
2476 return ret;
2477 }
2478
2479 static void serial8250_config_port(struct uart_port *port, int flags)
2480 {
2481 struct uart_8250_port *up = (struct uart_8250_port *)port;
2482 int probeflags = PROBE_ANY;
2483 int ret;
2484
2485 /*
2486 * Find the region that we can probe for. This in turn
2487 * tells us whether we can probe for the type of port.
2488 */
2489 ret = serial8250_request_std_resource(up);
2490 if (ret < 0)
2491 return;
2492
2493 ret = serial8250_request_rsa_resource(up);
2494 if (ret < 0)
2495 probeflags &= ~PROBE_RSA;
2496
2497 if (flags & UART_CONFIG_TYPE)
2498 autoconfig(up, probeflags);
2499 if (up->port.type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
2500 autoconfig_irq(up);
2501
2502 if (up->port.type != PORT_RSA && probeflags & PROBE_RSA)
2503 serial8250_release_rsa_resource(up);
2504 if (up->port.type == PORT_UNKNOWN)
2505 serial8250_release_std_resource(up);
2506 }
2507
2508 static int
2509 serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
2510 {
2511 if (ser->irq >= nr_irqs || ser->irq < 0 ||
2512 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
2513 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
2514 ser->type == PORT_STARTECH)
2515 return -EINVAL;
2516 return 0;
2517 }
2518
2519 static const char *
2520 serial8250_type(struct uart_port *port)
2521 {
2522 int type = port->type;
2523
2524 if (type >= ARRAY_SIZE(uart_config))
2525 type = 0;
2526 return uart_config[type].name;
2527 }
2528
2529 static struct uart_ops serial8250_pops = {
2530 .tx_empty = serial8250_tx_empty,
2531 .set_mctrl = serial8250_set_mctrl,
2532 .get_mctrl = serial8250_get_mctrl,
2533 .stop_tx = serial8250_stop_tx,
2534 .start_tx = serial8250_start_tx,
2535 .stop_rx = serial8250_stop_rx,
2536 .enable_ms = serial8250_enable_ms,
2537 .break_ctl = serial8250_break_ctl,
2538 .startup = serial8250_startup,
2539 .shutdown = serial8250_shutdown,
2540 .set_termios = serial8250_set_termios,
2541 .pm = serial8250_pm,
2542 .type = serial8250_type,
2543 .release_port = serial8250_release_port,
2544 .request_port = serial8250_request_port,
2545 .config_port = serial8250_config_port,
2546 .verify_port = serial8250_verify_port,
2547 #ifdef CONFIG_CONSOLE_POLL
2548 .poll_get_char = serial8250_get_poll_char,
2549 .poll_put_char = serial8250_put_poll_char,
2550 #endif
2551 };
2552
2553 static struct uart_8250_port serial8250_ports[UART_NR];
2554
2555 static void __init serial8250_isa_init_ports(void)
2556 {
2557 struct uart_8250_port *up;
2558 static int first = 1;
2559 int i;
2560
2561 if (!first)
2562 return;
2563 first = 0;
2564
2565 for (i = 0; i < nr_uarts; i++) {
2566 struct uart_8250_port *up = &serial8250_ports[i];
2567
2568 up->port.line = i;
2569 spin_lock_init(&up->port.lock);
2570
2571 init_timer(&up->timer);
2572 up->timer.function = serial8250_timeout;
2573
2574 /*
2575 * ALPHA_KLUDGE_MCR needs to be killed.
2576 */
2577 up->mcr_mask = ~ALPHA_KLUDGE_MCR;
2578 up->mcr_force = ALPHA_KLUDGE_MCR;
2579
2580 up->port.ops = &serial8250_pops;
2581 }
2582
2583 for (i = 0, up = serial8250_ports;
2584 i < ARRAY_SIZE(old_serial_port) && i < nr_uarts;
2585 i++, up++) {
2586 up->port.iobase = old_serial_port[i].port;
2587 up->port.irq = irq_canonicalize(old_serial_port[i].irq);
2588 up->port.uartclk = old_serial_port[i].baud_base * 16;
2589 up->port.flags = old_serial_port[i].flags;
2590 up->port.hub6 = old_serial_port[i].hub6;
2591 up->port.membase = old_serial_port[i].iomem_base;
2592 up->port.iotype = old_serial_port[i].io_type;
2593 up->port.regshift = old_serial_port[i].iomem_reg_shift;
2594 if (share_irqs)
2595 up->port.flags |= UPF_SHARE_IRQ;
2596 }
2597 }
2598
2599 static void __init
2600 serial8250_register_ports(struct uart_driver *drv, struct device *dev)
2601 {
2602 int i;
2603
2604 serial8250_isa_init_ports();
2605
2606 for (i = 0; i < nr_uarts; i++) {
2607 struct uart_8250_port *up = &serial8250_ports[i];
2608
2609 up->port.dev = dev;
2610 uart_add_one_port(drv, &up->port);
2611 }
2612 }
2613
2614 #ifdef CONFIG_SERIAL_8250_CONSOLE
2615
2616 static void serial8250_console_putchar(struct uart_port *port, int ch)
2617 {
2618 struct uart_8250_port *up = (struct uart_8250_port *)port;
2619
2620 wait_for_xmitr(up, UART_LSR_THRE);
2621 serial_out(up, UART_TX, ch);
2622 }
2623
2624 /*
2625 * Print a string to the serial port trying not to disturb
2626 * any possible real use of the port...
2627 *
2628 * The console_lock must be held when we get here.
2629 */
2630 static void
2631 serial8250_console_write(struct console *co, const char *s, unsigned int count)
2632 {
2633 struct uart_8250_port *up = &serial8250_ports[co->index];
2634 unsigned long flags;
2635 unsigned int ier;
2636 int locked = 1;
2637
2638 touch_nmi_watchdog();
2639
2640 local_irq_save(flags);
2641 if (up->port.sysrq) {
2642 /* serial8250_handle_port() already took the lock */
2643 locked = 0;
2644 } else if (oops_in_progress) {
2645 locked = spin_trylock(&up->port.lock);
2646 } else
2647 spin_lock(&up->port.lock);
2648
2649 /*
2650 * First save the IER then disable the interrupts
2651 */
2652 ier = serial_in(up, UART_IER);
2653
2654 if (up->capabilities & UART_CAP_UUE)
2655 serial_out(up, UART_IER, UART_IER_UUE);
2656 else
2657 serial_out(up, UART_IER, 0);
2658
2659 uart_console_write(&up->port, s, count, serial8250_console_putchar);
2660
2661 /*
2662 * Finally, wait for transmitter to become empty
2663 * and restore the IER
2664 */
2665 wait_for_xmitr(up, BOTH_EMPTY);
2666 serial_out(up, UART_IER, ier);
2667
2668 /*
2669 * The receive handling will happen properly because the
2670 * receive ready bit will still be set; it is not cleared
2671 * on read. However, modem control will not, we must
2672 * call it if we have saved something in the saved flags
2673 * while processing with interrupts off.
2674 */
2675 if (up->msr_saved_flags)
2676 check_modem_status(up);
2677
2678 if (locked)
2679 spin_unlock(&up->port.lock);
2680 local_irq_restore(flags);
2681 }
2682
2683 static int __init serial8250_console_setup(struct console *co, char *options)
2684 {
2685 struct uart_port *port;
2686 int baud = 9600;
2687 int bits = 8;
2688 int parity = 'n';
2689 int flow = 'n';
2690
2691 /*
2692 * Check whether an invalid uart number has been specified, and
2693 * if so, search for the first available port that does have
2694 * console support.
2695 */
2696 if (co->index >= nr_uarts)
2697 co->index = 0;
2698 port = &serial8250_ports[co->index].port;
2699 if (!port->iobase && !port->membase)
2700 return -ENODEV;
2701
2702 if (options)
2703 uart_parse_options(options, &baud, &parity, &bits, &flow);
2704
2705 return uart_set_options(port, co, baud, parity, bits, flow);
2706 }
2707
2708 static int serial8250_console_early_setup(void)
2709 {
2710 return serial8250_find_port_for_earlycon();
2711 }
2712
2713 static struct console serial8250_console = {
2714 .name = "ttyS",
2715 .write = serial8250_console_write,
2716 .device = uart_console_device,
2717 .setup = serial8250_console_setup,
2718 .early_setup = serial8250_console_early_setup,
2719 .flags = CON_PRINTBUFFER,
2720 .index = -1,
2721 .data = &serial8250_reg,
2722 };
2723
2724 static int __init serial8250_console_init(void)
2725 {
2726 if (nr_uarts > UART_NR)
2727 nr_uarts = UART_NR;
2728
2729 serial8250_isa_init_ports();
2730 register_console(&serial8250_console);
2731 return 0;
2732 }
2733 console_initcall(serial8250_console_init);
2734
2735 int serial8250_find_port(struct uart_port *p)
2736 {
2737 int line;
2738 struct uart_port *port;
2739
2740 for (line = 0; line < nr_uarts; line++) {
2741 port = &serial8250_ports[line].port;
2742 if (uart_match_port(p, port))
2743 return line;
2744 }
2745 return -ENODEV;
2746 }
2747
2748 #define SERIAL8250_CONSOLE &serial8250_console
2749 #else
2750 #define SERIAL8250_CONSOLE NULL
2751 #endif
2752
2753 static struct uart_driver serial8250_reg = {
2754 .owner = THIS_MODULE,
2755 .driver_name = "serial",
2756 .dev_name = "ttyS",
2757 .major = TTY_MAJOR,
2758 .minor = 64,
2759 .cons = SERIAL8250_CONSOLE,
2760 };
2761
2762 /*
2763 * early_serial_setup - early registration for 8250 ports
2764 *
2765 * Setup an 8250 port structure prior to console initialisation. Use
2766 * after console initialisation will cause undefined behaviour.
2767 */
2768 int __init early_serial_setup(struct uart_port *port)
2769 {
2770 if (port->line >= ARRAY_SIZE(serial8250_ports))
2771 return -ENODEV;
2772
2773 serial8250_isa_init_ports();
2774 serial8250_ports[port->line].port = *port;
2775 serial8250_ports[port->line].port.ops = &serial8250_pops;
2776 return 0;
2777 }
2778
2779 /**
2780 * serial8250_suspend_port - suspend one serial port
2781 * @line: serial line number
2782 *
2783 * Suspend one serial port.
2784 */
2785 void serial8250_suspend_port(int line)
2786 {
2787 uart_suspend_port(&serial8250_reg, &serial8250_ports[line].port);
2788 }
2789
2790 /**
2791 * serial8250_resume_port - resume one serial port
2792 * @line: serial line number
2793 *
2794 * Resume one serial port.
2795 */
2796 void serial8250_resume_port(int line)
2797 {
2798 struct uart_8250_port *up = &serial8250_ports[line];
2799
2800 if (up->capabilities & UART_NATSEMI) {
2801 unsigned char tmp;
2802
2803 /* Ensure it's still in high speed mode */
2804 serial_outp(up, UART_LCR, 0xE0);
2805
2806 tmp = serial_in(up, 0x04); /* EXCR2 */
2807 tmp &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
2808 tmp |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
2809 serial_outp(up, 0x04, tmp);
2810
2811 serial_outp(up, UART_LCR, 0);
2812 }
2813 uart_resume_port(&serial8250_reg, &up->port);
2814 }
2815
2816 /*
2817 * Register a set of serial devices attached to a platform device. The
2818 * list is terminated with a zero flags entry, which means we expect
2819 * all entries to have at least UPF_BOOT_AUTOCONF set.
2820 */
2821 static int __devinit serial8250_probe(struct platform_device *dev)
2822 {
2823 struct plat_serial8250_port *p = dev->dev.platform_data;
2824 struct uart_port port;
2825 int ret, i;
2826
2827 memset(&port, 0, sizeof(struct uart_port));
2828
2829 for (i = 0; p && p->flags != 0; p++, i++) {
2830 port.iobase = p->iobase;
2831 port.membase = p->membase;
2832 port.irq = p->irq;
2833 port.uartclk = p->uartclk;
2834 port.regshift = p->regshift;
2835 port.iotype = p->iotype;
2836 port.flags = p->flags;
2837 port.mapbase = p->mapbase;
2838 port.hub6 = p->hub6;
2839 port.private_data = p->private_data;
2840 port.dev = &dev->dev;
2841 if (share_irqs)
2842 port.flags |= UPF_SHARE_IRQ;
2843 ret = serial8250_register_port(&port);
2844 if (ret < 0) {
2845 dev_err(&dev->dev, "unable to register port at index %d "
2846 "(IO%lx MEM%llx IRQ%d): %d\n", i,
2847 p->iobase, (unsigned long long)p->mapbase,
2848 p->irq, ret);
2849 }
2850 }
2851 return 0;
2852 }
2853
2854 /*
2855 * Remove serial ports registered against a platform device.
2856 */
2857 static int __devexit serial8250_remove(struct platform_device *dev)
2858 {
2859 int i;
2860
2861 for (i = 0; i < nr_uarts; i++) {
2862 struct uart_8250_port *up = &serial8250_ports[i];
2863
2864 if (up->port.dev == &dev->dev)
2865 serial8250_unregister_port(i);
2866 }
2867 return 0;
2868 }
2869
2870 static int serial8250_suspend(struct platform_device *dev, pm_message_t state)
2871 {
2872 int i;
2873
2874 for (i = 0; i < UART_NR; i++) {
2875 struct uart_8250_port *up = &serial8250_ports[i];
2876
2877 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
2878 uart_suspend_port(&serial8250_reg, &up->port);
2879 }
2880
2881 return 0;
2882 }
2883
2884 static int serial8250_resume(struct platform_device *dev)
2885 {
2886 int i;
2887
2888 for (i = 0; i < UART_NR; i++) {
2889 struct uart_8250_port *up = &serial8250_ports[i];
2890
2891 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
2892 serial8250_resume_port(i);
2893 }
2894
2895 return 0;
2896 }
2897
2898 static struct platform_driver serial8250_isa_driver = {
2899 .probe = serial8250_probe,
2900 .remove = __devexit_p(serial8250_remove),
2901 .suspend = serial8250_suspend,
2902 .resume = serial8250_resume,
2903 .driver = {
2904 .name = "serial8250",
2905 .owner = THIS_MODULE,
2906 },
2907 };
2908
2909 /*
2910 * This "device" covers _all_ ISA 8250-compatible serial devices listed
2911 * in the table in include/asm/serial.h
2912 */
2913 static struct platform_device *serial8250_isa_devs;
2914
2915 /*
2916 * serial8250_register_port and serial8250_unregister_port allows for
2917 * 16x50 serial ports to be configured at run-time, to support PCMCIA
2918 * modems and PCI multiport cards.
2919 */
2920 static DEFINE_MUTEX(serial_mutex);
2921
2922 static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *port)
2923 {
2924 int i;
2925
2926 /*
2927 * First, find a port entry which matches.
2928 */
2929 for (i = 0; i < nr_uarts; i++)
2930 if (uart_match_port(&serial8250_ports[i].port, port))
2931 return &serial8250_ports[i];
2932
2933 /*
2934 * We didn't find a matching entry, so look for the first
2935 * free entry. We look for one which hasn't been previously
2936 * used (indicated by zero iobase).
2937 */
2938 for (i = 0; i < nr_uarts; i++)
2939 if (serial8250_ports[i].port.type == PORT_UNKNOWN &&
2940 serial8250_ports[i].port.iobase == 0)
2941 return &serial8250_ports[i];
2942
2943 /*
2944 * That also failed. Last resort is to find any entry which
2945 * doesn't have a real port associated with it.
2946 */
2947 for (i = 0; i < nr_uarts; i++)
2948 if (serial8250_ports[i].port.type == PORT_UNKNOWN)
2949 return &serial8250_ports[i];
2950
2951 return NULL;
2952 }
2953
2954 /**
2955 * serial8250_register_port - register a serial port
2956 * @port: serial port template
2957 *
2958 * Configure the serial port specified by the request. If the
2959 * port exists and is in use, it is hung up and unregistered
2960 * first.
2961 *
2962 * The port is then probed and if necessary the IRQ is autodetected
2963 * If this fails an error is returned.
2964 *
2965 * On success the port is ready to use and the line number is returned.
2966 */
2967 int serial8250_register_port(struct uart_port *port)
2968 {
2969 struct uart_8250_port *uart;
2970 int ret = -ENOSPC;
2971
2972 if (port->uartclk == 0)
2973 return -EINVAL;
2974
2975 mutex_lock(&serial_mutex);
2976
2977 uart = serial8250_find_match_or_unused(port);
2978 if (uart) {
2979 uart_remove_one_port(&serial8250_reg, &uart->port);
2980
2981 uart->port.iobase = port->iobase;
2982 uart->port.membase = port->membase;
2983 uart->port.irq = port->irq;
2984 uart->port.uartclk = port->uartclk;
2985 uart->port.fifosize = port->fifosize;
2986 uart->port.regshift = port->regshift;
2987 uart->port.iotype = port->iotype;
2988 uart->port.flags = port->flags | UPF_BOOT_AUTOCONF;
2989 uart->port.mapbase = port->mapbase;
2990 uart->port.private_data = port->private_data;
2991 if (port->dev)
2992 uart->port.dev = port->dev;
2993
2994 ret = uart_add_one_port(&serial8250_reg, &uart->port);
2995 if (ret == 0)
2996 ret = uart->port.line;
2997 }
2998 mutex_unlock(&serial_mutex);
2999
3000 return ret;
3001 }
3002 EXPORT_SYMBOL(serial8250_register_port);
3003
3004 /**
3005 * serial8250_unregister_port - remove a 16x50 serial port at runtime
3006 * @line: serial line number
3007 *
3008 * Remove one serial port. This may not be called from interrupt
3009 * context. We hand the port back to the our control.
3010 */
3011 void serial8250_unregister_port(int line)
3012 {
3013 struct uart_8250_port *uart = &serial8250_ports[line];
3014
3015 mutex_lock(&serial_mutex);
3016 uart_remove_one_port(&serial8250_reg, &uart->port);
3017 if (serial8250_isa_devs) {
3018 uart->port.flags &= ~UPF_BOOT_AUTOCONF;
3019 uart->port.type = PORT_UNKNOWN;
3020 uart->port.dev = &serial8250_isa_devs->dev;
3021 uart_add_one_port(&serial8250_reg, &uart->port);
3022 } else {
3023 uart->port.dev = NULL;
3024 }
3025 mutex_unlock(&serial_mutex);
3026 }
3027 EXPORT_SYMBOL(serial8250_unregister_port);
3028
3029 static int __init serial8250_init(void)
3030 {
3031 int ret;
3032
3033 if (nr_uarts > UART_NR)
3034 nr_uarts = UART_NR;
3035
3036 printk(KERN_INFO "Serial: 8250/16550 driver"
3037 "%d ports, IRQ sharing %sabled\n", nr_uarts,
3038 share_irqs ? "en" : "dis");
3039
3040 #ifdef CONFIG_SPARC
3041 ret = sunserial_register_minors(&serial8250_reg, UART_NR);
3042 #else
3043 serial8250_reg.nr = UART_NR;
3044 ret = uart_register_driver(&serial8250_reg);
3045 #endif
3046 if (ret)
3047 goto out;
3048
3049 serial8250_isa_devs = platform_device_alloc("serial8250",
3050 PLAT8250_DEV_LEGACY);
3051 if (!serial8250_isa_devs) {
3052 ret = -ENOMEM;
3053 goto unreg_uart_drv;
3054 }
3055
3056 ret = platform_device_add(serial8250_isa_devs);
3057 if (ret)
3058 goto put_dev;
3059
3060 serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev);
3061
3062 ret = platform_driver_register(&serial8250_isa_driver);
3063 if (ret == 0)
3064 goto out;
3065
3066 platform_device_del(serial8250_isa_devs);
3067 put_dev:
3068 platform_device_put(serial8250_isa_devs);
3069 unreg_uart_drv:
3070 #ifdef CONFIG_SPARC
3071 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3072 #else
3073 uart_unregister_driver(&serial8250_reg);
3074 #endif
3075 out:
3076 return ret;
3077 }
3078
3079 static void __exit serial8250_exit(void)
3080 {
3081 struct platform_device *isa_dev = serial8250_isa_devs;
3082
3083 /*
3084 * This tells serial8250_unregister_port() not to re-register
3085 * the ports (thereby making serial8250_isa_driver permanently
3086 * in use.)
3087 */
3088 serial8250_isa_devs = NULL;
3089
3090 platform_driver_unregister(&serial8250_isa_driver);
3091 platform_device_unregister(isa_dev);
3092
3093 #ifdef CONFIG_SPARC
3094 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3095 #else
3096 uart_unregister_driver(&serial8250_reg);
3097 #endif
3098 }
3099
3100 module_init(serial8250_init);
3101 module_exit(serial8250_exit);
3102
3103 EXPORT_SYMBOL(serial8250_suspend_port);
3104 EXPORT_SYMBOL(serial8250_resume_port);
3105
3106 MODULE_LICENSE("GPL");
3107 MODULE_DESCRIPTION("Generic 8250/16x50 serial driver");
3108
3109 module_param(share_irqs, uint, 0644);
3110 MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices"
3111 " (unsafe)");
3112
3113 module_param(nr_uarts, uint, 0644);
3114 MODULE_PARM_DESC(nr_uarts, "Maximum number of UARTs supported. (1-" __MODULE_STRING(CONFIG_SERIAL_8250_NR_UARTS) ")");
3115
3116 #ifdef CONFIG_SERIAL_8250_RSA
3117 module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444);
3118 MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA");
3119 #endif
3120 MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree