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ath9k: do btcoex ASPM disabling at initialization time
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / wireless / ath / ath9k / hw.c
blob875faf6894aeb64469f3bb9d489bbf9ad5850e53
1 /*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/io.h>
18 #include <linux/slab.h>
19 #include <asm/unaligned.h>
20
21 #include "hw.h"
22 #include "hw-ops.h"
23 #include "rc.h"
24 #include "ar9003_mac.h"
25
26 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
27
28 MODULE_AUTHOR("Atheros Communications");
29 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
30 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
31 MODULE_LICENSE("Dual BSD/GPL");
32
33 static int __init ath9k_init(void)
34 {
35 return 0;
36 }
37 module_init(ath9k_init);
38
39 static void __exit ath9k_exit(void)
40 {
41 return;
42 }
43 module_exit(ath9k_exit);
44
45 /* Private hardware callbacks */
46
47 static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
48 {
49 ath9k_hw_private_ops(ah)->init_cal_settings(ah);
50 }
51
52 static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
53 {
54 ath9k_hw_private_ops(ah)->init_mode_regs(ah);
55 }
56
57 static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah,
58 struct ath9k_channel *chan)
59 {
60 return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan);
61 }
62
63 static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
64 {
65 if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs)
66 return;
67
68 ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah);
69 }
70
71 static void ath9k_hw_ani_cache_ini_regs(struct ath_hw *ah)
72 {
73 /* You will not have this callback if using the old ANI */
74 if (!ath9k_hw_private_ops(ah)->ani_cache_ini_regs)
75 return;
76
77 ath9k_hw_private_ops(ah)->ani_cache_ini_regs(ah);
78 }
79
80 /********************/
81 /* Helper Functions */
82 /********************/
83
84 static void ath9k_hw_set_clockrate(struct ath_hw *ah)
85 {
86 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
87 struct ath_common *common = ath9k_hw_common(ah);
88 unsigned int clockrate;
89
90 /* AR9287 v1.3+ uses async FIFO and runs the MAC at 117 MHz */
91 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah))
92 clockrate = 117;
93 else if (!ah->curchan) /* should really check for CCK instead */
94 clockrate = ATH9K_CLOCK_RATE_CCK;
95 else if (conf->channel->band == IEEE80211_BAND_2GHZ)
96 clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM;
97 else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)
98 clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM;
99 else
100 clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM;
101
102 if (conf_is_ht40(conf))
103 clockrate *= 2;
104
105 if (ah->curchan) {
106 if (IS_CHAN_HALF_RATE(ah->curchan))
107 clockrate /= 2;
108 if (IS_CHAN_QUARTER_RATE(ah->curchan))
109 clockrate /= 4;
110 }
111
112 common->clockrate = clockrate;
113 }
114
115 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
116 {
117 struct ath_common *common = ath9k_hw_common(ah);
118
119 return usecs * common->clockrate;
120 }
121
122 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
123 {
124 int i;
125
126 BUG_ON(timeout < AH_TIME_QUANTUM);
127
128 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
129 if ((REG_READ(ah, reg) & mask) == val)
130 return true;
131
132 udelay(AH_TIME_QUANTUM);
133 }
134
135 ath_dbg(ath9k_hw_common(ah), ATH_DBG_ANY,
136 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
137 timeout, reg, REG_READ(ah, reg), mask, val);
138
139 return false;
140 }
141 EXPORT_SYMBOL(ath9k_hw_wait);
142
143 void ath9k_hw_write_array(struct ath_hw *ah, struct ar5416IniArray *array,
144 int column, unsigned int *writecnt)
145 {
146 int r;
147
148 ENABLE_REGWRITE_BUFFER(ah);
149 for (r = 0; r < array->ia_rows; r++) {
150 REG_WRITE(ah, INI_RA(array, r, 0),
151 INI_RA(array, r, column));
152 DO_DELAY(*writecnt);
153 }
154 REGWRITE_BUFFER_FLUSH(ah);
155 }
156
157 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
158 {
159 u32 retval;
160 int i;
161
162 for (i = 0, retval = 0; i < n; i++) {
163 retval = (retval << 1) | (val & 1);
164 val >>= 1;
165 }
166 return retval;
167 }
168
169 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
170 u8 phy, int kbps,
171 u32 frameLen, u16 rateix,
172 bool shortPreamble)
173 {
174 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
175
176 if (kbps == 0)
177 return 0;
178
179 switch (phy) {
180 case WLAN_RC_PHY_CCK:
181 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
182 if (shortPreamble)
183 phyTime >>= 1;
184 numBits = frameLen << 3;
185 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
186 break;
187 case WLAN_RC_PHY_OFDM:
188 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
189 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
190 numBits = OFDM_PLCP_BITS + (frameLen << 3);
191 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
192 txTime = OFDM_SIFS_TIME_QUARTER
193 + OFDM_PREAMBLE_TIME_QUARTER
194 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
195 } else if (ah->curchan &&
196 IS_CHAN_HALF_RATE(ah->curchan)) {
197 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
198 numBits = OFDM_PLCP_BITS + (frameLen << 3);
199 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
200 txTime = OFDM_SIFS_TIME_HALF +
201 OFDM_PREAMBLE_TIME_HALF
202 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
203 } else {
204 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
205 numBits = OFDM_PLCP_BITS + (frameLen << 3);
206 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
207 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
208 + (numSymbols * OFDM_SYMBOL_TIME);
209 }
210 break;
211 default:
212 ath_err(ath9k_hw_common(ah),
213 "Unknown phy %u (rate ix %u)\n", phy, rateix);
214 txTime = 0;
215 break;
216 }
217
218 return txTime;
219 }
220 EXPORT_SYMBOL(ath9k_hw_computetxtime);
221
222 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
223 struct ath9k_channel *chan,
224 struct chan_centers *centers)
225 {
226 int8_t extoff;
227
228 if (!IS_CHAN_HT40(chan)) {
229 centers->ctl_center = centers->ext_center =
230 centers->synth_center = chan->channel;
231 return;
232 }
233
234 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
235 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
236 centers->synth_center =
237 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
238 extoff = 1;
239 } else {
240 centers->synth_center =
241 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
242 extoff = -1;
243 }
244
245 centers->ctl_center =
246 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
247 /* 25 MHz spacing is supported by hw but not on upper layers */
248 centers->ext_center =
249 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
250 }
251
252 /******************/
253 /* Chip Revisions */
254 /******************/
255
256 static void ath9k_hw_read_revisions(struct ath_hw *ah)
257 {
258 u32 val;
259
260 switch (ah->hw_version.devid) {
261 case AR5416_AR9100_DEVID:
262 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
263 break;
264 case AR9300_DEVID_AR9330:
265 ah->hw_version.macVersion = AR_SREV_VERSION_9330;
266 if (ah->get_mac_revision) {
267 ah->hw_version.macRev = ah->get_mac_revision();
268 } else {
269 val = REG_READ(ah, AR_SREV);
270 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
271 }
272 return;
273 case AR9300_DEVID_AR9340:
274 ah->hw_version.macVersion = AR_SREV_VERSION_9340;
275 val = REG_READ(ah, AR_SREV);
276 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
277 return;
278 }
279
280 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
281
282 if (val == 0xFF) {
283 val = REG_READ(ah, AR_SREV);
284 ah->hw_version.macVersion =
285 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
286 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
287 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
288 } else {
289 if (!AR_SREV_9100(ah))
290 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
291
292 ah->hw_version.macRev = val & AR_SREV_REVISION;
293
294 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
295 ah->is_pciexpress = true;
296 }
297 }
298
299 /************************************/
300 /* HW Attach, Detach, Init Routines */
301 /************************************/
302
303 static void ath9k_hw_disablepcie(struct ath_hw *ah)
304 {
305 if (!AR_SREV_5416(ah))
306 return;
307
308 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
309 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
310 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
311 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
312 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
313 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
314 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
315 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
316 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
317
318 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
319 }
320
321 static void ath9k_hw_aspm_init(struct ath_hw *ah)
322 {
323 struct ath_common *common = ath9k_hw_common(ah);
324
325 if (common->bus_ops->aspm_init)
326 common->bus_ops->aspm_init(common);
327 }
328
329 /* This should work for all families including legacy */
330 static bool ath9k_hw_chip_test(struct ath_hw *ah)
331 {
332 struct ath_common *common = ath9k_hw_common(ah);
333 u32 regAddr[2] = { AR_STA_ID0 };
334 u32 regHold[2];
335 static const u32 patternData[4] = {
336 0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999
337 };
338 int i, j, loop_max;
339
340 if (!AR_SREV_9300_20_OR_LATER(ah)) {
341 loop_max = 2;
342 regAddr[1] = AR_PHY_BASE + (8 << 2);
343 } else
344 loop_max = 1;
345
346 for (i = 0; i < loop_max; i++) {
347 u32 addr = regAddr[i];
348 u32 wrData, rdData;
349
350 regHold[i] = REG_READ(ah, addr);
351 for (j = 0; j < 0x100; j++) {
352 wrData = (j << 16) | j;
353 REG_WRITE(ah, addr, wrData);
354 rdData = REG_READ(ah, addr);
355 if (rdData != wrData) {
356 ath_err(common,
357 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
358 addr, wrData, rdData);
359 return false;
360 }
361 }
362 for (j = 0; j < 4; j++) {
363 wrData = patternData[j];
364 REG_WRITE(ah, addr, wrData);
365 rdData = REG_READ(ah, addr);
366 if (wrData != rdData) {
367 ath_err(common,
368 "address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
369 addr, wrData, rdData);
370 return false;
371 }
372 }
373 REG_WRITE(ah, regAddr[i], regHold[i]);
374 }
375 udelay(100);
376
377 return true;
378 }
379
380 static void ath9k_hw_init_config(struct ath_hw *ah)
381 {
382 int i;
383
384 ah->config.dma_beacon_response_time = 2;
385 ah->config.sw_beacon_response_time = 10;
386 ah->config.additional_swba_backoff = 0;
387 ah->config.ack_6mb = 0x0;
388 ah->config.cwm_ignore_extcca = 0;
389 ah->config.pcie_clock_req = 0;
390 ah->config.pcie_waen = 0;
391 ah->config.analog_shiftreg = 1;
392 ah->config.enable_ani = true;
393
394 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
395 ah->config.spurchans[i][0] = AR_NO_SPUR;
396 ah->config.spurchans[i][1] = AR_NO_SPUR;
397 }
398
399 /* PAPRD needs some more work to be enabled */
400 ah->config.paprd_disable = 1;
401
402 ah->config.rx_intr_mitigation = true;
403 ah->config.pcieSerDesWrite = true;
404
405 /*
406 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
407 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
408 * This means we use it for all AR5416 devices, and the few
409 * minor PCI AR9280 devices out there.
410 *
411 * Serialization is required because these devices do not handle
412 * well the case of two concurrent reads/writes due to the latency
413 * involved. During one read/write another read/write can be issued
414 * on another CPU while the previous read/write may still be working
415 * on our hardware, if we hit this case the hardware poops in a loop.
416 * We prevent this by serializing reads and writes.
417 *
418 * This issue is not present on PCI-Express devices or pre-AR5416
419 * devices (legacy, 802.11abg).
420 */
421 if (num_possible_cpus() > 1)
422 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
423 }
424
425 static void ath9k_hw_init_defaults(struct ath_hw *ah)
426 {
427 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
428
429 regulatory->country_code = CTRY_DEFAULT;
430 regulatory->power_limit = MAX_RATE_POWER;
431 regulatory->tp_scale = ATH9K_TP_SCALE_MAX;
432
433 ah->hw_version.magic = AR5416_MAGIC;
434 ah->hw_version.subvendorid = 0;
435
436 ah->atim_window = 0;
437 ah->sta_id1_defaults =
438 AR_STA_ID1_CRPT_MIC_ENABLE |
439 AR_STA_ID1_MCAST_KSRCH;
440 if (AR_SREV_9100(ah))
441 ah->sta_id1_defaults |= AR_STA_ID1_AR9100_BA_FIX;
442 ah->enable_32kHz_clock = DONT_USE_32KHZ;
443 ah->slottime = 20;
444 ah->globaltxtimeout = (u32) -1;
445 ah->power_mode = ATH9K_PM_UNDEFINED;
446 }
447
448 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
449 {
450 struct ath_common *common = ath9k_hw_common(ah);
451 u32 sum;
452 int i;
453 u16 eeval;
454 static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
455
456 sum = 0;
457 for (i = 0; i < 3; i++) {
458 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]);
459 sum += eeval;
460 common->macaddr[2 * i] = eeval >> 8;
461 common->macaddr[2 * i + 1] = eeval & 0xff;
462 }
463 if (sum == 0 || sum == 0xffff * 3)
464 return -EADDRNOTAVAIL;
465
466 return 0;
467 }
468
469 static int ath9k_hw_post_init(struct ath_hw *ah)
470 {
471 struct ath_common *common = ath9k_hw_common(ah);
472 int ecode;
473
474 if (common->bus_ops->ath_bus_type != ATH_USB) {
475 if (!ath9k_hw_chip_test(ah))
476 return -ENODEV;
477 }
478
479 if (!AR_SREV_9300_20_OR_LATER(ah)) {
480 ecode = ar9002_hw_rf_claim(ah);
481 if (ecode != 0)
482 return ecode;
483 }
484
485 ecode = ath9k_hw_eeprom_init(ah);
486 if (ecode != 0)
487 return ecode;
488
489 ath_dbg(ath9k_hw_common(ah), ATH_DBG_CONFIG,
490 "Eeprom VER: %d, REV: %d\n",
491 ah->eep_ops->get_eeprom_ver(ah),
492 ah->eep_ops->get_eeprom_rev(ah));
493
494 ecode = ath9k_hw_rf_alloc_ext_banks(ah);
495 if (ecode) {
496 ath_err(ath9k_hw_common(ah),
497 "Failed allocating banks for external radio\n");
498 ath9k_hw_rf_free_ext_banks(ah);
499 return ecode;
500 }
501
502 if (!AR_SREV_9100(ah) && !AR_SREV_9340(ah)) {
503 ath9k_hw_ani_setup(ah);
504 ath9k_hw_ani_init(ah);
505 }
506
507 return 0;
508 }
509
510 static void ath9k_hw_attach_ops(struct ath_hw *ah)
511 {
512 if (AR_SREV_9300_20_OR_LATER(ah))
513 ar9003_hw_attach_ops(ah);
514 else
515 ar9002_hw_attach_ops(ah);
516 }
517
518 /* Called for all hardware families */
519 static int __ath9k_hw_init(struct ath_hw *ah)
520 {
521 struct ath_common *common = ath9k_hw_common(ah);
522 int r = 0;
523
524 ath9k_hw_read_revisions(ah);
525
526 /*
527 * Read back AR_WA into a permanent copy and set bits 14 and 17.
528 * We need to do this to avoid RMW of this register. We cannot
529 * read the reg when chip is asleep.
530 */
531 ah->WARegVal = REG_READ(ah, AR_WA);
532 ah->WARegVal |= (AR_WA_D3_L1_DISABLE |
533 AR_WA_ASPM_TIMER_BASED_DISABLE);
534
535 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
536 ath_err(common, "Couldn't reset chip\n");
537 return -EIO;
538 }
539
540 ath9k_hw_init_defaults(ah);
541 ath9k_hw_init_config(ah);
542
543 ath9k_hw_attach_ops(ah);
544
545 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
546 ath_err(common, "Couldn't wakeup chip\n");
547 return -EIO;
548 }
549
550 if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
551 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
552 ((AR_SREV_9160(ah) || AR_SREV_9280(ah)) &&
553 !ah->is_pciexpress)) {
554 ah->config.serialize_regmode =
555 SER_REG_MODE_ON;
556 } else {
557 ah->config.serialize_regmode =
558 SER_REG_MODE_OFF;
559 }
560 }
561
562 ath_dbg(common, ATH_DBG_RESET, "serialize_regmode is %d\n",
563 ah->config.serialize_regmode);
564
565 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
566 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
567 else
568 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
569
570 switch (ah->hw_version.macVersion) {
571 case AR_SREV_VERSION_5416_PCI:
572 case AR_SREV_VERSION_5416_PCIE:
573 case AR_SREV_VERSION_9160:
574 case AR_SREV_VERSION_9100:
575 case AR_SREV_VERSION_9280:
576 case AR_SREV_VERSION_9285:
577 case AR_SREV_VERSION_9287:
578 case AR_SREV_VERSION_9271:
579 case AR_SREV_VERSION_9300:
580 case AR_SREV_VERSION_9330:
581 case AR_SREV_VERSION_9485:
582 case AR_SREV_VERSION_9340:
583 break;
584 default:
585 ath_err(common,
586 "Mac Chip Rev 0x%02x.%x is not supported by this driver\n",
587 ah->hw_version.macVersion, ah->hw_version.macRev);
588 return -EOPNOTSUPP;
589 }
590
591 if (AR_SREV_9271(ah) || AR_SREV_9100(ah) || AR_SREV_9340(ah) ||
592 AR_SREV_9330(ah))
593 ah->is_pciexpress = false;
594
595 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
596 ath9k_hw_init_cal_settings(ah);
597
598 ah->ani_function = ATH9K_ANI_ALL;
599 if (AR_SREV_9280_20_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah))
600 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
601 if (!AR_SREV_9300_20_OR_LATER(ah))
602 ah->ani_function &= ~ATH9K_ANI_MRC_CCK;
603
604 ath9k_hw_init_mode_regs(ah);
605
606 if (!ah->is_pciexpress)
607 ath9k_hw_disablepcie(ah);
608
609 if (!AR_SREV_9300_20_OR_LATER(ah))
610 ar9002_hw_cck_chan14_spread(ah);
611
612 r = ath9k_hw_post_init(ah);
613 if (r)
614 return r;
615
616 ath9k_hw_init_mode_gain_regs(ah);
617 r = ath9k_hw_fill_cap_info(ah);
618 if (r)
619 return r;
620
621 if (ah->is_pciexpress)
622 ath9k_hw_aspm_init(ah);
623
624 r = ath9k_hw_init_macaddr(ah);
625 if (r) {
626 ath_err(common, "Failed to initialize MAC address\n");
627 return r;
628 }
629
630 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
631 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
632 else
633 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
634
635 if (AR_SREV_9330(ah))
636 ah->bb_watchdog_timeout_ms = 85;
637 else
638 ah->bb_watchdog_timeout_ms = 25;
639
640 common->state = ATH_HW_INITIALIZED;
641
642 return 0;
643 }
644
645 int ath9k_hw_init(struct ath_hw *ah)
646 {
647 int ret;
648 struct ath_common *common = ath9k_hw_common(ah);
649
650 /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */
651 switch (ah->hw_version.devid) {
652 case AR5416_DEVID_PCI:
653 case AR5416_DEVID_PCIE:
654 case AR5416_AR9100_DEVID:
655 case AR9160_DEVID_PCI:
656 case AR9280_DEVID_PCI:
657 case AR9280_DEVID_PCIE:
658 case AR9285_DEVID_PCIE:
659 case AR9287_DEVID_PCI:
660 case AR9287_DEVID_PCIE:
661 case AR2427_DEVID_PCIE:
662 case AR9300_DEVID_PCIE:
663 case AR9300_DEVID_AR9485_PCIE:
664 case AR9300_DEVID_AR9330:
665 case AR9300_DEVID_AR9340:
666 break;
667 default:
668 if (common->bus_ops->ath_bus_type == ATH_USB)
669 break;
670 ath_err(common, "Hardware device ID 0x%04x not supported\n",
671 ah->hw_version.devid);
672 return -EOPNOTSUPP;
673 }
674
675 ret = __ath9k_hw_init(ah);
676 if (ret) {
677 ath_err(common,
678 "Unable to initialize hardware; initialization status: %d\n",
679 ret);
680 return ret;
681 }
682
683 return 0;
684 }
685 EXPORT_SYMBOL(ath9k_hw_init);
686
687 static void ath9k_hw_init_qos(struct ath_hw *ah)
688 {
689 ENABLE_REGWRITE_BUFFER(ah);
690
691 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
692 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
693
694 REG_WRITE(ah, AR_QOS_NO_ACK,
695 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
696 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
697 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
698
699 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
700 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
701 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
702 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
703 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
704
705 REGWRITE_BUFFER_FLUSH(ah);
706 }
707
708 u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah)
709 {
710 REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
711 udelay(100);
712 REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
713
714 while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0)
715 udelay(100);
716
717 return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3;
718 }
719 EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc);
720
721 static void ath9k_hw_init_pll(struct ath_hw *ah,
722 struct ath9k_channel *chan)
723 {
724 u32 pll;
725
726 if (AR_SREV_9485(ah)) {
727
728 /* program BB PLL ki and kd value, ki=0x4, kd=0x40 */
729 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
730 AR_CH0_BB_DPLL2_PLL_PWD, 0x1);
731 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
732 AR_CH0_DPLL2_KD, 0x40);
733 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
734 AR_CH0_DPLL2_KI, 0x4);
735
736 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
737 AR_CH0_BB_DPLL1_REFDIV, 0x5);
738 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
739 AR_CH0_BB_DPLL1_NINI, 0x58);
740 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
741 AR_CH0_BB_DPLL1_NFRAC, 0x0);
742
743 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
744 AR_CH0_BB_DPLL2_OUTDIV, 0x1);
745 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
746 AR_CH0_BB_DPLL2_LOCAL_PLL, 0x1);
747 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
748 AR_CH0_BB_DPLL2_EN_NEGTRIG, 0x1);
749
750 /* program BB PLL phase_shift to 0x6 */
751 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
752 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x6);
753
754 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
755 AR_CH0_BB_DPLL2_PLL_PWD, 0x0);
756 udelay(1000);
757 } else if (AR_SREV_9330(ah)) {
758 u32 ddr_dpll2, pll_control2, kd;
759
760 if (ah->is_clk_25mhz) {
761 ddr_dpll2 = 0x18e82f01;
762 pll_control2 = 0xe04a3d;
763 kd = 0x1d;
764 } else {
765 ddr_dpll2 = 0x19e82f01;
766 pll_control2 = 0x886666;
767 kd = 0x3d;
768 }
769
770 /* program DDR PLL ki and kd value */
771 REG_WRITE(ah, AR_CH0_DDR_DPLL2, ddr_dpll2);
772
773 /* program DDR PLL phase_shift */
774 REG_RMW_FIELD(ah, AR_CH0_DDR_DPLL3,
775 AR_CH0_DPLL3_PHASE_SHIFT, 0x1);
776
777 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
778 udelay(1000);
779
780 /* program refdiv, nint, frac to RTC register */
781 REG_WRITE(ah, AR_RTC_PLL_CONTROL2, pll_control2);
782
783 /* program BB PLL kd and ki value */
784 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KD, kd);
785 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KI, 0x06);
786
787 /* program BB PLL phase_shift */
788 REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
789 AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x1);
790 } else if (AR_SREV_9340(ah)) {
791 u32 regval, pll2_divint, pll2_divfrac, refdiv;
792
793 REG_WRITE(ah, AR_RTC_PLL_CONTROL, 0x1142c);
794 udelay(1000);
795
796 REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16);
797 udelay(100);
798
799 if (ah->is_clk_25mhz) {
800 pll2_divint = 0x54;
801 pll2_divfrac = 0x1eb85;
802 refdiv = 3;
803 } else {
804 pll2_divint = 88;
805 pll2_divfrac = 0;
806 refdiv = 5;
807 }
808
809 regval = REG_READ(ah, AR_PHY_PLL_MODE);
810 regval |= (0x1 << 16);
811 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
812 udelay(100);
813
814 REG_WRITE(ah, AR_PHY_PLL_CONTROL, (refdiv << 27) |
815 (pll2_divint << 18) | pll2_divfrac);
816 udelay(100);
817
818 regval = REG_READ(ah, AR_PHY_PLL_MODE);
819 regval = (regval & 0x80071fff) | (0x1 << 30) | (0x1 << 13) |
820 (0x4 << 26) | (0x18 << 19);
821 REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
822 REG_WRITE(ah, AR_PHY_PLL_MODE,
823 REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff);
824 udelay(1000);
825 }
826
827 pll = ath9k_hw_compute_pll_control(ah, chan);
828
829 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
830
831 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah))
832 udelay(1000);
833
834 /* Switch the core clock for ar9271 to 117Mhz */
835 if (AR_SREV_9271(ah)) {
836 udelay(500);
837 REG_WRITE(ah, 0x50040, 0x304);
838 }
839
840 udelay(RTC_PLL_SETTLE_DELAY);
841
842 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
843
844 if (AR_SREV_9340(ah)) {
845 if (ah->is_clk_25mhz) {
846 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x17c << 1);
847 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7);
848 REG_WRITE(ah, AR_SLP32_INC, 0x0001e7ae);
849 } else {
850 REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x261 << 1);
851 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400);
852 REG_WRITE(ah, AR_SLP32_INC, 0x0001e800);
853 }
854 udelay(100);
855 }
856 }
857
858 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
859 enum nl80211_iftype opmode)
860 {
861 u32 sync_default = AR_INTR_SYNC_DEFAULT;
862 u32 imr_reg = AR_IMR_TXERR |
863 AR_IMR_TXURN |
864 AR_IMR_RXERR |
865 AR_IMR_RXORN |
866 AR_IMR_BCNMISC;
867
868 if (AR_SREV_9340(ah))
869 sync_default &= ~AR_INTR_SYNC_HOST1_FATAL;
870
871 if (AR_SREV_9300_20_OR_LATER(ah)) {
872 imr_reg |= AR_IMR_RXOK_HP;
873 if (ah->config.rx_intr_mitigation)
874 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
875 else
876 imr_reg |= AR_IMR_RXOK_LP;
877
878 } else {
879 if (ah->config.rx_intr_mitigation)
880 imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
881 else
882 imr_reg |= AR_IMR_RXOK;
883 }
884
885 if (ah->config.tx_intr_mitigation)
886 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR;
887 else
888 imr_reg |= AR_IMR_TXOK;
889
890 if (opmode == NL80211_IFTYPE_AP)
891 imr_reg |= AR_IMR_MIB;
892
893 ENABLE_REGWRITE_BUFFER(ah);
894
895 REG_WRITE(ah, AR_IMR, imr_reg);
896 ah->imrs2_reg |= AR_IMR_S2_GTT;
897 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
898
899 if (!AR_SREV_9100(ah)) {
900 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
901 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default);
902 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
903 }
904
905 REGWRITE_BUFFER_FLUSH(ah);
906
907 if (AR_SREV_9300_20_OR_LATER(ah)) {
908 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0);
909 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0);
910 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0);
911 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0);
912 }
913 }
914
915 static void ath9k_hw_set_sifs_time(struct ath_hw *ah, u32 us)
916 {
917 u32 val = ath9k_hw_mac_to_clks(ah, us - 2);
918 val = min(val, (u32) 0xFFFF);
919 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, val);
920 }
921
922 static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
923 {
924 u32 val = ath9k_hw_mac_to_clks(ah, us);
925 val = min(val, (u32) 0xFFFF);
926 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
927 }
928
929 static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
930 {
931 u32 val = ath9k_hw_mac_to_clks(ah, us);
932 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
933 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
934 }
935
936 static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
937 {
938 u32 val = ath9k_hw_mac_to_clks(ah, us);
939 val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
940 REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
941 }
942
943 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
944 {
945 if (tu > 0xFFFF) {
946 ath_dbg(ath9k_hw_common(ah), ATH_DBG_XMIT,
947 "bad global tx timeout %u\n", tu);
948 ah->globaltxtimeout = (u32) -1;
949 return false;
950 } else {
951 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
952 ah->globaltxtimeout = tu;
953 return true;
954 }
955 }
956
957 void ath9k_hw_init_global_settings(struct ath_hw *ah)
958 {
959 struct ath_common *common = ath9k_hw_common(ah);
960 struct ieee80211_conf *conf = &common->hw->conf;
961 const struct ath9k_channel *chan = ah->curchan;
962 int acktimeout;
963 int slottime;
964 int sifstime;
965 int rx_lat = 0, tx_lat = 0, eifs = 0;
966 u32 reg;
967
968 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
969 ah->misc_mode);
970
971 if (!chan)
972 return;
973
974 if (ah->misc_mode != 0)
975 REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode);
976
977 rx_lat = 37;
978 tx_lat = 54;
979
980 if (IS_CHAN_HALF_RATE(chan)) {
981 eifs = 175;
982 rx_lat *= 2;
983 tx_lat *= 2;
984 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
985 tx_lat += 11;
986
987 slottime = 13;
988 sifstime = 32;
989 } else if (IS_CHAN_QUARTER_RATE(chan)) {
990 eifs = 340;
991 rx_lat *= 4;
992 tx_lat *= 4;
993 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
994 tx_lat += 22;
995
996 slottime = 21;
997 sifstime = 64;
998 } else {
999 eifs = REG_READ(ah, AR_D_GBL_IFS_EIFS);
1000 reg = REG_READ(ah, AR_USEC);
1001 rx_lat = MS(reg, AR_USEC_RX_LAT);
1002 tx_lat = MS(reg, AR_USEC_TX_LAT);
1003
1004 slottime = ah->slottime;
1005 if (IS_CHAN_5GHZ(chan))
1006 sifstime = 16;
1007 else
1008 sifstime = 10;
1009 }
1010
1011 /* As defined by IEEE 802.11-2007 17.3.8.6 */
1012 acktimeout = slottime + sifstime + 3 * ah->coverage_class;
1013
1014 /*
1015 * Workaround for early ACK timeouts, add an offset to match the
1016 * initval's 64us ack timeout value.
1017 * This was initially only meant to work around an issue with delayed
1018 * BA frames in some implementations, but it has been found to fix ACK
1019 * timeout issues in other cases as well.
1020 */
1021 if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ)
1022 acktimeout += 64 - sifstime - ah->slottime;
1023
1024 ath9k_hw_set_sifs_time(ah, sifstime);
1025 ath9k_hw_setslottime(ah, slottime);
1026 ath9k_hw_set_ack_timeout(ah, acktimeout);
1027 ath9k_hw_set_cts_timeout(ah, acktimeout);
1028 if (ah->globaltxtimeout != (u32) -1)
1029 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
1030
1031 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, ath9k_hw_mac_to_clks(ah, eifs));
1032 REG_RMW(ah, AR_USEC,
1033 (common->clockrate - 1) |
1034 SM(rx_lat, AR_USEC_RX_LAT) |
1035 SM(tx_lat, AR_USEC_TX_LAT),
1036 AR_USEC_TX_LAT | AR_USEC_RX_LAT | AR_USEC_USEC);
1037
1038 }
1039 EXPORT_SYMBOL(ath9k_hw_init_global_settings);
1040
1041 void ath9k_hw_deinit(struct ath_hw *ah)
1042 {
1043 struct ath_common *common = ath9k_hw_common(ah);
1044
1045 if (common->state < ATH_HW_INITIALIZED)
1046 goto free_hw;
1047
1048 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1049
1050 free_hw:
1051 ath9k_hw_rf_free_ext_banks(ah);
1052 }
1053 EXPORT_SYMBOL(ath9k_hw_deinit);
1054
1055 /*******/
1056 /* INI */
1057 /*******/
1058
1059 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
1060 {
1061 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1062
1063 if (IS_CHAN_B(chan))
1064 ctl |= CTL_11B;
1065 else if (IS_CHAN_G(chan))
1066 ctl |= CTL_11G;
1067 else
1068 ctl |= CTL_11A;
1069
1070 return ctl;
1071 }
1072
1073 /****************************************/
1074 /* Reset and Channel Switching Routines */
1075 /****************************************/
1076
1077 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
1078 {
1079 struct ath_common *common = ath9k_hw_common(ah);
1080
1081 ENABLE_REGWRITE_BUFFER(ah);
1082
1083 /*
1084 * set AHB_MODE not to do cacheline prefetches
1085 */
1086 if (!AR_SREV_9300_20_OR_LATER(ah))
1087 REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN);
1088
1089 /*
1090 * let mac dma reads be in 128 byte chunks
1091 */
1092 REG_RMW(ah, AR_TXCFG, AR_TXCFG_DMASZ_128B, AR_TXCFG_DMASZ_MASK);
1093
1094 REGWRITE_BUFFER_FLUSH(ah);
1095
1096 /*
1097 * Restore TX Trigger Level to its pre-reset value.
1098 * The initial value depends on whether aggregation is enabled, and is
1099 * adjusted whenever underruns are detected.
1100 */
1101 if (!AR_SREV_9300_20_OR_LATER(ah))
1102 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
1103
1104 ENABLE_REGWRITE_BUFFER(ah);
1105
1106 /*
1107 * let mac dma writes be in 128 byte chunks
1108 */
1109 REG_RMW(ah, AR_RXCFG, AR_RXCFG_DMASZ_128B, AR_RXCFG_DMASZ_MASK);
1110
1111 /*
1112 * Setup receive FIFO threshold to hold off TX activities
1113 */
1114 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1115
1116 if (AR_SREV_9300_20_OR_LATER(ah)) {
1117 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1);
1118 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1);
1119
1120 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
1121 ah->caps.rx_status_len);
1122 }
1123
1124 /*
1125 * reduce the number of usable entries in PCU TXBUF to avoid
1126 * wrap around issues.
1127 */
1128 if (AR_SREV_9285(ah)) {
1129 /* For AR9285 the number of Fifos are reduced to half.
1130 * So set the usable tx buf size also to half to
1131 * avoid data/delimiter underruns
1132 */
1133 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1134 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
1135 } else if (!AR_SREV_9271(ah)) {
1136 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1137 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1138 }
1139
1140 REGWRITE_BUFFER_FLUSH(ah);
1141
1142 if (AR_SREV_9300_20_OR_LATER(ah))
1143 ath9k_hw_reset_txstatus_ring(ah);
1144 }
1145
1146 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
1147 {
1148 u32 mask = AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC;
1149 u32 set = AR_STA_ID1_KSRCH_MODE;
1150
1151 switch (opmode) {
1152 case NL80211_IFTYPE_ADHOC:
1153 case NL80211_IFTYPE_MESH_POINT:
1154 set |= AR_STA_ID1_ADHOC;
1155 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1156 break;
1157 case NL80211_IFTYPE_AP:
1158 set |= AR_STA_ID1_STA_AP;
1159 /* fall through */
1160 case NL80211_IFTYPE_STATION:
1161 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1162 break;
1163 default:
1164 if (!ah->is_monitoring)
1165 set = 0;
1166 break;
1167 }
1168 REG_RMW(ah, AR_STA_ID1, set, mask);
1169 }
1170
1171 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
1172 u32 *coef_mantissa, u32 *coef_exponent)
1173 {
1174 u32 coef_exp, coef_man;
1175
1176 for (coef_exp = 31; coef_exp > 0; coef_exp--)
1177 if ((coef_scaled >> coef_exp) & 0x1)
1178 break;
1179
1180 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1181
1182 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1183
1184 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1185 *coef_exponent = coef_exp - 16;
1186 }
1187
1188 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1189 {
1190 u32 rst_flags;
1191 u32 tmpReg;
1192
1193 if (AR_SREV_9100(ah)) {
1194 REG_RMW_FIELD(ah, AR_RTC_DERIVED_CLK,
1195 AR_RTC_DERIVED_CLK_PERIOD, 1);
1196 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1197 }
1198
1199 ENABLE_REGWRITE_BUFFER(ah);
1200
1201 if (AR_SREV_9300_20_OR_LATER(ah)) {
1202 REG_WRITE(ah, AR_WA, ah->WARegVal);
1203 udelay(10);
1204 }
1205
1206 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1207 AR_RTC_FORCE_WAKE_ON_INT);
1208
1209 if (AR_SREV_9100(ah)) {
1210 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1211 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1212 } else {
1213 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1214 if (tmpReg &
1215 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1216 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1217 u32 val;
1218 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1219
1220 val = AR_RC_HOSTIF;
1221 if (!AR_SREV_9300_20_OR_LATER(ah))
1222 val |= AR_RC_AHB;
1223 REG_WRITE(ah, AR_RC, val);
1224
1225 } else if (!AR_SREV_9300_20_OR_LATER(ah))
1226 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1227
1228 rst_flags = AR_RTC_RC_MAC_WARM;
1229 if (type == ATH9K_RESET_COLD)
1230 rst_flags |= AR_RTC_RC_MAC_COLD;
1231 }
1232
1233 if (AR_SREV_9330(ah)) {
1234 int npend = 0;
1235 int i;
1236
1237 /* AR9330 WAR:
1238 * call external reset function to reset WMAC if:
1239 * - doing a cold reset
1240 * - we have pending frames in the TX queues
1241 */
1242
1243 for (i = 0; i < AR_NUM_QCU; i++) {
1244 npend = ath9k_hw_numtxpending(ah, i);
1245 if (npend)
1246 break;
1247 }
1248
1249 if (ah->external_reset &&
1250 (npend || type == ATH9K_RESET_COLD)) {
1251 int reset_err = 0;
1252
1253 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET,
1254 "reset MAC via external reset\n");
1255
1256 reset_err = ah->external_reset();
1257 if (reset_err) {
1258 ath_err(ath9k_hw_common(ah),
1259 "External reset failed, err=%d\n",
1260 reset_err);
1261 return false;
1262 }
1263
1264 REG_WRITE(ah, AR_RTC_RESET, 1);
1265 }
1266 }
1267
1268 REG_WRITE(ah, AR_RTC_RC, rst_flags);
1269
1270 REGWRITE_BUFFER_FLUSH(ah);
1271
1272 udelay(50);
1273
1274 REG_WRITE(ah, AR_RTC_RC, 0);
1275 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1276 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET,
1277 "RTC stuck in MAC reset\n");
1278 return false;
1279 }
1280
1281 if (!AR_SREV_9100(ah))
1282 REG_WRITE(ah, AR_RC, 0);
1283
1284 if (AR_SREV_9100(ah))
1285 udelay(50);
1286
1287 return true;
1288 }
1289
1290 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1291 {
1292 ENABLE_REGWRITE_BUFFER(ah);
1293
1294 if (AR_SREV_9300_20_OR_LATER(ah)) {
1295 REG_WRITE(ah, AR_WA, ah->WARegVal);
1296 udelay(10);
1297 }
1298
1299 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1300 AR_RTC_FORCE_WAKE_ON_INT);
1301
1302 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1303 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1304
1305 REG_WRITE(ah, AR_RTC_RESET, 0);
1306
1307 REGWRITE_BUFFER_FLUSH(ah);
1308
1309 if (!AR_SREV_9300_20_OR_LATER(ah))
1310 udelay(2);
1311
1312 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1313 REG_WRITE(ah, AR_RC, 0);
1314
1315 REG_WRITE(ah, AR_RTC_RESET, 1);
1316
1317 if (!ath9k_hw_wait(ah,
1318 AR_RTC_STATUS,
1319 AR_RTC_STATUS_M,
1320 AR_RTC_STATUS_ON,
1321 AH_WAIT_TIMEOUT)) {
1322 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET,
1323 "RTC not waking up\n");
1324 return false;
1325 }
1326
1327 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1328 }
1329
1330 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1331 {
1332 if (AR_SREV_9300_20_OR_LATER(ah)) {
1333 REG_WRITE(ah, AR_WA, ah->WARegVal);
1334 udelay(10);
1335 }
1336
1337 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1338 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1339
1340 switch (type) {
1341 case ATH9K_RESET_POWER_ON:
1342 return ath9k_hw_set_reset_power_on(ah);
1343 case ATH9K_RESET_WARM:
1344 case ATH9K_RESET_COLD:
1345 return ath9k_hw_set_reset(ah, type);
1346 default:
1347 return false;
1348 }
1349 }
1350
1351 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1352 struct ath9k_channel *chan)
1353 {
1354 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) {
1355 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1356 return false;
1357 } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1358 return false;
1359
1360 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1361 return false;
1362
1363 ah->chip_fullsleep = false;
1364 ath9k_hw_init_pll(ah, chan);
1365 ath9k_hw_set_rfmode(ah, chan);
1366
1367 return true;
1368 }
1369
1370 static bool ath9k_hw_channel_change(struct ath_hw *ah,
1371 struct ath9k_channel *chan)
1372 {
1373 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1374 struct ath_common *common = ath9k_hw_common(ah);
1375 struct ieee80211_channel *channel = chan->chan;
1376 u32 qnum;
1377 int r;
1378
1379 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1380 if (ath9k_hw_numtxpending(ah, qnum)) {
1381 ath_dbg(common, ATH_DBG_QUEUE,
1382 "Transmit frames pending on queue %d\n", qnum);
1383 return false;
1384 }
1385 }
1386
1387 if (!ath9k_hw_rfbus_req(ah)) {
1388 ath_err(common, "Could not kill baseband RX\n");
1389 return false;
1390 }
1391
1392 ath9k_hw_set_channel_regs(ah, chan);
1393
1394 r = ath9k_hw_rf_set_freq(ah, chan);
1395 if (r) {
1396 ath_err(common, "Failed to set channel\n");
1397 return false;
1398 }
1399 ath9k_hw_set_clockrate(ah);
1400
1401 ah->eep_ops->set_txpower(ah, chan,
1402 ath9k_regd_get_ctl(regulatory, chan),
1403 channel->max_antenna_gain * 2,
1404 channel->max_power * 2,
1405 min((u32) MAX_RATE_POWER,
1406 (u32) regulatory->power_limit), false);
1407
1408 ath9k_hw_rfbus_done(ah);
1409
1410 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1411 ath9k_hw_set_delta_slope(ah, chan);
1412
1413 ath9k_hw_spur_mitigate_freq(ah, chan);
1414
1415 return true;
1416 }
1417
1418 static void ath9k_hw_apply_gpio_override(struct ath_hw *ah)
1419 {
1420 u32 gpio_mask = ah->gpio_mask;
1421 int i;
1422
1423 for (i = 0; gpio_mask; i++, gpio_mask >>= 1) {
1424 if (!(gpio_mask & 1))
1425 continue;
1426
1427 ath9k_hw_cfg_output(ah, i, AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1428 ath9k_hw_set_gpio(ah, i, !!(ah->gpio_val & BIT(i)));
1429 }
1430 }
1431
1432 bool ath9k_hw_check_alive(struct ath_hw *ah)
1433 {
1434 int count = 50;
1435 u32 reg;
1436
1437 if (AR_SREV_9285_12_OR_LATER(ah))
1438 return true;
1439
1440 do {
1441 reg = REG_READ(ah, AR_OBS_BUS_1);
1442
1443 if ((reg & 0x7E7FFFEF) == 0x00702400)
1444 continue;
1445
1446 switch (reg & 0x7E000B00) {
1447 case 0x1E000000:
1448 case 0x52000B00:
1449 case 0x18000B00:
1450 continue;
1451 default:
1452 return true;
1453 }
1454 } while (count-- > 0);
1455
1456 return false;
1457 }
1458 EXPORT_SYMBOL(ath9k_hw_check_alive);
1459
1460 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1461 struct ath9k_hw_cal_data *caldata, bool bChannelChange)
1462 {
1463 struct ath_common *common = ath9k_hw_common(ah);
1464 u32 saveLedState;
1465 struct ath9k_channel *curchan = ah->curchan;
1466 u32 saveDefAntenna;
1467 u32 macStaId1;
1468 u64 tsf = 0;
1469 int i, r;
1470
1471 ah->txchainmask = common->tx_chainmask;
1472 ah->rxchainmask = common->rx_chainmask;
1473
1474 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1475 return -EIO;
1476
1477 if (curchan && !ah->chip_fullsleep)
1478 ath9k_hw_getnf(ah, curchan);
1479
1480 ah->caldata = caldata;
1481 if (caldata &&
1482 (chan->channel != caldata->channel ||
1483 (chan->channelFlags & ~CHANNEL_CW_INT) !=
1484 (caldata->channelFlags & ~CHANNEL_CW_INT))) {
1485 /* Operating channel changed, reset channel calibration data */
1486 memset(caldata, 0, sizeof(*caldata));
1487 ath9k_init_nfcal_hist_buffer(ah, chan);
1488 }
1489 ah->noise = ath9k_hw_getchan_noise(ah, chan);
1490
1491 if (bChannelChange &&
1492 (ah->chip_fullsleep != true) &&
1493 (ah->curchan != NULL) &&
1494 (chan->channel != ah->curchan->channel) &&
1495 ((chan->channelFlags & CHANNEL_ALL) ==
1496 (ah->curchan->channelFlags & CHANNEL_ALL)) &&
1497 (!AR_SREV_9280(ah) || AR_DEVID_7010(ah))) {
1498
1499 if (ath9k_hw_channel_change(ah, chan)) {
1500 ath9k_hw_loadnf(ah, ah->curchan);
1501 ath9k_hw_start_nfcal(ah, true);
1502 if (AR_SREV_9271(ah))
1503 ar9002_hw_load_ani_reg(ah, chan);
1504 return 0;
1505 }
1506 }
1507
1508 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1509 if (saveDefAntenna == 0)
1510 saveDefAntenna = 1;
1511
1512 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1513
1514 /* For chips on which RTC reset is done, save TSF before it gets cleared */
1515 if (AR_SREV_9100(ah) ||
1516 (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)))
1517 tsf = ath9k_hw_gettsf64(ah);
1518
1519 saveLedState = REG_READ(ah, AR_CFG_LED) &
1520 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1521 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1522
1523 ath9k_hw_mark_phy_inactive(ah);
1524
1525 ah->paprd_table_write_done = false;
1526
1527 /* Only required on the first reset */
1528 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1529 REG_WRITE(ah,
1530 AR9271_RESET_POWER_DOWN_CONTROL,
1531 AR9271_RADIO_RF_RST);
1532 udelay(50);
1533 }
1534
1535 if (!ath9k_hw_chip_reset(ah, chan)) {
1536 ath_err(common, "Chip reset failed\n");
1537 return -EINVAL;
1538 }
1539
1540 /* Only required on the first reset */
1541 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1542 ah->htc_reset_init = false;
1543 REG_WRITE(ah,
1544 AR9271_RESET_POWER_DOWN_CONTROL,
1545 AR9271_GATE_MAC_CTL);
1546 udelay(50);
1547 }
1548
1549 /* Restore TSF */
1550 if (tsf)
1551 ath9k_hw_settsf64(ah, tsf);
1552
1553 if (AR_SREV_9280_20_OR_LATER(ah))
1554 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
1555
1556 if (!AR_SREV_9300_20_OR_LATER(ah))
1557 ar9002_hw_enable_async_fifo(ah);
1558
1559 r = ath9k_hw_process_ini(ah, chan);
1560 if (r)
1561 return r;
1562
1563 /*
1564 * Some AR91xx SoC devices frequently fail to accept TSF writes
1565 * right after the chip reset. When that happens, write a new
1566 * value after the initvals have been applied, with an offset
1567 * based on measured time difference
1568 */
1569 if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) {
1570 tsf += 1500;
1571 ath9k_hw_settsf64(ah, tsf);
1572 }
1573
1574 /* Setup MFP options for CCMP */
1575 if (AR_SREV_9280_20_OR_LATER(ah)) {
1576 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1577 * frames when constructing CCMP AAD. */
1578 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1579 0xc7ff);
1580 ah->sw_mgmt_crypto = false;
1581 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1582 /* Disable hardware crypto for management frames */
1583 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
1584 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
1585 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1586 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
1587 ah->sw_mgmt_crypto = true;
1588 } else
1589 ah->sw_mgmt_crypto = true;
1590
1591 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1592 ath9k_hw_set_delta_slope(ah, chan);
1593
1594 ath9k_hw_spur_mitigate_freq(ah, chan);
1595 ah->eep_ops->set_board_values(ah, chan);
1596
1597 ENABLE_REGWRITE_BUFFER(ah);
1598
1599 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
1600 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
1601 | macStaId1
1602 | AR_STA_ID1_RTS_USE_DEF
1603 | (ah->config.
1604 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
1605 | ah->sta_id1_defaults);
1606 ath_hw_setbssidmask(common);
1607 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
1608 ath9k_hw_write_associd(ah);
1609 REG_WRITE(ah, AR_ISR, ~0);
1610 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
1611
1612 REGWRITE_BUFFER_FLUSH(ah);
1613
1614 ath9k_hw_set_operating_mode(ah, ah->opmode);
1615
1616 r = ath9k_hw_rf_set_freq(ah, chan);
1617 if (r)
1618 return r;
1619
1620 ath9k_hw_set_clockrate(ah);
1621
1622 ENABLE_REGWRITE_BUFFER(ah);
1623
1624 for (i = 0; i < AR_NUM_DCU; i++)
1625 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
1626
1627 REGWRITE_BUFFER_FLUSH(ah);
1628
1629 ah->intr_txqs = 0;
1630 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1631 ath9k_hw_resettxqueue(ah, i);
1632
1633 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
1634 ath9k_hw_ani_cache_ini_regs(ah);
1635 ath9k_hw_init_qos(ah);
1636
1637 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1638 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
1639
1640 ath9k_hw_init_global_settings(ah);
1641
1642 if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
1643 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
1644 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
1645 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
1646 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
1647 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1648 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
1649 }
1650
1651 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM);
1652
1653 ath9k_hw_set_dma(ah);
1654
1655 REG_WRITE(ah, AR_OBS, 8);
1656
1657 if (ah->config.rx_intr_mitigation) {
1658 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
1659 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
1660 }
1661
1662 if (ah->config.tx_intr_mitigation) {
1663 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300);
1664 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750);
1665 }
1666
1667 ath9k_hw_init_bb(ah, chan);
1668
1669 if (!ath9k_hw_init_cal(ah, chan))
1670 return -EIO;
1671
1672 ENABLE_REGWRITE_BUFFER(ah);
1673
1674 ath9k_hw_restore_chainmask(ah);
1675 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
1676
1677 REGWRITE_BUFFER_FLUSH(ah);
1678
1679 /*
1680 * For big endian systems turn on swapping for descriptors
1681 */
1682 if (AR_SREV_9100(ah)) {
1683 u32 mask;
1684 mask = REG_READ(ah, AR_CFG);
1685 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
1686 ath_dbg(common, ATH_DBG_RESET,
1687 "CFG Byte Swap Set 0x%x\n", mask);
1688 } else {
1689 mask =
1690 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
1691 REG_WRITE(ah, AR_CFG, mask);
1692 ath_dbg(common, ATH_DBG_RESET,
1693 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
1694 }
1695 } else {
1696 if (common->bus_ops->ath_bus_type == ATH_USB) {
1697 /* Configure AR9271 target WLAN */
1698 if (AR_SREV_9271(ah))
1699 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
1700 else
1701 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1702 }
1703 #ifdef __BIG_ENDIAN
1704 else if (AR_SREV_9330(ah) || AR_SREV_9340(ah))
1705 REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0);
1706 else
1707 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1708 #endif
1709 }
1710
1711 if (ah->btcoex_hw.enabled)
1712 ath9k_hw_btcoex_enable(ah);
1713
1714 if (AR_SREV_9300_20_OR_LATER(ah)) {
1715 ar9003_hw_bb_watchdog_config(ah);
1716
1717 ar9003_hw_disable_phy_restart(ah);
1718 }
1719
1720 ath9k_hw_apply_gpio_override(ah);
1721
1722 return 0;
1723 }
1724 EXPORT_SYMBOL(ath9k_hw_reset);
1725
1726 /******************************/
1727 /* Power Management (Chipset) */
1728 /******************************/
1729
1730 /*
1731 * Notify Power Mgt is disabled in self-generated frames.
1732 * If requested, force chip to sleep.
1733 */
1734 static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
1735 {
1736 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1737 if (setChip) {
1738 /*
1739 * Clear the RTC force wake bit to allow the
1740 * mac to go to sleep.
1741 */
1742 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
1743 AR_RTC_FORCE_WAKE_EN);
1744 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1745 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1746
1747 /* Shutdown chip. Active low */
1748 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah))
1749 REG_CLR_BIT(ah, (AR_RTC_RESET),
1750 AR_RTC_RESET_EN);
1751 }
1752
1753 /* Clear Bit 14 of AR_WA after putting chip into Full Sleep mode. */
1754 if (AR_SREV_9300_20_OR_LATER(ah))
1755 REG_WRITE(ah, AR_WA,
1756 ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
1757 }
1758
1759 /*
1760 * Notify Power Management is enabled in self-generating
1761 * frames. If request, set power mode of chip to
1762 * auto/normal. Duration in units of 128us (1/8 TU).
1763 */
1764 static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
1765 {
1766 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1767 if (setChip) {
1768 struct ath9k_hw_capabilities *pCap = &ah->caps;
1769
1770 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1771 /* Set WakeOnInterrupt bit; clear ForceWake bit */
1772 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1773 AR_RTC_FORCE_WAKE_ON_INT);
1774 } else {
1775 /*
1776 * Clear the RTC force wake bit to allow the
1777 * mac to go to sleep.
1778 */
1779 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
1780 AR_RTC_FORCE_WAKE_EN);
1781 }
1782 }
1783
1784 /* Clear Bit 14 of AR_WA after putting chip into Net Sleep mode. */
1785 if (AR_SREV_9300_20_OR_LATER(ah))
1786 REG_WRITE(ah, AR_WA, ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
1787 }
1788
1789 static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
1790 {
1791 u32 val;
1792 int i;
1793
1794 /* Set Bits 14 and 17 of AR_WA before powering on the chip. */
1795 if (AR_SREV_9300_20_OR_LATER(ah)) {
1796 REG_WRITE(ah, AR_WA, ah->WARegVal);
1797 udelay(10);
1798 }
1799
1800 if (setChip) {
1801 if ((REG_READ(ah, AR_RTC_STATUS) &
1802 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
1803 if (ath9k_hw_set_reset_reg(ah,
1804 ATH9K_RESET_POWER_ON) != true) {
1805 return false;
1806 }
1807 if (!AR_SREV_9300_20_OR_LATER(ah))
1808 ath9k_hw_init_pll(ah, NULL);
1809 }
1810 if (AR_SREV_9100(ah))
1811 REG_SET_BIT(ah, AR_RTC_RESET,
1812 AR_RTC_RESET_EN);
1813
1814 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
1815 AR_RTC_FORCE_WAKE_EN);
1816 udelay(50);
1817
1818 for (i = POWER_UP_TIME / 50; i > 0; i--) {
1819 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
1820 if (val == AR_RTC_STATUS_ON)
1821 break;
1822 udelay(50);
1823 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
1824 AR_RTC_FORCE_WAKE_EN);
1825 }
1826 if (i == 0) {
1827 ath_err(ath9k_hw_common(ah),
1828 "Failed to wakeup in %uus\n",
1829 POWER_UP_TIME / 20);
1830 return false;
1831 }
1832 }
1833
1834 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1835
1836 return true;
1837 }
1838
1839 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
1840 {
1841 struct ath_common *common = ath9k_hw_common(ah);
1842 int status = true, setChip = true;
1843 static const char *modes[] = {
1844 "AWAKE",
1845 "FULL-SLEEP",
1846 "NETWORK SLEEP",
1847 "UNDEFINED"
1848 };
1849
1850 if (ah->power_mode == mode)
1851 return status;
1852
1853 ath_dbg(common, ATH_DBG_RESET, "%s -> %s\n",
1854 modes[ah->power_mode], modes[mode]);
1855
1856 switch (mode) {
1857 case ATH9K_PM_AWAKE:
1858 status = ath9k_hw_set_power_awake(ah, setChip);
1859 break;
1860 case ATH9K_PM_FULL_SLEEP:
1861 ath9k_set_power_sleep(ah, setChip);
1862 ah->chip_fullsleep = true;
1863 break;
1864 case ATH9K_PM_NETWORK_SLEEP:
1865 ath9k_set_power_network_sleep(ah, setChip);
1866 break;
1867 default:
1868 ath_err(common, "Unknown power mode %u\n", mode);
1869 return false;
1870 }
1871 ah->power_mode = mode;
1872
1873 /*
1874 * XXX: If this warning never comes up after a while then
1875 * simply keep the ATH_DBG_WARN_ON_ONCE() but make
1876 * ath9k_hw_setpower() return type void.
1877 */
1878
1879 if (!(ah->ah_flags & AH_UNPLUGGED))
1880 ATH_DBG_WARN_ON_ONCE(!status);
1881
1882 return status;
1883 }
1884 EXPORT_SYMBOL(ath9k_hw_setpower);
1885
1886 /*******************/
1887 /* Beacon Handling */
1888 /*******************/
1889
1890 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
1891 {
1892 int flags = 0;
1893
1894 ENABLE_REGWRITE_BUFFER(ah);
1895
1896 switch (ah->opmode) {
1897 case NL80211_IFTYPE_ADHOC:
1898 case NL80211_IFTYPE_MESH_POINT:
1899 REG_SET_BIT(ah, AR_TXCFG,
1900 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
1901 REG_WRITE(ah, AR_NEXT_NDP_TIMER, next_beacon +
1902 TU_TO_USEC(ah->atim_window ? ah->atim_window : 1));
1903 flags |= AR_NDP_TIMER_EN;
1904 case NL80211_IFTYPE_AP:
1905 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon);
1906 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, next_beacon -
1907 TU_TO_USEC(ah->config.dma_beacon_response_time));
1908 REG_WRITE(ah, AR_NEXT_SWBA, next_beacon -
1909 TU_TO_USEC(ah->config.sw_beacon_response_time));
1910 flags |=
1911 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
1912 break;
1913 default:
1914 ath_dbg(ath9k_hw_common(ah), ATH_DBG_BEACON,
1915 "%s: unsupported opmode: %d\n",
1916 __func__, ah->opmode);
1917 return;
1918 break;
1919 }
1920
1921 REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period);
1922 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period);
1923 REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period);
1924 REG_WRITE(ah, AR_NDP_PERIOD, beacon_period);
1925
1926 REGWRITE_BUFFER_FLUSH(ah);
1927
1928 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
1929 }
1930 EXPORT_SYMBOL(ath9k_hw_beaconinit);
1931
1932 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
1933 const struct ath9k_beacon_state *bs)
1934 {
1935 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
1936 struct ath9k_hw_capabilities *pCap = &ah->caps;
1937 struct ath_common *common = ath9k_hw_common(ah);
1938
1939 ENABLE_REGWRITE_BUFFER(ah);
1940
1941 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
1942
1943 REG_WRITE(ah, AR_BEACON_PERIOD,
1944 TU_TO_USEC(bs->bs_intval));
1945 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
1946 TU_TO_USEC(bs->bs_intval));
1947
1948 REGWRITE_BUFFER_FLUSH(ah);
1949
1950 REG_RMW_FIELD(ah, AR_RSSI_THR,
1951 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
1952
1953 beaconintval = bs->bs_intval;
1954
1955 if (bs->bs_sleepduration > beaconintval)
1956 beaconintval = bs->bs_sleepduration;
1957
1958 dtimperiod = bs->bs_dtimperiod;
1959 if (bs->bs_sleepduration > dtimperiod)
1960 dtimperiod = bs->bs_sleepduration;
1961
1962 if (beaconintval == dtimperiod)
1963 nextTbtt = bs->bs_nextdtim;
1964 else
1965 nextTbtt = bs->bs_nexttbtt;
1966
1967 ath_dbg(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
1968 ath_dbg(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
1969 ath_dbg(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
1970 ath_dbg(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
1971
1972 ENABLE_REGWRITE_BUFFER(ah);
1973
1974 REG_WRITE(ah, AR_NEXT_DTIM,
1975 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
1976 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
1977
1978 REG_WRITE(ah, AR_SLEEP1,
1979 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
1980 | AR_SLEEP1_ASSUME_DTIM);
1981
1982 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
1983 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
1984 else
1985 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
1986
1987 REG_WRITE(ah, AR_SLEEP2,
1988 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
1989
1990 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
1991 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
1992
1993 REGWRITE_BUFFER_FLUSH(ah);
1994
1995 REG_SET_BIT(ah, AR_TIMER_MODE,
1996 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
1997 AR_DTIM_TIMER_EN);
1998
1999 /* TSF Out of Range Threshold */
2000 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
2001 }
2002 EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
2003
2004 /*******************/
2005 /* HW Capabilities */
2006 /*******************/
2007
2008 static u8 fixup_chainmask(u8 chip_chainmask, u8 eeprom_chainmask)
2009 {
2010 eeprom_chainmask &= chip_chainmask;
2011 if (eeprom_chainmask)
2012 return eeprom_chainmask;
2013 else
2014 return chip_chainmask;
2015 }
2016
2017 int ath9k_hw_fill_cap_info(struct ath_hw *ah)
2018 {
2019 struct ath9k_hw_capabilities *pCap = &ah->caps;
2020 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2021 struct ath_common *common = ath9k_hw_common(ah);
2022 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
2023 unsigned int chip_chainmask;
2024
2025 u16 eeval;
2026 u8 ant_div_ctl1, tx_chainmask, rx_chainmask;
2027
2028 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
2029 regulatory->current_rd = eeval;
2030
2031 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
2032 if (AR_SREV_9285_12_OR_LATER(ah))
2033 eeval |= AR9285_RDEXT_DEFAULT;
2034 regulatory->current_rd_ext = eeval;
2035
2036 if (ah->opmode != NL80211_IFTYPE_AP &&
2037 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
2038 if (regulatory->current_rd == 0x64 ||
2039 regulatory->current_rd == 0x65)
2040 regulatory->current_rd += 5;
2041 else if (regulatory->current_rd == 0x41)
2042 regulatory->current_rd = 0x43;
2043 ath_dbg(common, ATH_DBG_REGULATORY,
2044 "regdomain mapped to 0x%x\n", regulatory->current_rd);
2045 }
2046
2047 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
2048 if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
2049 ath_err(common,
2050 "no band has been marked as supported in EEPROM\n");
2051 return -EINVAL;
2052 }
2053
2054 if (eeval & AR5416_OPFLAGS_11A)
2055 pCap->hw_caps |= ATH9K_HW_CAP_5GHZ;
2056
2057 if (eeval & AR5416_OPFLAGS_11G)
2058 pCap->hw_caps |= ATH9K_HW_CAP_2GHZ;
2059
2060 if (AR_SREV_9485(ah) || AR_SREV_9285(ah) || AR_SREV_9330(ah))
2061 chip_chainmask = 1;
2062 else if (!AR_SREV_9280_20_OR_LATER(ah))
2063 chip_chainmask = 7;
2064 else if (!AR_SREV_9300_20_OR_LATER(ah) || AR_SREV_9340(ah))
2065 chip_chainmask = 3;
2066 else
2067 chip_chainmask = 7;
2068
2069 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
2070 /*
2071 * For AR9271 we will temporarilly uses the rx chainmax as read from
2072 * the EEPROM.
2073 */
2074 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
2075 !(eeval & AR5416_OPFLAGS_11A) &&
2076 !(AR_SREV_9271(ah)))
2077 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
2078 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
2079 else if (AR_SREV_9100(ah))
2080 pCap->rx_chainmask = 0x7;
2081 else
2082 /* Use rx_chainmask from EEPROM. */
2083 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
2084
2085 pCap->tx_chainmask = fixup_chainmask(chip_chainmask, pCap->tx_chainmask);
2086 pCap->rx_chainmask = fixup_chainmask(chip_chainmask, pCap->rx_chainmask);
2087
2088 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
2089
2090 /* enable key search for every frame in an aggregate */
2091 if (AR_SREV_9300_20_OR_LATER(ah))
2092 ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH;
2093
2094 common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM;
2095
2096 if (ah->hw_version.devid != AR2427_DEVID_PCIE)
2097 pCap->hw_caps |= ATH9K_HW_CAP_HT;
2098 else
2099 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
2100
2101 if (AR_SREV_9271(ah))
2102 pCap->num_gpio_pins = AR9271_NUM_GPIO;
2103 else if (AR_DEVID_7010(ah))
2104 pCap->num_gpio_pins = AR7010_NUM_GPIO;
2105 else if (AR_SREV_9285_12_OR_LATER(ah))
2106 pCap->num_gpio_pins = AR9285_NUM_GPIO;
2107 else if (AR_SREV_9280_20_OR_LATER(ah))
2108 pCap->num_gpio_pins = AR928X_NUM_GPIO;
2109 else
2110 pCap->num_gpio_pins = AR_NUM_GPIO;
2111
2112 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
2113 pCap->hw_caps |= ATH9K_HW_CAP_CST;
2114 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
2115 } else {
2116 pCap->rts_aggr_limit = (8 * 1024);
2117 }
2118
2119 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2120 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
2121 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
2122 ah->rfkill_gpio =
2123 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
2124 ah->rfkill_polarity =
2125 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
2126
2127 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
2128 }
2129 #endif
2130 if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah))
2131 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
2132 else
2133 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
2134
2135 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
2136 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
2137 else
2138 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
2139
2140 if (common->btcoex_enabled) {
2141 if (AR_SREV_9300_20_OR_LATER(ah)) {
2142 btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
2143 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO_9300;
2144 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO_9300;
2145 btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO_9300;
2146 } else if (AR_SREV_9280_20_OR_LATER(ah)) {
2147 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO_9280;
2148 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO_9280;
2149
2150 if (AR_SREV_9285(ah)) {
2151 btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
2152 btcoex_hw->btpriority_gpio =
2153 ATH_BTPRIORITY_GPIO_9285;
2154 } else {
2155 btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE;
2156 }
2157 }
2158 } else {
2159 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
2160 }
2161
2162 if (AR_SREV_9300_20_OR_LATER(ah)) {
2163 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK;
2164 if (!AR_SREV_9330(ah) && !AR_SREV_9485(ah))
2165 pCap->hw_caps |= ATH9K_HW_CAP_LDPC;
2166
2167 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
2168 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
2169 pCap->rx_status_len = sizeof(struct ar9003_rxs);
2170 pCap->tx_desc_len = sizeof(struct ar9003_txc);
2171 pCap->txs_len = sizeof(struct ar9003_txs);
2172 if (!ah->config.paprd_disable &&
2173 ah->eep_ops->get_eeprom(ah, EEP_PAPRD))
2174 pCap->hw_caps |= ATH9K_HW_CAP_PAPRD;
2175 } else {
2176 pCap->tx_desc_len = sizeof(struct ath_desc);
2177 if (AR_SREV_9280_20(ah))
2178 pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK;
2179 }
2180
2181 if (AR_SREV_9300_20_OR_LATER(ah))
2182 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
2183
2184 if (AR_SREV_9300_20_OR_LATER(ah))
2185 ah->ent_mode = REG_READ(ah, AR_ENT_OTP);
2186
2187 if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah))
2188 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20;
2189
2190 if (AR_SREV_9285(ah))
2191 if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) {
2192 ant_div_ctl1 =
2193 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
2194 if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1))
2195 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
2196 }
2197 if (AR_SREV_9300_20_OR_LATER(ah)) {
2198 if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE))
2199 pCap->hw_caps |= ATH9K_HW_CAP_APM;
2200 }
2201
2202
2203 if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) {
2204 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
2205 /*
2206 * enable the diversity-combining algorithm only when
2207 * both enable_lna_div and enable_fast_div are set
2208 * Table for Diversity
2209 * ant_div_alt_lnaconf bit 0-1
2210 * ant_div_main_lnaconf bit 2-3
2211 * ant_div_alt_gaintb bit 4
2212 * ant_div_main_gaintb bit 5
2213 * enable_ant_div_lnadiv bit 6
2214 * enable_ant_fast_div bit 7
2215 */
2216 if ((ant_div_ctl1 >> 0x6) == 0x3)
2217 pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
2218 }
2219
2220 if (AR_SREV_9485_10(ah)) {
2221 pCap->pcie_lcr_extsync_en = true;
2222 pCap->pcie_lcr_offset = 0x80;
2223 }
2224
2225 tx_chainmask = pCap->tx_chainmask;
2226 rx_chainmask = pCap->rx_chainmask;
2227 while (tx_chainmask || rx_chainmask) {
2228 if (tx_chainmask & BIT(0))
2229 pCap->max_txchains++;
2230 if (rx_chainmask & BIT(0))
2231 pCap->max_rxchains++;
2232
2233 tx_chainmask >>= 1;
2234 rx_chainmask >>= 1;
2235 }
2236
2237 return 0;
2238 }
2239
2240 /****************************/
2241 /* GPIO / RFKILL / Antennae */
2242 /****************************/
2243
2244 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
2245 u32 gpio, u32 type)
2246 {
2247 int addr;
2248 u32 gpio_shift, tmp;
2249
2250 if (gpio > 11)
2251 addr = AR_GPIO_OUTPUT_MUX3;
2252 else if (gpio > 5)
2253 addr = AR_GPIO_OUTPUT_MUX2;
2254 else
2255 addr = AR_GPIO_OUTPUT_MUX1;
2256
2257 gpio_shift = (gpio % 6) * 5;
2258
2259 if (AR_SREV_9280_20_OR_LATER(ah)
2260 || (addr != AR_GPIO_OUTPUT_MUX1)) {
2261 REG_RMW(ah, addr, (type << gpio_shift),
2262 (0x1f << gpio_shift));
2263 } else {
2264 tmp = REG_READ(ah, addr);
2265 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
2266 tmp &= ~(0x1f << gpio_shift);
2267 tmp |= (type << gpio_shift);
2268 REG_WRITE(ah, addr, tmp);
2269 }
2270 }
2271
2272 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
2273 {
2274 u32 gpio_shift;
2275
2276 BUG_ON(gpio >= ah->caps.num_gpio_pins);
2277
2278 if (AR_DEVID_7010(ah)) {
2279 gpio_shift = gpio;
2280 REG_RMW(ah, AR7010_GPIO_OE,
2281 (AR7010_GPIO_OE_AS_INPUT << gpio_shift),
2282 (AR7010_GPIO_OE_MASK << gpio_shift));
2283 return;
2284 }
2285
2286 gpio_shift = gpio << 1;
2287 REG_RMW(ah,
2288 AR_GPIO_OE_OUT,
2289 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
2290 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2291 }
2292 EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
2293
2294 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
2295 {
2296 #define MS_REG_READ(x, y) \
2297 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
2298
2299 if (gpio >= ah->caps.num_gpio_pins)
2300 return 0xffffffff;
2301
2302 if (AR_DEVID_7010(ah)) {
2303 u32 val;
2304 val = REG_READ(ah, AR7010_GPIO_IN);
2305 return (MS(val, AR7010_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) == 0;
2306 } else if (AR_SREV_9300_20_OR_LATER(ah))
2307 return (MS(REG_READ(ah, AR_GPIO_IN), AR9300_GPIO_IN_VAL) &
2308 AR_GPIO_BIT(gpio)) != 0;
2309 else if (AR_SREV_9271(ah))
2310 return MS_REG_READ(AR9271, gpio) != 0;
2311 else if (AR_SREV_9287_11_OR_LATER(ah))
2312 return MS_REG_READ(AR9287, gpio) != 0;
2313 else if (AR_SREV_9285_12_OR_LATER(ah))
2314 return MS_REG_READ(AR9285, gpio) != 0;
2315 else if (AR_SREV_9280_20_OR_LATER(ah))
2316 return MS_REG_READ(AR928X, gpio) != 0;
2317 else
2318 return MS_REG_READ(AR, gpio) != 0;
2319 }
2320 EXPORT_SYMBOL(ath9k_hw_gpio_get);
2321
2322 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
2323 u32 ah_signal_type)
2324 {
2325 u32 gpio_shift;
2326
2327 if (AR_DEVID_7010(ah)) {
2328 gpio_shift = gpio;
2329 REG_RMW(ah, AR7010_GPIO_OE,
2330 (AR7010_GPIO_OE_AS_OUTPUT << gpio_shift),
2331 (AR7010_GPIO_OE_MASK << gpio_shift));
2332 return;
2333 }
2334
2335 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
2336 gpio_shift = 2 * gpio;
2337 REG_RMW(ah,
2338 AR_GPIO_OE_OUT,
2339 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
2340 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2341 }
2342 EXPORT_SYMBOL(ath9k_hw_cfg_output);
2343
2344 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
2345 {
2346 if (AR_DEVID_7010(ah)) {
2347 val = val ? 0 : 1;
2348 REG_RMW(ah, AR7010_GPIO_OUT, ((val&1) << gpio),
2349 AR_GPIO_BIT(gpio));
2350 return;
2351 }
2352
2353 if (AR_SREV_9271(ah))
2354 val = ~val;
2355
2356 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
2357 AR_GPIO_BIT(gpio));
2358 }
2359 EXPORT_SYMBOL(ath9k_hw_set_gpio);
2360
2361 u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
2362 {
2363 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
2364 }
2365 EXPORT_SYMBOL(ath9k_hw_getdefantenna);
2366
2367 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
2368 {
2369 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
2370 }
2371 EXPORT_SYMBOL(ath9k_hw_setantenna);
2372
2373 /*********************/
2374 /* General Operation */
2375 /*********************/
2376
2377 u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
2378 {
2379 u32 bits = REG_READ(ah, AR_RX_FILTER);
2380 u32 phybits = REG_READ(ah, AR_PHY_ERR);
2381
2382 if (phybits & AR_PHY_ERR_RADAR)
2383 bits |= ATH9K_RX_FILTER_PHYRADAR;
2384 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
2385 bits |= ATH9K_RX_FILTER_PHYERR;
2386
2387 return bits;
2388 }
2389 EXPORT_SYMBOL(ath9k_hw_getrxfilter);
2390
2391 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
2392 {
2393 u32 phybits;
2394
2395 ENABLE_REGWRITE_BUFFER(ah);
2396
2397 REG_WRITE(ah, AR_RX_FILTER, bits);
2398
2399 phybits = 0;
2400 if (bits & ATH9K_RX_FILTER_PHYRADAR)
2401 phybits |= AR_PHY_ERR_RADAR;
2402 if (bits & ATH9K_RX_FILTER_PHYERR)
2403 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
2404 REG_WRITE(ah, AR_PHY_ERR, phybits);
2405
2406 if (phybits)
2407 REG_SET_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
2408 else
2409 REG_CLR_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
2410
2411 REGWRITE_BUFFER_FLUSH(ah);
2412 }
2413 EXPORT_SYMBOL(ath9k_hw_setrxfilter);
2414
2415 bool ath9k_hw_phy_disable(struct ath_hw *ah)
2416 {
2417 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
2418 return false;
2419
2420 ath9k_hw_init_pll(ah, NULL);
2421 return true;
2422 }
2423 EXPORT_SYMBOL(ath9k_hw_phy_disable);
2424
2425 bool ath9k_hw_disable(struct ath_hw *ah)
2426 {
2427 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2428 return false;
2429
2430 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
2431 return false;
2432
2433 ath9k_hw_init_pll(ah, NULL);
2434 return true;
2435 }
2436 EXPORT_SYMBOL(ath9k_hw_disable);
2437
2438 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test)
2439 {
2440 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2441 struct ath9k_channel *chan = ah->curchan;
2442 struct ieee80211_channel *channel = chan->chan;
2443 int reg_pwr = min_t(int, MAX_RATE_POWER, regulatory->power_limit);
2444 int chan_pwr = channel->max_power * 2;
2445
2446 if (test)
2447 reg_pwr = chan_pwr = MAX_RATE_POWER;
2448
2449 regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER);
2450
2451 ah->eep_ops->set_txpower(ah, chan,
2452 ath9k_regd_get_ctl(regulatory, chan),
2453 channel->max_antenna_gain * 2,
2454 chan_pwr, reg_pwr, test);
2455 }
2456 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
2457
2458 void ath9k_hw_setopmode(struct ath_hw *ah)
2459 {
2460 ath9k_hw_set_operating_mode(ah, ah->opmode);
2461 }
2462 EXPORT_SYMBOL(ath9k_hw_setopmode);
2463
2464 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
2465 {
2466 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
2467 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
2468 }
2469 EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
2470
2471 void ath9k_hw_write_associd(struct ath_hw *ah)
2472 {
2473 struct ath_common *common = ath9k_hw_common(ah);
2474
2475 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
2476 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
2477 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
2478 }
2479 EXPORT_SYMBOL(ath9k_hw_write_associd);
2480
2481 #define ATH9K_MAX_TSF_READ 10
2482
2483 u64 ath9k_hw_gettsf64(struct ath_hw *ah)
2484 {
2485 u32 tsf_lower, tsf_upper1, tsf_upper2;
2486 int i;
2487
2488 tsf_upper1 = REG_READ(ah, AR_TSF_U32);
2489 for (i = 0; i < ATH9K_MAX_TSF_READ; i++) {
2490 tsf_lower = REG_READ(ah, AR_TSF_L32);
2491 tsf_upper2 = REG_READ(ah, AR_TSF_U32);
2492 if (tsf_upper2 == tsf_upper1)
2493 break;
2494 tsf_upper1 = tsf_upper2;
2495 }
2496
2497 WARN_ON( i == ATH9K_MAX_TSF_READ );
2498
2499 return (((u64)tsf_upper1 << 32) | tsf_lower);
2500 }
2501 EXPORT_SYMBOL(ath9k_hw_gettsf64);
2502
2503 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
2504 {
2505 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
2506 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
2507 }
2508 EXPORT_SYMBOL(ath9k_hw_settsf64);
2509
2510 void ath9k_hw_reset_tsf(struct ath_hw *ah)
2511 {
2512 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
2513 AH_TSF_WRITE_TIMEOUT))
2514 ath_dbg(ath9k_hw_common(ah), ATH_DBG_RESET,
2515 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
2516
2517 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
2518 }
2519 EXPORT_SYMBOL(ath9k_hw_reset_tsf);
2520
2521 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
2522 {
2523 if (setting)
2524 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
2525 else
2526 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
2527 }
2528 EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
2529
2530 void ath9k_hw_set11nmac2040(struct ath_hw *ah)
2531 {
2532 struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
2533 u32 macmode;
2534
2535 if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
2536 macmode = AR_2040_JOINED_RX_CLEAR;
2537 else
2538 macmode = 0;
2539
2540 REG_WRITE(ah, AR_2040_MODE, macmode);
2541 }
2542
2543 /* HW Generic timers configuration */
2544
2545 static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
2546 {
2547 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2548 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2549 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2550 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2551 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2552 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2553 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2554 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2555 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
2556 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
2557 AR_NDP2_TIMER_MODE, 0x0002},
2558 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
2559 AR_NDP2_TIMER_MODE, 0x0004},
2560 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
2561 AR_NDP2_TIMER_MODE, 0x0008},
2562 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
2563 AR_NDP2_TIMER_MODE, 0x0010},
2564 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
2565 AR_NDP2_TIMER_MODE, 0x0020},
2566 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
2567 AR_NDP2_TIMER_MODE, 0x0040},
2568 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
2569 AR_NDP2_TIMER_MODE, 0x0080}
2570 };
2571
2572 /* HW generic timer primitives */
2573
2574 /* compute and clear index of rightmost 1 */
2575 static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
2576 {
2577 u32 b;
2578
2579 b = *mask;
2580 b &= (0-b);
2581 *mask &= ~b;
2582 b *= debruijn32;
2583 b >>= 27;
2584
2585 return timer_table->gen_timer_index[b];
2586 }
2587
2588 u32 ath9k_hw_gettsf32(struct ath_hw *ah)
2589 {
2590 return REG_READ(ah, AR_TSF_L32);
2591 }
2592 EXPORT_SYMBOL(ath9k_hw_gettsf32);
2593
2594 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
2595 void (*trigger)(void *),
2596 void (*overflow)(void *),
2597 void *arg,
2598 u8 timer_index)
2599 {
2600 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2601 struct ath_gen_timer *timer;
2602
2603 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
2604
2605 if (timer == NULL) {
2606 ath_err(ath9k_hw_common(ah),
2607 "Failed to allocate memory for hw timer[%d]\n",
2608 timer_index);
2609 return NULL;
2610 }
2611
2612 /* allocate a hardware generic timer slot */
2613 timer_table->timers[timer_index] = timer;
2614 timer->index = timer_index;
2615 timer->trigger = trigger;
2616 timer->overflow = overflow;
2617 timer->arg = arg;
2618
2619 return timer;
2620 }
2621 EXPORT_SYMBOL(ath_gen_timer_alloc);
2622
2623 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
2624 struct ath_gen_timer *timer,
2625 u32 trig_timeout,
2626 u32 timer_period)
2627 {
2628 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2629 u32 tsf, timer_next;
2630
2631 BUG_ON(!timer_period);
2632
2633 set_bit(timer->index, &timer_table->timer_mask.timer_bits);
2634
2635 tsf = ath9k_hw_gettsf32(ah);
2636
2637 timer_next = tsf + trig_timeout;
2638
2639 ath_dbg(ath9k_hw_common(ah), ATH_DBG_HWTIMER,
2640 "current tsf %x period %x timer_next %x\n",
2641 tsf, timer_period, timer_next);
2642
2643 /*
2644 * Program generic timer registers
2645 */
2646 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
2647 timer_next);
2648 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
2649 timer_period);
2650 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2651 gen_tmr_configuration[timer->index].mode_mask);
2652
2653 /* Enable both trigger and thresh interrupt masks */
2654 REG_SET_BIT(ah, AR_IMR_S5,
2655 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2656 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
2657 }
2658 EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
2659
2660 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
2661 {
2662 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2663
2664 if ((timer->index < AR_FIRST_NDP_TIMER) ||
2665 (timer->index >= ATH_MAX_GEN_TIMER)) {
2666 return;
2667 }
2668
2669 /* Clear generic timer enable bits. */
2670 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2671 gen_tmr_configuration[timer->index].mode_mask);
2672
2673 /* Disable both trigger and thresh interrupt masks */
2674 REG_CLR_BIT(ah, AR_IMR_S5,
2675 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2676 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
2677
2678 clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
2679 }
2680 EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
2681
2682 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
2683 {
2684 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2685
2686 /* free the hardware generic timer slot */
2687 timer_table->timers[timer->index] = NULL;
2688 kfree(timer);
2689 }
2690 EXPORT_SYMBOL(ath_gen_timer_free);
2691
2692 /*
2693 * Generic Timer Interrupts handling
2694 */
2695 void ath_gen_timer_isr(struct ath_hw *ah)
2696 {
2697 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2698 struct ath_gen_timer *timer;
2699 struct ath_common *common = ath9k_hw_common(ah);
2700 u32 trigger_mask, thresh_mask, index;
2701
2702 /* get hardware generic timer interrupt status */
2703 trigger_mask = ah->intr_gen_timer_trigger;
2704 thresh_mask = ah->intr_gen_timer_thresh;
2705 trigger_mask &= timer_table->timer_mask.val;
2706 thresh_mask &= timer_table->timer_mask.val;
2707
2708 trigger_mask &= ~thresh_mask;
2709
2710 while (thresh_mask) {
2711 index = rightmost_index(timer_table, &thresh_mask);
2712 timer = timer_table->timers[index];
2713 BUG_ON(!timer);
2714 ath_dbg(common, ATH_DBG_HWTIMER,
2715 "TSF overflow for Gen timer %d\n", index);
2716 timer->overflow(timer->arg);
2717 }
2718
2719 while (trigger_mask) {
2720 index = rightmost_index(timer_table, &trigger_mask);
2721 timer = timer_table->timers[index];
2722 BUG_ON(!timer);
2723 ath_dbg(common, ATH_DBG_HWTIMER,
2724 "Gen timer[%d] trigger\n", index);
2725 timer->trigger(timer->arg);
2726 }
2727 }
2728 EXPORT_SYMBOL(ath_gen_timer_isr);
2729
2730 /********/
2731 /* HTC */
2732 /********/
2733
2734 void ath9k_hw_htc_resetinit(struct ath_hw *ah)
2735 {
2736 ah->htc_reset_init = true;
2737 }
2738 EXPORT_SYMBOL(ath9k_hw_htc_resetinit);
2739
2740 static struct {
2741 u32 version;
2742 const char * name;
2743 } ath_mac_bb_names[] = {
2744 /* Devices with external radios */
2745 { AR_SREV_VERSION_5416_PCI, "5416" },
2746 { AR_SREV_VERSION_5416_PCIE, "5418" },
2747 { AR_SREV_VERSION_9100, "9100" },
2748 { AR_SREV_VERSION_9160, "9160" },
2749 /* Single-chip solutions */
2750 { AR_SREV_VERSION_9280, "9280" },
2751 { AR_SREV_VERSION_9285, "9285" },
2752 { AR_SREV_VERSION_9287, "9287" },
2753 { AR_SREV_VERSION_9271, "9271" },
2754 { AR_SREV_VERSION_9300, "9300" },
2755 { AR_SREV_VERSION_9330, "9330" },
2756 { AR_SREV_VERSION_9485, "9485" },
2757 };
2758
2759 /* For devices with external radios */
2760 static struct {
2761 u16 version;
2762 const char * name;
2763 } ath_rf_names[] = {
2764 { 0, "5133" },
2765 { AR_RAD5133_SREV_MAJOR, "5133" },
2766 { AR_RAD5122_SREV_MAJOR, "5122" },
2767 { AR_RAD2133_SREV_MAJOR, "2133" },
2768 { AR_RAD2122_SREV_MAJOR, "2122" }
2769 };
2770
2771 /*
2772 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2773 */
2774 static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
2775 {
2776 int i;
2777
2778 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2779 if (ath_mac_bb_names[i].version == mac_bb_version) {
2780 return ath_mac_bb_names[i].name;
2781 }
2782 }
2783
2784 return "????";
2785 }
2786
2787 /*
2788 * Return the RF name. "????" is returned if the RF is unknown.
2789 * Used for devices with external radios.
2790 */
2791 static const char *ath9k_hw_rf_name(u16 rf_version)
2792 {
2793 int i;
2794
2795 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2796 if (ath_rf_names[i].version == rf_version) {
2797 return ath_rf_names[i].name;
2798 }
2799 }
2800
2801 return "????";
2802 }
2803
2804 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
2805 {
2806 int used;
2807
2808 /* chipsets >= AR9280 are single-chip */
2809 if (AR_SREV_9280_20_OR_LATER(ah)) {
2810 used = snprintf(hw_name, len,
2811 "Atheros AR%s Rev:%x",
2812 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
2813 ah->hw_version.macRev);
2814 }
2815 else {
2816 used = snprintf(hw_name, len,
2817 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
2818 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
2819 ah->hw_version.macRev,
2820 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
2821 AR_RADIO_SREV_MAJOR)),
2822 ah->hw_version.phyRev);
2823 }
2824
2825 hw_name[used] = '\0';
2826 }
2827 EXPORT_SYMBOL(ath9k_hw_name);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree