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drm/radeon/kms: set HPD polarity in hpd_init()
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / gpu / drm / radeon / evergreen.c
blob7ce9c87e695eb5dade402e748ce9d268b58251d1
1 /*
2 * Copyright 2010 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
24 #include <linux/firmware.h>
25 #include <linux/platform_device.h>
26 #include <linux/slab.h>
27 #include "drmP.h"
28 #include "radeon.h"
29 #include "radeon_asic.h"
30 #include "radeon_drm.h"
31 #include "evergreend.h"
32 #include "atom.h"
33 #include "avivod.h"
34 #include "evergreen_reg.h"
35 #include "evergreen_blit_shaders.h"
36
37 #define EVERGREEN_PFP_UCODE_SIZE 1120
38 #define EVERGREEN_PM4_UCODE_SIZE 1376
39
40 static void evergreen_gpu_init(struct radeon_device *rdev);
41 void evergreen_fini(struct radeon_device *rdev);
42 void evergreen_pcie_gen2_enable(struct radeon_device *rdev);
43
44 void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev)
45 {
46 u16 ctl, v;
47 int cap, err;
48
49 cap = pci_pcie_cap(rdev->pdev);
50 if (!cap)
51 return;
52
53 err = pci_read_config_word(rdev->pdev, cap + PCI_EXP_DEVCTL, &ctl);
54 if (err)
55 return;
56
57 v = (ctl & PCI_EXP_DEVCTL_READRQ) >> 12;
58
59 /* if bios or OS sets MAX_READ_REQUEST_SIZE to an invalid value, fix it
60 * to avoid hangs or perfomance issues
61 */
62 if ((v == 0) || (v == 6) || (v == 7)) {
63 ctl &= ~PCI_EXP_DEVCTL_READRQ;
64 ctl |= (2 << 12);
65 pci_write_config_word(rdev->pdev, cap + PCI_EXP_DEVCTL, ctl);
66 }
67 }
68
69 void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc)
70 {
71 /* enable the pflip int */
72 radeon_irq_kms_pflip_irq_get(rdev, crtc);
73 }
74
75 void evergreen_post_page_flip(struct radeon_device *rdev, int crtc)
76 {
77 /* disable the pflip int */
78 radeon_irq_kms_pflip_irq_put(rdev, crtc);
79 }
80
81 u32 evergreen_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
82 {
83 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
84 u32 tmp = RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset);
85
86 /* Lock the graphics update lock */
87 tmp |= EVERGREEN_GRPH_UPDATE_LOCK;
88 WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
89
90 /* update the scanout addresses */
91 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
92 upper_32_bits(crtc_base));
93 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
94 (u32)crtc_base);
95
96 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
97 upper_32_bits(crtc_base));
98 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
99 (u32)crtc_base);
100
101 /* Wait for update_pending to go high. */
102 while (!(RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING));
103 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
104
105 /* Unlock the lock, so double-buffering can take place inside vblank */
106 tmp &= ~EVERGREEN_GRPH_UPDATE_LOCK;
107 WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
108
109 /* Return current update_pending status: */
110 return RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING;
111 }
112
113 /* get temperature in millidegrees */
114 int evergreen_get_temp(struct radeon_device *rdev)
115 {
116 u32 temp, toffset;
117 int actual_temp = 0;
118
119 if (rdev->family == CHIP_JUNIPER) {
120 toffset = (RREG32(CG_THERMAL_CTRL) & TOFFSET_MASK) >>
121 TOFFSET_SHIFT;
122 temp = (RREG32(CG_TS0_STATUS) & TS0_ADC_DOUT_MASK) >>
123 TS0_ADC_DOUT_SHIFT;
124
125 if (toffset & 0x100)
126 actual_temp = temp / 2 - (0x200 - toffset);
127 else
128 actual_temp = temp / 2 + toffset;
129
130 actual_temp = actual_temp * 1000;
131
132 } else {
133 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >>
134 ASIC_T_SHIFT;
135
136 if (temp & 0x400)
137 actual_temp = -256;
138 else if (temp & 0x200)
139 actual_temp = 255;
140 else if (temp & 0x100) {
141 actual_temp = temp & 0x1ff;
142 actual_temp |= ~0x1ff;
143 } else
144 actual_temp = temp & 0xff;
145
146 actual_temp = (actual_temp * 1000) / 2;
147 }
148
149 return actual_temp;
150 }
151
152 int sumo_get_temp(struct radeon_device *rdev)
153 {
154 u32 temp = RREG32(CG_THERMAL_STATUS) & 0xff;
155 int actual_temp = temp - 49;
156
157 return actual_temp * 1000;
158 }
159
160 void evergreen_pm_misc(struct radeon_device *rdev)
161 {
162 int req_ps_idx = rdev->pm.requested_power_state_index;
163 int req_cm_idx = rdev->pm.requested_clock_mode_index;
164 struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
165 struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
166
167 if (voltage->type == VOLTAGE_SW) {
168 /* 0xff01 is a flag rather then an actual voltage */
169 if (voltage->voltage == 0xff01)
170 return;
171 if (voltage->voltage && (voltage->voltage != rdev->pm.current_vddc)) {
172 radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
173 rdev->pm.current_vddc = voltage->voltage;
174 DRM_DEBUG("Setting: vddc: %d\n", voltage->voltage);
175 }
176 /* 0xff01 is a flag rather then an actual voltage */
177 if (voltage->vddci == 0xff01)
178 return;
179 if (voltage->vddci && (voltage->vddci != rdev->pm.current_vddci)) {
180 radeon_atom_set_voltage(rdev, voltage->vddci, SET_VOLTAGE_TYPE_ASIC_VDDCI);
181 rdev->pm.current_vddci = voltage->vddci;
182 DRM_DEBUG("Setting: vddci: %d\n", voltage->vddci);
183 }
184 }
185 }
186
187 void evergreen_pm_prepare(struct radeon_device *rdev)
188 {
189 struct drm_device *ddev = rdev->ddev;
190 struct drm_crtc *crtc;
191 struct radeon_crtc *radeon_crtc;
192 u32 tmp;
193
194 /* disable any active CRTCs */
195 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
196 radeon_crtc = to_radeon_crtc(crtc);
197 if (radeon_crtc->enabled) {
198 tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
199 tmp |= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
200 WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
201 }
202 }
203 }
204
205 void evergreen_pm_finish(struct radeon_device *rdev)
206 {
207 struct drm_device *ddev = rdev->ddev;
208 struct drm_crtc *crtc;
209 struct radeon_crtc *radeon_crtc;
210 u32 tmp;
211
212 /* enable any active CRTCs */
213 list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
214 radeon_crtc = to_radeon_crtc(crtc);
215 if (radeon_crtc->enabled) {
216 tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
217 tmp &= ~EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
218 WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
219 }
220 }
221 }
222
223 bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
224 {
225 bool connected = false;
226
227 switch (hpd) {
228 case RADEON_HPD_1:
229 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
230 connected = true;
231 break;
232 case RADEON_HPD_2:
233 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
234 connected = true;
235 break;
236 case RADEON_HPD_3:
237 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
238 connected = true;
239 break;
240 case RADEON_HPD_4:
241 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
242 connected = true;
243 break;
244 case RADEON_HPD_5:
245 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
246 connected = true;
247 break;
248 case RADEON_HPD_6:
249 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
250 connected = true;
251 break;
252 default:
253 break;
254 }
255
256 return connected;
257 }
258
259 void evergreen_hpd_set_polarity(struct radeon_device *rdev,
260 enum radeon_hpd_id hpd)
261 {
262 u32 tmp;
263 bool connected = evergreen_hpd_sense(rdev, hpd);
264
265 switch (hpd) {
266 case RADEON_HPD_1:
267 tmp = RREG32(DC_HPD1_INT_CONTROL);
268 if (connected)
269 tmp &= ~DC_HPDx_INT_POLARITY;
270 else
271 tmp |= DC_HPDx_INT_POLARITY;
272 WREG32(DC_HPD1_INT_CONTROL, tmp);
273 break;
274 case RADEON_HPD_2:
275 tmp = RREG32(DC_HPD2_INT_CONTROL);
276 if (connected)
277 tmp &= ~DC_HPDx_INT_POLARITY;
278 else
279 tmp |= DC_HPDx_INT_POLARITY;
280 WREG32(DC_HPD2_INT_CONTROL, tmp);
281 break;
282 case RADEON_HPD_3:
283 tmp = RREG32(DC_HPD3_INT_CONTROL);
284 if (connected)
285 tmp &= ~DC_HPDx_INT_POLARITY;
286 else
287 tmp |= DC_HPDx_INT_POLARITY;
288 WREG32(DC_HPD3_INT_CONTROL, tmp);
289 break;
290 case RADEON_HPD_4:
291 tmp = RREG32(DC_HPD4_INT_CONTROL);
292 if (connected)
293 tmp &= ~DC_HPDx_INT_POLARITY;
294 else
295 tmp |= DC_HPDx_INT_POLARITY;
296 WREG32(DC_HPD4_INT_CONTROL, tmp);
297 break;
298 case RADEON_HPD_5:
299 tmp = RREG32(DC_HPD5_INT_CONTROL);
300 if (connected)
301 tmp &= ~DC_HPDx_INT_POLARITY;
302 else
303 tmp |= DC_HPDx_INT_POLARITY;
304 WREG32(DC_HPD5_INT_CONTROL, tmp);
305 break;
306 case RADEON_HPD_6:
307 tmp = RREG32(DC_HPD6_INT_CONTROL);
308 if (connected)
309 tmp &= ~DC_HPDx_INT_POLARITY;
310 else
311 tmp |= DC_HPDx_INT_POLARITY;
312 WREG32(DC_HPD6_INT_CONTROL, tmp);
313 break;
314 default:
315 break;
316 }
317 }
318
319 void evergreen_hpd_init(struct radeon_device *rdev)
320 {
321 struct drm_device *dev = rdev->ddev;
322 struct drm_connector *connector;
323 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) |
324 DC_HPDx_RX_INT_TIMER(0xfa) | DC_HPDx_EN;
325
326 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
327 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
328 switch (radeon_connector->hpd.hpd) {
329 case RADEON_HPD_1:
330 WREG32(DC_HPD1_CONTROL, tmp);
331 rdev->irq.hpd[0] = true;
332 break;
333 case RADEON_HPD_2:
334 WREG32(DC_HPD2_CONTROL, tmp);
335 rdev->irq.hpd[1] = true;
336 break;
337 case RADEON_HPD_3:
338 WREG32(DC_HPD3_CONTROL, tmp);
339 rdev->irq.hpd[2] = true;
340 break;
341 case RADEON_HPD_4:
342 WREG32(DC_HPD4_CONTROL, tmp);
343 rdev->irq.hpd[3] = true;
344 break;
345 case RADEON_HPD_5:
346 WREG32(DC_HPD5_CONTROL, tmp);
347 rdev->irq.hpd[4] = true;
348 break;
349 case RADEON_HPD_6:
350 WREG32(DC_HPD6_CONTROL, tmp);
351 rdev->irq.hpd[5] = true;
352 break;
353 default:
354 break;
355 }
356 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
357 }
358 if (rdev->irq.installed)
359 evergreen_irq_set(rdev);
360 }
361
362 void evergreen_hpd_fini(struct radeon_device *rdev)
363 {
364 struct drm_device *dev = rdev->ddev;
365 struct drm_connector *connector;
366
367 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
368 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
369 switch (radeon_connector->hpd.hpd) {
370 case RADEON_HPD_1:
371 WREG32(DC_HPD1_CONTROL, 0);
372 rdev->irq.hpd[0] = false;
373 break;
374 case RADEON_HPD_2:
375 WREG32(DC_HPD2_CONTROL, 0);
376 rdev->irq.hpd[1] = false;
377 break;
378 case RADEON_HPD_3:
379 WREG32(DC_HPD3_CONTROL, 0);
380 rdev->irq.hpd[2] = false;
381 break;
382 case RADEON_HPD_4:
383 WREG32(DC_HPD4_CONTROL, 0);
384 rdev->irq.hpd[3] = false;
385 break;
386 case RADEON_HPD_5:
387 WREG32(DC_HPD5_CONTROL, 0);
388 rdev->irq.hpd[4] = false;
389 break;
390 case RADEON_HPD_6:
391 WREG32(DC_HPD6_CONTROL, 0);
392 rdev->irq.hpd[5] = false;
393 break;
394 default:
395 break;
396 }
397 }
398 }
399
400 /* watermark setup */
401
402 static u32 evergreen_line_buffer_adjust(struct radeon_device *rdev,
403 struct radeon_crtc *radeon_crtc,
404 struct drm_display_mode *mode,
405 struct drm_display_mode *other_mode)
406 {
407 u32 tmp;
408 /*
409 * Line Buffer Setup
410 * There are 3 line buffers, each one shared by 2 display controllers.
411 * DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
412 * the display controllers. The paritioning is done via one of four
413 * preset allocations specified in bits 2:0:
414 * first display controller
415 * 0 - first half of lb (3840 * 2)
416 * 1 - first 3/4 of lb (5760 * 2)
417 * 2 - whole lb (7680 * 2), other crtc must be disabled
418 * 3 - first 1/4 of lb (1920 * 2)
419 * second display controller
420 * 4 - second half of lb (3840 * 2)
421 * 5 - second 3/4 of lb (5760 * 2)
422 * 6 - whole lb (7680 * 2), other crtc must be disabled
423 * 7 - last 1/4 of lb (1920 * 2)
424 */
425 /* this can get tricky if we have two large displays on a paired group
426 * of crtcs. Ideally for multiple large displays we'd assign them to
427 * non-linked crtcs for maximum line buffer allocation.
428 */
429 if (radeon_crtc->base.enabled && mode) {
430 if (other_mode)
431 tmp = 0; /* 1/2 */
432 else
433 tmp = 2; /* whole */
434 } else
435 tmp = 0;
436
437 /* second controller of the pair uses second half of the lb */
438 if (radeon_crtc->crtc_id % 2)
439 tmp += 4;
440 WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset, tmp);
441
442 if (radeon_crtc->base.enabled && mode) {
443 switch (tmp) {
444 case 0:
445 case 4:
446 default:
447 if (ASIC_IS_DCE5(rdev))
448 return 4096 * 2;
449 else
450 return 3840 * 2;
451 case 1:
452 case 5:
453 if (ASIC_IS_DCE5(rdev))
454 return 6144 * 2;
455 else
456 return 5760 * 2;
457 case 2:
458 case 6:
459 if (ASIC_IS_DCE5(rdev))
460 return 8192 * 2;
461 else
462 return 7680 * 2;
463 case 3:
464 case 7:
465 if (ASIC_IS_DCE5(rdev))
466 return 2048 * 2;
467 else
468 return 1920 * 2;
469 }
470 }
471
472 /* controller not enabled, so no lb used */
473 return 0;
474 }
475
476 static u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev)
477 {
478 u32 tmp = RREG32(MC_SHARED_CHMAP);
479
480 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
481 case 0:
482 default:
483 return 1;
484 case 1:
485 return 2;
486 case 2:
487 return 4;
488 case 3:
489 return 8;
490 }
491 }
492
493 struct evergreen_wm_params {
494 u32 dram_channels; /* number of dram channels */
495 u32 yclk; /* bandwidth per dram data pin in kHz */
496 u32 sclk; /* engine clock in kHz */
497 u32 disp_clk; /* display clock in kHz */
498 u32 src_width; /* viewport width */
499 u32 active_time; /* active display time in ns */
500 u32 blank_time; /* blank time in ns */
501 bool interlaced; /* mode is interlaced */
502 fixed20_12 vsc; /* vertical scale ratio */
503 u32 num_heads; /* number of active crtcs */
504 u32 bytes_per_pixel; /* bytes per pixel display + overlay */
505 u32 lb_size; /* line buffer allocated to pipe */
506 u32 vtaps; /* vertical scaler taps */
507 };
508
509 static u32 evergreen_dram_bandwidth(struct evergreen_wm_params *wm)
510 {
511 /* Calculate DRAM Bandwidth and the part allocated to display. */
512 fixed20_12 dram_efficiency; /* 0.7 */
513 fixed20_12 yclk, dram_channels, bandwidth;
514 fixed20_12 a;
515
516 a.full = dfixed_const(1000);
517 yclk.full = dfixed_const(wm->yclk);
518 yclk.full = dfixed_div(yclk, a);
519 dram_channels.full = dfixed_const(wm->dram_channels * 4);
520 a.full = dfixed_const(10);
521 dram_efficiency.full = dfixed_const(7);
522 dram_efficiency.full = dfixed_div(dram_efficiency, a);
523 bandwidth.full = dfixed_mul(dram_channels, yclk);
524 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
525
526 return dfixed_trunc(bandwidth);
527 }
528
529 static u32 evergreen_dram_bandwidth_for_display(struct evergreen_wm_params *wm)
530 {
531 /* Calculate DRAM Bandwidth and the part allocated to display. */
532 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
533 fixed20_12 yclk, dram_channels, bandwidth;
534 fixed20_12 a;
535
536 a.full = dfixed_const(1000);
537 yclk.full = dfixed_const(wm->yclk);
538 yclk.full = dfixed_div(yclk, a);
539 dram_channels.full = dfixed_const(wm->dram_channels * 4);
540 a.full = dfixed_const(10);
541 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
542 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
543 bandwidth.full = dfixed_mul(dram_channels, yclk);
544 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
545
546 return dfixed_trunc(bandwidth);
547 }
548
549 static u32 evergreen_data_return_bandwidth(struct evergreen_wm_params *wm)
550 {
551 /* Calculate the display Data return Bandwidth */
552 fixed20_12 return_efficiency; /* 0.8 */
553 fixed20_12 sclk, bandwidth;
554 fixed20_12 a;
555
556 a.full = dfixed_const(1000);
557 sclk.full = dfixed_const(wm->sclk);
558 sclk.full = dfixed_div(sclk, a);
559 a.full = dfixed_const(10);
560 return_efficiency.full = dfixed_const(8);
561 return_efficiency.full = dfixed_div(return_efficiency, a);
562 a.full = dfixed_const(32);
563 bandwidth.full = dfixed_mul(a, sclk);
564 bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
565
566 return dfixed_trunc(bandwidth);
567 }
568
569 static u32 evergreen_dmif_request_bandwidth(struct evergreen_wm_params *wm)
570 {
571 /* Calculate the DMIF Request Bandwidth */
572 fixed20_12 disp_clk_request_efficiency; /* 0.8 */
573 fixed20_12 disp_clk, bandwidth;
574 fixed20_12 a;
575
576 a.full = dfixed_const(1000);
577 disp_clk.full = dfixed_const(wm->disp_clk);
578 disp_clk.full = dfixed_div(disp_clk, a);
579 a.full = dfixed_const(10);
580 disp_clk_request_efficiency.full = dfixed_const(8);
581 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
582 a.full = dfixed_const(32);
583 bandwidth.full = dfixed_mul(a, disp_clk);
584 bandwidth.full = dfixed_mul(bandwidth, disp_clk_request_efficiency);
585
586 return dfixed_trunc(bandwidth);
587 }
588
589 static u32 evergreen_available_bandwidth(struct evergreen_wm_params *wm)
590 {
591 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
592 u32 dram_bandwidth = evergreen_dram_bandwidth(wm);
593 u32 data_return_bandwidth = evergreen_data_return_bandwidth(wm);
594 u32 dmif_req_bandwidth = evergreen_dmif_request_bandwidth(wm);
595
596 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
597 }
598
599 static u32 evergreen_average_bandwidth(struct evergreen_wm_params *wm)
600 {
601 /* Calculate the display mode Average Bandwidth
602 * DisplayMode should contain the source and destination dimensions,
603 * timing, etc.
604 */
605 fixed20_12 bpp;
606 fixed20_12 line_time;
607 fixed20_12 src_width;
608 fixed20_12 bandwidth;
609 fixed20_12 a;
610
611 a.full = dfixed_const(1000);
612 line_time.full = dfixed_const(wm->active_time + wm->blank_time);
613 line_time.full = dfixed_div(line_time, a);
614 bpp.full = dfixed_const(wm->bytes_per_pixel);
615 src_width.full = dfixed_const(wm->src_width);
616 bandwidth.full = dfixed_mul(src_width, bpp);
617 bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
618 bandwidth.full = dfixed_div(bandwidth, line_time);
619
620 return dfixed_trunc(bandwidth);
621 }
622
623 static u32 evergreen_latency_watermark(struct evergreen_wm_params *wm)
624 {
625 /* First calcualte the latency in ns */
626 u32 mc_latency = 2000; /* 2000 ns. */
627 u32 available_bandwidth = evergreen_available_bandwidth(wm);
628 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
629 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
630 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
631 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
632 (wm->num_heads * cursor_line_pair_return_time);
633 u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
634 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
635 fixed20_12 a, b, c;
636
637 if (wm->num_heads == 0)
638 return 0;
639
640 a.full = dfixed_const(2);
641 b.full = dfixed_const(1);
642 if ((wm->vsc.full > a.full) ||
643 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
644 (wm->vtaps >= 5) ||
645 ((wm->vsc.full >= a.full) && wm->interlaced))
646 max_src_lines_per_dst_line = 4;
647 else
648 max_src_lines_per_dst_line = 2;
649
650 a.full = dfixed_const(available_bandwidth);
651 b.full = dfixed_const(wm->num_heads);
652 a.full = dfixed_div(a, b);
653
654 b.full = dfixed_const(1000);
655 c.full = dfixed_const(wm->disp_clk);
656 b.full = dfixed_div(c, b);
657 c.full = dfixed_const(wm->bytes_per_pixel);
658 b.full = dfixed_mul(b, c);
659
660 lb_fill_bw = min(dfixed_trunc(a), dfixed_trunc(b));
661
662 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
663 b.full = dfixed_const(1000);
664 c.full = dfixed_const(lb_fill_bw);
665 b.full = dfixed_div(c, b);
666 a.full = dfixed_div(a, b);
667 line_fill_time = dfixed_trunc(a);
668
669 if (line_fill_time < wm->active_time)
670 return latency;
671 else
672 return latency + (line_fill_time - wm->active_time);
673
674 }
675
676 static bool evergreen_average_bandwidth_vs_dram_bandwidth_for_display(struct evergreen_wm_params *wm)
677 {
678 if (evergreen_average_bandwidth(wm) <=
679 (evergreen_dram_bandwidth_for_display(wm) / wm->num_heads))
680 return true;
681 else
682 return false;
683 };
684
685 static bool evergreen_average_bandwidth_vs_available_bandwidth(struct evergreen_wm_params *wm)
686 {
687 if (evergreen_average_bandwidth(wm) <=
688 (evergreen_available_bandwidth(wm) / wm->num_heads))
689 return true;
690 else
691 return false;
692 };
693
694 static bool evergreen_check_latency_hiding(struct evergreen_wm_params *wm)
695 {
696 u32 lb_partitions = wm->lb_size / wm->src_width;
697 u32 line_time = wm->active_time + wm->blank_time;
698 u32 latency_tolerant_lines;
699 u32 latency_hiding;
700 fixed20_12 a;
701
702 a.full = dfixed_const(1);
703 if (wm->vsc.full > a.full)
704 latency_tolerant_lines = 1;
705 else {
706 if (lb_partitions <= (wm->vtaps + 1))
707 latency_tolerant_lines = 1;
708 else
709 latency_tolerant_lines = 2;
710 }
711
712 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
713
714 if (evergreen_latency_watermark(wm) <= latency_hiding)
715 return true;
716 else
717 return false;
718 }
719
720 static void evergreen_program_watermarks(struct radeon_device *rdev,
721 struct radeon_crtc *radeon_crtc,
722 u32 lb_size, u32 num_heads)
723 {
724 struct drm_display_mode *mode = &radeon_crtc->base.mode;
725 struct evergreen_wm_params wm;
726 u32 pixel_period;
727 u32 line_time = 0;
728 u32 latency_watermark_a = 0, latency_watermark_b = 0;
729 u32 priority_a_mark = 0, priority_b_mark = 0;
730 u32 priority_a_cnt = PRIORITY_OFF;
731 u32 priority_b_cnt = PRIORITY_OFF;
732 u32 pipe_offset = radeon_crtc->crtc_id * 16;
733 u32 tmp, arb_control3;
734 fixed20_12 a, b, c;
735
736 if (radeon_crtc->base.enabled && num_heads && mode) {
737 pixel_period = 1000000 / (u32)mode->clock;
738 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
739 priority_a_cnt = 0;
740 priority_b_cnt = 0;
741
742 wm.yclk = rdev->pm.current_mclk * 10;
743 wm.sclk = rdev->pm.current_sclk * 10;
744 wm.disp_clk = mode->clock;
745 wm.src_width = mode->crtc_hdisplay;
746 wm.active_time = mode->crtc_hdisplay * pixel_period;
747 wm.blank_time = line_time - wm.active_time;
748 wm.interlaced = false;
749 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
750 wm.interlaced = true;
751 wm.vsc = radeon_crtc->vsc;
752 wm.vtaps = 1;
753 if (radeon_crtc->rmx_type != RMX_OFF)
754 wm.vtaps = 2;
755 wm.bytes_per_pixel = 4; /* XXX: get this from fb config */
756 wm.lb_size = lb_size;
757 wm.dram_channels = evergreen_get_number_of_dram_channels(rdev);
758 wm.num_heads = num_heads;
759
760 /* set for high clocks */
761 latency_watermark_a = min(evergreen_latency_watermark(&wm), (u32)65535);
762 /* set for low clocks */
763 /* wm.yclk = low clk; wm.sclk = low clk */
764 latency_watermark_b = min(evergreen_latency_watermark(&wm), (u32)65535);
765
766 /* possibly force display priority to high */
767 /* should really do this at mode validation time... */
768 if (!evergreen_average_bandwidth_vs_dram_bandwidth_for_display(&wm) ||
769 !evergreen_average_bandwidth_vs_available_bandwidth(&wm) ||
770 !evergreen_check_latency_hiding(&wm) ||
771 (rdev->disp_priority == 2)) {
772 DRM_DEBUG_KMS("force priority to high\n");
773 priority_a_cnt |= PRIORITY_ALWAYS_ON;
774 priority_b_cnt |= PRIORITY_ALWAYS_ON;
775 }
776
777 a.full = dfixed_const(1000);
778 b.full = dfixed_const(mode->clock);
779 b.full = dfixed_div(b, a);
780 c.full = dfixed_const(latency_watermark_a);
781 c.full = dfixed_mul(c, b);
782 c.full = dfixed_mul(c, radeon_crtc->hsc);
783 c.full = dfixed_div(c, a);
784 a.full = dfixed_const(16);
785 c.full = dfixed_div(c, a);
786 priority_a_mark = dfixed_trunc(c);
787 priority_a_cnt |= priority_a_mark & PRIORITY_MARK_MASK;
788
789 a.full = dfixed_const(1000);
790 b.full = dfixed_const(mode->clock);
791 b.full = dfixed_div(b, a);
792 c.full = dfixed_const(latency_watermark_b);
793 c.full = dfixed_mul(c, b);
794 c.full = dfixed_mul(c, radeon_crtc->hsc);
795 c.full = dfixed_div(c, a);
796 a.full = dfixed_const(16);
797 c.full = dfixed_div(c, a);
798 priority_b_mark = dfixed_trunc(c);
799 priority_b_cnt |= priority_b_mark & PRIORITY_MARK_MASK;
800 }
801
802 /* select wm A */
803 arb_control3 = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset);
804 tmp = arb_control3;
805 tmp &= ~LATENCY_WATERMARK_MASK(3);
806 tmp |= LATENCY_WATERMARK_MASK(1);
807 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);
808 WREG32(PIPE0_LATENCY_CONTROL + pipe_offset,
809 (LATENCY_LOW_WATERMARK(latency_watermark_a) |
810 LATENCY_HIGH_WATERMARK(line_time)));
811 /* select wm B */
812 tmp = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset);
813 tmp &= ~LATENCY_WATERMARK_MASK(3);
814 tmp |= LATENCY_WATERMARK_MASK(2);
815 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);
816 WREG32(PIPE0_LATENCY_CONTROL + pipe_offset,
817 (LATENCY_LOW_WATERMARK(latency_watermark_b) |
818 LATENCY_HIGH_WATERMARK(line_time)));
819 /* restore original selection */
820 WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, arb_control3);
821
822 /* write the priority marks */
823 WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt);
824 WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt);
825
826 }
827
828 void evergreen_bandwidth_update(struct radeon_device *rdev)
829 {
830 struct drm_display_mode *mode0 = NULL;
831 struct drm_display_mode *mode1 = NULL;
832 u32 num_heads = 0, lb_size;
833 int i;
834
835 radeon_update_display_priority(rdev);
836
837 for (i = 0; i < rdev->num_crtc; i++) {
838 if (rdev->mode_info.crtcs[i]->base.enabled)
839 num_heads++;
840 }
841 for (i = 0; i < rdev->num_crtc; i += 2) {
842 mode0 = &rdev->mode_info.crtcs[i]->base.mode;
843 mode1 = &rdev->mode_info.crtcs[i+1]->base.mode;
844 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i], mode0, mode1);
845 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i], lb_size, num_heads);
846 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i+1], mode1, mode0);
847 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i+1], lb_size, num_heads);
848 }
849 }
850
851 int evergreen_mc_wait_for_idle(struct radeon_device *rdev)
852 {
853 unsigned i;
854 u32 tmp;
855
856 for (i = 0; i < rdev->usec_timeout; i++) {
857 /* read MC_STATUS */
858 tmp = RREG32(SRBM_STATUS) & 0x1F00;
859 if (!tmp)
860 return 0;
861 udelay(1);
862 }
863 return -1;
864 }
865
866 /*
867 * GART
868 */
869 void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev)
870 {
871 unsigned i;
872 u32 tmp;
873
874 WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
875
876 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
877 for (i = 0; i < rdev->usec_timeout; i++) {
878 /* read MC_STATUS */
879 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
880 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
881 if (tmp == 2) {
882 printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
883 return;
884 }
885 if (tmp) {
886 return;
887 }
888 udelay(1);
889 }
890 }
891
892 int evergreen_pcie_gart_enable(struct radeon_device *rdev)
893 {
894 u32 tmp;
895 int r;
896
897 if (rdev->gart.table.vram.robj == NULL) {
898 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
899 return -EINVAL;
900 }
901 r = radeon_gart_table_vram_pin(rdev);
902 if (r)
903 return r;
904 radeon_gart_restore(rdev);
905 /* Setup L2 cache */
906 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
907 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
908 EFFECTIVE_L2_QUEUE_SIZE(7));
909 WREG32(VM_L2_CNTL2, 0);
910 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
911 /* Setup TLB control */
912 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
913 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
914 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
915 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
916 if (rdev->flags & RADEON_IS_IGP) {
917 WREG32(FUS_MC_VM_MD_L1_TLB0_CNTL, tmp);
918 WREG32(FUS_MC_VM_MD_L1_TLB1_CNTL, tmp);
919 WREG32(FUS_MC_VM_MD_L1_TLB2_CNTL, tmp);
920 } else {
921 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
922 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
923 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
924 }
925 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
926 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
927 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
928 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
929 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
930 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
931 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
932 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
933 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
934 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
935 (u32)(rdev->dummy_page.addr >> 12));
936 WREG32(VM_CONTEXT1_CNTL, 0);
937
938 evergreen_pcie_gart_tlb_flush(rdev);
939 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
940 (unsigned)(rdev->mc.gtt_size >> 20),
941 (unsigned long long)rdev->gart.table_addr);
942 rdev->gart.ready = true;
943 return 0;
944 }
945
946 void evergreen_pcie_gart_disable(struct radeon_device *rdev)
947 {
948 u32 tmp;
949 int r;
950
951 /* Disable all tables */
952 WREG32(VM_CONTEXT0_CNTL, 0);
953 WREG32(VM_CONTEXT1_CNTL, 0);
954
955 /* Setup L2 cache */
956 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
957 EFFECTIVE_L2_QUEUE_SIZE(7));
958 WREG32(VM_L2_CNTL2, 0);
959 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
960 /* Setup TLB control */
961 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
962 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
963 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
964 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
965 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
966 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
967 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
968 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
969 if (rdev->gart.table.vram.robj) {
970 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
971 if (likely(r == 0)) {
972 radeon_bo_kunmap(rdev->gart.table.vram.robj);
973 radeon_bo_unpin(rdev->gart.table.vram.robj);
974 radeon_bo_unreserve(rdev->gart.table.vram.robj);
975 }
976 }
977 }
978
979 void evergreen_pcie_gart_fini(struct radeon_device *rdev)
980 {
981 evergreen_pcie_gart_disable(rdev);
982 radeon_gart_table_vram_free(rdev);
983 radeon_gart_fini(rdev);
984 }
985
986
987 void evergreen_agp_enable(struct radeon_device *rdev)
988 {
989 u32 tmp;
990
991 /* Setup L2 cache */
992 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
993 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
994 EFFECTIVE_L2_QUEUE_SIZE(7));
995 WREG32(VM_L2_CNTL2, 0);
996 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
997 /* Setup TLB control */
998 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
999 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1000 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
1001 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
1002 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
1003 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
1004 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
1005 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
1006 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
1007 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
1008 WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
1009 WREG32(VM_CONTEXT0_CNTL, 0);
1010 WREG32(VM_CONTEXT1_CNTL, 0);
1011 }
1012
1013 void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save)
1014 {
1015 save->vga_control[0] = RREG32(D1VGA_CONTROL);
1016 save->vga_control[1] = RREG32(D2VGA_CONTROL);
1017 save->vga_render_control = RREG32(VGA_RENDER_CONTROL);
1018 save->vga_hdp_control = RREG32(VGA_HDP_CONTROL);
1019 save->crtc_control[0] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET);
1020 save->crtc_control[1] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
1021 if (rdev->num_crtc >= 4) {
1022 save->vga_control[2] = RREG32(EVERGREEN_D3VGA_CONTROL);
1023 save->vga_control[3] = RREG32(EVERGREEN_D4VGA_CONTROL);
1024 save->crtc_control[2] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET);
1025 save->crtc_control[3] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
1026 }
1027 if (rdev->num_crtc >= 6) {
1028 save->vga_control[4] = RREG32(EVERGREEN_D5VGA_CONTROL);
1029 save->vga_control[5] = RREG32(EVERGREEN_D6VGA_CONTROL);
1030 save->crtc_control[4] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET);
1031 save->crtc_control[5] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
1032 }
1033
1034 /* Stop all video */
1035 WREG32(VGA_RENDER_CONTROL, 0);
1036 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1);
1037 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1);
1038 if (rdev->num_crtc >= 4) {
1039 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1);
1040 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1);
1041 }
1042 if (rdev->num_crtc >= 6) {
1043 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1);
1044 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1);
1045 }
1046 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
1047 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
1048 if (rdev->num_crtc >= 4) {
1049 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
1050 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
1051 }
1052 if (rdev->num_crtc >= 6) {
1053 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1054 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1055 }
1056 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
1057 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
1058 if (rdev->num_crtc >= 4) {
1059 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
1060 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
1061 }
1062 if (rdev->num_crtc >= 6) {
1063 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1064 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1065 }
1066
1067 WREG32(D1VGA_CONTROL, 0);
1068 WREG32(D2VGA_CONTROL, 0);
1069 if (rdev->num_crtc >= 4) {
1070 WREG32(EVERGREEN_D3VGA_CONTROL, 0);
1071 WREG32(EVERGREEN_D4VGA_CONTROL, 0);
1072 }
1073 if (rdev->num_crtc >= 6) {
1074 WREG32(EVERGREEN_D5VGA_CONTROL, 0);
1075 WREG32(EVERGREEN_D6VGA_CONTROL, 0);
1076 }
1077 }
1078
1079 void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save)
1080 {
1081 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC0_REGISTER_OFFSET,
1082 upper_32_bits(rdev->mc.vram_start));
1083 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC0_REGISTER_OFFSET,
1084 upper_32_bits(rdev->mc.vram_start));
1085 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC0_REGISTER_OFFSET,
1086 (u32)rdev->mc.vram_start);
1087 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC0_REGISTER_OFFSET,
1088 (u32)rdev->mc.vram_start);
1089
1090 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC1_REGISTER_OFFSET,
1091 upper_32_bits(rdev->mc.vram_start));
1092 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC1_REGISTER_OFFSET,
1093 upper_32_bits(rdev->mc.vram_start));
1094 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET,
1095 (u32)rdev->mc.vram_start);
1096 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET,
1097 (u32)rdev->mc.vram_start);
1098
1099 if (rdev->num_crtc >= 4) {
1100 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET,
1101 upper_32_bits(rdev->mc.vram_start));
1102 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET,
1103 upper_32_bits(rdev->mc.vram_start));
1104 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET,
1105 (u32)rdev->mc.vram_start);
1106 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET,
1107 (u32)rdev->mc.vram_start);
1108
1109 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET,
1110 upper_32_bits(rdev->mc.vram_start));
1111 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET,
1112 upper_32_bits(rdev->mc.vram_start));
1113 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET,
1114 (u32)rdev->mc.vram_start);
1115 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET,
1116 (u32)rdev->mc.vram_start);
1117 }
1118 if (rdev->num_crtc >= 6) {
1119 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET,
1120 upper_32_bits(rdev->mc.vram_start));
1121 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET,
1122 upper_32_bits(rdev->mc.vram_start));
1123 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET,
1124 (u32)rdev->mc.vram_start);
1125 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET,
1126 (u32)rdev->mc.vram_start);
1127
1128 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET,
1129 upper_32_bits(rdev->mc.vram_start));
1130 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET,
1131 upper_32_bits(rdev->mc.vram_start));
1132 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET,
1133 (u32)rdev->mc.vram_start);
1134 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET,
1135 (u32)rdev->mc.vram_start);
1136 }
1137
1138 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start));
1139 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);
1140 /* Unlock host access */
1141 WREG32(VGA_HDP_CONTROL, save->vga_hdp_control);
1142 mdelay(1);
1143 /* Restore video state */
1144 WREG32(D1VGA_CONTROL, save->vga_control[0]);
1145 WREG32(D2VGA_CONTROL, save->vga_control[1]);
1146 if (rdev->num_crtc >= 4) {
1147 WREG32(EVERGREEN_D3VGA_CONTROL, save->vga_control[2]);
1148 WREG32(EVERGREEN_D4VGA_CONTROL, save->vga_control[3]);
1149 }
1150 if (rdev->num_crtc >= 6) {
1151 WREG32(EVERGREEN_D5VGA_CONTROL, save->vga_control[4]);
1152 WREG32(EVERGREEN_D6VGA_CONTROL, save->vga_control[5]);
1153 }
1154 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1);
1155 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1);
1156 if (rdev->num_crtc >= 4) {
1157 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1);
1158 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1);
1159 }
1160 if (rdev->num_crtc >= 6) {
1161 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1);
1162 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1);
1163 }
1164 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, save->crtc_control[0]);
1165 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, save->crtc_control[1]);
1166 if (rdev->num_crtc >= 4) {
1167 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, save->crtc_control[2]);
1168 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, save->crtc_control[3]);
1169 }
1170 if (rdev->num_crtc >= 6) {
1171 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, save->crtc_control[4]);
1172 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, save->crtc_control[5]);
1173 }
1174 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
1175 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
1176 if (rdev->num_crtc >= 4) {
1177 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
1178 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
1179 }
1180 if (rdev->num_crtc >= 6) {
1181 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1182 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1183 }
1184 WREG32(VGA_RENDER_CONTROL, save->vga_render_control);
1185 }
1186
1187 void evergreen_mc_program(struct radeon_device *rdev)
1188 {
1189 struct evergreen_mc_save save;
1190 u32 tmp;
1191 int i, j;
1192
1193 /* Initialize HDP */
1194 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1195 WREG32((0x2c14 + j), 0x00000000);
1196 WREG32((0x2c18 + j), 0x00000000);
1197 WREG32((0x2c1c + j), 0x00000000);
1198 WREG32((0x2c20 + j), 0x00000000);
1199 WREG32((0x2c24 + j), 0x00000000);
1200 }
1201 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
1202
1203 evergreen_mc_stop(rdev, &save);
1204 if (evergreen_mc_wait_for_idle(rdev)) {
1205 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1206 }
1207 /* Lockout access through VGA aperture*/
1208 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
1209 /* Update configuration */
1210 if (rdev->flags & RADEON_IS_AGP) {
1211 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1212 /* VRAM before AGP */
1213 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1214 rdev->mc.vram_start >> 12);
1215 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1216 rdev->mc.gtt_end >> 12);
1217 } else {
1218 /* VRAM after AGP */
1219 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1220 rdev->mc.gtt_start >> 12);
1221 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1222 rdev->mc.vram_end >> 12);
1223 }
1224 } else {
1225 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1226 rdev->mc.vram_start >> 12);
1227 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1228 rdev->mc.vram_end >> 12);
1229 }
1230 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
1231 if (rdev->flags & RADEON_IS_IGP) {
1232 tmp = RREG32(MC_FUS_VM_FB_OFFSET) & 0x000FFFFF;
1233 tmp |= ((rdev->mc.vram_end >> 20) & 0xF) << 24;
1234 tmp |= ((rdev->mc.vram_start >> 20) & 0xF) << 20;
1235 WREG32(MC_FUS_VM_FB_OFFSET, tmp);
1236 }
1237 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
1238 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1239 WREG32(MC_VM_FB_LOCATION, tmp);
1240 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
1241 WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
1242 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
1243 if (rdev->flags & RADEON_IS_AGP) {
1244 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
1245 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
1246 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1247 } else {
1248 WREG32(MC_VM_AGP_BASE, 0);
1249 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1250 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1251 }
1252 if (evergreen_mc_wait_for_idle(rdev)) {
1253 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1254 }
1255 evergreen_mc_resume(rdev, &save);
1256 /* we need to own VRAM, so turn off the VGA renderer here
1257 * to stop it overwriting our objects */
1258 rv515_vga_render_disable(rdev);
1259 }
1260
1261 /*
1262 * CP.
1263 */
1264 void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
1265 {
1266 /* set to DX10/11 mode */
1267 radeon_ring_write(rdev, PACKET3(PACKET3_MODE_CONTROL, 0));
1268 radeon_ring_write(rdev, 1);
1269 /* FIXME: implement */
1270 radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
1271 radeon_ring_write(rdev,
1272 #ifdef __BIG_ENDIAN
1273 (2 << 0) |
1274 #endif
1275 (ib->gpu_addr & 0xFFFFFFFC));
1276 radeon_ring_write(rdev, upper_32_bits(ib->gpu_addr) & 0xFF);
1277 radeon_ring_write(rdev, ib->length_dw);
1278 }
1279
1280
1281 static int evergreen_cp_load_microcode(struct radeon_device *rdev)
1282 {
1283 const __be32 *fw_data;
1284 int i;
1285
1286 if (!rdev->me_fw || !rdev->pfp_fw)
1287 return -EINVAL;
1288
1289 r700_cp_stop(rdev);
1290 WREG32(CP_RB_CNTL,
1291 #ifdef __BIG_ENDIAN
1292 BUF_SWAP_32BIT |
1293 #endif
1294 RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
1295
1296 fw_data = (const __be32 *)rdev->pfp_fw->data;
1297 WREG32(CP_PFP_UCODE_ADDR, 0);
1298 for (i = 0; i < EVERGREEN_PFP_UCODE_SIZE; i++)
1299 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
1300 WREG32(CP_PFP_UCODE_ADDR, 0);
1301
1302 fw_data = (const __be32 *)rdev->me_fw->data;
1303 WREG32(CP_ME_RAM_WADDR, 0);
1304 for (i = 0; i < EVERGREEN_PM4_UCODE_SIZE; i++)
1305 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
1306
1307 WREG32(CP_PFP_UCODE_ADDR, 0);
1308 WREG32(CP_ME_RAM_WADDR, 0);
1309 WREG32(CP_ME_RAM_RADDR, 0);
1310 return 0;
1311 }
1312
1313 static int evergreen_cp_start(struct radeon_device *rdev)
1314 {
1315 int r, i;
1316 uint32_t cp_me;
1317
1318 r = radeon_ring_lock(rdev, 7);
1319 if (r) {
1320 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1321 return r;
1322 }
1323 radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5));
1324 radeon_ring_write(rdev, 0x1);
1325 radeon_ring_write(rdev, 0x0);
1326 radeon_ring_write(rdev, rdev->config.evergreen.max_hw_contexts - 1);
1327 radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1328 radeon_ring_write(rdev, 0);
1329 radeon_ring_write(rdev, 0);
1330 radeon_ring_unlock_commit(rdev);
1331
1332 cp_me = 0xff;
1333 WREG32(CP_ME_CNTL, cp_me);
1334
1335 r = radeon_ring_lock(rdev, evergreen_default_size + 19);
1336 if (r) {
1337 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1338 return r;
1339 }
1340
1341 /* setup clear context state */
1342 radeon_ring_write(rdev, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1343 radeon_ring_write(rdev, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
1344
1345 for (i = 0; i < evergreen_default_size; i++)
1346 radeon_ring_write(rdev, evergreen_default_state[i]);
1347
1348 radeon_ring_write(rdev, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1349 radeon_ring_write(rdev, PACKET3_PREAMBLE_END_CLEAR_STATE);
1350
1351 /* set clear context state */
1352 radeon_ring_write(rdev, PACKET3(PACKET3_CLEAR_STATE, 0));
1353 radeon_ring_write(rdev, 0);
1354
1355 /* SQ_VTX_BASE_VTX_LOC */
1356 radeon_ring_write(rdev, 0xc0026f00);
1357 radeon_ring_write(rdev, 0x00000000);
1358 radeon_ring_write(rdev, 0x00000000);
1359 radeon_ring_write(rdev, 0x00000000);
1360
1361 /* Clear consts */
1362 radeon_ring_write(rdev, 0xc0036f00);
1363 radeon_ring_write(rdev, 0x00000bc4);
1364 radeon_ring_write(rdev, 0xffffffff);
1365 radeon_ring_write(rdev, 0xffffffff);
1366 radeon_ring_write(rdev, 0xffffffff);
1367
1368 radeon_ring_write(rdev, 0xc0026900);
1369 radeon_ring_write(rdev, 0x00000316);
1370 radeon_ring_write(rdev, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
1371 radeon_ring_write(rdev, 0x00000010); /* */
1372
1373 radeon_ring_unlock_commit(rdev);
1374
1375 return 0;
1376 }
1377
1378 int evergreen_cp_resume(struct radeon_device *rdev)
1379 {
1380 u32 tmp;
1381 u32 rb_bufsz;
1382 int r;
1383
1384 /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
1385 WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
1386 SOFT_RESET_PA |
1387 SOFT_RESET_SH |
1388 SOFT_RESET_VGT |
1389 SOFT_RESET_SPI |
1390 SOFT_RESET_SX));
1391 RREG32(GRBM_SOFT_RESET);
1392 mdelay(15);
1393 WREG32(GRBM_SOFT_RESET, 0);
1394 RREG32(GRBM_SOFT_RESET);
1395
1396 /* Set ring buffer size */
1397 rb_bufsz = drm_order(rdev->cp.ring_size / 8);
1398 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1399 #ifdef __BIG_ENDIAN
1400 tmp |= BUF_SWAP_32BIT;
1401 #endif
1402 WREG32(CP_RB_CNTL, tmp);
1403 WREG32(CP_SEM_WAIT_TIMER, 0x4);
1404
1405 /* Set the write pointer delay */
1406 WREG32(CP_RB_WPTR_DELAY, 0);
1407
1408 /* Initialize the ring buffer's read and write pointers */
1409 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
1410 WREG32(CP_RB_RPTR_WR, 0);
1411 rdev->cp.wptr = 0;
1412 WREG32(CP_RB_WPTR, rdev->cp.wptr);
1413
1414 /* set the wb address wether it's enabled or not */
1415 WREG32(CP_RB_RPTR_ADDR,
1416 ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC));
1417 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
1418 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
1419
1420 if (rdev->wb.enabled)
1421 WREG32(SCRATCH_UMSK, 0xff);
1422 else {
1423 tmp |= RB_NO_UPDATE;
1424 WREG32(SCRATCH_UMSK, 0);
1425 }
1426
1427 mdelay(1);
1428 WREG32(CP_RB_CNTL, tmp);
1429
1430 WREG32(CP_RB_BASE, rdev->cp.gpu_addr >> 8);
1431 WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
1432
1433 rdev->cp.rptr = RREG32(CP_RB_RPTR);
1434
1435 evergreen_cp_start(rdev);
1436 rdev->cp.ready = true;
1437 r = radeon_ring_test(rdev);
1438 if (r) {
1439 rdev->cp.ready = false;
1440 return r;
1441 }
1442 return 0;
1443 }
1444
1445 /*
1446 * Core functions
1447 */
1448 static u32 evergreen_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
1449 u32 num_tile_pipes,
1450 u32 num_backends,
1451 u32 backend_disable_mask)
1452 {
1453 u32 backend_map = 0;
1454 u32 enabled_backends_mask = 0;
1455 u32 enabled_backends_count = 0;
1456 u32 cur_pipe;
1457 u32 swizzle_pipe[EVERGREEN_MAX_PIPES];
1458 u32 cur_backend = 0;
1459 u32 i;
1460 bool force_no_swizzle;
1461
1462 if (num_tile_pipes > EVERGREEN_MAX_PIPES)
1463 num_tile_pipes = EVERGREEN_MAX_PIPES;
1464 if (num_tile_pipes < 1)
1465 num_tile_pipes = 1;
1466 if (num_backends > EVERGREEN_MAX_BACKENDS)
1467 num_backends = EVERGREEN_MAX_BACKENDS;
1468 if (num_backends < 1)
1469 num_backends = 1;
1470
1471 for (i = 0; i < EVERGREEN_MAX_BACKENDS; ++i) {
1472 if (((backend_disable_mask >> i) & 1) == 0) {
1473 enabled_backends_mask |= (1 << i);
1474 ++enabled_backends_count;
1475 }
1476 if (enabled_backends_count == num_backends)
1477 break;
1478 }
1479
1480 if (enabled_backends_count == 0) {
1481 enabled_backends_mask = 1;
1482 enabled_backends_count = 1;
1483 }
1484
1485 if (enabled_backends_count != num_backends)
1486 num_backends = enabled_backends_count;
1487
1488 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * EVERGREEN_MAX_PIPES);
1489 switch (rdev->family) {
1490 case CHIP_CEDAR:
1491 case CHIP_REDWOOD:
1492 case CHIP_PALM:
1493 case CHIP_SUMO:
1494 case CHIP_SUMO2:
1495 case CHIP_TURKS:
1496 case CHIP_CAICOS:
1497 force_no_swizzle = false;
1498 break;
1499 case CHIP_CYPRESS:
1500 case CHIP_HEMLOCK:
1501 case CHIP_JUNIPER:
1502 case CHIP_BARTS:
1503 default:
1504 force_no_swizzle = true;
1505 break;
1506 }
1507 if (force_no_swizzle) {
1508 bool last_backend_enabled = false;
1509
1510 force_no_swizzle = false;
1511 for (i = 0; i < EVERGREEN_MAX_BACKENDS; ++i) {
1512 if (((enabled_backends_mask >> i) & 1) == 1) {
1513 if (last_backend_enabled)
1514 force_no_swizzle = true;
1515 last_backend_enabled = true;
1516 } else
1517 last_backend_enabled = false;
1518 }
1519 }
1520
1521 switch (num_tile_pipes) {
1522 case 1:
1523 case 3:
1524 case 5:
1525 case 7:
1526 DRM_ERROR("odd number of pipes!\n");
1527 break;
1528 case 2:
1529 swizzle_pipe[0] = 0;
1530 swizzle_pipe[1] = 1;
1531 break;
1532 case 4:
1533 if (force_no_swizzle) {
1534 swizzle_pipe[0] = 0;
1535 swizzle_pipe[1] = 1;
1536 swizzle_pipe[2] = 2;
1537 swizzle_pipe[3] = 3;
1538 } else {
1539 swizzle_pipe[0] = 0;
1540 swizzle_pipe[1] = 2;
1541 swizzle_pipe[2] = 1;
1542 swizzle_pipe[3] = 3;
1543 }
1544 break;
1545 case 6:
1546 if (force_no_swizzle) {
1547 swizzle_pipe[0] = 0;
1548 swizzle_pipe[1] = 1;
1549 swizzle_pipe[2] = 2;
1550 swizzle_pipe[3] = 3;
1551 swizzle_pipe[4] = 4;
1552 swizzle_pipe[5] = 5;
1553 } else {
1554 swizzle_pipe[0] = 0;
1555 swizzle_pipe[1] = 2;
1556 swizzle_pipe[2] = 4;
1557 swizzle_pipe[3] = 1;
1558 swizzle_pipe[4] = 3;
1559 swizzle_pipe[5] = 5;
1560 }
1561 break;
1562 case 8:
1563 if (force_no_swizzle) {
1564 swizzle_pipe[0] = 0;
1565 swizzle_pipe[1] = 1;
1566 swizzle_pipe[2] = 2;
1567 swizzle_pipe[3] = 3;
1568 swizzle_pipe[4] = 4;
1569 swizzle_pipe[5] = 5;
1570 swizzle_pipe[6] = 6;
1571 swizzle_pipe[7] = 7;
1572 } else {
1573 swizzle_pipe[0] = 0;
1574 swizzle_pipe[1] = 2;
1575 swizzle_pipe[2] = 4;
1576 swizzle_pipe[3] = 6;
1577 swizzle_pipe[4] = 1;
1578 swizzle_pipe[5] = 3;
1579 swizzle_pipe[6] = 5;
1580 swizzle_pipe[7] = 7;
1581 }
1582 break;
1583 }
1584
1585 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
1586 while (((1 << cur_backend) & enabled_backends_mask) == 0)
1587 cur_backend = (cur_backend + 1) % EVERGREEN_MAX_BACKENDS;
1588
1589 backend_map |= (((cur_backend & 0xf) << (swizzle_pipe[cur_pipe] * 4)));
1590
1591 cur_backend = (cur_backend + 1) % EVERGREEN_MAX_BACKENDS;
1592 }
1593
1594 return backend_map;
1595 }
1596
1597 static void evergreen_gpu_init(struct radeon_device *rdev)
1598 {
1599 u32 cc_rb_backend_disable = 0;
1600 u32 cc_gc_shader_pipe_config;
1601 u32 gb_addr_config = 0;
1602 u32 mc_shared_chmap, mc_arb_ramcfg;
1603 u32 gb_backend_map;
1604 u32 grbm_gfx_index;
1605 u32 sx_debug_1;
1606 u32 smx_dc_ctl0;
1607 u32 sq_config;
1608 u32 sq_lds_resource_mgmt;
1609 u32 sq_gpr_resource_mgmt_1;
1610 u32 sq_gpr_resource_mgmt_2;
1611 u32 sq_gpr_resource_mgmt_3;
1612 u32 sq_thread_resource_mgmt;
1613 u32 sq_thread_resource_mgmt_2;
1614 u32 sq_stack_resource_mgmt_1;
1615 u32 sq_stack_resource_mgmt_2;
1616 u32 sq_stack_resource_mgmt_3;
1617 u32 vgt_cache_invalidation;
1618 u32 hdp_host_path_cntl, tmp;
1619 int i, j, num_shader_engines, ps_thread_count;
1620
1621 switch (rdev->family) {
1622 case CHIP_CYPRESS:
1623 case CHIP_HEMLOCK:
1624 rdev->config.evergreen.num_ses = 2;
1625 rdev->config.evergreen.max_pipes = 4;
1626 rdev->config.evergreen.max_tile_pipes = 8;
1627 rdev->config.evergreen.max_simds = 10;
1628 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1629 rdev->config.evergreen.max_gprs = 256;
1630 rdev->config.evergreen.max_threads = 248;
1631 rdev->config.evergreen.max_gs_threads = 32;
1632 rdev->config.evergreen.max_stack_entries = 512;
1633 rdev->config.evergreen.sx_num_of_sets = 4;
1634 rdev->config.evergreen.sx_max_export_size = 256;
1635 rdev->config.evergreen.sx_max_export_pos_size = 64;
1636 rdev->config.evergreen.sx_max_export_smx_size = 192;
1637 rdev->config.evergreen.max_hw_contexts = 8;
1638 rdev->config.evergreen.sq_num_cf_insts = 2;
1639
1640 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1641 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1642 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1643 break;
1644 case CHIP_JUNIPER:
1645 rdev->config.evergreen.num_ses = 1;
1646 rdev->config.evergreen.max_pipes = 4;
1647 rdev->config.evergreen.max_tile_pipes = 4;
1648 rdev->config.evergreen.max_simds = 10;
1649 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1650 rdev->config.evergreen.max_gprs = 256;
1651 rdev->config.evergreen.max_threads = 248;
1652 rdev->config.evergreen.max_gs_threads = 32;
1653 rdev->config.evergreen.max_stack_entries = 512;
1654 rdev->config.evergreen.sx_num_of_sets = 4;
1655 rdev->config.evergreen.sx_max_export_size = 256;
1656 rdev->config.evergreen.sx_max_export_pos_size = 64;
1657 rdev->config.evergreen.sx_max_export_smx_size = 192;
1658 rdev->config.evergreen.max_hw_contexts = 8;
1659 rdev->config.evergreen.sq_num_cf_insts = 2;
1660
1661 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1662 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1663 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1664 break;
1665 case CHIP_REDWOOD:
1666 rdev->config.evergreen.num_ses = 1;
1667 rdev->config.evergreen.max_pipes = 4;
1668 rdev->config.evergreen.max_tile_pipes = 4;
1669 rdev->config.evergreen.max_simds = 5;
1670 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
1671 rdev->config.evergreen.max_gprs = 256;
1672 rdev->config.evergreen.max_threads = 248;
1673 rdev->config.evergreen.max_gs_threads = 32;
1674 rdev->config.evergreen.max_stack_entries = 256;
1675 rdev->config.evergreen.sx_num_of_sets = 4;
1676 rdev->config.evergreen.sx_max_export_size = 256;
1677 rdev->config.evergreen.sx_max_export_pos_size = 64;
1678 rdev->config.evergreen.sx_max_export_smx_size = 192;
1679 rdev->config.evergreen.max_hw_contexts = 8;
1680 rdev->config.evergreen.sq_num_cf_insts = 2;
1681
1682 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1683 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1684 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1685 break;
1686 case CHIP_CEDAR:
1687 default:
1688 rdev->config.evergreen.num_ses = 1;
1689 rdev->config.evergreen.max_pipes = 2;
1690 rdev->config.evergreen.max_tile_pipes = 2;
1691 rdev->config.evergreen.max_simds = 2;
1692 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1693 rdev->config.evergreen.max_gprs = 256;
1694 rdev->config.evergreen.max_threads = 192;
1695 rdev->config.evergreen.max_gs_threads = 16;
1696 rdev->config.evergreen.max_stack_entries = 256;
1697 rdev->config.evergreen.sx_num_of_sets = 4;
1698 rdev->config.evergreen.sx_max_export_size = 128;
1699 rdev->config.evergreen.sx_max_export_pos_size = 32;
1700 rdev->config.evergreen.sx_max_export_smx_size = 96;
1701 rdev->config.evergreen.max_hw_contexts = 4;
1702 rdev->config.evergreen.sq_num_cf_insts = 1;
1703
1704 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1705 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1706 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1707 break;
1708 case CHIP_PALM:
1709 rdev->config.evergreen.num_ses = 1;
1710 rdev->config.evergreen.max_pipes = 2;
1711 rdev->config.evergreen.max_tile_pipes = 2;
1712 rdev->config.evergreen.max_simds = 2;
1713 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1714 rdev->config.evergreen.max_gprs = 256;
1715 rdev->config.evergreen.max_threads = 192;
1716 rdev->config.evergreen.max_gs_threads = 16;
1717 rdev->config.evergreen.max_stack_entries = 256;
1718 rdev->config.evergreen.sx_num_of_sets = 4;
1719 rdev->config.evergreen.sx_max_export_size = 128;
1720 rdev->config.evergreen.sx_max_export_pos_size = 32;
1721 rdev->config.evergreen.sx_max_export_smx_size = 96;
1722 rdev->config.evergreen.max_hw_contexts = 4;
1723 rdev->config.evergreen.sq_num_cf_insts = 1;
1724
1725 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1726 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1727 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1728 break;
1729 case CHIP_SUMO:
1730 rdev->config.evergreen.num_ses = 1;
1731 rdev->config.evergreen.max_pipes = 4;
1732 rdev->config.evergreen.max_tile_pipes = 2;
1733 if (rdev->pdev->device == 0x9648)
1734 rdev->config.evergreen.max_simds = 3;
1735 else if ((rdev->pdev->device == 0x9647) ||
1736 (rdev->pdev->device == 0x964a))
1737 rdev->config.evergreen.max_simds = 4;
1738 else
1739 rdev->config.evergreen.max_simds = 5;
1740 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
1741 rdev->config.evergreen.max_gprs = 256;
1742 rdev->config.evergreen.max_threads = 248;
1743 rdev->config.evergreen.max_gs_threads = 32;
1744 rdev->config.evergreen.max_stack_entries = 256;
1745 rdev->config.evergreen.sx_num_of_sets = 4;
1746 rdev->config.evergreen.sx_max_export_size = 256;
1747 rdev->config.evergreen.sx_max_export_pos_size = 64;
1748 rdev->config.evergreen.sx_max_export_smx_size = 192;
1749 rdev->config.evergreen.max_hw_contexts = 8;
1750 rdev->config.evergreen.sq_num_cf_insts = 2;
1751
1752 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1753 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1754 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1755 break;
1756 case CHIP_SUMO2:
1757 rdev->config.evergreen.num_ses = 1;
1758 rdev->config.evergreen.max_pipes = 4;
1759 rdev->config.evergreen.max_tile_pipes = 4;
1760 rdev->config.evergreen.max_simds = 2;
1761 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1762 rdev->config.evergreen.max_gprs = 256;
1763 rdev->config.evergreen.max_threads = 248;
1764 rdev->config.evergreen.max_gs_threads = 32;
1765 rdev->config.evergreen.max_stack_entries = 512;
1766 rdev->config.evergreen.sx_num_of_sets = 4;
1767 rdev->config.evergreen.sx_max_export_size = 256;
1768 rdev->config.evergreen.sx_max_export_pos_size = 64;
1769 rdev->config.evergreen.sx_max_export_smx_size = 192;
1770 rdev->config.evergreen.max_hw_contexts = 8;
1771 rdev->config.evergreen.sq_num_cf_insts = 2;
1772
1773 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1774 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1775 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1776 break;
1777 case CHIP_BARTS:
1778 rdev->config.evergreen.num_ses = 2;
1779 rdev->config.evergreen.max_pipes = 4;
1780 rdev->config.evergreen.max_tile_pipes = 8;
1781 rdev->config.evergreen.max_simds = 7;
1782 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1783 rdev->config.evergreen.max_gprs = 256;
1784 rdev->config.evergreen.max_threads = 248;
1785 rdev->config.evergreen.max_gs_threads = 32;
1786 rdev->config.evergreen.max_stack_entries = 512;
1787 rdev->config.evergreen.sx_num_of_sets = 4;
1788 rdev->config.evergreen.sx_max_export_size = 256;
1789 rdev->config.evergreen.sx_max_export_pos_size = 64;
1790 rdev->config.evergreen.sx_max_export_smx_size = 192;
1791 rdev->config.evergreen.max_hw_contexts = 8;
1792 rdev->config.evergreen.sq_num_cf_insts = 2;
1793
1794 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1795 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1796 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1797 break;
1798 case CHIP_TURKS:
1799 rdev->config.evergreen.num_ses = 1;
1800 rdev->config.evergreen.max_pipes = 4;
1801 rdev->config.evergreen.max_tile_pipes = 4;
1802 rdev->config.evergreen.max_simds = 6;
1803 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
1804 rdev->config.evergreen.max_gprs = 256;
1805 rdev->config.evergreen.max_threads = 248;
1806 rdev->config.evergreen.max_gs_threads = 32;
1807 rdev->config.evergreen.max_stack_entries = 256;
1808 rdev->config.evergreen.sx_num_of_sets = 4;
1809 rdev->config.evergreen.sx_max_export_size = 256;
1810 rdev->config.evergreen.sx_max_export_pos_size = 64;
1811 rdev->config.evergreen.sx_max_export_smx_size = 192;
1812 rdev->config.evergreen.max_hw_contexts = 8;
1813 rdev->config.evergreen.sq_num_cf_insts = 2;
1814
1815 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1816 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1817 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1818 break;
1819 case CHIP_CAICOS:
1820 rdev->config.evergreen.num_ses = 1;
1821 rdev->config.evergreen.max_pipes = 4;
1822 rdev->config.evergreen.max_tile_pipes = 2;
1823 rdev->config.evergreen.max_simds = 2;
1824 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1825 rdev->config.evergreen.max_gprs = 256;
1826 rdev->config.evergreen.max_threads = 192;
1827 rdev->config.evergreen.max_gs_threads = 16;
1828 rdev->config.evergreen.max_stack_entries = 256;
1829 rdev->config.evergreen.sx_num_of_sets = 4;
1830 rdev->config.evergreen.sx_max_export_size = 128;
1831 rdev->config.evergreen.sx_max_export_pos_size = 32;
1832 rdev->config.evergreen.sx_max_export_smx_size = 96;
1833 rdev->config.evergreen.max_hw_contexts = 4;
1834 rdev->config.evergreen.sq_num_cf_insts = 1;
1835
1836 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1837 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1838 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1839 break;
1840 }
1841
1842 /* Initialize HDP */
1843 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1844 WREG32((0x2c14 + j), 0x00000000);
1845 WREG32((0x2c18 + j), 0x00000000);
1846 WREG32((0x2c1c + j), 0x00000000);
1847 WREG32((0x2c20 + j), 0x00000000);
1848 WREG32((0x2c24 + j), 0x00000000);
1849 }
1850
1851 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1852
1853 evergreen_fix_pci_max_read_req_size(rdev);
1854
1855 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & ~2;
1856
1857 cc_gc_shader_pipe_config |=
1858 INACTIVE_QD_PIPES((EVERGREEN_MAX_PIPES_MASK << rdev->config.evergreen.max_pipes)
1859 & EVERGREEN_MAX_PIPES_MASK);
1860 cc_gc_shader_pipe_config |=
1861 INACTIVE_SIMDS((EVERGREEN_MAX_SIMDS_MASK << rdev->config.evergreen.max_simds)
1862 & EVERGREEN_MAX_SIMDS_MASK);
1863
1864 cc_rb_backend_disable =
1865 BACKEND_DISABLE((EVERGREEN_MAX_BACKENDS_MASK << rdev->config.evergreen.max_backends)
1866 & EVERGREEN_MAX_BACKENDS_MASK);
1867
1868
1869 mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
1870 if (rdev->flags & RADEON_IS_IGP)
1871 mc_arb_ramcfg = RREG32(FUS_MC_ARB_RAMCFG);
1872 else
1873 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
1874
1875 switch (rdev->config.evergreen.max_tile_pipes) {
1876 case 1:
1877 default:
1878 gb_addr_config |= NUM_PIPES(0);
1879 break;
1880 case 2:
1881 gb_addr_config |= NUM_PIPES(1);
1882 break;
1883 case 4:
1884 gb_addr_config |= NUM_PIPES(2);
1885 break;
1886 case 8:
1887 gb_addr_config |= NUM_PIPES(3);
1888 break;
1889 }
1890
1891 gb_addr_config |= PIPE_INTERLEAVE_SIZE((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
1892 gb_addr_config |= BANK_INTERLEAVE_SIZE(0);
1893 gb_addr_config |= NUM_SHADER_ENGINES(rdev->config.evergreen.num_ses - 1);
1894 gb_addr_config |= SHADER_ENGINE_TILE_SIZE(1);
1895 gb_addr_config |= NUM_GPUS(0); /* Hemlock? */
1896 gb_addr_config |= MULTI_GPU_TILE_SIZE(2);
1897
1898 if (((mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) > 2)
1899 gb_addr_config |= ROW_SIZE(2);
1900 else
1901 gb_addr_config |= ROW_SIZE((mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT);
1902
1903 if (rdev->ddev->pdev->device == 0x689e) {
1904 u32 efuse_straps_4;
1905 u32 efuse_straps_3;
1906 u8 efuse_box_bit_131_124;
1907
1908 WREG32(RCU_IND_INDEX, 0x204);
1909 efuse_straps_4 = RREG32(RCU_IND_DATA);
1910 WREG32(RCU_IND_INDEX, 0x203);
1911 efuse_straps_3 = RREG32(RCU_IND_DATA);
1912 efuse_box_bit_131_124 = (u8)(((efuse_straps_4 & 0xf) << 4) | ((efuse_straps_3 & 0xf0000000) >> 28));
1913
1914 switch(efuse_box_bit_131_124) {
1915 case 0x00:
1916 gb_backend_map = 0x76543210;
1917 break;
1918 case 0x55:
1919 gb_backend_map = 0x77553311;
1920 break;
1921 case 0x56:
1922 gb_backend_map = 0x77553300;
1923 break;
1924 case 0x59:
1925 gb_backend_map = 0x77552211;
1926 break;
1927 case 0x66:
1928 gb_backend_map = 0x77443300;
1929 break;
1930 case 0x99:
1931 gb_backend_map = 0x66552211;
1932 break;
1933 case 0x5a:
1934 gb_backend_map = 0x77552200;
1935 break;
1936 case 0xaa:
1937 gb_backend_map = 0x66442200;
1938 break;
1939 case 0x95:
1940 gb_backend_map = 0x66553311;
1941 break;
1942 default:
1943 DRM_ERROR("bad backend map, using default\n");
1944 gb_backend_map =
1945 evergreen_get_tile_pipe_to_backend_map(rdev,
1946 rdev->config.evergreen.max_tile_pipes,
1947 rdev->config.evergreen.max_backends,
1948 ((EVERGREEN_MAX_BACKENDS_MASK <<
1949 rdev->config.evergreen.max_backends) &
1950 EVERGREEN_MAX_BACKENDS_MASK));
1951 break;
1952 }
1953 } else if (rdev->ddev->pdev->device == 0x68b9) {
1954 u32 efuse_straps_3;
1955 u8 efuse_box_bit_127_124;
1956
1957 WREG32(RCU_IND_INDEX, 0x203);
1958 efuse_straps_3 = RREG32(RCU_IND_DATA);
1959 efuse_box_bit_127_124 = (u8)((efuse_straps_3 & 0xF0000000) >> 28);
1960
1961 switch(efuse_box_bit_127_124) {
1962 case 0x0:
1963 gb_backend_map = 0x00003210;
1964 break;
1965 case 0x5:
1966 case 0x6:
1967 case 0x9:
1968 case 0xa:
1969 gb_backend_map = 0x00003311;
1970 break;
1971 default:
1972 DRM_ERROR("bad backend map, using default\n");
1973 gb_backend_map =
1974 evergreen_get_tile_pipe_to_backend_map(rdev,
1975 rdev->config.evergreen.max_tile_pipes,
1976 rdev->config.evergreen.max_backends,
1977 ((EVERGREEN_MAX_BACKENDS_MASK <<
1978 rdev->config.evergreen.max_backends) &
1979 EVERGREEN_MAX_BACKENDS_MASK));
1980 break;
1981 }
1982 } else {
1983 switch (rdev->family) {
1984 case CHIP_CYPRESS:
1985 case CHIP_HEMLOCK:
1986 case CHIP_BARTS:
1987 gb_backend_map = 0x66442200;
1988 break;
1989 case CHIP_JUNIPER:
1990 gb_backend_map = 0x00002200;
1991 break;
1992 default:
1993 gb_backend_map =
1994 evergreen_get_tile_pipe_to_backend_map(rdev,
1995 rdev->config.evergreen.max_tile_pipes,
1996 rdev->config.evergreen.max_backends,
1997 ((EVERGREEN_MAX_BACKENDS_MASK <<
1998 rdev->config.evergreen.max_backends) &
1999 EVERGREEN_MAX_BACKENDS_MASK));
2000 }
2001 }
2002
2003 /* setup tiling info dword. gb_addr_config is not adequate since it does
2004 * not have bank info, so create a custom tiling dword.
2005 * bits 3:0 num_pipes
2006 * bits 7:4 num_banks
2007 * bits 11:8 group_size
2008 * bits 15:12 row_size
2009 */
2010 rdev->config.evergreen.tile_config = 0;
2011 switch (rdev->config.evergreen.max_tile_pipes) {
2012 case 1:
2013 default:
2014 rdev->config.evergreen.tile_config |= (0 << 0);
2015 break;
2016 case 2:
2017 rdev->config.evergreen.tile_config |= (1 << 0);
2018 break;
2019 case 4:
2020 rdev->config.evergreen.tile_config |= (2 << 0);
2021 break;
2022 case 8:
2023 rdev->config.evergreen.tile_config |= (3 << 0);
2024 break;
2025 }
2026 /* num banks is 8 on all fusion asics. 0 = 4, 1 = 8, 2 = 16 */
2027 if (rdev->flags & RADEON_IS_IGP)
2028 rdev->config.evergreen.tile_config |= 1 << 4;
2029 else
2030 rdev->config.evergreen.tile_config |=
2031 ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) << 4;
2032 rdev->config.evergreen.tile_config |=
2033 ((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT) << 8;
2034 rdev->config.evergreen.tile_config |=
2035 ((gb_addr_config & 0x30000000) >> 28) << 12;
2036
2037 rdev->config.evergreen.backend_map = gb_backend_map;
2038 WREG32(GB_BACKEND_MAP, gb_backend_map);
2039 WREG32(GB_ADDR_CONFIG, gb_addr_config);
2040 WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
2041 WREG32(HDP_ADDR_CONFIG, gb_addr_config);
2042
2043 num_shader_engines = ((RREG32(GB_ADDR_CONFIG) & NUM_SHADER_ENGINES(3)) >> 12) + 1;
2044 grbm_gfx_index = INSTANCE_BROADCAST_WRITES;
2045
2046 for (i = 0; i < rdev->config.evergreen.num_ses; i++) {
2047 u32 rb = cc_rb_backend_disable | (0xf0 << 16);
2048 u32 sp = cc_gc_shader_pipe_config;
2049 u32 gfx = grbm_gfx_index | SE_INDEX(i);
2050
2051 if (i == num_shader_engines) {
2052 rb |= BACKEND_DISABLE(EVERGREEN_MAX_BACKENDS_MASK);
2053 sp |= INACTIVE_SIMDS(EVERGREEN_MAX_SIMDS_MASK);
2054 }
2055
2056 WREG32(GRBM_GFX_INDEX, gfx);
2057 WREG32(RLC_GFX_INDEX, gfx);
2058
2059 WREG32(CC_RB_BACKEND_DISABLE, rb);
2060 WREG32(CC_SYS_RB_BACKEND_DISABLE, rb);
2061 WREG32(GC_USER_RB_BACKEND_DISABLE, rb);
2062 WREG32(CC_GC_SHADER_PIPE_CONFIG, sp);
2063 }
2064
2065 grbm_gfx_index |= SE_BROADCAST_WRITES;
2066 WREG32(GRBM_GFX_INDEX, grbm_gfx_index);
2067 WREG32(RLC_GFX_INDEX, grbm_gfx_index);
2068
2069 WREG32(CGTS_SYS_TCC_DISABLE, 0);
2070 WREG32(CGTS_TCC_DISABLE, 0);
2071 WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);
2072 WREG32(CGTS_USER_TCC_DISABLE, 0);
2073
2074 /* set HW defaults for 3D engine */
2075 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
2076 ROQ_IB2_START(0x2b)));
2077
2078 WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));
2079
2080 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO |
2081 SYNC_GRADIENT |
2082 SYNC_WALKER |
2083 SYNC_ALIGNER));
2084
2085 sx_debug_1 = RREG32(SX_DEBUG_1);
2086 sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
2087 WREG32(SX_DEBUG_1, sx_debug_1);
2088
2089
2090 smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
2091 smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff);
2092 smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.evergreen.sx_num_of_sets);
2093 WREG32(SMX_DC_CTL0, smx_dc_ctl0);
2094
2095 WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_size / 4) - 1) |
2096 POSITION_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_pos_size / 4) - 1) |
2097 SMX_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_smx_size / 4) - 1)));
2098
2099 WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.evergreen.sc_prim_fifo_size) |
2100 SC_HIZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_hiz_tile_fifo_size) |
2101 SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_earlyz_tile_fifo_size)));
2102
2103 WREG32(VGT_NUM_INSTANCES, 1);
2104 WREG32(SPI_CONFIG_CNTL, 0);
2105 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
2106 WREG32(CP_PERFMON_CNTL, 0);
2107
2108 WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.evergreen.sq_num_cf_insts) |
2109 FETCH_FIFO_HIWATER(0x4) |
2110 DONE_FIFO_HIWATER(0xe0) |
2111 ALU_UPDATE_FIFO_HIWATER(0x8)));
2112
2113 sq_config = RREG32(SQ_CONFIG);
2114 sq_config &= ~(PS_PRIO(3) |
2115 VS_PRIO(3) |
2116 GS_PRIO(3) |
2117 ES_PRIO(3));
2118 sq_config |= (VC_ENABLE |
2119 EXPORT_SRC_C |
2120 PS_PRIO(0) |
2121 VS_PRIO(1) |
2122 GS_PRIO(2) |
2123 ES_PRIO(3));
2124
2125 switch (rdev->family) {
2126 case CHIP_CEDAR:
2127 case CHIP_PALM:
2128 case CHIP_SUMO:
2129 case CHIP_SUMO2:
2130 case CHIP_CAICOS:
2131 /* no vertex cache */
2132 sq_config &= ~VC_ENABLE;
2133 break;
2134 default:
2135 break;
2136 }
2137
2138 sq_lds_resource_mgmt = RREG32(SQ_LDS_RESOURCE_MGMT);
2139
2140 sq_gpr_resource_mgmt_1 = NUM_PS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2))* 12 / 32);
2141 sq_gpr_resource_mgmt_1 |= NUM_VS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 6 / 32);
2142 sq_gpr_resource_mgmt_1 |= NUM_CLAUSE_TEMP_GPRS(4);
2143 sq_gpr_resource_mgmt_2 = NUM_GS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);
2144 sq_gpr_resource_mgmt_2 |= NUM_ES_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);
2145 sq_gpr_resource_mgmt_3 = NUM_HS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
2146 sq_gpr_resource_mgmt_3 |= NUM_LS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
2147
2148 switch (rdev->family) {
2149 case CHIP_CEDAR:
2150 case CHIP_PALM:
2151 case CHIP_SUMO:
2152 case CHIP_SUMO2:
2153 ps_thread_count = 96;
2154 break;
2155 default:
2156 ps_thread_count = 128;
2157 break;
2158 }
2159
2160 sq_thread_resource_mgmt = NUM_PS_THREADS(ps_thread_count);
2161 sq_thread_resource_mgmt |= NUM_VS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2162 sq_thread_resource_mgmt |= NUM_GS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2163 sq_thread_resource_mgmt |= NUM_ES_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2164 sq_thread_resource_mgmt_2 = NUM_HS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2165 sq_thread_resource_mgmt_2 |= NUM_LS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2166
2167 sq_stack_resource_mgmt_1 = NUM_PS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2168 sq_stack_resource_mgmt_1 |= NUM_VS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2169 sq_stack_resource_mgmt_2 = NUM_GS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2170 sq_stack_resource_mgmt_2 |= NUM_ES_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2171 sq_stack_resource_mgmt_3 = NUM_HS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2172 sq_stack_resource_mgmt_3 |= NUM_LS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2173
2174 WREG32(SQ_CONFIG, sq_config);
2175 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
2176 WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
2177 WREG32(SQ_GPR_RESOURCE_MGMT_3, sq_gpr_resource_mgmt_3);
2178 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
2179 WREG32(SQ_THREAD_RESOURCE_MGMT_2, sq_thread_resource_mgmt_2);
2180 WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
2181 WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
2182 WREG32(SQ_STACK_RESOURCE_MGMT_3, sq_stack_resource_mgmt_3);
2183 WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
2184 WREG32(SQ_LDS_RESOURCE_MGMT, sq_lds_resource_mgmt);
2185
2186 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
2187 FORCE_EOV_MAX_REZ_CNT(255)));
2188
2189 switch (rdev->family) {
2190 case CHIP_CEDAR:
2191 case CHIP_PALM:
2192 case CHIP_SUMO:
2193 case CHIP_SUMO2:
2194 case CHIP_CAICOS:
2195 vgt_cache_invalidation = CACHE_INVALIDATION(TC_ONLY);
2196 break;
2197 default:
2198 vgt_cache_invalidation = CACHE_INVALIDATION(VC_AND_TC);
2199 break;
2200 }
2201 vgt_cache_invalidation |= AUTO_INVLD_EN(ES_AND_GS_AUTO);
2202 WREG32(VGT_CACHE_INVALIDATION, vgt_cache_invalidation);
2203
2204 WREG32(VGT_GS_VERTEX_REUSE, 16);
2205 WREG32(PA_SU_LINE_STIPPLE_VALUE, 0);
2206 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
2207
2208 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
2209 WREG32(VGT_OUT_DEALLOC_CNTL, 16);
2210
2211 WREG32(CB_PERF_CTR0_SEL_0, 0);
2212 WREG32(CB_PERF_CTR0_SEL_1, 0);
2213 WREG32(CB_PERF_CTR1_SEL_0, 0);
2214 WREG32(CB_PERF_CTR1_SEL_1, 0);
2215 WREG32(CB_PERF_CTR2_SEL_0, 0);
2216 WREG32(CB_PERF_CTR2_SEL_1, 0);
2217 WREG32(CB_PERF_CTR3_SEL_0, 0);
2218 WREG32(CB_PERF_CTR3_SEL_1, 0);
2219
2220 /* clear render buffer base addresses */
2221 WREG32(CB_COLOR0_BASE, 0);
2222 WREG32(CB_COLOR1_BASE, 0);
2223 WREG32(CB_COLOR2_BASE, 0);
2224 WREG32(CB_COLOR3_BASE, 0);
2225 WREG32(CB_COLOR4_BASE, 0);
2226 WREG32(CB_COLOR5_BASE, 0);
2227 WREG32(CB_COLOR6_BASE, 0);
2228 WREG32(CB_COLOR7_BASE, 0);
2229 WREG32(CB_COLOR8_BASE, 0);
2230 WREG32(CB_COLOR9_BASE, 0);
2231 WREG32(CB_COLOR10_BASE, 0);
2232 WREG32(CB_COLOR11_BASE, 0);
2233
2234 /* set the shader const cache sizes to 0 */
2235 for (i = SQ_ALU_CONST_BUFFER_SIZE_PS_0; i < 0x28200; i += 4)
2236 WREG32(i, 0);
2237 for (i = SQ_ALU_CONST_BUFFER_SIZE_HS_0; i < 0x29000; i += 4)
2238 WREG32(i, 0);
2239
2240 tmp = RREG32(HDP_MISC_CNTL);
2241 tmp |= HDP_FLUSH_INVALIDATE_CACHE;
2242 WREG32(HDP_MISC_CNTL, tmp);
2243
2244 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
2245 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
2246
2247 WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
2248
2249 udelay(50);
2250
2251 }
2252
2253 int evergreen_mc_init(struct radeon_device *rdev)
2254 {
2255 u32 tmp;
2256 int chansize, numchan;
2257
2258 /* Get VRAM informations */
2259 rdev->mc.vram_is_ddr = true;
2260 if (rdev->flags & RADEON_IS_IGP)
2261 tmp = RREG32(FUS_MC_ARB_RAMCFG);
2262 else
2263 tmp = RREG32(MC_ARB_RAMCFG);
2264 if (tmp & CHANSIZE_OVERRIDE) {
2265 chansize = 16;
2266 } else if (tmp & CHANSIZE_MASK) {
2267 chansize = 64;
2268 } else {
2269 chansize = 32;
2270 }
2271 tmp = RREG32(MC_SHARED_CHMAP);
2272 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
2273 case 0:
2274 default:
2275 numchan = 1;
2276 break;
2277 case 1:
2278 numchan = 2;
2279 break;
2280 case 2:
2281 numchan = 4;
2282 break;
2283 case 3:
2284 numchan = 8;
2285 break;
2286 }
2287 rdev->mc.vram_width = numchan * chansize;
2288 /* Could aper size report 0 ? */
2289 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
2290 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
2291 /* Setup GPU memory space */
2292 if (rdev->flags & RADEON_IS_IGP) {
2293 /* size in bytes on fusion */
2294 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
2295 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
2296 } else {
2297 /* size in MB on evergreen */
2298 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
2299 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
2300 }
2301 rdev->mc.visible_vram_size = rdev->mc.aper_size;
2302 r700_vram_gtt_location(rdev, &rdev->mc);
2303 radeon_update_bandwidth_info(rdev);
2304
2305 return 0;
2306 }
2307
2308 bool evergreen_gpu_is_lockup(struct radeon_device *rdev)
2309 {
2310 u32 srbm_status;
2311 u32 grbm_status;
2312 u32 grbm_status_se0, grbm_status_se1;
2313 struct r100_gpu_lockup *lockup = &rdev->config.evergreen.lockup;
2314 int r;
2315
2316 srbm_status = RREG32(SRBM_STATUS);
2317 grbm_status = RREG32(GRBM_STATUS);
2318 grbm_status_se0 = RREG32(GRBM_STATUS_SE0);
2319 grbm_status_se1 = RREG32(GRBM_STATUS_SE1);
2320 if (!(grbm_status & GUI_ACTIVE)) {
2321 r100_gpu_lockup_update(lockup, &rdev->cp);
2322 return false;
2323 }
2324 /* force CP activities */
2325 r = radeon_ring_lock(rdev, 2);
2326 if (!r) {
2327 /* PACKET2 NOP */
2328 radeon_ring_write(rdev, 0x80000000);
2329 radeon_ring_write(rdev, 0x80000000);
2330 radeon_ring_unlock_commit(rdev);
2331 }
2332 rdev->cp.rptr = RREG32(CP_RB_RPTR);
2333 return r100_gpu_cp_is_lockup(rdev, lockup, &rdev->cp);
2334 }
2335
2336 static int evergreen_gpu_soft_reset(struct radeon_device *rdev)
2337 {
2338 struct evergreen_mc_save save;
2339 u32 grbm_reset = 0;
2340
2341 if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
2342 return 0;
2343
2344 dev_info(rdev->dev, "GPU softreset \n");
2345 dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
2346 RREG32(GRBM_STATUS));
2347 dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
2348 RREG32(GRBM_STATUS_SE0));
2349 dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n",
2350 RREG32(GRBM_STATUS_SE1));
2351 dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
2352 RREG32(SRBM_STATUS));
2353 evergreen_mc_stop(rdev, &save);
2354 if (evergreen_mc_wait_for_idle(rdev)) {
2355 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
2356 }
2357 /* Disable CP parsing/prefetching */
2358 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
2359
2360 /* reset all the gfx blocks */
2361 grbm_reset = (SOFT_RESET_CP |
2362 SOFT_RESET_CB |
2363 SOFT_RESET_DB |
2364 SOFT_RESET_PA |
2365 SOFT_RESET_SC |
2366 SOFT_RESET_SPI |
2367 SOFT_RESET_SH |
2368 SOFT_RESET_SX |
2369 SOFT_RESET_TC |
2370 SOFT_RESET_TA |
2371 SOFT_RESET_VC |
2372 SOFT_RESET_VGT);
2373
2374 dev_info(rdev->dev, " GRBM_SOFT_RESET=0x%08X\n", grbm_reset);
2375 WREG32(GRBM_SOFT_RESET, grbm_reset);
2376 (void)RREG32(GRBM_SOFT_RESET);
2377 udelay(50);
2378 WREG32(GRBM_SOFT_RESET, 0);
2379 (void)RREG32(GRBM_SOFT_RESET);
2380 /* Wait a little for things to settle down */
2381 udelay(50);
2382 dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
2383 RREG32(GRBM_STATUS));
2384 dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
2385 RREG32(GRBM_STATUS_SE0));
2386 dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n",
2387 RREG32(GRBM_STATUS_SE1));
2388 dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
2389 RREG32(SRBM_STATUS));
2390 evergreen_mc_resume(rdev, &save);
2391 return 0;
2392 }
2393
2394 int evergreen_asic_reset(struct radeon_device *rdev)
2395 {
2396 return evergreen_gpu_soft_reset(rdev);
2397 }
2398
2399 /* Interrupts */
2400
2401 u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc)
2402 {
2403 switch (crtc) {
2404 case 0:
2405 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC0_REGISTER_OFFSET);
2406 case 1:
2407 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC1_REGISTER_OFFSET);
2408 case 2:
2409 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC2_REGISTER_OFFSET);
2410 case 3:
2411 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC3_REGISTER_OFFSET);
2412 case 4:
2413 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC4_REGISTER_OFFSET);
2414 case 5:
2415 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC5_REGISTER_OFFSET);
2416 default:
2417 return 0;
2418 }
2419 }
2420
2421 void evergreen_disable_interrupt_state(struct radeon_device *rdev)
2422 {
2423 u32 tmp;
2424
2425 WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
2426 WREG32(GRBM_INT_CNTL, 0);
2427 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
2428 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
2429 if (rdev->num_crtc >= 4) {
2430 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
2431 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
2432 }
2433 if (rdev->num_crtc >= 6) {
2434 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
2435 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
2436 }
2437
2438 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
2439 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
2440 if (rdev->num_crtc >= 4) {
2441 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
2442 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
2443 }
2444 if (rdev->num_crtc >= 6) {
2445 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
2446 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
2447 }
2448
2449 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
2450 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
2451
2452 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2453 WREG32(DC_HPD1_INT_CONTROL, tmp);
2454 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2455 WREG32(DC_HPD2_INT_CONTROL, tmp);
2456 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2457 WREG32(DC_HPD3_INT_CONTROL, tmp);
2458 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2459 WREG32(DC_HPD4_INT_CONTROL, tmp);
2460 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2461 WREG32(DC_HPD5_INT_CONTROL, tmp);
2462 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2463 WREG32(DC_HPD6_INT_CONTROL, tmp);
2464
2465 }
2466
2467 int evergreen_irq_set(struct radeon_device *rdev)
2468 {
2469 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
2470 u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0;
2471 u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6;
2472 u32 grbm_int_cntl = 0;
2473 u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0;
2474
2475 if (!rdev->irq.installed) {
2476 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
2477 return -EINVAL;
2478 }
2479 /* don't enable anything if the ih is disabled */
2480 if (!rdev->ih.enabled) {
2481 r600_disable_interrupts(rdev);
2482 /* force the active interrupt state to all disabled */
2483 evergreen_disable_interrupt_state(rdev);
2484 return 0;
2485 }
2486
2487 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
2488 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
2489 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
2490 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
2491 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
2492 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
2493
2494 if (rdev->irq.sw_int) {
2495 DRM_DEBUG("evergreen_irq_set: sw int\n");
2496 cp_int_cntl |= RB_INT_ENABLE;
2497 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
2498 }
2499 if (rdev->irq.crtc_vblank_int[0] ||
2500 rdev->irq.pflip[0]) {
2501 DRM_DEBUG("evergreen_irq_set: vblank 0\n");
2502 crtc1 |= VBLANK_INT_MASK;
2503 }
2504 if (rdev->irq.crtc_vblank_int[1] ||
2505 rdev->irq.pflip[1]) {
2506 DRM_DEBUG("evergreen_irq_set: vblank 1\n");
2507 crtc2 |= VBLANK_INT_MASK;
2508 }
2509 if (rdev->irq.crtc_vblank_int[2] ||
2510 rdev->irq.pflip[2]) {
2511 DRM_DEBUG("evergreen_irq_set: vblank 2\n");
2512 crtc3 |= VBLANK_INT_MASK;
2513 }
2514 if (rdev->irq.crtc_vblank_int[3] ||
2515 rdev->irq.pflip[3]) {
2516 DRM_DEBUG("evergreen_irq_set: vblank 3\n");
2517 crtc4 |= VBLANK_INT_MASK;
2518 }
2519 if (rdev->irq.crtc_vblank_int[4] ||
2520 rdev->irq.pflip[4]) {
2521 DRM_DEBUG("evergreen_irq_set: vblank 4\n");
2522 crtc5 |= VBLANK_INT_MASK;
2523 }
2524 if (rdev->irq.crtc_vblank_int[5] ||
2525 rdev->irq.pflip[5]) {
2526 DRM_DEBUG("evergreen_irq_set: vblank 5\n");
2527 crtc6 |= VBLANK_INT_MASK;
2528 }
2529 if (rdev->irq.hpd[0]) {
2530 DRM_DEBUG("evergreen_irq_set: hpd 1\n");
2531 hpd1 |= DC_HPDx_INT_EN;
2532 }
2533 if (rdev->irq.hpd[1]) {
2534 DRM_DEBUG("evergreen_irq_set: hpd 2\n");
2535 hpd2 |= DC_HPDx_INT_EN;
2536 }
2537 if (rdev->irq.hpd[2]) {
2538 DRM_DEBUG("evergreen_irq_set: hpd 3\n");
2539 hpd3 |= DC_HPDx_INT_EN;
2540 }
2541 if (rdev->irq.hpd[3]) {
2542 DRM_DEBUG("evergreen_irq_set: hpd 4\n");
2543 hpd4 |= DC_HPDx_INT_EN;
2544 }
2545 if (rdev->irq.hpd[4]) {
2546 DRM_DEBUG("evergreen_irq_set: hpd 5\n");
2547 hpd5 |= DC_HPDx_INT_EN;
2548 }
2549 if (rdev->irq.hpd[5]) {
2550 DRM_DEBUG("evergreen_irq_set: hpd 6\n");
2551 hpd6 |= DC_HPDx_INT_EN;
2552 }
2553 if (rdev->irq.gui_idle) {
2554 DRM_DEBUG("gui idle\n");
2555 grbm_int_cntl |= GUI_IDLE_INT_ENABLE;
2556 }
2557
2558 WREG32(CP_INT_CNTL, cp_int_cntl);
2559 WREG32(GRBM_INT_CNTL, grbm_int_cntl);
2560
2561 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1);
2562 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2);
2563 if (rdev->num_crtc >= 4) {
2564 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3);
2565 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4);
2566 }
2567 if (rdev->num_crtc >= 6) {
2568 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5);
2569 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6);
2570 }
2571
2572 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, grph1);
2573 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, grph2);
2574 if (rdev->num_crtc >= 4) {
2575 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, grph3);
2576 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, grph4);
2577 }
2578 if (rdev->num_crtc >= 6) {
2579 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, grph5);
2580 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, grph6);
2581 }
2582
2583 WREG32(DC_HPD1_INT_CONTROL, hpd1);
2584 WREG32(DC_HPD2_INT_CONTROL, hpd2);
2585 WREG32(DC_HPD3_INT_CONTROL, hpd3);
2586 WREG32(DC_HPD4_INT_CONTROL, hpd4);
2587 WREG32(DC_HPD5_INT_CONTROL, hpd5);
2588 WREG32(DC_HPD6_INT_CONTROL, hpd6);
2589
2590 return 0;
2591 }
2592
2593 static void evergreen_irq_ack(struct radeon_device *rdev)
2594 {
2595 u32 tmp;
2596
2597 rdev->irq.stat_regs.evergreen.disp_int = RREG32(DISP_INTERRUPT_STATUS);
2598 rdev->irq.stat_regs.evergreen.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
2599 rdev->irq.stat_regs.evergreen.disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2);
2600 rdev->irq.stat_regs.evergreen.disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3);
2601 rdev->irq.stat_regs.evergreen.disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4);
2602 rdev->irq.stat_regs.evergreen.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5);
2603 rdev->irq.stat_regs.evergreen.d1grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET);
2604 rdev->irq.stat_regs.evergreen.d2grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET);
2605 if (rdev->num_crtc >= 4) {
2606 rdev->irq.stat_regs.evergreen.d3grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET);
2607 rdev->irq.stat_regs.evergreen.d4grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET);
2608 }
2609 if (rdev->num_crtc >= 6) {
2610 rdev->irq.stat_regs.evergreen.d5grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET);
2611 rdev->irq.stat_regs.evergreen.d6grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET);
2612 }
2613
2614 if (rdev->irq.stat_regs.evergreen.d1grph_int & GRPH_PFLIP_INT_OCCURRED)
2615 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2616 if (rdev->irq.stat_regs.evergreen.d2grph_int & GRPH_PFLIP_INT_OCCURRED)
2617 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2618 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT)
2619 WREG32(VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK);
2620 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT)
2621 WREG32(VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK);
2622 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT)
2623 WREG32(VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK);
2624 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT)
2625 WREG32(VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK);
2626
2627 if (rdev->num_crtc >= 4) {
2628 if (rdev->irq.stat_regs.evergreen.d3grph_int & GRPH_PFLIP_INT_OCCURRED)
2629 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2630 if (rdev->irq.stat_regs.evergreen.d4grph_int & GRPH_PFLIP_INT_OCCURRED)
2631 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2632 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT)
2633 WREG32(VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK);
2634 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT)
2635 WREG32(VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK);
2636 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT)
2637 WREG32(VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK);
2638 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT)
2639 WREG32(VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK);
2640 }
2641
2642 if (rdev->num_crtc >= 6) {
2643 if (rdev->irq.stat_regs.evergreen.d5grph_int & GRPH_PFLIP_INT_OCCURRED)
2644 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2645 if (rdev->irq.stat_regs.evergreen.d6grph_int & GRPH_PFLIP_INT_OCCURRED)
2646 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2647 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT)
2648 WREG32(VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK);
2649 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT)
2650 WREG32(VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK);
2651 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT)
2652 WREG32(VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK);
2653 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT)
2654 WREG32(VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK);
2655 }
2656
2657 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
2658 tmp = RREG32(DC_HPD1_INT_CONTROL);
2659 tmp |= DC_HPDx_INT_ACK;
2660 WREG32(DC_HPD1_INT_CONTROL, tmp);
2661 }
2662 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
2663 tmp = RREG32(DC_HPD2_INT_CONTROL);
2664 tmp |= DC_HPDx_INT_ACK;
2665 WREG32(DC_HPD2_INT_CONTROL, tmp);
2666 }
2667 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
2668 tmp = RREG32(DC_HPD3_INT_CONTROL);
2669 tmp |= DC_HPDx_INT_ACK;
2670 WREG32(DC_HPD3_INT_CONTROL, tmp);
2671 }
2672 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
2673 tmp = RREG32(DC_HPD4_INT_CONTROL);
2674 tmp |= DC_HPDx_INT_ACK;
2675 WREG32(DC_HPD4_INT_CONTROL, tmp);
2676 }
2677 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
2678 tmp = RREG32(DC_HPD5_INT_CONTROL);
2679 tmp |= DC_HPDx_INT_ACK;
2680 WREG32(DC_HPD5_INT_CONTROL, tmp);
2681 }
2682 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
2683 tmp = RREG32(DC_HPD5_INT_CONTROL);
2684 tmp |= DC_HPDx_INT_ACK;
2685 WREG32(DC_HPD6_INT_CONTROL, tmp);
2686 }
2687 }
2688
2689 void evergreen_irq_disable(struct radeon_device *rdev)
2690 {
2691 r600_disable_interrupts(rdev);
2692 /* Wait and acknowledge irq */
2693 mdelay(1);
2694 evergreen_irq_ack(rdev);
2695 evergreen_disable_interrupt_state(rdev);
2696 }
2697
2698 void evergreen_irq_suspend(struct radeon_device *rdev)
2699 {
2700 evergreen_irq_disable(rdev);
2701 r600_rlc_stop(rdev);
2702 }
2703
2704 static u32 evergreen_get_ih_wptr(struct radeon_device *rdev)
2705 {
2706 u32 wptr, tmp;
2707
2708 if (rdev->wb.enabled)
2709 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]);
2710 else
2711 wptr = RREG32(IH_RB_WPTR);
2712
2713 if (wptr & RB_OVERFLOW) {
2714 /* When a ring buffer overflow happen start parsing interrupt
2715 * from the last not overwritten vector (wptr + 16). Hopefully
2716 * this should allow us to catchup.
2717 */
2718 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
2719 wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
2720 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
2721 tmp = RREG32(IH_RB_CNTL);
2722 tmp |= IH_WPTR_OVERFLOW_CLEAR;
2723 WREG32(IH_RB_CNTL, tmp);
2724 }
2725 return (wptr & rdev->ih.ptr_mask);
2726 }
2727
2728 int evergreen_irq_process(struct radeon_device *rdev)
2729 {
2730 u32 wptr;
2731 u32 rptr;
2732 u32 src_id, src_data;
2733 u32 ring_index;
2734 unsigned long flags;
2735 bool queue_hotplug = false;
2736
2737 if (!rdev->ih.enabled || rdev->shutdown)
2738 return IRQ_NONE;
2739
2740 wptr = evergreen_get_ih_wptr(rdev);
2741 rptr = rdev->ih.rptr;
2742 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
2743
2744 spin_lock_irqsave(&rdev->ih.lock, flags);
2745 if (rptr == wptr) {
2746 spin_unlock_irqrestore(&rdev->ih.lock, flags);
2747 return IRQ_NONE;
2748 }
2749 restart_ih:
2750 /* Order reading of wptr vs. reading of IH ring data */
2751 rmb();
2752
2753 /* display interrupts */
2754 evergreen_irq_ack(rdev);
2755
2756 rdev->ih.wptr = wptr;
2757 while (rptr != wptr) {
2758 /* wptr/rptr are in bytes! */
2759 ring_index = rptr / 4;
2760 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
2761 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;
2762
2763 switch (src_id) {
2764 case 1: /* D1 vblank/vline */
2765 switch (src_data) {
2766 case 0: /* D1 vblank */
2767 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT) {
2768 if (rdev->irq.crtc_vblank_int[0]) {
2769 drm_handle_vblank(rdev->ddev, 0);
2770 rdev->pm.vblank_sync = true;
2771 wake_up(&rdev->irq.vblank_queue);
2772 }
2773 if (rdev->irq.pflip[0])
2774 radeon_crtc_handle_flip(rdev, 0);
2775 rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
2776 DRM_DEBUG("IH: D1 vblank\n");
2777 }
2778 break;
2779 case 1: /* D1 vline */
2780 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT) {
2781 rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VLINE_INTERRUPT;
2782 DRM_DEBUG("IH: D1 vline\n");
2783 }
2784 break;
2785 default:
2786 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2787 break;
2788 }
2789 break;
2790 case 2: /* D2 vblank/vline */
2791 switch (src_data) {
2792 case 0: /* D2 vblank */
2793 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT) {
2794 if (rdev->irq.crtc_vblank_int[1]) {
2795 drm_handle_vblank(rdev->ddev, 1);
2796 rdev->pm.vblank_sync = true;
2797 wake_up(&rdev->irq.vblank_queue);
2798 }
2799 if (rdev->irq.pflip[1])
2800 radeon_crtc_handle_flip(rdev, 1);
2801 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT;
2802 DRM_DEBUG("IH: D2 vblank\n");
2803 }
2804 break;
2805 case 1: /* D2 vline */
2806 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT) {
2807 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VLINE_INTERRUPT;
2808 DRM_DEBUG("IH: D2 vline\n");
2809 }
2810 break;
2811 default:
2812 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2813 break;
2814 }
2815 break;
2816 case 3: /* D3 vblank/vline */
2817 switch (src_data) {
2818 case 0: /* D3 vblank */
2819 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) {
2820 if (rdev->irq.crtc_vblank_int[2]) {
2821 drm_handle_vblank(rdev->ddev, 2);
2822 rdev->pm.vblank_sync = true;
2823 wake_up(&rdev->irq.vblank_queue);
2824 }
2825 if (rdev->irq.pflip[2])
2826 radeon_crtc_handle_flip(rdev, 2);
2827 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT;
2828 DRM_DEBUG("IH: D3 vblank\n");
2829 }
2830 break;
2831 case 1: /* D3 vline */
2832 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT) {
2833 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT;
2834 DRM_DEBUG("IH: D3 vline\n");
2835 }
2836 break;
2837 default:
2838 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2839 break;
2840 }
2841 break;
2842 case 4: /* D4 vblank/vline */
2843 switch (src_data) {
2844 case 0: /* D4 vblank */
2845 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) {
2846 if (rdev->irq.crtc_vblank_int[3]) {
2847 drm_handle_vblank(rdev->ddev, 3);
2848 rdev->pm.vblank_sync = true;
2849 wake_up(&rdev->irq.vblank_queue);
2850 }
2851 if (rdev->irq.pflip[3])
2852 radeon_crtc_handle_flip(rdev, 3);
2853 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT;
2854 DRM_DEBUG("IH: D4 vblank\n");
2855 }
2856 break;
2857 case 1: /* D4 vline */
2858 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT) {
2859 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT;
2860 DRM_DEBUG("IH: D4 vline\n");
2861 }
2862 break;
2863 default:
2864 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2865 break;
2866 }
2867 break;
2868 case 5: /* D5 vblank/vline */
2869 switch (src_data) {
2870 case 0: /* D5 vblank */
2871 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) {
2872 if (rdev->irq.crtc_vblank_int[4]) {
2873 drm_handle_vblank(rdev->ddev, 4);
2874 rdev->pm.vblank_sync = true;
2875 wake_up(&rdev->irq.vblank_queue);
2876 }
2877 if (rdev->irq.pflip[4])
2878 radeon_crtc_handle_flip(rdev, 4);
2879 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT;
2880 DRM_DEBUG("IH: D5 vblank\n");
2881 }
2882 break;
2883 case 1: /* D5 vline */
2884 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT) {
2885 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT;
2886 DRM_DEBUG("IH: D5 vline\n");
2887 }
2888 break;
2889 default:
2890 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2891 break;
2892 }
2893 break;
2894 case 6: /* D6 vblank/vline */
2895 switch (src_data) {
2896 case 0: /* D6 vblank */
2897 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) {
2898 if (rdev->irq.crtc_vblank_int[5]) {
2899 drm_handle_vblank(rdev->ddev, 5);
2900 rdev->pm.vblank_sync = true;
2901 wake_up(&rdev->irq.vblank_queue);
2902 }
2903 if (rdev->irq.pflip[5])
2904 radeon_crtc_handle_flip(rdev, 5);
2905 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT;
2906 DRM_DEBUG("IH: D6 vblank\n");
2907 }
2908 break;
2909 case 1: /* D6 vline */
2910 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT) {
2911 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT;
2912 DRM_DEBUG("IH: D6 vline\n");
2913 }
2914 break;
2915 default:
2916 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2917 break;
2918 }
2919 break;
2920 case 42: /* HPD hotplug */
2921 switch (src_data) {
2922 case 0:
2923 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
2924 rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_INTERRUPT;
2925 queue_hotplug = true;
2926 DRM_DEBUG("IH: HPD1\n");
2927 }
2928 break;
2929 case 1:
2930 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
2931 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_INTERRUPT;
2932 queue_hotplug = true;
2933 DRM_DEBUG("IH: HPD2\n");
2934 }
2935 break;
2936 case 2:
2937 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
2938 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_INTERRUPT;
2939 queue_hotplug = true;
2940 DRM_DEBUG("IH: HPD3\n");
2941 }
2942 break;
2943 case 3:
2944 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
2945 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_INTERRUPT;
2946 queue_hotplug = true;
2947 DRM_DEBUG("IH: HPD4\n");
2948 }
2949 break;
2950 case 4:
2951 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
2952 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_INTERRUPT;
2953 queue_hotplug = true;
2954 DRM_DEBUG("IH: HPD5\n");
2955 }
2956 break;
2957 case 5:
2958 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
2959 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_INTERRUPT;
2960 queue_hotplug = true;
2961 DRM_DEBUG("IH: HPD6\n");
2962 }
2963 break;
2964 default:
2965 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2966 break;
2967 }
2968 break;
2969 case 176: /* CP_INT in ring buffer */
2970 case 177: /* CP_INT in IB1 */
2971 case 178: /* CP_INT in IB2 */
2972 DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
2973 radeon_fence_process(rdev);
2974 break;
2975 case 181: /* CP EOP event */
2976 DRM_DEBUG("IH: CP EOP\n");
2977 radeon_fence_process(rdev);
2978 break;
2979 case 233: /* GUI IDLE */
2980 DRM_DEBUG("IH: GUI idle\n");
2981 rdev->pm.gui_idle = true;
2982 wake_up(&rdev->irq.idle_queue);
2983 break;
2984 default:
2985 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2986 break;
2987 }
2988
2989 /* wptr/rptr are in bytes! */
2990 rptr += 16;
2991 rptr &= rdev->ih.ptr_mask;
2992 }
2993 /* make sure wptr hasn't changed while processing */
2994 wptr = evergreen_get_ih_wptr(rdev);
2995 if (wptr != rdev->ih.wptr)
2996 goto restart_ih;
2997 if (queue_hotplug)
2998 schedule_work(&rdev->hotplug_work);
2999 rdev->ih.rptr = rptr;
3000 WREG32(IH_RB_RPTR, rdev->ih.rptr);
3001 spin_unlock_irqrestore(&rdev->ih.lock, flags);
3002 return IRQ_HANDLED;
3003 }
3004
3005 static int evergreen_startup(struct radeon_device *rdev)
3006 {
3007 int r;
3008
3009 /* enable pcie gen2 link */
3010 evergreen_pcie_gen2_enable(rdev);
3011
3012 if (ASIC_IS_DCE5(rdev)) {
3013 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) {
3014 r = ni_init_microcode(rdev);
3015 if (r) {
3016 DRM_ERROR("Failed to load firmware!\n");
3017 return r;
3018 }
3019 }
3020 r = ni_mc_load_microcode(rdev);
3021 if (r) {
3022 DRM_ERROR("Failed to load MC firmware!\n");
3023 return r;
3024 }
3025 } else {
3026 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
3027 r = r600_init_microcode(rdev);
3028 if (r) {
3029 DRM_ERROR("Failed to load firmware!\n");
3030 return r;
3031 }
3032 }
3033 }
3034
3035 r = r600_vram_scratch_init(rdev);
3036 if (r)
3037 return r;
3038
3039 evergreen_mc_program(rdev);
3040 if (rdev->flags & RADEON_IS_AGP) {
3041 evergreen_agp_enable(rdev);
3042 } else {
3043 r = evergreen_pcie_gart_enable(rdev);
3044 if (r)
3045 return r;
3046 }
3047 evergreen_gpu_init(rdev);
3048
3049 r = evergreen_blit_init(rdev);
3050 if (r) {
3051 r600_blit_fini(rdev);
3052 rdev->asic->copy = NULL;
3053 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
3054 }
3055
3056 /* allocate wb buffer */
3057 r = radeon_wb_init(rdev);
3058 if (r)
3059 return r;
3060
3061 /* Enable IRQ */
3062 r = r600_irq_init(rdev);
3063 if (r) {
3064 DRM_ERROR("radeon: IH init failed (%d).\n", r);
3065 radeon_irq_kms_fini(rdev);
3066 return r;
3067 }
3068 evergreen_irq_set(rdev);
3069
3070 r = radeon_ring_init(rdev, rdev->cp.ring_size);
3071 if (r)
3072 return r;
3073 r = evergreen_cp_load_microcode(rdev);
3074 if (r)
3075 return r;
3076 r = evergreen_cp_resume(rdev);
3077 if (r)
3078 return r;
3079
3080 return 0;
3081 }
3082
3083 int evergreen_resume(struct radeon_device *rdev)
3084 {
3085 int r;
3086
3087 /* reset the asic, the gfx blocks are often in a bad state
3088 * after the driver is unloaded or after a resume
3089 */
3090 if (radeon_asic_reset(rdev))
3091 dev_warn(rdev->dev, "GPU reset failed !\n");
3092 /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
3093 * posting will perform necessary task to bring back GPU into good
3094 * shape.
3095 */
3096 /* post card */
3097 atom_asic_init(rdev->mode_info.atom_context);
3098
3099 r = evergreen_startup(rdev);
3100 if (r) {
3101 DRM_ERROR("evergreen startup failed on resume\n");
3102 return r;
3103 }
3104
3105 r = r600_ib_test(rdev);
3106 if (r) {
3107 DRM_ERROR("radeon: failed testing IB (%d).\n", r);
3108 return r;
3109 }
3110
3111 return r;
3112
3113 }
3114
3115 int evergreen_suspend(struct radeon_device *rdev)
3116 {
3117 /* FIXME: we should wait for ring to be empty */
3118 r700_cp_stop(rdev);
3119 rdev->cp.ready = false;
3120 evergreen_irq_suspend(rdev);
3121 radeon_wb_disable(rdev);
3122 evergreen_pcie_gart_disable(rdev);
3123 r600_blit_suspend(rdev);
3124
3125 return 0;
3126 }
3127
3128 /* Plan is to move initialization in that function and use
3129 * helper function so that radeon_device_init pretty much
3130 * do nothing more than calling asic specific function. This
3131 * should also allow to remove a bunch of callback function
3132 * like vram_info.
3133 */
3134 int evergreen_init(struct radeon_device *rdev)
3135 {
3136 int r;
3137
3138 /* This don't do much */
3139 r = radeon_gem_init(rdev);
3140 if (r)
3141 return r;
3142 /* Read BIOS */
3143 if (!radeon_get_bios(rdev)) {
3144 if (ASIC_IS_AVIVO(rdev))
3145 return -EINVAL;
3146 }
3147 /* Must be an ATOMBIOS */
3148 if (!rdev->is_atom_bios) {
3149 dev_err(rdev->dev, "Expecting atombios for evergreen GPU\n");
3150 return -EINVAL;
3151 }
3152 r = radeon_atombios_init(rdev);
3153 if (r)
3154 return r;
3155 /* reset the asic, the gfx blocks are often in a bad state
3156 * after the driver is unloaded or after a resume
3157 */
3158 if (radeon_asic_reset(rdev))
3159 dev_warn(rdev->dev, "GPU reset failed !\n");
3160 /* Post card if necessary */
3161 if (!radeon_card_posted(rdev)) {
3162 if (!rdev->bios) {
3163 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
3164 return -EINVAL;
3165 }
3166 DRM_INFO("GPU not posted. posting now...\n");
3167 atom_asic_init(rdev->mode_info.atom_context);
3168 }
3169 /* Initialize scratch registers */
3170 r600_scratch_init(rdev);
3171 /* Initialize surface registers */
3172 radeon_surface_init(rdev);
3173 /* Initialize clocks */
3174 radeon_get_clock_info(rdev->ddev);
3175 /* Fence driver */
3176 r = radeon_fence_driver_init(rdev);
3177 if (r)
3178 return r;
3179 /* initialize AGP */
3180 if (rdev->flags & RADEON_IS_AGP) {
3181 r = radeon_agp_init(rdev);
3182 if (r)
3183 radeon_agp_disable(rdev);
3184 }
3185 /* initialize memory controller */
3186 r = evergreen_mc_init(rdev);
3187 if (r)
3188 return r;
3189 /* Memory manager */
3190 r = radeon_bo_init(rdev);
3191 if (r)
3192 return r;
3193
3194 r = radeon_irq_kms_init(rdev);
3195 if (r)
3196 return r;
3197
3198 rdev->cp.ring_obj = NULL;
3199 r600_ring_init(rdev, 1024 * 1024);
3200
3201 rdev->ih.ring_obj = NULL;
3202 r600_ih_ring_init(rdev, 64 * 1024);
3203
3204 r = r600_pcie_gart_init(rdev);
3205 if (r)
3206 return r;
3207
3208 rdev->accel_working = true;
3209 r = evergreen_startup(rdev);
3210 if (r) {
3211 dev_err(rdev->dev, "disabling GPU acceleration\n");
3212 r700_cp_fini(rdev);
3213 r600_irq_fini(rdev);
3214 radeon_wb_fini(rdev);
3215 radeon_irq_kms_fini(rdev);
3216 evergreen_pcie_gart_fini(rdev);
3217 rdev->accel_working = false;
3218 }
3219 if (rdev->accel_working) {
3220 r = radeon_ib_pool_init(rdev);
3221 if (r) {
3222 DRM_ERROR("radeon: failed initializing IB pool (%d).\n", r);
3223 rdev->accel_working = false;
3224 }
3225 r = r600_ib_test(rdev);
3226 if (r) {
3227 DRM_ERROR("radeon: failed testing IB (%d).\n", r);
3228 rdev->accel_working = false;
3229 }
3230 }
3231 return 0;
3232 }
3233
3234 void evergreen_fini(struct radeon_device *rdev)
3235 {
3236 r600_blit_fini(rdev);
3237 r700_cp_fini(rdev);
3238 r600_irq_fini(rdev);
3239 radeon_wb_fini(rdev);
3240 radeon_ib_pool_fini(rdev);
3241 radeon_irq_kms_fini(rdev);
3242 evergreen_pcie_gart_fini(rdev);
3243 r600_vram_scratch_fini(rdev);
3244 radeon_gem_fini(rdev);
3245 radeon_fence_driver_fini(rdev);
3246 radeon_agp_fini(rdev);
3247 radeon_bo_fini(rdev);
3248 radeon_atombios_fini(rdev);
3249 kfree(rdev->bios);
3250 rdev->bios = NULL;
3251 }
3252
3253 void evergreen_pcie_gen2_enable(struct radeon_device *rdev)
3254 {
3255 u32 link_width_cntl, speed_cntl;
3256
3257 if (radeon_pcie_gen2 == 0)
3258 return;
3259
3260 if (rdev->flags & RADEON_IS_IGP)
3261 return;
3262
3263 if (!(rdev->flags & RADEON_IS_PCIE))
3264 return;
3265
3266 /* x2 cards have a special sequence */
3267 if (ASIC_IS_X2(rdev))
3268 return;
3269
3270 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3271 if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) ||
3272 (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
3273
3274 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3275 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
3276 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3277
3278 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3279 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
3280 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3281
3282 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3283 speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT;
3284 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3285
3286 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3287 speed_cntl &= ~LC_CLR_FAILED_SPD_CHANGE_CNT;
3288 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3289
3290 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3291 speed_cntl |= LC_GEN2_EN_STRAP;
3292 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3293
3294 } else {
3295 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3296 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
3297 if (1)
3298 link_width_cntl |= LC_UPCONFIGURE_DIS;
3299 else
3300 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
3301 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3302 }
3303 }
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree