x86, apic: Fix spurious error interrupts triggering on all non-boot APs
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / ata / libata-sff.c
blob06e7204d7b93fcc9808098ad01826b4484cc9074
1 /*
2 * libata-sff.c - helper library for PCI IDE BMDMA
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
8 * Copyright 2003-2006 Red Hat, Inc. All rights reserved.
9 * Copyright 2003-2006 Jeff Garzik
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2, or (at your option)
15 * any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; see the file COPYING. If not, write to
24 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
27 * libata documentation is available via 'make {ps|pdf}docs',
28 * as Documentation/DocBook/libata.*
30 * Hardware documentation available from http://www.t13.org/ and
31 * http://www.sata-io.org/
35 #include <linux/kernel.h>
36 #include <linux/pci.h>
37 #include <linux/libata.h>
38 #include <linux/highmem.h>
40 #include "libata.h"
42 const struct ata_port_operations ata_sff_port_ops = {
43 .inherits = &ata_base_port_ops,
45 .qc_prep = ata_sff_qc_prep,
46 .qc_issue = ata_sff_qc_issue,
47 .qc_fill_rtf = ata_sff_qc_fill_rtf,
49 .freeze = ata_sff_freeze,
50 .thaw = ata_sff_thaw,
51 .prereset = ata_sff_prereset,
52 .softreset = ata_sff_softreset,
53 .hardreset = sata_sff_hardreset,
54 .postreset = ata_sff_postreset,
55 .drain_fifo = ata_sff_drain_fifo,
56 .error_handler = ata_sff_error_handler,
57 .post_internal_cmd = ata_sff_post_internal_cmd,
59 .sff_dev_select = ata_sff_dev_select,
60 .sff_check_status = ata_sff_check_status,
61 .sff_tf_load = ata_sff_tf_load,
62 .sff_tf_read = ata_sff_tf_read,
63 .sff_exec_command = ata_sff_exec_command,
64 .sff_data_xfer = ata_sff_data_xfer,
65 .sff_irq_on = ata_sff_irq_on,
66 .sff_irq_clear = ata_sff_irq_clear,
68 .lost_interrupt = ata_sff_lost_interrupt,
70 .port_start = ata_sff_port_start,
72 EXPORT_SYMBOL_GPL(ata_sff_port_ops);
74 const struct ata_port_operations ata_bmdma_port_ops = {
75 .inherits = &ata_sff_port_ops,
77 .mode_filter = ata_bmdma_mode_filter,
79 .bmdma_setup = ata_bmdma_setup,
80 .bmdma_start = ata_bmdma_start,
81 .bmdma_stop = ata_bmdma_stop,
82 .bmdma_status = ata_bmdma_status,
84 EXPORT_SYMBOL_GPL(ata_bmdma_port_ops);
86 const struct ata_port_operations ata_bmdma32_port_ops = {
87 .inherits = &ata_bmdma_port_ops,
89 .sff_data_xfer = ata_sff_data_xfer32,
90 .port_start = ata_sff_port_start32,
92 EXPORT_SYMBOL_GPL(ata_bmdma32_port_ops);
94 /**
95 * ata_fill_sg - Fill PCI IDE PRD table
96 * @qc: Metadata associated with taskfile to be transferred
98 * Fill PCI IDE PRD (scatter-gather) table with segments
99 * associated with the current disk command.
101 * LOCKING:
102 * spin_lock_irqsave(host lock)
105 static void ata_fill_sg(struct ata_queued_cmd *qc)
107 struct ata_port *ap = qc->ap;
108 struct scatterlist *sg;
109 unsigned int si, pi;
111 pi = 0;
112 for_each_sg(qc->sg, sg, qc->n_elem, si) {
113 u32 addr, offset;
114 u32 sg_len, len;
116 /* determine if physical DMA addr spans 64K boundary.
117 * Note h/w doesn't support 64-bit, so we unconditionally
118 * truncate dma_addr_t to u32.
120 addr = (u32) sg_dma_address(sg);
121 sg_len = sg_dma_len(sg);
123 while (sg_len) {
124 offset = addr & 0xffff;
125 len = sg_len;
126 if ((offset + sg_len) > 0x10000)
127 len = 0x10000 - offset;
129 ap->prd[pi].addr = cpu_to_le32(addr);
130 ap->prd[pi].flags_len = cpu_to_le32(len & 0xffff);
131 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", pi, addr, len);
133 pi++;
134 sg_len -= len;
135 addr += len;
139 ap->prd[pi - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT);
143 * ata_fill_sg_dumb - Fill PCI IDE PRD table
144 * @qc: Metadata associated with taskfile to be transferred
146 * Fill PCI IDE PRD (scatter-gather) table with segments
147 * associated with the current disk command. Perform the fill
148 * so that we avoid writing any length 64K records for
149 * controllers that don't follow the spec.
151 * LOCKING:
152 * spin_lock_irqsave(host lock)
155 static void ata_fill_sg_dumb(struct ata_queued_cmd *qc)
157 struct ata_port *ap = qc->ap;
158 struct scatterlist *sg;
159 unsigned int si, pi;
161 pi = 0;
162 for_each_sg(qc->sg, sg, qc->n_elem, si) {
163 u32 addr, offset;
164 u32 sg_len, len, blen;
166 /* determine if physical DMA addr spans 64K boundary.
167 * Note h/w doesn't support 64-bit, so we unconditionally
168 * truncate dma_addr_t to u32.
170 addr = (u32) sg_dma_address(sg);
171 sg_len = sg_dma_len(sg);
173 while (sg_len) {
174 offset = addr & 0xffff;
175 len = sg_len;
176 if ((offset + sg_len) > 0x10000)
177 len = 0x10000 - offset;
179 blen = len & 0xffff;
180 ap->prd[pi].addr = cpu_to_le32(addr);
181 if (blen == 0) {
182 /* Some PATA chipsets like the CS5530 can't
183 cope with 0x0000 meaning 64K as the spec
184 says */
185 ap->prd[pi].flags_len = cpu_to_le32(0x8000);
186 blen = 0x8000;
187 ap->prd[++pi].addr = cpu_to_le32(addr + 0x8000);
189 ap->prd[pi].flags_len = cpu_to_le32(blen);
190 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", pi, addr, len);
192 pi++;
193 sg_len -= len;
194 addr += len;
198 ap->prd[pi - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT);
202 * ata_sff_qc_prep - Prepare taskfile for submission
203 * @qc: Metadata associated with taskfile to be prepared
205 * Prepare ATA taskfile for submission.
207 * LOCKING:
208 * spin_lock_irqsave(host lock)
210 void ata_sff_qc_prep(struct ata_queued_cmd *qc)
212 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
213 return;
215 ata_fill_sg(qc);
217 EXPORT_SYMBOL_GPL(ata_sff_qc_prep);
220 * ata_sff_dumb_qc_prep - Prepare taskfile for submission
221 * @qc: Metadata associated with taskfile to be prepared
223 * Prepare ATA taskfile for submission.
225 * LOCKING:
226 * spin_lock_irqsave(host lock)
228 void ata_sff_dumb_qc_prep(struct ata_queued_cmd *qc)
230 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
231 return;
233 ata_fill_sg_dumb(qc);
235 EXPORT_SYMBOL_GPL(ata_sff_dumb_qc_prep);
238 * ata_sff_check_status - Read device status reg & clear interrupt
239 * @ap: port where the device is
241 * Reads ATA taskfile status register for currently-selected device
242 * and return its value. This also clears pending interrupts
243 * from this device
245 * LOCKING:
246 * Inherited from caller.
248 u8 ata_sff_check_status(struct ata_port *ap)
250 return ioread8(ap->ioaddr.status_addr);
252 EXPORT_SYMBOL_GPL(ata_sff_check_status);
255 * ata_sff_altstatus - Read device alternate status reg
256 * @ap: port where the device is
258 * Reads ATA taskfile alternate status register for
259 * currently-selected device and return its value.
261 * Note: may NOT be used as the check_altstatus() entry in
262 * ata_port_operations.
264 * LOCKING:
265 * Inherited from caller.
267 static u8 ata_sff_altstatus(struct ata_port *ap)
269 if (ap->ops->sff_check_altstatus)
270 return ap->ops->sff_check_altstatus(ap);
272 return ioread8(ap->ioaddr.altstatus_addr);
276 * ata_sff_irq_status - Check if the device is busy
277 * @ap: port where the device is
279 * Determine if the port is currently busy. Uses altstatus
280 * if available in order to avoid clearing shared IRQ status
281 * when finding an IRQ source. Non ctl capable devices don't
282 * share interrupt lines fortunately for us.
284 * LOCKING:
285 * Inherited from caller.
287 static u8 ata_sff_irq_status(struct ata_port *ap)
289 u8 status;
291 if (ap->ops->sff_check_altstatus || ap->ioaddr.altstatus_addr) {
292 status = ata_sff_altstatus(ap);
293 /* Not us: We are busy */
294 if (status & ATA_BUSY)
295 return status;
297 /* Clear INTRQ latch */
298 status = ap->ops->sff_check_status(ap);
299 return status;
303 * ata_sff_sync - Flush writes
304 * @ap: Port to wait for.
306 * CAUTION:
307 * If we have an mmio device with no ctl and no altstatus
308 * method this will fail. No such devices are known to exist.
310 * LOCKING:
311 * Inherited from caller.
314 static void ata_sff_sync(struct ata_port *ap)
316 if (ap->ops->sff_check_altstatus)
317 ap->ops->sff_check_altstatus(ap);
318 else if (ap->ioaddr.altstatus_addr)
319 ioread8(ap->ioaddr.altstatus_addr);
323 * ata_sff_pause - Flush writes and wait 400nS
324 * @ap: Port to pause for.
326 * CAUTION:
327 * If we have an mmio device with no ctl and no altstatus
328 * method this will fail. No such devices are known to exist.
330 * LOCKING:
331 * Inherited from caller.
334 void ata_sff_pause(struct ata_port *ap)
336 ata_sff_sync(ap);
337 ndelay(400);
339 EXPORT_SYMBOL_GPL(ata_sff_pause);
342 * ata_sff_dma_pause - Pause before commencing DMA
343 * @ap: Port to pause for.
345 * Perform I/O fencing and ensure sufficient cycle delays occur
346 * for the HDMA1:0 transition
349 void ata_sff_dma_pause(struct ata_port *ap)
351 if (ap->ops->sff_check_altstatus || ap->ioaddr.altstatus_addr) {
352 /* An altstatus read will cause the needed delay without
353 messing up the IRQ status */
354 ata_sff_altstatus(ap);
355 return;
357 /* There are no DMA controllers without ctl. BUG here to ensure
358 we never violate the HDMA1:0 transition timing and risk
359 corruption. */
360 BUG();
362 EXPORT_SYMBOL_GPL(ata_sff_dma_pause);
365 * ata_sff_busy_sleep - sleep until BSY clears, or timeout
366 * @ap: port containing status register to be polled
367 * @tmout_pat: impatience timeout in msecs
368 * @tmout: overall timeout in msecs
370 * Sleep until ATA Status register bit BSY clears,
371 * or a timeout occurs.
373 * LOCKING:
374 * Kernel thread context (may sleep).
376 * RETURNS:
377 * 0 on success, -errno otherwise.
379 int ata_sff_busy_sleep(struct ata_port *ap,
380 unsigned long tmout_pat, unsigned long tmout)
382 unsigned long timer_start, timeout;
383 u8 status;
385 status = ata_sff_busy_wait(ap, ATA_BUSY, 300);
386 timer_start = jiffies;
387 timeout = ata_deadline(timer_start, tmout_pat);
388 while (status != 0xff && (status & ATA_BUSY) &&
389 time_before(jiffies, timeout)) {
390 msleep(50);
391 status = ata_sff_busy_wait(ap, ATA_BUSY, 3);
394 if (status != 0xff && (status & ATA_BUSY))
395 ata_port_printk(ap, KERN_WARNING,
396 "port is slow to respond, please be patient "
397 "(Status 0x%x)\n", status);
399 timeout = ata_deadline(timer_start, tmout);
400 while (status != 0xff && (status & ATA_BUSY) &&
401 time_before(jiffies, timeout)) {
402 msleep(50);
403 status = ap->ops->sff_check_status(ap);
406 if (status == 0xff)
407 return -ENODEV;
409 if (status & ATA_BUSY) {
410 ata_port_printk(ap, KERN_ERR, "port failed to respond "
411 "(%lu secs, Status 0x%x)\n",
412 DIV_ROUND_UP(tmout, 1000), status);
413 return -EBUSY;
416 return 0;
418 EXPORT_SYMBOL_GPL(ata_sff_busy_sleep);
420 static int ata_sff_check_ready(struct ata_link *link)
422 u8 status = link->ap->ops->sff_check_status(link->ap);
424 return ata_check_ready(status);
428 * ata_sff_wait_ready - sleep until BSY clears, or timeout
429 * @link: SFF link to wait ready status for
430 * @deadline: deadline jiffies for the operation
432 * Sleep until ATA Status register bit BSY clears, or timeout
433 * occurs.
435 * LOCKING:
436 * Kernel thread context (may sleep).
438 * RETURNS:
439 * 0 on success, -errno otherwise.
441 int ata_sff_wait_ready(struct ata_link *link, unsigned long deadline)
443 return ata_wait_ready(link, deadline, ata_sff_check_ready);
445 EXPORT_SYMBOL_GPL(ata_sff_wait_ready);
448 * ata_sff_dev_select - Select device 0/1 on ATA bus
449 * @ap: ATA channel to manipulate
450 * @device: ATA device (numbered from zero) to select
452 * Use the method defined in the ATA specification to
453 * make either device 0, or device 1, active on the
454 * ATA channel. Works with both PIO and MMIO.
456 * May be used as the dev_select() entry in ata_port_operations.
458 * LOCKING:
459 * caller.
461 void ata_sff_dev_select(struct ata_port *ap, unsigned int device)
463 u8 tmp;
465 if (device == 0)
466 tmp = ATA_DEVICE_OBS;
467 else
468 tmp = ATA_DEVICE_OBS | ATA_DEV1;
470 iowrite8(tmp, ap->ioaddr.device_addr);
471 ata_sff_pause(ap); /* needed; also flushes, for mmio */
473 EXPORT_SYMBOL_GPL(ata_sff_dev_select);
476 * ata_dev_select - Select device 0/1 on ATA bus
477 * @ap: ATA channel to manipulate
478 * @device: ATA device (numbered from zero) to select
479 * @wait: non-zero to wait for Status register BSY bit to clear
480 * @can_sleep: non-zero if context allows sleeping
482 * Use the method defined in the ATA specification to
483 * make either device 0, or device 1, active on the
484 * ATA channel.
486 * This is a high-level version of ata_sff_dev_select(), which
487 * additionally provides the services of inserting the proper
488 * pauses and status polling, where needed.
490 * LOCKING:
491 * caller.
493 void ata_dev_select(struct ata_port *ap, unsigned int device,
494 unsigned int wait, unsigned int can_sleep)
496 if (ata_msg_probe(ap))
497 ata_port_printk(ap, KERN_INFO, "ata_dev_select: ENTER, "
498 "device %u, wait %u\n", device, wait);
500 if (wait)
501 ata_wait_idle(ap);
503 ap->ops->sff_dev_select(ap, device);
505 if (wait) {
506 if (can_sleep && ap->link.device[device].class == ATA_DEV_ATAPI)
507 msleep(150);
508 ata_wait_idle(ap);
513 * ata_sff_irq_on - Enable interrupts on a port.
514 * @ap: Port on which interrupts are enabled.
516 * Enable interrupts on a legacy IDE device using MMIO or PIO,
517 * wait for idle, clear any pending interrupts.
519 * LOCKING:
520 * Inherited from caller.
522 u8 ata_sff_irq_on(struct ata_port *ap)
524 struct ata_ioports *ioaddr = &ap->ioaddr;
525 u8 tmp;
527 ap->ctl &= ~ATA_NIEN;
528 ap->last_ctl = ap->ctl;
530 if (ioaddr->ctl_addr)
531 iowrite8(ap->ctl, ioaddr->ctl_addr);
532 tmp = ata_wait_idle(ap);
534 ap->ops->sff_irq_clear(ap);
536 return tmp;
538 EXPORT_SYMBOL_GPL(ata_sff_irq_on);
541 * ata_sff_irq_clear - Clear PCI IDE BMDMA interrupt.
542 * @ap: Port associated with this ATA transaction.
544 * Clear interrupt and error flags in DMA status register.
546 * May be used as the irq_clear() entry in ata_port_operations.
548 * LOCKING:
549 * spin_lock_irqsave(host lock)
551 void ata_sff_irq_clear(struct ata_port *ap)
553 void __iomem *mmio = ap->ioaddr.bmdma_addr;
555 if (!mmio)
556 return;
558 iowrite8(ioread8(mmio + ATA_DMA_STATUS), mmio + ATA_DMA_STATUS);
560 EXPORT_SYMBOL_GPL(ata_sff_irq_clear);
563 * ata_sff_tf_load - send taskfile registers to host controller
564 * @ap: Port to which output is sent
565 * @tf: ATA taskfile register set
567 * Outputs ATA taskfile to standard ATA host controller.
569 * LOCKING:
570 * Inherited from caller.
572 void ata_sff_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
574 struct ata_ioports *ioaddr = &ap->ioaddr;
575 unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
577 if (tf->ctl != ap->last_ctl) {
578 if (ioaddr->ctl_addr)
579 iowrite8(tf->ctl, ioaddr->ctl_addr);
580 ap->last_ctl = tf->ctl;
581 ata_wait_idle(ap);
584 if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
585 WARN_ON_ONCE(!ioaddr->ctl_addr);
586 iowrite8(tf->hob_feature, ioaddr->feature_addr);
587 iowrite8(tf->hob_nsect, ioaddr->nsect_addr);
588 iowrite8(tf->hob_lbal, ioaddr->lbal_addr);
589 iowrite8(tf->hob_lbam, ioaddr->lbam_addr);
590 iowrite8(tf->hob_lbah, ioaddr->lbah_addr);
591 VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n",
592 tf->hob_feature,
593 tf->hob_nsect,
594 tf->hob_lbal,
595 tf->hob_lbam,
596 tf->hob_lbah);
599 if (is_addr) {
600 iowrite8(tf->feature, ioaddr->feature_addr);
601 iowrite8(tf->nsect, ioaddr->nsect_addr);
602 iowrite8(tf->lbal, ioaddr->lbal_addr);
603 iowrite8(tf->lbam, ioaddr->lbam_addr);
604 iowrite8(tf->lbah, ioaddr->lbah_addr);
605 VPRINTK("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n",
606 tf->feature,
607 tf->nsect,
608 tf->lbal,
609 tf->lbam,
610 tf->lbah);
613 if (tf->flags & ATA_TFLAG_DEVICE) {
614 iowrite8(tf->device, ioaddr->device_addr);
615 VPRINTK("device 0x%X\n", tf->device);
618 ata_wait_idle(ap);
620 EXPORT_SYMBOL_GPL(ata_sff_tf_load);
623 * ata_sff_tf_read - input device's ATA taskfile shadow registers
624 * @ap: Port from which input is read
625 * @tf: ATA taskfile register set for storing input
627 * Reads ATA taskfile registers for currently-selected device
628 * into @tf. Assumes the device has a fully SFF compliant task file
629 * layout and behaviour. If you device does not (eg has a different
630 * status method) then you will need to provide a replacement tf_read
632 * LOCKING:
633 * Inherited from caller.
635 void ata_sff_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
637 struct ata_ioports *ioaddr = &ap->ioaddr;
639 tf->command = ata_sff_check_status(ap);
640 tf->feature = ioread8(ioaddr->error_addr);
641 tf->nsect = ioread8(ioaddr->nsect_addr);
642 tf->lbal = ioread8(ioaddr->lbal_addr);
643 tf->lbam = ioread8(ioaddr->lbam_addr);
644 tf->lbah = ioread8(ioaddr->lbah_addr);
645 tf->device = ioread8(ioaddr->device_addr);
647 if (tf->flags & ATA_TFLAG_LBA48) {
648 if (likely(ioaddr->ctl_addr)) {
649 iowrite8(tf->ctl | ATA_HOB, ioaddr->ctl_addr);
650 tf->hob_feature = ioread8(ioaddr->error_addr);
651 tf->hob_nsect = ioread8(ioaddr->nsect_addr);
652 tf->hob_lbal = ioread8(ioaddr->lbal_addr);
653 tf->hob_lbam = ioread8(ioaddr->lbam_addr);
654 tf->hob_lbah = ioread8(ioaddr->lbah_addr);
655 iowrite8(tf->ctl, ioaddr->ctl_addr);
656 ap->last_ctl = tf->ctl;
657 } else
658 WARN_ON_ONCE(1);
661 EXPORT_SYMBOL_GPL(ata_sff_tf_read);
664 * ata_sff_exec_command - issue ATA command to host controller
665 * @ap: port to which command is being issued
666 * @tf: ATA taskfile register set
668 * Issues ATA command, with proper synchronization with interrupt
669 * handler / other threads.
671 * LOCKING:
672 * spin_lock_irqsave(host lock)
674 void ata_sff_exec_command(struct ata_port *ap, const struct ata_taskfile *tf)
676 DPRINTK("ata%u: cmd 0x%X\n", ap->print_id, tf->command);
678 iowrite8(tf->command, ap->ioaddr.command_addr);
679 ata_sff_pause(ap);
681 EXPORT_SYMBOL_GPL(ata_sff_exec_command);
684 * ata_tf_to_host - issue ATA taskfile to host controller
685 * @ap: port to which command is being issued
686 * @tf: ATA taskfile register set
688 * Issues ATA taskfile register set to ATA host controller,
689 * with proper synchronization with interrupt handler and
690 * other threads.
692 * LOCKING:
693 * spin_lock_irqsave(host lock)
695 static inline void ata_tf_to_host(struct ata_port *ap,
696 const struct ata_taskfile *tf)
698 ap->ops->sff_tf_load(ap, tf);
699 ap->ops->sff_exec_command(ap, tf);
703 * ata_sff_data_xfer - Transfer data by PIO
704 * @dev: device to target
705 * @buf: data buffer
706 * @buflen: buffer length
707 * @rw: read/write
709 * Transfer data from/to the device data register by PIO.
711 * LOCKING:
712 * Inherited from caller.
714 * RETURNS:
715 * Bytes consumed.
717 unsigned int ata_sff_data_xfer(struct ata_device *dev, unsigned char *buf,
718 unsigned int buflen, int rw)
720 struct ata_port *ap = dev->link->ap;
721 void __iomem *data_addr = ap->ioaddr.data_addr;
722 unsigned int words = buflen >> 1;
724 /* Transfer multiple of 2 bytes */
725 if (rw == READ)
726 ioread16_rep(data_addr, buf, words);
727 else
728 iowrite16_rep(data_addr, buf, words);
730 /* Transfer trailing byte, if any. */
731 if (unlikely(buflen & 0x01)) {
732 unsigned char pad[2];
734 /* Point buf to the tail of buffer */
735 buf += buflen - 1;
738 * Use io*16_rep() accessors here as well to avoid pointlessly
739 * swapping bytes to and from on the big endian machines...
741 if (rw == READ) {
742 ioread16_rep(data_addr, pad, 1);
743 *buf = pad[0];
744 } else {
745 pad[0] = *buf;
746 iowrite16_rep(data_addr, pad, 1);
748 words++;
751 return words << 1;
753 EXPORT_SYMBOL_GPL(ata_sff_data_xfer);
756 * ata_sff_data_xfer32 - Transfer data by PIO
757 * @dev: device to target
758 * @buf: data buffer
759 * @buflen: buffer length
760 * @rw: read/write
762 * Transfer data from/to the device data register by PIO using 32bit
763 * I/O operations.
765 * LOCKING:
766 * Inherited from caller.
768 * RETURNS:
769 * Bytes consumed.
772 unsigned int ata_sff_data_xfer32(struct ata_device *dev, unsigned char *buf,
773 unsigned int buflen, int rw)
775 struct ata_port *ap = dev->link->ap;
776 void __iomem *data_addr = ap->ioaddr.data_addr;
777 unsigned int words = buflen >> 2;
778 int slop = buflen & 3;
780 if (!(ap->pflags & ATA_PFLAG_PIO32))
781 return ata_sff_data_xfer(dev, buf, buflen, rw);
783 /* Transfer multiple of 4 bytes */
784 if (rw == READ)
785 ioread32_rep(data_addr, buf, words);
786 else
787 iowrite32_rep(data_addr, buf, words);
789 /* Transfer trailing bytes, if any */
790 if (unlikely(slop)) {
791 unsigned char pad[4];
793 /* Point buf to the tail of buffer */
794 buf += buflen - slop;
797 * Use io*_rep() accessors here as well to avoid pointlessly
798 * swapping bytes to and from on the big endian machines...
800 if (rw == READ) {
801 if (slop < 3)
802 ioread16_rep(data_addr, pad, 1);
803 else
804 ioread32_rep(data_addr, pad, 1);
805 memcpy(buf, pad, slop);
806 } else {
807 memcpy(pad, buf, slop);
808 if (slop < 3)
809 iowrite16_rep(data_addr, pad, 1);
810 else
811 iowrite32_rep(data_addr, pad, 1);
814 return (buflen + 1) & ~1;
816 EXPORT_SYMBOL_GPL(ata_sff_data_xfer32);
819 * ata_sff_data_xfer_noirq - Transfer data by PIO
820 * @dev: device to target
821 * @buf: data buffer
822 * @buflen: buffer length
823 * @rw: read/write
825 * Transfer data from/to the device data register by PIO. Do the
826 * transfer with interrupts disabled.
828 * LOCKING:
829 * Inherited from caller.
831 * RETURNS:
832 * Bytes consumed.
834 unsigned int ata_sff_data_xfer_noirq(struct ata_device *dev, unsigned char *buf,
835 unsigned int buflen, int rw)
837 unsigned long flags;
838 unsigned int consumed;
840 local_irq_save(flags);
841 consumed = ata_sff_data_xfer(dev, buf, buflen, rw);
842 local_irq_restore(flags);
844 return consumed;
846 EXPORT_SYMBOL_GPL(ata_sff_data_xfer_noirq);
849 * ata_pio_sector - Transfer a sector of data.
850 * @qc: Command on going
852 * Transfer qc->sect_size bytes of data from/to the ATA device.
854 * LOCKING:
855 * Inherited from caller.
857 static void ata_pio_sector(struct ata_queued_cmd *qc)
859 int do_write = (qc->tf.flags & ATA_TFLAG_WRITE);
860 struct ata_port *ap = qc->ap;
861 struct page *page;
862 unsigned int offset;
863 unsigned char *buf;
865 if (qc->curbytes == qc->nbytes - qc->sect_size)
866 ap->hsm_task_state = HSM_ST_LAST;
868 page = sg_page(qc->cursg);
869 offset = qc->cursg->offset + qc->cursg_ofs;
871 /* get the current page and offset */
872 page = nth_page(page, (offset >> PAGE_SHIFT));
873 offset %= PAGE_SIZE;
875 DPRINTK("data %s\n", qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read");
877 if (PageHighMem(page)) {
878 unsigned long flags;
880 /* FIXME: use a bounce buffer */
881 local_irq_save(flags);
882 buf = kmap_atomic(page, KM_IRQ0);
884 /* do the actual data transfer */
885 ap->ops->sff_data_xfer(qc->dev, buf + offset, qc->sect_size,
886 do_write);
888 kunmap_atomic(buf, KM_IRQ0);
889 local_irq_restore(flags);
890 } else {
891 buf = page_address(page);
892 ap->ops->sff_data_xfer(qc->dev, buf + offset, qc->sect_size,
893 do_write);
896 if (!do_write && !PageSlab(page))
897 flush_dcache_page(page);
899 qc->curbytes += qc->sect_size;
900 qc->cursg_ofs += qc->sect_size;
902 if (qc->cursg_ofs == qc->cursg->length) {
903 qc->cursg = sg_next(qc->cursg);
904 qc->cursg_ofs = 0;
909 * ata_pio_sectors - Transfer one or many sectors.
910 * @qc: Command on going
912 * Transfer one or many sectors of data from/to the
913 * ATA device for the DRQ request.
915 * LOCKING:
916 * Inherited from caller.
918 static void ata_pio_sectors(struct ata_queued_cmd *qc)
920 if (is_multi_taskfile(&qc->tf)) {
921 /* READ/WRITE MULTIPLE */
922 unsigned int nsect;
924 WARN_ON_ONCE(qc->dev->multi_count == 0);
926 nsect = min((qc->nbytes - qc->curbytes) / qc->sect_size,
927 qc->dev->multi_count);
928 while (nsect--)
929 ata_pio_sector(qc);
930 } else
931 ata_pio_sector(qc);
933 ata_sff_sync(qc->ap); /* flush */
937 * atapi_send_cdb - Write CDB bytes to hardware
938 * @ap: Port to which ATAPI device is attached.
939 * @qc: Taskfile currently active
941 * When device has indicated its readiness to accept
942 * a CDB, this function is called. Send the CDB.
944 * LOCKING:
945 * caller.
947 static void atapi_send_cdb(struct ata_port *ap, struct ata_queued_cmd *qc)
949 /* send SCSI cdb */
950 DPRINTK("send cdb\n");
951 WARN_ON_ONCE(qc->dev->cdb_len < 12);
953 ap->ops->sff_data_xfer(qc->dev, qc->cdb, qc->dev->cdb_len, 1);
954 ata_sff_sync(ap);
955 /* FIXME: If the CDB is for DMA do we need to do the transition delay
956 or is bmdma_start guaranteed to do it ? */
957 switch (qc->tf.protocol) {
958 case ATAPI_PROT_PIO:
959 ap->hsm_task_state = HSM_ST;
960 break;
961 case ATAPI_PROT_NODATA:
962 ap->hsm_task_state = HSM_ST_LAST;
963 break;
964 case ATAPI_PROT_DMA:
965 ap->hsm_task_state = HSM_ST_LAST;
966 /* initiate bmdma */
967 ap->ops->bmdma_start(qc);
968 break;
973 * __atapi_pio_bytes - Transfer data from/to the ATAPI device.
974 * @qc: Command on going
975 * @bytes: number of bytes
977 * Transfer Transfer data from/to the ATAPI device.
979 * LOCKING:
980 * Inherited from caller.
983 static int __atapi_pio_bytes(struct ata_queued_cmd *qc, unsigned int bytes)
985 int rw = (qc->tf.flags & ATA_TFLAG_WRITE) ? WRITE : READ;
986 struct ata_port *ap = qc->ap;
987 struct ata_device *dev = qc->dev;
988 struct ata_eh_info *ehi = &dev->link->eh_info;
989 struct scatterlist *sg;
990 struct page *page;
991 unsigned char *buf;
992 unsigned int offset, count, consumed;
994 next_sg:
995 sg = qc->cursg;
996 if (unlikely(!sg)) {
997 ata_ehi_push_desc(ehi, "unexpected or too much trailing data "
998 "buf=%u cur=%u bytes=%u",
999 qc->nbytes, qc->curbytes, bytes);
1000 return -1;
1003 page = sg_page(sg);
1004 offset = sg->offset + qc->cursg_ofs;
1006 /* get the current page and offset */
1007 page = nth_page(page, (offset >> PAGE_SHIFT));
1008 offset %= PAGE_SIZE;
1010 /* don't overrun current sg */
1011 count = min(sg->length - qc->cursg_ofs, bytes);
1013 /* don't cross page boundaries */
1014 count = min(count, (unsigned int)PAGE_SIZE - offset);
1016 DPRINTK("data %s\n", qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read");
1018 if (PageHighMem(page)) {
1019 unsigned long flags;
1021 /* FIXME: use bounce buffer */
1022 local_irq_save(flags);
1023 buf = kmap_atomic(page, KM_IRQ0);
1025 /* do the actual data transfer */
1026 consumed = ap->ops->sff_data_xfer(dev, buf + offset,
1027 count, rw);
1029 kunmap_atomic(buf, KM_IRQ0);
1030 local_irq_restore(flags);
1031 } else {
1032 buf = page_address(page);
1033 consumed = ap->ops->sff_data_xfer(dev, buf + offset,
1034 count, rw);
1037 bytes -= min(bytes, consumed);
1038 qc->curbytes += count;
1039 qc->cursg_ofs += count;
1041 if (qc->cursg_ofs == sg->length) {
1042 qc->cursg = sg_next(qc->cursg);
1043 qc->cursg_ofs = 0;
1047 * There used to be a WARN_ON_ONCE(qc->cursg && count != consumed);
1048 * Unfortunately __atapi_pio_bytes doesn't know enough to do the WARN
1049 * check correctly as it doesn't know if it is the last request being
1050 * made. Somebody should implement a proper sanity check.
1052 if (bytes)
1053 goto next_sg;
1054 return 0;
1058 * atapi_pio_bytes - Transfer data from/to the ATAPI device.
1059 * @qc: Command on going
1061 * Transfer Transfer data from/to the ATAPI device.
1063 * LOCKING:
1064 * Inherited from caller.
1066 static void atapi_pio_bytes(struct ata_queued_cmd *qc)
1068 struct ata_port *ap = qc->ap;
1069 struct ata_device *dev = qc->dev;
1070 struct ata_eh_info *ehi = &dev->link->eh_info;
1071 unsigned int ireason, bc_lo, bc_hi, bytes;
1072 int i_write, do_write = (qc->tf.flags & ATA_TFLAG_WRITE) ? 1 : 0;
1074 /* Abuse qc->result_tf for temp storage of intermediate TF
1075 * here to save some kernel stack usage.
1076 * For normal completion, qc->result_tf is not relevant. For
1077 * error, qc->result_tf is later overwritten by ata_qc_complete().
1078 * So, the correctness of qc->result_tf is not affected.
1080 ap->ops->sff_tf_read(ap, &qc->result_tf);
1081 ireason = qc->result_tf.nsect;
1082 bc_lo = qc->result_tf.lbam;
1083 bc_hi = qc->result_tf.lbah;
1084 bytes = (bc_hi << 8) | bc_lo;
1086 /* shall be cleared to zero, indicating xfer of data */
1087 if (unlikely(ireason & (1 << 0)))
1088 goto atapi_check;
1090 /* make sure transfer direction matches expected */
1091 i_write = ((ireason & (1 << 1)) == 0) ? 1 : 0;
1092 if (unlikely(do_write != i_write))
1093 goto atapi_check;
1095 if (unlikely(!bytes))
1096 goto atapi_check;
1098 VPRINTK("ata%u: xfering %d bytes\n", ap->print_id, bytes);
1100 if (unlikely(__atapi_pio_bytes(qc, bytes)))
1101 goto err_out;
1102 ata_sff_sync(ap); /* flush */
1104 return;
1106 atapi_check:
1107 ata_ehi_push_desc(ehi, "ATAPI check failed (ireason=0x%x bytes=%u)",
1108 ireason, bytes);
1109 err_out:
1110 qc->err_mask |= AC_ERR_HSM;
1111 ap->hsm_task_state = HSM_ST_ERR;
1115 * ata_hsm_ok_in_wq - Check if the qc can be handled in the workqueue.
1116 * @ap: the target ata_port
1117 * @qc: qc on going
1119 * RETURNS:
1120 * 1 if ok in workqueue, 0 otherwise.
1122 static inline int ata_hsm_ok_in_wq(struct ata_port *ap,
1123 struct ata_queued_cmd *qc)
1125 if (qc->tf.flags & ATA_TFLAG_POLLING)
1126 return 1;
1128 if (ap->hsm_task_state == HSM_ST_FIRST) {
1129 if (qc->tf.protocol == ATA_PROT_PIO &&
1130 (qc->tf.flags & ATA_TFLAG_WRITE))
1131 return 1;
1133 if (ata_is_atapi(qc->tf.protocol) &&
1134 !(qc->dev->flags & ATA_DFLAG_CDB_INTR))
1135 return 1;
1138 return 0;
1142 * ata_hsm_qc_complete - finish a qc running on standard HSM
1143 * @qc: Command to complete
1144 * @in_wq: 1 if called from workqueue, 0 otherwise
1146 * Finish @qc which is running on standard HSM.
1148 * LOCKING:
1149 * If @in_wq is zero, spin_lock_irqsave(host lock).
1150 * Otherwise, none on entry and grabs host lock.
1152 static void ata_hsm_qc_complete(struct ata_queued_cmd *qc, int in_wq)
1154 struct ata_port *ap = qc->ap;
1155 unsigned long flags;
1157 if (ap->ops->error_handler) {
1158 if (in_wq) {
1159 spin_lock_irqsave(ap->lock, flags);
1161 /* EH might have kicked in while host lock is
1162 * released.
1164 qc = ata_qc_from_tag(ap, qc->tag);
1165 if (qc) {
1166 if (likely(!(qc->err_mask & AC_ERR_HSM))) {
1167 ap->ops->sff_irq_on(ap);
1168 ata_qc_complete(qc);
1169 } else
1170 ata_port_freeze(ap);
1173 spin_unlock_irqrestore(ap->lock, flags);
1174 } else {
1175 if (likely(!(qc->err_mask & AC_ERR_HSM)))
1176 ata_qc_complete(qc);
1177 else
1178 ata_port_freeze(ap);
1180 } else {
1181 if (in_wq) {
1182 spin_lock_irqsave(ap->lock, flags);
1183 ap->ops->sff_irq_on(ap);
1184 ata_qc_complete(qc);
1185 spin_unlock_irqrestore(ap->lock, flags);
1186 } else
1187 ata_qc_complete(qc);
1192 * ata_sff_hsm_move - move the HSM to the next state.
1193 * @ap: the target ata_port
1194 * @qc: qc on going
1195 * @status: current device status
1196 * @in_wq: 1 if called from workqueue, 0 otherwise
1198 * RETURNS:
1199 * 1 when poll next status needed, 0 otherwise.
1201 int ata_sff_hsm_move(struct ata_port *ap, struct ata_queued_cmd *qc,
1202 u8 status, int in_wq)
1204 struct ata_eh_info *ehi = &ap->link.eh_info;
1205 unsigned long flags = 0;
1206 int poll_next;
1208 WARN_ON_ONCE((qc->flags & ATA_QCFLAG_ACTIVE) == 0);
1210 /* Make sure ata_sff_qc_issue() does not throw things
1211 * like DMA polling into the workqueue. Notice that
1212 * in_wq is not equivalent to (qc->tf.flags & ATA_TFLAG_POLLING).
1214 WARN_ON_ONCE(in_wq != ata_hsm_ok_in_wq(ap, qc));
1216 fsm_start:
1217 DPRINTK("ata%u: protocol %d task_state %d (dev_stat 0x%X)\n",
1218 ap->print_id, qc->tf.protocol, ap->hsm_task_state, status);
1220 switch (ap->hsm_task_state) {
1221 case HSM_ST_FIRST:
1222 /* Send first data block or PACKET CDB */
1224 /* If polling, we will stay in the work queue after
1225 * sending the data. Otherwise, interrupt handler
1226 * takes over after sending the data.
1228 poll_next = (qc->tf.flags & ATA_TFLAG_POLLING);
1230 /* check device status */
1231 if (unlikely((status & ATA_DRQ) == 0)) {
1232 /* handle BSY=0, DRQ=0 as error */
1233 if (likely(status & (ATA_ERR | ATA_DF)))
1234 /* device stops HSM for abort/error */
1235 qc->err_mask |= AC_ERR_DEV;
1236 else {
1237 /* HSM violation. Let EH handle this */
1238 ata_ehi_push_desc(ehi,
1239 "ST_FIRST: !(DRQ|ERR|DF)");
1240 qc->err_mask |= AC_ERR_HSM;
1243 ap->hsm_task_state = HSM_ST_ERR;
1244 goto fsm_start;
1247 /* Device should not ask for data transfer (DRQ=1)
1248 * when it finds something wrong.
1249 * We ignore DRQ here and stop the HSM by
1250 * changing hsm_task_state to HSM_ST_ERR and
1251 * let the EH abort the command or reset the device.
1253 if (unlikely(status & (ATA_ERR | ATA_DF))) {
1254 /* Some ATAPI tape drives forget to clear the ERR bit
1255 * when doing the next command (mostly request sense).
1256 * We ignore ERR here to workaround and proceed sending
1257 * the CDB.
1259 if (!(qc->dev->horkage & ATA_HORKAGE_STUCK_ERR)) {
1260 ata_ehi_push_desc(ehi, "ST_FIRST: "
1261 "DRQ=1 with device error, "
1262 "dev_stat 0x%X", status);
1263 qc->err_mask |= AC_ERR_HSM;
1264 ap->hsm_task_state = HSM_ST_ERR;
1265 goto fsm_start;
1269 /* Send the CDB (atapi) or the first data block (ata pio out).
1270 * During the state transition, interrupt handler shouldn't
1271 * be invoked before the data transfer is complete and
1272 * hsm_task_state is changed. Hence, the following locking.
1274 if (in_wq)
1275 spin_lock_irqsave(ap->lock, flags);
1277 if (qc->tf.protocol == ATA_PROT_PIO) {
1278 /* PIO data out protocol.
1279 * send first data block.
1282 /* ata_pio_sectors() might change the state
1283 * to HSM_ST_LAST. so, the state is changed here
1284 * before ata_pio_sectors().
1286 ap->hsm_task_state = HSM_ST;
1287 ata_pio_sectors(qc);
1288 } else
1289 /* send CDB */
1290 atapi_send_cdb(ap, qc);
1292 if (in_wq)
1293 spin_unlock_irqrestore(ap->lock, flags);
1295 /* if polling, ata_pio_task() handles the rest.
1296 * otherwise, interrupt handler takes over from here.
1298 break;
1300 case HSM_ST:
1301 /* complete command or read/write the data register */
1302 if (qc->tf.protocol == ATAPI_PROT_PIO) {
1303 /* ATAPI PIO protocol */
1304 if ((status & ATA_DRQ) == 0) {
1305 /* No more data to transfer or device error.
1306 * Device error will be tagged in HSM_ST_LAST.
1308 ap->hsm_task_state = HSM_ST_LAST;
1309 goto fsm_start;
1312 /* Device should not ask for data transfer (DRQ=1)
1313 * when it finds something wrong.
1314 * We ignore DRQ here and stop the HSM by
1315 * changing hsm_task_state to HSM_ST_ERR and
1316 * let the EH abort the command or reset the device.
1318 if (unlikely(status & (ATA_ERR | ATA_DF))) {
1319 ata_ehi_push_desc(ehi, "ST-ATAPI: "
1320 "DRQ=1 with device error, "
1321 "dev_stat 0x%X", status);
1322 qc->err_mask |= AC_ERR_HSM;
1323 ap->hsm_task_state = HSM_ST_ERR;
1324 goto fsm_start;
1327 atapi_pio_bytes(qc);
1329 if (unlikely(ap->hsm_task_state == HSM_ST_ERR))
1330 /* bad ireason reported by device */
1331 goto fsm_start;
1333 } else {
1334 /* ATA PIO protocol */
1335 if (unlikely((status & ATA_DRQ) == 0)) {
1336 /* handle BSY=0, DRQ=0 as error */
1337 if (likely(status & (ATA_ERR | ATA_DF))) {
1338 /* device stops HSM for abort/error */
1339 qc->err_mask |= AC_ERR_DEV;
1341 /* If diagnostic failed and this is
1342 * IDENTIFY, it's likely a phantom
1343 * device. Mark hint.
1345 if (qc->dev->horkage &
1346 ATA_HORKAGE_DIAGNOSTIC)
1347 qc->err_mask |=
1348 AC_ERR_NODEV_HINT;
1349 } else {
1350 /* HSM violation. Let EH handle this.
1351 * Phantom devices also trigger this
1352 * condition. Mark hint.
1354 ata_ehi_push_desc(ehi, "ST-ATA: "
1355 "DRQ=0 without device error, "
1356 "dev_stat 0x%X", status);
1357 qc->err_mask |= AC_ERR_HSM |
1358 AC_ERR_NODEV_HINT;
1361 ap->hsm_task_state = HSM_ST_ERR;
1362 goto fsm_start;
1365 /* For PIO reads, some devices may ask for
1366 * data transfer (DRQ=1) alone with ERR=1.
1367 * We respect DRQ here and transfer one
1368 * block of junk data before changing the
1369 * hsm_task_state to HSM_ST_ERR.
1371 * For PIO writes, ERR=1 DRQ=1 doesn't make
1372 * sense since the data block has been
1373 * transferred to the device.
1375 if (unlikely(status & (ATA_ERR | ATA_DF))) {
1376 /* data might be corrputed */
1377 qc->err_mask |= AC_ERR_DEV;
1379 if (!(qc->tf.flags & ATA_TFLAG_WRITE)) {
1380 ata_pio_sectors(qc);
1381 status = ata_wait_idle(ap);
1384 if (status & (ATA_BUSY | ATA_DRQ)) {
1385 ata_ehi_push_desc(ehi, "ST-ATA: "
1386 "BUSY|DRQ persists on ERR|DF, "
1387 "dev_stat 0x%X", status);
1388 qc->err_mask |= AC_ERR_HSM;
1391 /* There are oddball controllers with
1392 * status register stuck at 0x7f and
1393 * lbal/m/h at zero which makes it
1394 * pass all other presence detection
1395 * mechanisms we have. Set NODEV_HINT
1396 * for it. Kernel bz#7241.
1398 if (status == 0x7f)
1399 qc->err_mask |= AC_ERR_NODEV_HINT;
1401 /* ata_pio_sectors() might change the
1402 * state to HSM_ST_LAST. so, the state
1403 * is changed after ata_pio_sectors().
1405 ap->hsm_task_state = HSM_ST_ERR;
1406 goto fsm_start;
1409 ata_pio_sectors(qc);
1411 if (ap->hsm_task_state == HSM_ST_LAST &&
1412 (!(qc->tf.flags & ATA_TFLAG_WRITE))) {
1413 /* all data read */
1414 status = ata_wait_idle(ap);
1415 goto fsm_start;
1419 poll_next = 1;
1420 break;
1422 case HSM_ST_LAST:
1423 if (unlikely(!ata_ok(status))) {
1424 qc->err_mask |= __ac_err_mask(status);
1425 ap->hsm_task_state = HSM_ST_ERR;
1426 goto fsm_start;
1429 /* no more data to transfer */
1430 DPRINTK("ata%u: dev %u command complete, drv_stat 0x%x\n",
1431 ap->print_id, qc->dev->devno, status);
1433 WARN_ON_ONCE(qc->err_mask & (AC_ERR_DEV | AC_ERR_HSM));
1435 ap->hsm_task_state = HSM_ST_IDLE;
1437 /* complete taskfile transaction */
1438 ata_hsm_qc_complete(qc, in_wq);
1440 poll_next = 0;
1441 break;
1443 case HSM_ST_ERR:
1444 ap->hsm_task_state = HSM_ST_IDLE;
1446 /* complete taskfile transaction */
1447 ata_hsm_qc_complete(qc, in_wq);
1449 poll_next = 0;
1450 break;
1451 default:
1452 poll_next = 0;
1453 BUG();
1456 return poll_next;
1458 EXPORT_SYMBOL_GPL(ata_sff_hsm_move);
1460 void ata_pio_task(struct work_struct *work)
1462 struct ata_port *ap =
1463 container_of(work, struct ata_port, port_task.work);
1464 struct ata_queued_cmd *qc = ap->port_task_data;
1465 u8 status;
1466 int poll_next;
1468 fsm_start:
1469 WARN_ON_ONCE(ap->hsm_task_state == HSM_ST_IDLE);
1472 * This is purely heuristic. This is a fast path.
1473 * Sometimes when we enter, BSY will be cleared in
1474 * a chk-status or two. If not, the drive is probably seeking
1475 * or something. Snooze for a couple msecs, then
1476 * chk-status again. If still busy, queue delayed work.
1478 status = ata_sff_busy_wait(ap, ATA_BUSY, 5);
1479 if (status & ATA_BUSY) {
1480 msleep(2);
1481 status = ata_sff_busy_wait(ap, ATA_BUSY, 10);
1482 if (status & ATA_BUSY) {
1483 ata_pio_queue_task(ap, qc, ATA_SHORT_PAUSE);
1484 return;
1488 /* move the HSM */
1489 poll_next = ata_sff_hsm_move(ap, qc, status, 1);
1491 /* another command or interrupt handler
1492 * may be running at this point.
1494 if (poll_next)
1495 goto fsm_start;
1499 * ata_sff_qc_issue - issue taskfile to device in proto-dependent manner
1500 * @qc: command to issue to device
1502 * Using various libata functions and hooks, this function
1503 * starts an ATA command. ATA commands are grouped into
1504 * classes called "protocols", and issuing each type of protocol
1505 * is slightly different.
1507 * May be used as the qc_issue() entry in ata_port_operations.
1509 * LOCKING:
1510 * spin_lock_irqsave(host lock)
1512 * RETURNS:
1513 * Zero on success, AC_ERR_* mask on failure
1515 unsigned int ata_sff_qc_issue(struct ata_queued_cmd *qc)
1517 struct ata_port *ap = qc->ap;
1519 /* Use polling pio if the LLD doesn't handle
1520 * interrupt driven pio and atapi CDB interrupt.
1522 if (ap->flags & ATA_FLAG_PIO_POLLING) {
1523 switch (qc->tf.protocol) {
1524 case ATA_PROT_PIO:
1525 case ATA_PROT_NODATA:
1526 case ATAPI_PROT_PIO:
1527 case ATAPI_PROT_NODATA:
1528 qc->tf.flags |= ATA_TFLAG_POLLING;
1529 break;
1530 case ATAPI_PROT_DMA:
1531 if (qc->dev->flags & ATA_DFLAG_CDB_INTR)
1532 /* see ata_dma_blacklisted() */
1533 BUG();
1534 break;
1535 default:
1536 break;
1540 /* select the device */
1541 ata_dev_select(ap, qc->dev->devno, 1, 0);
1543 /* start the command */
1544 switch (qc->tf.protocol) {
1545 case ATA_PROT_NODATA:
1546 if (qc->tf.flags & ATA_TFLAG_POLLING)
1547 ata_qc_set_polling(qc);
1549 ata_tf_to_host(ap, &qc->tf);
1550 ap->hsm_task_state = HSM_ST_LAST;
1552 if (qc->tf.flags & ATA_TFLAG_POLLING)
1553 ata_pio_queue_task(ap, qc, 0);
1555 break;
1557 case ATA_PROT_DMA:
1558 WARN_ON_ONCE(qc->tf.flags & ATA_TFLAG_POLLING);
1560 ap->ops->sff_tf_load(ap, &qc->tf); /* load tf registers */
1561 ap->ops->bmdma_setup(qc); /* set up bmdma */
1562 ap->ops->bmdma_start(qc); /* initiate bmdma */
1563 ap->hsm_task_state = HSM_ST_LAST;
1564 break;
1566 case ATA_PROT_PIO:
1567 if (qc->tf.flags & ATA_TFLAG_POLLING)
1568 ata_qc_set_polling(qc);
1570 ata_tf_to_host(ap, &qc->tf);
1572 if (qc->tf.flags & ATA_TFLAG_WRITE) {
1573 /* PIO data out protocol */
1574 ap->hsm_task_state = HSM_ST_FIRST;
1575 ata_pio_queue_task(ap, qc, 0);
1577 /* always send first data block using
1578 * the ata_pio_task() codepath.
1580 } else {
1581 /* PIO data in protocol */
1582 ap->hsm_task_state = HSM_ST;
1584 if (qc->tf.flags & ATA_TFLAG_POLLING)
1585 ata_pio_queue_task(ap, qc, 0);
1587 /* if polling, ata_pio_task() handles the rest.
1588 * otherwise, interrupt handler takes over from here.
1592 break;
1594 case ATAPI_PROT_PIO:
1595 case ATAPI_PROT_NODATA:
1596 if (qc->tf.flags & ATA_TFLAG_POLLING)
1597 ata_qc_set_polling(qc);
1599 ata_tf_to_host(ap, &qc->tf);
1601 ap->hsm_task_state = HSM_ST_FIRST;
1603 /* send cdb by polling if no cdb interrupt */
1604 if ((!(qc->dev->flags & ATA_DFLAG_CDB_INTR)) ||
1605 (qc->tf.flags & ATA_TFLAG_POLLING))
1606 ata_pio_queue_task(ap, qc, 0);
1607 break;
1609 case ATAPI_PROT_DMA:
1610 WARN_ON_ONCE(qc->tf.flags & ATA_TFLAG_POLLING);
1612 ap->ops->sff_tf_load(ap, &qc->tf); /* load tf registers */
1613 ap->ops->bmdma_setup(qc); /* set up bmdma */
1614 ap->hsm_task_state = HSM_ST_FIRST;
1616 /* send cdb by polling if no cdb interrupt */
1617 if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR))
1618 ata_pio_queue_task(ap, qc, 0);
1619 break;
1621 default:
1622 WARN_ON_ONCE(1);
1623 return AC_ERR_SYSTEM;
1626 return 0;
1628 EXPORT_SYMBOL_GPL(ata_sff_qc_issue);
1631 * ata_sff_qc_fill_rtf - fill result TF using ->sff_tf_read
1632 * @qc: qc to fill result TF for
1634 * @qc is finished and result TF needs to be filled. Fill it
1635 * using ->sff_tf_read.
1637 * LOCKING:
1638 * spin_lock_irqsave(host lock)
1640 * RETURNS:
1641 * true indicating that result TF is successfully filled.
1643 bool ata_sff_qc_fill_rtf(struct ata_queued_cmd *qc)
1645 qc->ap->ops->sff_tf_read(qc->ap, &qc->result_tf);
1646 return true;
1648 EXPORT_SYMBOL_GPL(ata_sff_qc_fill_rtf);
1651 * ata_sff_host_intr - Handle host interrupt for given (port, task)
1652 * @ap: Port on which interrupt arrived (possibly...)
1653 * @qc: Taskfile currently active in engine
1655 * Handle host interrupt for given queued command. Currently,
1656 * only DMA interrupts are handled. All other commands are
1657 * handled via polling with interrupts disabled (nIEN bit).
1659 * LOCKING:
1660 * spin_lock_irqsave(host lock)
1662 * RETURNS:
1663 * One if interrupt was handled, zero if not (shared irq).
1665 unsigned int ata_sff_host_intr(struct ata_port *ap,
1666 struct ata_queued_cmd *qc)
1668 struct ata_eh_info *ehi = &ap->link.eh_info;
1669 u8 status, host_stat = 0;
1671 VPRINTK("ata%u: protocol %d task_state %d\n",
1672 ap->print_id, qc->tf.protocol, ap->hsm_task_state);
1674 /* Check whether we are expecting interrupt in this state */
1675 switch (ap->hsm_task_state) {
1676 case HSM_ST_FIRST:
1677 /* Some pre-ATAPI-4 devices assert INTRQ
1678 * at this state when ready to receive CDB.
1681 /* Check the ATA_DFLAG_CDB_INTR flag is enough here.
1682 * The flag was turned on only for atapi devices. No
1683 * need to check ata_is_atapi(qc->tf.protocol) again.
1685 if (!(qc->dev->flags & ATA_DFLAG_CDB_INTR))
1686 goto idle_irq;
1687 break;
1688 case HSM_ST_LAST:
1689 if (qc->tf.protocol == ATA_PROT_DMA ||
1690 qc->tf.protocol == ATAPI_PROT_DMA) {
1691 /* check status of DMA engine */
1692 host_stat = ap->ops->bmdma_status(ap);
1693 VPRINTK("ata%u: host_stat 0x%X\n",
1694 ap->print_id, host_stat);
1696 /* if it's not our irq... */
1697 if (!(host_stat & ATA_DMA_INTR))
1698 goto idle_irq;
1700 /* before we do anything else, clear DMA-Start bit */
1701 ap->ops->bmdma_stop(qc);
1703 if (unlikely(host_stat & ATA_DMA_ERR)) {
1704 /* error when transfering data to/from memory */
1705 qc->err_mask |= AC_ERR_HOST_BUS;
1706 ap->hsm_task_state = HSM_ST_ERR;
1709 break;
1710 case HSM_ST:
1711 break;
1712 default:
1713 goto idle_irq;
1717 /* check main status, clearing INTRQ if needed */
1718 status = ata_sff_irq_status(ap);
1719 if (status & ATA_BUSY)
1720 goto idle_irq;
1722 /* ack bmdma irq events */
1723 ap->ops->sff_irq_clear(ap);
1725 ata_sff_hsm_move(ap, qc, status, 0);
1727 if (unlikely(qc->err_mask) && (qc->tf.protocol == ATA_PROT_DMA ||
1728 qc->tf.protocol == ATAPI_PROT_DMA))
1729 ata_ehi_push_desc(ehi, "BMDMA stat 0x%x", host_stat);
1731 return 1; /* irq handled */
1733 idle_irq:
1734 ap->stats.idle_irq++;
1736 #ifdef ATA_IRQ_TRAP
1737 if ((ap->stats.idle_irq % 1000) == 0) {
1738 ap->ops->sff_check_status(ap);
1739 ap->ops->sff_irq_clear(ap);
1740 ata_port_printk(ap, KERN_WARNING, "irq trap\n");
1741 return 1;
1743 #endif
1744 return 0; /* irq not handled */
1746 EXPORT_SYMBOL_GPL(ata_sff_host_intr);
1749 * ata_sff_interrupt - Default ATA host interrupt handler
1750 * @irq: irq line (unused)
1751 * @dev_instance: pointer to our ata_host information structure
1753 * Default interrupt handler for PCI IDE devices. Calls
1754 * ata_sff_host_intr() for each port that is not disabled.
1756 * LOCKING:
1757 * Obtains host lock during operation.
1759 * RETURNS:
1760 * IRQ_NONE or IRQ_HANDLED.
1762 irqreturn_t ata_sff_interrupt(int irq, void *dev_instance)
1764 struct ata_host *host = dev_instance;
1765 unsigned int i;
1766 unsigned int handled = 0;
1767 unsigned long flags;
1769 /* TODO: make _irqsave conditional on x86 PCI IDE legacy mode */
1770 spin_lock_irqsave(&host->lock, flags);
1772 for (i = 0; i < host->n_ports; i++) {
1773 struct ata_port *ap;
1775 ap = host->ports[i];
1776 if (ap &&
1777 !(ap->flags & ATA_FLAG_DISABLED)) {
1778 struct ata_queued_cmd *qc;
1780 qc = ata_qc_from_tag(ap, ap->link.active_tag);
1781 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)) &&
1782 (qc->flags & ATA_QCFLAG_ACTIVE))
1783 handled |= ata_sff_host_intr(ap, qc);
1787 spin_unlock_irqrestore(&host->lock, flags);
1789 return IRQ_RETVAL(handled);
1791 EXPORT_SYMBOL_GPL(ata_sff_interrupt);
1794 * ata_sff_lost_interrupt - Check for an apparent lost interrupt
1795 * @ap: port that appears to have timed out
1797 * Called from the libata error handlers when the core code suspects
1798 * an interrupt has been lost. If it has complete anything we can and
1799 * then return. Interface must support altstatus for this faster
1800 * recovery to occur.
1802 * Locking:
1803 * Caller holds host lock
1806 void ata_sff_lost_interrupt(struct ata_port *ap)
1808 u8 status;
1809 struct ata_queued_cmd *qc;
1811 /* Only one outstanding command per SFF channel */
1812 qc = ata_qc_from_tag(ap, ap->link.active_tag);
1813 /* Check we have a live one.. */
1814 if (qc == NULL || !(qc->flags & ATA_QCFLAG_ACTIVE))
1815 return;
1816 /* We cannot lose an interrupt on a polled command */
1817 if (qc->tf.flags & ATA_TFLAG_POLLING)
1818 return;
1819 /* See if the controller thinks it is still busy - if so the command
1820 isn't a lost IRQ but is still in progress */
1821 status = ata_sff_altstatus(ap);
1822 if (status & ATA_BUSY)
1823 return;
1825 /* There was a command running, we are no longer busy and we have
1826 no interrupt. */
1827 ata_port_printk(ap, KERN_WARNING, "lost interrupt (Status 0x%x)\n",
1828 status);
1829 /* Run the host interrupt logic as if the interrupt had not been
1830 lost */
1831 ata_sff_host_intr(ap, qc);
1833 EXPORT_SYMBOL_GPL(ata_sff_lost_interrupt);
1836 * ata_sff_freeze - Freeze SFF controller port
1837 * @ap: port to freeze
1839 * Freeze BMDMA controller port.
1841 * LOCKING:
1842 * Inherited from caller.
1844 void ata_sff_freeze(struct ata_port *ap)
1846 struct ata_ioports *ioaddr = &ap->ioaddr;
1848 ap->ctl |= ATA_NIEN;
1849 ap->last_ctl = ap->ctl;
1851 if (ioaddr->ctl_addr)
1852 iowrite8(ap->ctl, ioaddr->ctl_addr);
1854 /* Under certain circumstances, some controllers raise IRQ on
1855 * ATA_NIEN manipulation. Also, many controllers fail to mask
1856 * previously pending IRQ on ATA_NIEN assertion. Clear it.
1858 ap->ops->sff_check_status(ap);
1860 ap->ops->sff_irq_clear(ap);
1862 EXPORT_SYMBOL_GPL(ata_sff_freeze);
1865 * ata_sff_thaw - Thaw SFF controller port
1866 * @ap: port to thaw
1868 * Thaw SFF controller port.
1870 * LOCKING:
1871 * Inherited from caller.
1873 void ata_sff_thaw(struct ata_port *ap)
1875 /* clear & re-enable interrupts */
1876 ap->ops->sff_check_status(ap);
1877 ap->ops->sff_irq_clear(ap);
1878 ap->ops->sff_irq_on(ap);
1880 EXPORT_SYMBOL_GPL(ata_sff_thaw);
1883 * ata_sff_prereset - prepare SFF link for reset
1884 * @link: SFF link to be reset
1885 * @deadline: deadline jiffies for the operation
1887 * SFF link @link is about to be reset. Initialize it. It first
1888 * calls ata_std_prereset() and wait for !BSY if the port is
1889 * being softreset.
1891 * LOCKING:
1892 * Kernel thread context (may sleep)
1894 * RETURNS:
1895 * 0 on success, -errno otherwise.
1897 int ata_sff_prereset(struct ata_link *link, unsigned long deadline)
1899 struct ata_eh_context *ehc = &link->eh_context;
1900 int rc;
1902 rc = ata_std_prereset(link, deadline);
1903 if (rc)
1904 return rc;
1906 /* if we're about to do hardreset, nothing more to do */
1907 if (ehc->i.action & ATA_EH_HARDRESET)
1908 return 0;
1910 /* wait for !BSY if we don't know that no device is attached */
1911 if (!ata_link_offline(link)) {
1912 rc = ata_sff_wait_ready(link, deadline);
1913 if (rc && rc != -ENODEV) {
1914 ata_link_printk(link, KERN_WARNING, "device not ready "
1915 "(errno=%d), forcing hardreset\n", rc);
1916 ehc->i.action |= ATA_EH_HARDRESET;
1920 return 0;
1922 EXPORT_SYMBOL_GPL(ata_sff_prereset);
1925 * ata_devchk - PATA device presence detection
1926 * @ap: ATA channel to examine
1927 * @device: Device to examine (starting at zero)
1929 * This technique was originally described in
1930 * Hale Landis's ATADRVR (www.ata-atapi.com), and
1931 * later found its way into the ATA/ATAPI spec.
1933 * Write a pattern to the ATA shadow registers,
1934 * and if a device is present, it will respond by
1935 * correctly storing and echoing back the
1936 * ATA shadow register contents.
1938 * LOCKING:
1939 * caller.
1941 static unsigned int ata_devchk(struct ata_port *ap, unsigned int device)
1943 struct ata_ioports *ioaddr = &ap->ioaddr;
1944 u8 nsect, lbal;
1946 ap->ops->sff_dev_select(ap, device);
1948 iowrite8(0x55, ioaddr->nsect_addr);
1949 iowrite8(0xaa, ioaddr->lbal_addr);
1951 iowrite8(0xaa, ioaddr->nsect_addr);
1952 iowrite8(0x55, ioaddr->lbal_addr);
1954 iowrite8(0x55, ioaddr->nsect_addr);
1955 iowrite8(0xaa, ioaddr->lbal_addr);
1957 nsect = ioread8(ioaddr->nsect_addr);
1958 lbal = ioread8(ioaddr->lbal_addr);
1960 if ((nsect == 0x55) && (lbal == 0xaa))
1961 return 1; /* we found a device */
1963 return 0; /* nothing found */
1967 * ata_sff_dev_classify - Parse returned ATA device signature
1968 * @dev: ATA device to classify (starting at zero)
1969 * @present: device seems present
1970 * @r_err: Value of error register on completion
1972 * After an event -- SRST, E.D.D., or SATA COMRESET -- occurs,
1973 * an ATA/ATAPI-defined set of values is placed in the ATA
1974 * shadow registers, indicating the results of device detection
1975 * and diagnostics.
1977 * Select the ATA device, and read the values from the ATA shadow
1978 * registers. Then parse according to the Error register value,
1979 * and the spec-defined values examined by ata_dev_classify().
1981 * LOCKING:
1982 * caller.
1984 * RETURNS:
1985 * Device type - %ATA_DEV_ATA, %ATA_DEV_ATAPI or %ATA_DEV_NONE.
1987 unsigned int ata_sff_dev_classify(struct ata_device *dev, int present,
1988 u8 *r_err)
1990 struct ata_port *ap = dev->link->ap;
1991 struct ata_taskfile tf;
1992 unsigned int class;
1993 u8 err;
1995 ap->ops->sff_dev_select(ap, dev->devno);
1997 memset(&tf, 0, sizeof(tf));
1999 ap->ops->sff_tf_read(ap, &tf);
2000 err = tf.feature;
2001 if (r_err)
2002 *r_err = err;
2004 /* see if device passed diags: continue and warn later */
2005 if (err == 0)
2006 /* diagnostic fail : do nothing _YET_ */
2007 dev->horkage |= ATA_HORKAGE_DIAGNOSTIC;
2008 else if (err == 1)
2009 /* do nothing */ ;
2010 else if ((dev->devno == 0) && (err == 0x81))
2011 /* do nothing */ ;
2012 else
2013 return ATA_DEV_NONE;
2015 /* determine if device is ATA or ATAPI */
2016 class = ata_dev_classify(&tf);
2018 if (class == ATA_DEV_UNKNOWN) {
2019 /* If the device failed diagnostic, it's likely to
2020 * have reported incorrect device signature too.
2021 * Assume ATA device if the device seems present but
2022 * device signature is invalid with diagnostic
2023 * failure.
2025 if (present && (dev->horkage & ATA_HORKAGE_DIAGNOSTIC))
2026 class = ATA_DEV_ATA;
2027 else
2028 class = ATA_DEV_NONE;
2029 } else if ((class == ATA_DEV_ATA) &&
2030 (ap->ops->sff_check_status(ap) == 0))
2031 class = ATA_DEV_NONE;
2033 return class;
2035 EXPORT_SYMBOL_GPL(ata_sff_dev_classify);
2038 * ata_sff_wait_after_reset - wait for devices to become ready after reset
2039 * @link: SFF link which is just reset
2040 * @devmask: mask of present devices
2041 * @deadline: deadline jiffies for the operation
2043 * Wait devices attached to SFF @link to become ready after
2044 * reset. It contains preceding 150ms wait to avoid accessing TF
2045 * status register too early.
2047 * LOCKING:
2048 * Kernel thread context (may sleep).
2050 * RETURNS:
2051 * 0 on success, -ENODEV if some or all of devices in @devmask
2052 * don't seem to exist. -errno on other errors.
2054 int ata_sff_wait_after_reset(struct ata_link *link, unsigned int devmask,
2055 unsigned long deadline)
2057 struct ata_port *ap = link->ap;
2058 struct ata_ioports *ioaddr = &ap->ioaddr;
2059 unsigned int dev0 = devmask & (1 << 0);
2060 unsigned int dev1 = devmask & (1 << 1);
2061 int rc, ret = 0;
2063 msleep(ATA_WAIT_AFTER_RESET);
2065 /* always check readiness of the master device */
2066 rc = ata_sff_wait_ready(link, deadline);
2067 /* -ENODEV means the odd clown forgot the D7 pulldown resistor
2068 * and TF status is 0xff, bail out on it too.
2070 if (rc)
2071 return rc;
2073 /* if device 1 was found in ata_devchk, wait for register
2074 * access briefly, then wait for BSY to clear.
2076 if (dev1) {
2077 int i;
2079 ap->ops->sff_dev_select(ap, 1);
2081 /* Wait for register access. Some ATAPI devices fail
2082 * to set nsect/lbal after reset, so don't waste too
2083 * much time on it. We're gonna wait for !BSY anyway.
2085 for (i = 0; i < 2; i++) {
2086 u8 nsect, lbal;
2088 nsect = ioread8(ioaddr->nsect_addr);
2089 lbal = ioread8(ioaddr->lbal_addr);
2090 if ((nsect == 1) && (lbal == 1))
2091 break;
2092 msleep(50); /* give drive a breather */
2095 rc = ata_sff_wait_ready(link, deadline);
2096 if (rc) {
2097 if (rc != -ENODEV)
2098 return rc;
2099 ret = rc;
2103 /* is all this really necessary? */
2104 ap->ops->sff_dev_select(ap, 0);
2105 if (dev1)
2106 ap->ops->sff_dev_select(ap, 1);
2107 if (dev0)
2108 ap->ops->sff_dev_select(ap, 0);
2110 return ret;
2112 EXPORT_SYMBOL_GPL(ata_sff_wait_after_reset);
2114 static int ata_bus_softreset(struct ata_port *ap, unsigned int devmask,
2115 unsigned long deadline)
2117 struct ata_ioports *ioaddr = &ap->ioaddr;
2119 DPRINTK("ata%u: bus reset via SRST\n", ap->print_id);
2121 /* software reset. causes dev0 to be selected */
2122 iowrite8(ap->ctl, ioaddr->ctl_addr);
2123 udelay(20); /* FIXME: flush */
2124 iowrite8(ap->ctl | ATA_SRST, ioaddr->ctl_addr);
2125 udelay(20); /* FIXME: flush */
2126 iowrite8(ap->ctl, ioaddr->ctl_addr);
2127 ap->last_ctl = ap->ctl;
2129 /* wait the port to become ready */
2130 return ata_sff_wait_after_reset(&ap->link, devmask, deadline);
2134 * ata_sff_softreset - reset host port via ATA SRST
2135 * @link: ATA link to reset
2136 * @classes: resulting classes of attached devices
2137 * @deadline: deadline jiffies for the operation
2139 * Reset host port using ATA SRST.
2141 * LOCKING:
2142 * Kernel thread context (may sleep)
2144 * RETURNS:
2145 * 0 on success, -errno otherwise.
2147 int ata_sff_softreset(struct ata_link *link, unsigned int *classes,
2148 unsigned long deadline)
2150 struct ata_port *ap = link->ap;
2151 unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS;
2152 unsigned int devmask = 0;
2153 int rc;
2154 u8 err;
2156 DPRINTK("ENTER\n");
2158 /* determine if device 0/1 are present */
2159 if (ata_devchk(ap, 0))
2160 devmask |= (1 << 0);
2161 if (slave_possible && ata_devchk(ap, 1))
2162 devmask |= (1 << 1);
2164 /* select device 0 again */
2165 ap->ops->sff_dev_select(ap, 0);
2167 /* issue bus reset */
2168 DPRINTK("about to softreset, devmask=%x\n", devmask);
2169 rc = ata_bus_softreset(ap, devmask, deadline);
2170 /* if link is occupied, -ENODEV too is an error */
2171 if (rc && (rc != -ENODEV || sata_scr_valid(link))) {
2172 ata_link_printk(link, KERN_ERR, "SRST failed (errno=%d)\n", rc);
2173 return rc;
2176 /* determine by signature whether we have ATA or ATAPI devices */
2177 classes[0] = ata_sff_dev_classify(&link->device[0],
2178 devmask & (1 << 0), &err);
2179 if (slave_possible && err != 0x81)
2180 classes[1] = ata_sff_dev_classify(&link->device[1],
2181 devmask & (1 << 1), &err);
2183 DPRINTK("EXIT, classes[0]=%u [1]=%u\n", classes[0], classes[1]);
2184 return 0;
2186 EXPORT_SYMBOL_GPL(ata_sff_softreset);
2189 * sata_sff_hardreset - reset host port via SATA phy reset
2190 * @link: link to reset
2191 * @class: resulting class of attached device
2192 * @deadline: deadline jiffies for the operation
2194 * SATA phy-reset host port using DET bits of SControl register,
2195 * wait for !BSY and classify the attached device.
2197 * LOCKING:
2198 * Kernel thread context (may sleep)
2200 * RETURNS:
2201 * 0 on success, -errno otherwise.
2203 int sata_sff_hardreset(struct ata_link *link, unsigned int *class,
2204 unsigned long deadline)
2206 struct ata_eh_context *ehc = &link->eh_context;
2207 const unsigned long *timing = sata_ehc_deb_timing(ehc);
2208 bool online;
2209 int rc;
2211 rc = sata_link_hardreset(link, timing, deadline, &online,
2212 ata_sff_check_ready);
2213 if (online)
2214 *class = ata_sff_dev_classify(link->device, 1, NULL);
2216 DPRINTK("EXIT, class=%u\n", *class);
2217 return rc;
2219 EXPORT_SYMBOL_GPL(sata_sff_hardreset);
2222 * ata_sff_postreset - SFF postreset callback
2223 * @link: the target SFF ata_link
2224 * @classes: classes of attached devices
2226 * This function is invoked after a successful reset. It first
2227 * calls ata_std_postreset() and performs SFF specific postreset
2228 * processing.
2230 * LOCKING:
2231 * Kernel thread context (may sleep)
2233 void ata_sff_postreset(struct ata_link *link, unsigned int *classes)
2235 struct ata_port *ap = link->ap;
2237 ata_std_postreset(link, classes);
2239 /* is double-select really necessary? */
2240 if (classes[0] != ATA_DEV_NONE)
2241 ap->ops->sff_dev_select(ap, 1);
2242 if (classes[1] != ATA_DEV_NONE)
2243 ap->ops->sff_dev_select(ap, 0);
2245 /* bail out if no device is present */
2246 if (classes[0] == ATA_DEV_NONE && classes[1] == ATA_DEV_NONE) {
2247 DPRINTK("EXIT, no device\n");
2248 return;
2251 /* set up device control */
2252 if (ap->ioaddr.ctl_addr) {
2253 iowrite8(ap->ctl, ap->ioaddr.ctl_addr);
2254 ap->last_ctl = ap->ctl;
2257 EXPORT_SYMBOL_GPL(ata_sff_postreset);
2260 * ata_sff_drain_fifo - Stock FIFO drain logic for SFF controllers
2261 * @qc: command
2263 * Drain the FIFO and device of any stuck data following a command
2264 * failing to complete. In some cases this is neccessary before a
2265 * reset will recover the device.
2269 void ata_sff_drain_fifo(struct ata_queued_cmd *qc)
2271 int count;
2272 struct ata_port *ap;
2274 /* We only need to flush incoming data when a command was running */
2275 if (qc == NULL || qc->dma_dir == DMA_TO_DEVICE)
2276 return;
2278 ap = qc->ap;
2279 /* Drain up to 64K of data before we give up this recovery method */
2280 for (count = 0; (ap->ops->sff_check_status(ap) & ATA_DRQ)
2281 && count < 65536; count += 2)
2282 ioread16(ap->ioaddr.data_addr);
2284 /* Can become DEBUG later */
2285 if (count)
2286 ata_port_printk(ap, KERN_DEBUG,
2287 "drained %d bytes to clear DRQ.\n", count);
2290 EXPORT_SYMBOL_GPL(ata_sff_drain_fifo);
2293 * ata_sff_error_handler - Stock error handler for BMDMA controller
2294 * @ap: port to handle error for
2296 * Stock error handler for SFF controller. It can handle both
2297 * PATA and SATA controllers. Many controllers should be able to
2298 * use this EH as-is or with some added handling before and
2299 * after.
2301 * LOCKING:
2302 * Kernel thread context (may sleep)
2304 void ata_sff_error_handler(struct ata_port *ap)
2306 ata_reset_fn_t softreset = ap->ops->softreset;
2307 ata_reset_fn_t hardreset = ap->ops->hardreset;
2308 struct ata_queued_cmd *qc;
2309 unsigned long flags;
2310 int thaw = 0;
2312 qc = __ata_qc_from_tag(ap, ap->link.active_tag);
2313 if (qc && !(qc->flags & ATA_QCFLAG_FAILED))
2314 qc = NULL;
2316 /* reset PIO HSM and stop DMA engine */
2317 spin_lock_irqsave(ap->lock, flags);
2319 ap->hsm_task_state = HSM_ST_IDLE;
2321 if (ap->ioaddr.bmdma_addr &&
2322 qc && (qc->tf.protocol == ATA_PROT_DMA ||
2323 qc->tf.protocol == ATAPI_PROT_DMA)) {
2324 u8 host_stat;
2326 host_stat = ap->ops->bmdma_status(ap);
2328 /* BMDMA controllers indicate host bus error by
2329 * setting DMA_ERR bit and timing out. As it wasn't
2330 * really a timeout event, adjust error mask and
2331 * cancel frozen state.
2333 if (qc->err_mask == AC_ERR_TIMEOUT
2334 && (host_stat & ATA_DMA_ERR)) {
2335 qc->err_mask = AC_ERR_HOST_BUS;
2336 thaw = 1;
2339 ap->ops->bmdma_stop(qc);
2342 ata_sff_sync(ap); /* FIXME: We don't need this */
2343 ap->ops->sff_check_status(ap);
2344 ap->ops->sff_irq_clear(ap);
2345 /* We *MUST* do FIFO draining before we issue a reset as several
2346 * devices helpfully clear their internal state and will lock solid
2347 * if we touch the data port post reset. Pass qc in case anyone wants
2348 * to do different PIO/DMA recovery or has per command fixups
2350 if (ap->ops->drain_fifo)
2351 ap->ops->drain_fifo(qc);
2353 spin_unlock_irqrestore(ap->lock, flags);
2355 if (thaw)
2356 ata_eh_thaw_port(ap);
2358 /* PIO and DMA engines have been stopped, perform recovery */
2360 /* Ignore ata_sff_softreset if ctl isn't accessible and
2361 * built-in hardresets if SCR access isn't available.
2363 if (softreset == ata_sff_softreset && !ap->ioaddr.ctl_addr)
2364 softreset = NULL;
2365 if (ata_is_builtin_hardreset(hardreset) && !sata_scr_valid(&ap->link))
2366 hardreset = NULL;
2368 ata_do_eh(ap, ap->ops->prereset, softreset, hardreset,
2369 ap->ops->postreset);
2371 EXPORT_SYMBOL_GPL(ata_sff_error_handler);
2374 * ata_sff_post_internal_cmd - Stock post_internal_cmd for SFF controller
2375 * @qc: internal command to clean up
2377 * LOCKING:
2378 * Kernel thread context (may sleep)
2380 void ata_sff_post_internal_cmd(struct ata_queued_cmd *qc)
2382 struct ata_port *ap = qc->ap;
2383 unsigned long flags;
2385 spin_lock_irqsave(ap->lock, flags);
2387 ap->hsm_task_state = HSM_ST_IDLE;
2389 if (ap->ioaddr.bmdma_addr)
2390 ap->ops->bmdma_stop(qc);
2392 spin_unlock_irqrestore(ap->lock, flags);
2394 EXPORT_SYMBOL_GPL(ata_sff_post_internal_cmd);
2397 * ata_sff_port_start - Set port up for dma.
2398 * @ap: Port to initialize
2400 * Called just after data structures for each port are
2401 * initialized. Allocates space for PRD table if the device
2402 * is DMA capable SFF.
2404 * May be used as the port_start() entry in ata_port_operations.
2406 * LOCKING:
2407 * Inherited from caller.
2409 int ata_sff_port_start(struct ata_port *ap)
2411 if (ap->ioaddr.bmdma_addr)
2412 return ata_port_start(ap);
2413 return 0;
2415 EXPORT_SYMBOL_GPL(ata_sff_port_start);
2418 * ata_sff_port_start32 - Set port up for dma.
2419 * @ap: Port to initialize
2421 * Called just after data structures for each port are
2422 * initialized. Allocates space for PRD table if the device
2423 * is DMA capable SFF.
2425 * May be used as the port_start() entry in ata_port_operations for
2426 * devices that are capable of 32bit PIO.
2428 * LOCKING:
2429 * Inherited from caller.
2431 int ata_sff_port_start32(struct ata_port *ap)
2433 ap->pflags |= ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE;
2434 if (ap->ioaddr.bmdma_addr)
2435 return ata_port_start(ap);
2436 return 0;
2438 EXPORT_SYMBOL_GPL(ata_sff_port_start32);
2441 * ata_sff_std_ports - initialize ioaddr with standard port offsets.
2442 * @ioaddr: IO address structure to be initialized
2444 * Utility function which initializes data_addr, error_addr,
2445 * feature_addr, nsect_addr, lbal_addr, lbam_addr, lbah_addr,
2446 * device_addr, status_addr, and command_addr to standard offsets
2447 * relative to cmd_addr.
2449 * Does not set ctl_addr, altstatus_addr, bmdma_addr, or scr_addr.
2451 void ata_sff_std_ports(struct ata_ioports *ioaddr)
2453 ioaddr->data_addr = ioaddr->cmd_addr + ATA_REG_DATA;
2454 ioaddr->error_addr = ioaddr->cmd_addr + ATA_REG_ERR;
2455 ioaddr->feature_addr = ioaddr->cmd_addr + ATA_REG_FEATURE;
2456 ioaddr->nsect_addr = ioaddr->cmd_addr + ATA_REG_NSECT;
2457 ioaddr->lbal_addr = ioaddr->cmd_addr + ATA_REG_LBAL;
2458 ioaddr->lbam_addr = ioaddr->cmd_addr + ATA_REG_LBAM;
2459 ioaddr->lbah_addr = ioaddr->cmd_addr + ATA_REG_LBAH;
2460 ioaddr->device_addr = ioaddr->cmd_addr + ATA_REG_DEVICE;
2461 ioaddr->status_addr = ioaddr->cmd_addr + ATA_REG_STATUS;
2462 ioaddr->command_addr = ioaddr->cmd_addr + ATA_REG_CMD;
2464 EXPORT_SYMBOL_GPL(ata_sff_std_ports);
2466 unsigned long ata_bmdma_mode_filter(struct ata_device *adev,
2467 unsigned long xfer_mask)
2469 /* Filter out DMA modes if the device has been configured by
2470 the BIOS as PIO only */
2472 if (adev->link->ap->ioaddr.bmdma_addr == NULL)
2473 xfer_mask &= ~(ATA_MASK_MWDMA | ATA_MASK_UDMA);
2474 return xfer_mask;
2476 EXPORT_SYMBOL_GPL(ata_bmdma_mode_filter);
2479 * ata_bmdma_setup - Set up PCI IDE BMDMA transaction
2480 * @qc: Info associated with this ATA transaction.
2482 * LOCKING:
2483 * spin_lock_irqsave(host lock)
2485 void ata_bmdma_setup(struct ata_queued_cmd *qc)
2487 struct ata_port *ap = qc->ap;
2488 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
2489 u8 dmactl;
2491 /* load PRD table addr. */
2492 mb(); /* make sure PRD table writes are visible to controller */
2493 iowrite32(ap->prd_dma, ap->ioaddr.bmdma_addr + ATA_DMA_TABLE_OFS);
2495 /* specify data direction, triple-check start bit is clear */
2496 dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
2497 dmactl &= ~(ATA_DMA_WR | ATA_DMA_START);
2498 if (!rw)
2499 dmactl |= ATA_DMA_WR;
2500 iowrite8(dmactl, ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
2502 /* issue r/w command */
2503 ap->ops->sff_exec_command(ap, &qc->tf);
2505 EXPORT_SYMBOL_GPL(ata_bmdma_setup);
2508 * ata_bmdma_start - Start a PCI IDE BMDMA transaction
2509 * @qc: Info associated with this ATA transaction.
2511 * LOCKING:
2512 * spin_lock_irqsave(host lock)
2514 void ata_bmdma_start(struct ata_queued_cmd *qc)
2516 struct ata_port *ap = qc->ap;
2517 u8 dmactl;
2519 /* start host DMA transaction */
2520 dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
2521 iowrite8(dmactl | ATA_DMA_START, ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
2523 /* Strictly, one may wish to issue an ioread8() here, to
2524 * flush the mmio write. However, control also passes
2525 * to the hardware at this point, and it will interrupt
2526 * us when we are to resume control. So, in effect,
2527 * we don't care when the mmio write flushes.
2528 * Further, a read of the DMA status register _immediately_
2529 * following the write may not be what certain flaky hardware
2530 * is expected, so I think it is best to not add a readb()
2531 * without first all the MMIO ATA cards/mobos.
2532 * Or maybe I'm just being paranoid.
2534 * FIXME: The posting of this write means I/O starts are
2535 * unneccessarily delayed for MMIO
2538 EXPORT_SYMBOL_GPL(ata_bmdma_start);
2541 * ata_bmdma_stop - Stop PCI IDE BMDMA transfer
2542 * @qc: Command we are ending DMA for
2544 * Clears the ATA_DMA_START flag in the dma control register
2546 * May be used as the bmdma_stop() entry in ata_port_operations.
2548 * LOCKING:
2549 * spin_lock_irqsave(host lock)
2551 void ata_bmdma_stop(struct ata_queued_cmd *qc)
2553 struct ata_port *ap = qc->ap;
2554 void __iomem *mmio = ap->ioaddr.bmdma_addr;
2556 /* clear start/stop bit */
2557 iowrite8(ioread8(mmio + ATA_DMA_CMD) & ~ATA_DMA_START,
2558 mmio + ATA_DMA_CMD);
2560 /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
2561 ata_sff_dma_pause(ap);
2563 EXPORT_SYMBOL_GPL(ata_bmdma_stop);
2566 * ata_bmdma_status - Read PCI IDE BMDMA status
2567 * @ap: Port associated with this ATA transaction.
2569 * Read and return BMDMA status register.
2571 * May be used as the bmdma_status() entry in ata_port_operations.
2573 * LOCKING:
2574 * spin_lock_irqsave(host lock)
2576 u8 ata_bmdma_status(struct ata_port *ap)
2578 return ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS);
2580 EXPORT_SYMBOL_GPL(ata_bmdma_status);
2583 * ata_bus_reset - reset host port and associated ATA channel
2584 * @ap: port to reset
2586 * This is typically the first time we actually start issuing
2587 * commands to the ATA channel. We wait for BSY to clear, then
2588 * issue EXECUTE DEVICE DIAGNOSTIC command, polling for its
2589 * result. Determine what devices, if any, are on the channel
2590 * by looking at the device 0/1 error register. Look at the signature
2591 * stored in each device's taskfile registers, to determine if
2592 * the device is ATA or ATAPI.
2594 * LOCKING:
2595 * PCI/etc. bus probe sem.
2596 * Obtains host lock.
2598 * SIDE EFFECTS:
2599 * Sets ATA_FLAG_DISABLED if bus reset fails.
2601 * DEPRECATED:
2602 * This function is only for drivers which still use old EH and
2603 * will be removed soon.
2605 void ata_bus_reset(struct ata_port *ap)
2607 struct ata_device *device = ap->link.device;
2608 struct ata_ioports *ioaddr = &ap->ioaddr;
2609 unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS;
2610 u8 err;
2611 unsigned int dev0, dev1 = 0, devmask = 0;
2612 int rc;
2614 DPRINTK("ENTER, host %u, port %u\n", ap->print_id, ap->port_no);
2616 /* determine if device 0/1 are present */
2617 if (ap->flags & ATA_FLAG_SATA_RESET)
2618 dev0 = 1;
2619 else {
2620 dev0 = ata_devchk(ap, 0);
2621 if (slave_possible)
2622 dev1 = ata_devchk(ap, 1);
2625 if (dev0)
2626 devmask |= (1 << 0);
2627 if (dev1)
2628 devmask |= (1 << 1);
2630 /* select device 0 again */
2631 ap->ops->sff_dev_select(ap, 0);
2633 /* issue bus reset */
2634 if (ap->flags & ATA_FLAG_SRST) {
2635 rc = ata_bus_softreset(ap, devmask,
2636 ata_deadline(jiffies, 40000));
2637 if (rc && rc != -ENODEV)
2638 goto err_out;
2642 * determine by signature whether we have ATA or ATAPI devices
2644 device[0].class = ata_sff_dev_classify(&device[0], dev0, &err);
2645 if ((slave_possible) && (err != 0x81))
2646 device[1].class = ata_sff_dev_classify(&device[1], dev1, &err);
2648 /* is double-select really necessary? */
2649 if (device[1].class != ATA_DEV_NONE)
2650 ap->ops->sff_dev_select(ap, 1);
2651 if (device[0].class != ATA_DEV_NONE)
2652 ap->ops->sff_dev_select(ap, 0);
2654 /* if no devices were detected, disable this port */
2655 if ((device[0].class == ATA_DEV_NONE) &&
2656 (device[1].class == ATA_DEV_NONE))
2657 goto err_out;
2659 if (ap->flags & (ATA_FLAG_SATA_RESET | ATA_FLAG_SRST)) {
2660 /* set up device control for ATA_FLAG_SATA_RESET */
2661 iowrite8(ap->ctl, ioaddr->ctl_addr);
2662 ap->last_ctl = ap->ctl;
2665 DPRINTK("EXIT\n");
2666 return;
2668 err_out:
2669 ata_port_printk(ap, KERN_ERR, "disabling port\n");
2670 ata_port_disable(ap);
2672 DPRINTK("EXIT\n");
2674 EXPORT_SYMBOL_GPL(ata_bus_reset);
2676 #ifdef CONFIG_PCI
2679 * ata_pci_bmdma_clear_simplex - attempt to kick device out of simplex
2680 * @pdev: PCI device
2682 * Some PCI ATA devices report simplex mode but in fact can be told to
2683 * enter non simplex mode. This implements the necessary logic to
2684 * perform the task on such devices. Calling it on other devices will
2685 * have -undefined- behaviour.
2687 int ata_pci_bmdma_clear_simplex(struct pci_dev *pdev)
2689 unsigned long bmdma = pci_resource_start(pdev, 4);
2690 u8 simplex;
2692 if (bmdma == 0)
2693 return -ENOENT;
2695 simplex = inb(bmdma + 0x02);
2696 outb(simplex & 0x60, bmdma + 0x02);
2697 simplex = inb(bmdma + 0x02);
2698 if (simplex & 0x80)
2699 return -EOPNOTSUPP;
2700 return 0;
2702 EXPORT_SYMBOL_GPL(ata_pci_bmdma_clear_simplex);
2705 * ata_pci_bmdma_init - acquire PCI BMDMA resources and init ATA host
2706 * @host: target ATA host
2708 * Acquire PCI BMDMA resources and initialize @host accordingly.
2710 * LOCKING:
2711 * Inherited from calling layer (may sleep).
2713 * RETURNS:
2714 * 0 on success, -errno otherwise.
2716 int ata_pci_bmdma_init(struct ata_host *host)
2718 struct device *gdev = host->dev;
2719 struct pci_dev *pdev = to_pci_dev(gdev);
2720 int i, rc;
2722 /* No BAR4 allocation: No DMA */
2723 if (pci_resource_start(pdev, 4) == 0)
2724 return 0;
2726 /* TODO: If we get no DMA mask we should fall back to PIO */
2727 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
2728 if (rc)
2729 return rc;
2730 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
2731 if (rc)
2732 return rc;
2734 /* request and iomap DMA region */
2735 rc = pcim_iomap_regions(pdev, 1 << 4, dev_driver_string(gdev));
2736 if (rc) {
2737 dev_printk(KERN_ERR, gdev, "failed to request/iomap BAR4\n");
2738 return -ENOMEM;
2740 host->iomap = pcim_iomap_table(pdev);
2742 for (i = 0; i < 2; i++) {
2743 struct ata_port *ap = host->ports[i];
2744 void __iomem *bmdma = host->iomap[4] + 8 * i;
2746 if (ata_port_is_dummy(ap))
2747 continue;
2749 ap->ioaddr.bmdma_addr = bmdma;
2750 if ((!(ap->flags & ATA_FLAG_IGN_SIMPLEX)) &&
2751 (ioread8(bmdma + 2) & 0x80))
2752 host->flags |= ATA_HOST_SIMPLEX;
2754 ata_port_desc(ap, "bmdma 0x%llx",
2755 (unsigned long long)pci_resource_start(pdev, 4) + 8 * i);
2758 return 0;
2760 EXPORT_SYMBOL_GPL(ata_pci_bmdma_init);
2762 static int ata_resources_present(struct pci_dev *pdev, int port)
2764 int i;
2766 /* Check the PCI resources for this channel are enabled */
2767 port = port * 2;
2768 for (i = 0; i < 2; i++) {
2769 if (pci_resource_start(pdev, port + i) == 0 ||
2770 pci_resource_len(pdev, port + i) == 0)
2771 return 0;
2773 return 1;
2777 * ata_pci_sff_init_host - acquire native PCI ATA resources and init host
2778 * @host: target ATA host
2780 * Acquire native PCI ATA resources for @host and initialize the
2781 * first two ports of @host accordingly. Ports marked dummy are
2782 * skipped and allocation failure makes the port dummy.
2784 * Note that native PCI resources are valid even for legacy hosts
2785 * as we fix up pdev resources array early in boot, so this
2786 * function can be used for both native and legacy SFF hosts.
2788 * LOCKING:
2789 * Inherited from calling layer (may sleep).
2791 * RETURNS:
2792 * 0 if at least one port is initialized, -ENODEV if no port is
2793 * available.
2795 int ata_pci_sff_init_host(struct ata_host *host)
2797 struct device *gdev = host->dev;
2798 struct pci_dev *pdev = to_pci_dev(gdev);
2799 unsigned int mask = 0;
2800 int i, rc;
2802 /* request, iomap BARs and init port addresses accordingly */
2803 for (i = 0; i < 2; i++) {
2804 struct ata_port *ap = host->ports[i];
2805 int base = i * 2;
2806 void __iomem * const *iomap;
2808 if (ata_port_is_dummy(ap))
2809 continue;
2811 /* Discard disabled ports. Some controllers show
2812 * their unused channels this way. Disabled ports are
2813 * made dummy.
2815 if (!ata_resources_present(pdev, i)) {
2816 ap->ops = &ata_dummy_port_ops;
2817 continue;
2820 rc = pcim_iomap_regions(pdev, 0x3 << base,
2821 dev_driver_string(gdev));
2822 if (rc) {
2823 dev_printk(KERN_WARNING, gdev,
2824 "failed to request/iomap BARs for port %d "
2825 "(errno=%d)\n", i, rc);
2826 if (rc == -EBUSY)
2827 pcim_pin_device(pdev);
2828 ap->ops = &ata_dummy_port_ops;
2829 continue;
2831 host->iomap = iomap = pcim_iomap_table(pdev);
2833 ap->ioaddr.cmd_addr = iomap[base];
2834 ap->ioaddr.altstatus_addr =
2835 ap->ioaddr.ctl_addr = (void __iomem *)
2836 ((unsigned long)iomap[base + 1] | ATA_PCI_CTL_OFS);
2837 ata_sff_std_ports(&ap->ioaddr);
2839 ata_port_desc(ap, "cmd 0x%llx ctl 0x%llx",
2840 (unsigned long long)pci_resource_start(pdev, base),
2841 (unsigned long long)pci_resource_start(pdev, base + 1));
2843 mask |= 1 << i;
2846 if (!mask) {
2847 dev_printk(KERN_ERR, gdev, "no available native port\n");
2848 return -ENODEV;
2851 return 0;
2853 EXPORT_SYMBOL_GPL(ata_pci_sff_init_host);
2856 * ata_pci_sff_prepare_host - helper to prepare native PCI ATA host
2857 * @pdev: target PCI device
2858 * @ppi: array of port_info, must be enough for two ports
2859 * @r_host: out argument for the initialized ATA host
2861 * Helper to allocate ATA host for @pdev, acquire all native PCI
2862 * resources and initialize it accordingly in one go.
2864 * LOCKING:
2865 * Inherited from calling layer (may sleep).
2867 * RETURNS:
2868 * 0 on success, -errno otherwise.
2870 int ata_pci_sff_prepare_host(struct pci_dev *pdev,
2871 const struct ata_port_info * const *ppi,
2872 struct ata_host **r_host)
2874 struct ata_host *host;
2875 int rc;
2877 if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL))
2878 return -ENOMEM;
2880 host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2);
2881 if (!host) {
2882 dev_printk(KERN_ERR, &pdev->dev,
2883 "failed to allocate ATA host\n");
2884 rc = -ENOMEM;
2885 goto err_out;
2888 rc = ata_pci_sff_init_host(host);
2889 if (rc)
2890 goto err_out;
2892 /* init DMA related stuff */
2893 rc = ata_pci_bmdma_init(host);
2894 if (rc)
2895 goto err_bmdma;
2897 devres_remove_group(&pdev->dev, NULL);
2898 *r_host = host;
2899 return 0;
2901 err_bmdma:
2902 /* This is necessary because PCI and iomap resources are
2903 * merged and releasing the top group won't release the
2904 * acquired resources if some of those have been acquired
2905 * before entering this function.
2907 pcim_iounmap_regions(pdev, 0xf);
2908 err_out:
2909 devres_release_group(&pdev->dev, NULL);
2910 return rc;
2912 EXPORT_SYMBOL_GPL(ata_pci_sff_prepare_host);
2915 * ata_pci_sff_activate_host - start SFF host, request IRQ and register it
2916 * @host: target SFF ATA host
2917 * @irq_handler: irq_handler used when requesting IRQ(s)
2918 * @sht: scsi_host_template to use when registering the host
2920 * This is the counterpart of ata_host_activate() for SFF ATA
2921 * hosts. This separate helper is necessary because SFF hosts
2922 * use two separate interrupts in legacy mode.
2924 * LOCKING:
2925 * Inherited from calling layer (may sleep).
2927 * RETURNS:
2928 * 0 on success, -errno otherwise.
2930 int ata_pci_sff_activate_host(struct ata_host *host,
2931 irq_handler_t irq_handler,
2932 struct scsi_host_template *sht)
2934 struct device *dev = host->dev;
2935 struct pci_dev *pdev = to_pci_dev(dev);
2936 const char *drv_name = dev_driver_string(host->dev);
2937 int legacy_mode = 0, rc;
2939 rc = ata_host_start(host);
2940 if (rc)
2941 return rc;
2943 if ((pdev->class >> 8) == PCI_CLASS_STORAGE_IDE) {
2944 u8 tmp8, mask;
2946 /* TODO: What if one channel is in native mode ... */
2947 pci_read_config_byte(pdev, PCI_CLASS_PROG, &tmp8);
2948 mask = (1 << 2) | (1 << 0);
2949 if ((tmp8 & mask) != mask)
2950 legacy_mode = 1;
2951 #if defined(CONFIG_NO_ATA_LEGACY)
2952 /* Some platforms with PCI limits cannot address compat
2953 port space. In that case we punt if their firmware has
2954 left a device in compatibility mode */
2955 if (legacy_mode) {
2956 printk(KERN_ERR "ata: Compatibility mode ATA is not supported on this platform, skipping.\n");
2957 return -EOPNOTSUPP;
2959 #endif
2962 if (!devres_open_group(dev, NULL, GFP_KERNEL))
2963 return -ENOMEM;
2965 if (!legacy_mode && pdev->irq) {
2966 rc = devm_request_irq(dev, pdev->irq, irq_handler,
2967 IRQF_SHARED, drv_name, host);
2968 if (rc)
2969 goto out;
2971 ata_port_desc(host->ports[0], "irq %d", pdev->irq);
2972 ata_port_desc(host->ports[1], "irq %d", pdev->irq);
2973 } else if (legacy_mode) {
2974 if (!ata_port_is_dummy(host->ports[0])) {
2975 rc = devm_request_irq(dev, ATA_PRIMARY_IRQ(pdev),
2976 irq_handler, IRQF_SHARED,
2977 drv_name, host);
2978 if (rc)
2979 goto out;
2981 ata_port_desc(host->ports[0], "irq %d",
2982 ATA_PRIMARY_IRQ(pdev));
2985 if (!ata_port_is_dummy(host->ports[1])) {
2986 rc = devm_request_irq(dev, ATA_SECONDARY_IRQ(pdev),
2987 irq_handler, IRQF_SHARED,
2988 drv_name, host);
2989 if (rc)
2990 goto out;
2992 ata_port_desc(host->ports[1], "irq %d",
2993 ATA_SECONDARY_IRQ(pdev));
2997 rc = ata_host_register(host, sht);
2998 out:
2999 if (rc == 0)
3000 devres_remove_group(dev, NULL);
3001 else
3002 devres_release_group(dev, NULL);
3004 return rc;
3006 EXPORT_SYMBOL_GPL(ata_pci_sff_activate_host);
3009 * ata_pci_sff_init_one - Initialize/register PCI IDE host controller
3010 * @pdev: Controller to be initialized
3011 * @ppi: array of port_info, must be enough for two ports
3012 * @sht: scsi_host_template to use when registering the host
3013 * @host_priv: host private_data
3015 * This is a helper function which can be called from a driver's
3016 * xxx_init_one() probe function if the hardware uses traditional
3017 * IDE taskfile registers.
3019 * This function calls pci_enable_device(), reserves its register
3020 * regions, sets the dma mask, enables bus master mode, and calls
3021 * ata_device_add()
3023 * ASSUMPTION:
3024 * Nobody makes a single channel controller that appears solely as
3025 * the secondary legacy port on PCI.
3027 * LOCKING:
3028 * Inherited from PCI layer (may sleep).
3030 * RETURNS:
3031 * Zero on success, negative on errno-based value on error.
3033 int ata_pci_sff_init_one(struct pci_dev *pdev,
3034 const struct ata_port_info * const *ppi,
3035 struct scsi_host_template *sht, void *host_priv)
3037 struct device *dev = &pdev->dev;
3038 const struct ata_port_info *pi = NULL;
3039 struct ata_host *host = NULL;
3040 int i, rc;
3042 DPRINTK("ENTER\n");
3044 /* look up the first valid port_info */
3045 for (i = 0; i < 2 && ppi[i]; i++) {
3046 if (ppi[i]->port_ops != &ata_dummy_port_ops) {
3047 pi = ppi[i];
3048 break;
3052 if (!pi) {
3053 dev_printk(KERN_ERR, &pdev->dev,
3054 "no valid port_info specified\n");
3055 return -EINVAL;
3058 if (!devres_open_group(dev, NULL, GFP_KERNEL))
3059 return -ENOMEM;
3061 rc = pcim_enable_device(pdev);
3062 if (rc)
3063 goto out;
3065 /* prepare and activate SFF host */
3066 rc = ata_pci_sff_prepare_host(pdev, ppi, &host);
3067 if (rc)
3068 goto out;
3069 host->private_data = host_priv;
3071 pci_set_master(pdev);
3072 rc = ata_pci_sff_activate_host(host, ata_sff_interrupt, sht);
3073 out:
3074 if (rc == 0)
3075 devres_remove_group(&pdev->dev, NULL);
3076 else
3077 devres_release_group(&pdev->dev, NULL);
3079 return rc;
3081 EXPORT_SYMBOL_GPL(ata_pci_sff_init_one);
3083 #endif /* CONFIG_PCI */