drivers/gpu/drm/radeon/radeon.h

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #ifndef __RADEON_H__
  29 #define __RADEON_H__
  30
  31 /* TODO: Here are things that needs to be done :
  32  *      - surface allocator & initializer : (bit like scratch reg) should
  33  *        initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
  34  *        related to surface
  35  *      - WB : write back stuff (do it bit like scratch reg things)
  36  *      - Vblank : look at Jesse's rework and what we should do
  37  *      - r600/r700: gart & cp
  38  *      - cs : clean cs ioctl use bitmap & things like that.
  39  *      - power management stuff
  40  *      - Barrier in gart code
  41  *      - Unmappabled vram ?
  42  *      - TESTING, TESTING, TESTING
  43  */
  44
  45 /* Initialization path:
  46  *  We expect that acceleration initialization might fail for various
  47  *  reasons even thought we work hard to make it works on most
  48  *  configurations. In order to still have a working userspace in such
  49  *  situation the init path must succeed up to the memory controller
  50  *  initialization point. Failure before this point are considered as
  51  *  fatal error. Here is the init callchain :
  52  *      radeon_device_init  perform common structure, mutex initialization
  53  *      asic_init           setup the GPU memory layout and perform all
  54  *                          one time initialization (failure in this
  55  *                          function are considered fatal)
  56  *      asic_startup        setup the GPU acceleration, in order to
  57  *                          follow guideline the first thing this
  58  *                          function should do is setting the GPU
  59  *                          memory controller (only MC setup failure
  60  *                          are considered as fatal)
  61  */
  62
  63 #include <linux/atomic.h>
  64 #include <linux/wait.h>
  65 #include <linux/list.h>
  66 #include <linux/kref.h>
  67
  68 #include <ttm/ttm_bo_api.h>
  69 #include <ttm/ttm_bo_driver.h>
  70 #include <ttm/ttm_placement.h>
  71 #include <ttm/ttm_module.h>
  72 #include <ttm/ttm_execbuf_util.h>
  73
  74 #include "radeon_family.h"
  75 #include "radeon_mode.h"
  76 #include "radeon_reg.h"
  77
  78 /*
  79  * Modules parameters.
  80  */
  81 extern int radeon_no_wb;
  82 extern int radeon_modeset;
  83 extern int radeon_dynclks;
  84 extern int radeon_r4xx_atom;
  85 extern int radeon_agpmode;
  86 extern int radeon_vram_limit;
  87 extern int radeon_gart_size;
  88 extern int radeon_benchmarking;
  89 extern int radeon_testing;
  90 extern int radeon_connector_table;
  91 extern int radeon_tv;
  92 extern int radeon_audio;
  93 extern int radeon_disp_priority;
  94 extern int radeon_hw_i2c;
  95 extern int radeon_pcie_gen2;
  96 extern int radeon_msi;
  97
  98 /*
  99  * Copy from radeon_drv.h so we don't have to include both and have conflicting
 100  * symbol;
 101  */
 102 #define RADEON_MAX_USEC_TIMEOUT         100000  /* 100 ms */
 103 #define RADEON_FENCE_JIFFIES_TIMEOUT    (HZ / 2)
 104 /* RADEON_IB_POOL_SIZE must be a power of 2 */
 105 #define RADEON_IB_POOL_SIZE             16
 106 #define RADEON_DEBUGFS_MAX_NUM_FILES    32
 107 #define RADEONFB_CONN_LIMIT             4
 108 #define RADEON_BIOS_NUM_SCRATCH         8
 109
 110 /*
 111  * Errata workarounds.
 112  */
 113 enum radeon_pll_errata {
 114         CHIP_ERRATA_R300_CG             = 0x00000001,
 115         CHIP_ERRATA_PLL_DUMMYREADS      = 0x00000002,
 116         CHIP_ERRATA_PLL_DELAY           = 0x00000004
 117 };
 118
 119
 120 struct radeon_device;
 121
 122
 123 /*
 124  * BIOS.
 125  */
 126 #define ATRM_BIOS_PAGE 4096
 127
 128 #if defined(CONFIG_VGA_SWITCHEROO)
 129 bool radeon_atrm_supported(struct pci_dev *pdev);
 130 int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len);
 131 #else
 132 static inline bool radeon_atrm_supported(struct pci_dev *pdev)
 133 {
 134         return false;
 135 }
 136
 137 static inline int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len){
 138         return -EINVAL;
 139 }
 140 #endif
 141 bool radeon_get_bios(struct radeon_device *rdev);
 142
 143
 144 /*
 145  * Dummy page
 146  */
 147 struct radeon_dummy_page {
 148         struct page     *page;
 149         dma_addr_t      addr;
 150 };
 151 int radeon_dummy_page_init(struct radeon_device *rdev);
 152 void radeon_dummy_page_fini(struct radeon_device *rdev);
 153
 154
 155 /*
 156  * Clocks
 157  */
 158 struct radeon_clock {
 159         struct radeon_pll p1pll;
 160         struct radeon_pll p2pll;
 161         struct radeon_pll dcpll;
 162         struct radeon_pll spll;
 163         struct radeon_pll mpll;
 164         /* 10 Khz units */
 165         uint32_t default_mclk;
 166         uint32_t default_sclk;
 167         uint32_t default_dispclk;
 168         uint32_t dp_extclk;
 169         uint32_t max_pixel_clock;
 170 };
 171
 172 /*
 173  * Power management
 174  */
 175 int radeon_pm_init(struct radeon_device *rdev);
 176 void radeon_pm_fini(struct radeon_device *rdev);
 177 void radeon_pm_compute_clocks(struct radeon_device *rdev);
 178 void radeon_pm_suspend(struct radeon_device *rdev);
 179 void radeon_pm_resume(struct radeon_device *rdev);
 180 void radeon_combios_get_power_modes(struct radeon_device *rdev);
 181 void radeon_atombios_get_power_modes(struct radeon_device *rdev);
 182 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type);
 183 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u16 *voltage);
 184 void rs690_pm_info(struct radeon_device *rdev);
 185 extern int rv6xx_get_temp(struct radeon_device *rdev);
 186 extern int rv770_get_temp(struct radeon_device *rdev);
 187 extern int evergreen_get_temp(struct radeon_device *rdev);
 188 extern int sumo_get_temp(struct radeon_device *rdev);
 189
 190 /*
 191  * Fences.
 192  */
 193 struct radeon_fence_driver {
 194         uint32_t                        scratch_reg;
 195         atomic_t                        seq;
 196         uint32_t                        last_seq;
 197         unsigned long                   last_jiffies;
 198         unsigned long                   last_timeout;
 199         wait_queue_head_t               queue;
 200         rwlock_t                        lock;
 201         struct list_head                created;
 202         struct list_head                emited;
 203         struct list_head                signaled;
 204         bool                            initialized;
 205 };
 206
 207 struct radeon_fence {
 208         struct radeon_device            *rdev;
 209         struct kref                     kref;
 210         struct list_head                list;
 211         /* protected by radeon_fence.lock */
 212         uint32_t                        seq;
 213         bool                            emited;
 214         bool                            signaled;
 215 };
 216
 217 int radeon_fence_driver_init(struct radeon_device *rdev);
 218 void radeon_fence_driver_fini(struct radeon_device *rdev);
 219 int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence);
 220 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence);
 221 void radeon_fence_process(struct radeon_device *rdev);
 222 bool radeon_fence_signaled(struct radeon_fence *fence);
 223 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
 224 int radeon_fence_wait_next(struct radeon_device *rdev);
 225 int radeon_fence_wait_last(struct radeon_device *rdev);
 226 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
 227 void radeon_fence_unref(struct radeon_fence **fence);
 228
 229 /*
 230  * Tiling registers
 231  */
 232 struct radeon_surface_reg {
 233         struct radeon_bo *bo;
 234 };
 235
 236 #define RADEON_GEM_MAX_SURFACES 8
 237
 238 /*
 239  * TTM.
 240  */
 241 struct radeon_mman {
 242         struct ttm_bo_global_ref        bo_global_ref;
 243         struct drm_global_reference     mem_global_ref;
 244         struct ttm_bo_device            bdev;
 245         bool                            mem_global_referenced;
 246         bool                            initialized;
 247 };
 248
 249 struct radeon_bo {
 250         /* Protected by gem.mutex */
 251         struct list_head                list;
 252         /* Protected by tbo.reserved */
 253         u32                             placements[3];
 254         struct ttm_placement            placement;
 255         struct ttm_buffer_object        tbo;
 256         struct ttm_bo_kmap_obj          kmap;
 257         unsigned                        pin_count;
 258         void                            *kptr;
 259         u32                             tiling_flags;
 260         u32                             pitch;
 261         int                             surface_reg;
 262         /* Constant after initialization */
 263         struct radeon_device            *rdev;
 264         struct drm_gem_object           gem_base;
 265 };
 266 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
 267
 268 struct radeon_bo_list {
 269         struct ttm_validate_buffer tv;
 270         struct radeon_bo        *bo;
 271         uint64_t                gpu_offset;
 272         unsigned                rdomain;
 273         unsigned                wdomain;
 274         u32                     tiling_flags;
 275 };
 276
 277 /*
 278  * GEM objects.
 279  */
 280 struct radeon_gem {
 281         struct mutex            mutex;
 282         struct list_head        objects;
 283 };
 284
 285 int radeon_gem_init(struct radeon_device *rdev);
 286 void radeon_gem_fini(struct radeon_device *rdev);
 287 int radeon_gem_object_create(struct radeon_device *rdev, int size,
 288                                 int alignment, int initial_domain,
 289                                 bool discardable, bool kernel,
 290                                 struct drm_gem_object **obj);
 291 int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain,
 292                           uint64_t *gpu_addr);
 293 void radeon_gem_object_unpin(struct drm_gem_object *obj);
 294
 295 int radeon_mode_dumb_create(struct drm_file *file_priv,
 296                             struct drm_device *dev,
 297                             struct drm_mode_create_dumb *args);
 298 int radeon_mode_dumb_mmap(struct drm_file *filp,
 299                           struct drm_device *dev,
 300                           uint32_t handle, uint64_t *offset_p);
 301 int radeon_mode_dumb_destroy(struct drm_file *file_priv,
 302                              struct drm_device *dev,
 303                              uint32_t handle);
 304
 305 /*
 306  * GART structures, functions & helpers
 307  */
 308 struct radeon_mc;
 309
 310 struct radeon_gart_table_ram {
 311         volatile uint32_t               *ptr;
 312 };
 313
 314 struct radeon_gart_table_vram {
 315         struct radeon_bo                *robj;
 316         volatile uint32_t               *ptr;
 317 };
 318
 319 union radeon_gart_table {
 320         struct radeon_gart_table_ram    ram;
 321         struct radeon_gart_table_vram   vram;
 322 };
 323
 324 #define RADEON_GPU_PAGE_SIZE 4096
 325 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
 326 #define RADEON_GPU_PAGE_SHIFT 12
 327
 328 struct radeon_gart {
 329         dma_addr_t                      table_addr;
 330         unsigned                        num_gpu_pages;
 331         unsigned                        num_cpu_pages;
 332         unsigned                        table_size;
 333         union radeon_gart_table         table;
 334         struct page                     **pages;
 335         dma_addr_t                      *pages_addr;
 336         bool                            *ttm_alloced;
 337         bool                            ready;
 338 };
 339
 340 int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
 341 void radeon_gart_table_ram_free(struct radeon_device *rdev);
 342 int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
 343 void radeon_gart_table_vram_free(struct radeon_device *rdev);
 344 int radeon_gart_init(struct radeon_device *rdev);
 345 void radeon_gart_fini(struct radeon_device *rdev);
 346 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
 347                         int pages);
 348 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
 349                      int pages, struct page **pagelist,
 350                      dma_addr_t *dma_addr);
 351
 352
 353 /*
 354  * GPU MC structures, functions & helpers
 355  */
 356 struct radeon_mc {
 357         resource_size_t         aper_size;
 358         resource_size_t         aper_base;
 359         resource_size_t         agp_base;
 360         /* for some chips with <= 32MB we need to lie
 361          * about vram size near mc fb location */
 362         u64                     mc_vram_size;
 363         u64                     visible_vram_size;
 364         u64                     gtt_size;
 365         u64                     gtt_start;
 366         u64                     gtt_end;
 367         u64                     vram_start;
 368         u64                     vram_end;
 369         unsigned                vram_width;
 370         u64                     real_vram_size;
 371         int                     vram_mtrr;
 372         bool                    vram_is_ddr;
 373         bool                    igp_sideport_enabled;
 374         u64                     gtt_base_align;
 375 };
 376
 377 bool radeon_combios_sideport_present(struct radeon_device *rdev);
 378 bool radeon_atombios_sideport_present(struct radeon_device *rdev);
 379
 380 /*
 381  * GPU scratch registers structures, functions & helpers
 382  */
 383 struct radeon_scratch {
 384         unsigned                num_reg;
 385         uint32_t                reg_base;
 386         bool                    free[32];
 387         uint32_t                reg[32];
 388 };
 389
 390 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
 391 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
 392
 393
 394 /*
 395  * IRQS.
 396  */
 397
 398 struct radeon_unpin_work {
 399         struct work_struct work;
 400         struct radeon_device *rdev;
 401         int crtc_id;
 402         struct radeon_fence *fence;
 403         struct drm_pending_vblank_event *event;
 404         struct radeon_bo *old_rbo;
 405         u64 new_crtc_base;
 406 };
 407
 408 struct r500_irq_stat_regs {
 409         u32 disp_int;
 410 };
 411
 412 struct r600_irq_stat_regs {
 413         u32 disp_int;
 414         u32 disp_int_cont;
 415         u32 disp_int_cont2;
 416         u32 d1grph_int;
 417         u32 d2grph_int;
 418 };
 419
 420 struct evergreen_irq_stat_regs {
 421         u32 disp_int;
 422         u32 disp_int_cont;
 423         u32 disp_int_cont2;
 424         u32 disp_int_cont3;
 425         u32 disp_int_cont4;
 426         u32 disp_int_cont5;
 427         u32 d1grph_int;
 428         u32 d2grph_int;
 429         u32 d3grph_int;
 430         u32 d4grph_int;
 431         u32 d5grph_int;
 432         u32 d6grph_int;
 433 };
 434
 435 union radeon_irq_stat_regs {
 436         struct r500_irq_stat_regs r500;
 437         struct r600_irq_stat_regs r600;
 438         struct evergreen_irq_stat_regs evergreen;
 439 };
 440
 441 struct radeon_irq {
 442         bool            installed;
 443         bool            sw_int;
 444         /* FIXME: use a define max crtc rather than hardcode it */
 445         bool            crtc_vblank_int[6];
 446         bool            pflip[6];
 447         wait_queue_head_t       vblank_queue;
 448         /* FIXME: use defines for max hpd/dacs */
 449         bool            hpd[6];
 450         bool            gui_idle;
 451         bool            gui_idle_acked;
 452         wait_queue_head_t       idle_queue;
 453         /* FIXME: use defines for max HDMI blocks */
 454         bool            hdmi[2];
 455         spinlock_t sw_lock;
 456         int sw_refcount;
 457         union radeon_irq_stat_regs stat_regs;
 458         spinlock_t pflip_lock[6];
 459         int pflip_refcount[6];
 460 };
 461
 462 int radeon_irq_kms_init(struct radeon_device *rdev);
 463 void radeon_irq_kms_fini(struct radeon_device *rdev);
 464 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev);
 465 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev);
 466 void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
 467 void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
 468
 469 /*
 470  * CP & ring.
 471  */
 472 struct radeon_ib {
 473         struct list_head        list;
 474         unsigned                idx;
 475         uint64_t                gpu_addr;
 476         struct radeon_fence     *fence;
 477         uint32_t                *ptr;
 478         uint32_t                length_dw;
 479         bool                    free;
 480 };
 481
 482 /*
 483  * locking -
 484  * mutex protects scheduled_ibs, ready, alloc_bm
 485  */
 486 struct radeon_ib_pool {
 487         struct mutex            mutex;
 488         struct radeon_bo        *robj;
 489         struct list_head        bogus_ib;
 490         struct radeon_ib        ibs[RADEON_IB_POOL_SIZE];
 491         bool                    ready;
 492         unsigned                head_id;
 493 };
 494
 495 struct radeon_cp {
 496         struct radeon_bo        *ring_obj;
 497         volatile uint32_t       *ring;
 498         unsigned                rptr;
 499         unsigned                wptr;
 500         unsigned                wptr_old;
 501         unsigned                ring_size;
 502         unsigned                ring_free_dw;
 503         int                     count_dw;
 504         uint64_t                gpu_addr;
 505         uint32_t                align_mask;
 506         uint32_t                ptr_mask;
 507         struct mutex            mutex;
 508         bool                    ready;
 509 };
 510
 511 /*
 512  * R6xx+ IH ring
 513  */
 514 struct r600_ih {
 515         struct radeon_bo        *ring_obj;
 516         volatile uint32_t       *ring;
 517         unsigned                rptr;
 518         unsigned                wptr;
 519         unsigned                wptr_old;
 520         unsigned                ring_size;
 521         uint64_t                gpu_addr;
 522         uint32_t                ptr_mask;
 523         spinlock_t              lock;
 524         bool                    enabled;
 525 };
 526
 527 struct r600_blit {
 528         struct mutex            mutex;
 529         struct radeon_bo        *shader_obj;
 530         u64 shader_gpu_addr;
 531         u32 vs_offset, ps_offset;
 532         u32 state_offset;
 533         u32 state_len;
 534         u32 vb_used, vb_total;
 535         struct radeon_ib *vb_ib;
 536 };
 537
 538 int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib);
 539 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib);
 540 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib);
 541 int radeon_ib_pool_init(struct radeon_device *rdev);
 542 void radeon_ib_pool_fini(struct radeon_device *rdev);
 543 int radeon_ib_test(struct radeon_device *rdev);
 544 extern void radeon_ib_bogus_add(struct radeon_device *rdev, struct radeon_ib *ib);
 545 /* Ring access between begin & end cannot sleep */
 546 void radeon_ring_free_size(struct radeon_device *rdev);
 547 int radeon_ring_alloc(struct radeon_device *rdev, unsigned ndw);
 548 int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw);
 549 void radeon_ring_commit(struct radeon_device *rdev);
 550 void radeon_ring_unlock_commit(struct radeon_device *rdev);
 551 void radeon_ring_unlock_undo(struct radeon_device *rdev);
 552 int radeon_ring_test(struct radeon_device *rdev);
 553 int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size);
 554 void radeon_ring_fini(struct radeon_device *rdev);
 555
 556
 557 /*
 558  * CS.
 559  */
 560 struct radeon_cs_reloc {
 561         struct drm_gem_object           *gobj;
 562         struct radeon_bo                *robj;
 563         struct radeon_bo_list           lobj;
 564         uint32_t                        handle;
 565         uint32_t                        flags;
 566 };
 567
 568 struct radeon_cs_chunk {
 569         uint32_t                chunk_id;
 570         uint32_t                length_dw;
 571         int kpage_idx[2];
 572         uint32_t                *kpage[2];
 573         uint32_t                *kdata;
 574         void __user *user_ptr;
 575         int last_copied_page;
 576         int last_page_index;
 577 };
 578
 579 struct radeon_cs_parser {
 580         struct device           *dev;
 581         struct radeon_device    *rdev;
 582         struct drm_file         *filp;
 583         /* chunks */
 584         unsigned                nchunks;
 585         struct radeon_cs_chunk  *chunks;
 586         uint64_t                *chunks_array;
 587         /* IB */
 588         unsigned                idx;
 589         /* relocations */
 590         unsigned                nrelocs;
 591         struct radeon_cs_reloc  *relocs;
 592         struct radeon_cs_reloc  **relocs_ptr;
 593         struct list_head        validated;
 594         /* indices of various chunks */
 595         int                     chunk_ib_idx;
 596         int                     chunk_relocs_idx;
 597         struct radeon_ib        *ib;
 598         void                    *track;
 599         unsigned                family;
 600         int parser_error;
 601 };
 602
 603 extern int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx);
 604 extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
 605
 606
 607 static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
 608 {
 609         struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
 610         u32 pg_idx, pg_offset;
 611         u32 idx_value = 0;
 612         int new_page;
 613
 614         pg_idx = (idx * 4) / PAGE_SIZE;
 615         pg_offset = (idx * 4) % PAGE_SIZE;
 616
 617         if (ibc->kpage_idx[0] == pg_idx)
 618                 return ibc->kpage[0][pg_offset/4];
 619         if (ibc->kpage_idx[1] == pg_idx)
 620                 return ibc->kpage[1][pg_offset/4];
 621
 622         new_page = radeon_cs_update_pages(p, pg_idx);
 623         if (new_page < 0) {
 624                 p->parser_error = new_page;
 625                 return 0;
 626         }
 627
 628         idx_value = ibc->kpage[new_page][pg_offset/4];
 629         return idx_value;
 630 }
 631
 632 struct radeon_cs_packet {
 633         unsigned        idx;
 634         unsigned        type;
 635         unsigned        reg;
 636         unsigned        opcode;
 637         int             count;
 638         unsigned        one_reg_wr;
 639 };
 640
 641 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
 642                                       struct radeon_cs_packet *pkt,
 643                                       unsigned idx, unsigned reg);
 644 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
 645                                       struct radeon_cs_packet *pkt);
 646
 647
 648 /*
 649  * AGP
 650  */
 651 int radeon_agp_init(struct radeon_device *rdev);
 652 void radeon_agp_resume(struct radeon_device *rdev);
 653 void radeon_agp_suspend(struct radeon_device *rdev);
 654 void radeon_agp_fini(struct radeon_device *rdev);
 655
 656
 657 /*
 658  * Writeback
 659  */
 660 struct radeon_wb {
 661         struct radeon_bo        *wb_obj;
 662         volatile uint32_t       *wb;
 663         uint64_t                gpu_addr;
 664         bool                    enabled;
 665         bool                    use_event;
 666 };
 667
 668 #define RADEON_WB_SCRATCH_OFFSET 0
 669 #define RADEON_WB_CP_RPTR_OFFSET 1024
 670 #define RADEON_WB_CP1_RPTR_OFFSET 1280
 671 #define RADEON_WB_CP2_RPTR_OFFSET 1536
 672 #define R600_WB_IH_WPTR_OFFSET   2048
 673 #define R600_WB_EVENT_OFFSET     3072
 674
 675 /**
 676  * struct radeon_pm - power management datas
 677  * @max_bandwidth:      maximum bandwidth the gpu has (MByte/s)
 678  * @igp_sideport_mclk:  sideport memory clock Mhz (rs690,rs740,rs780,rs880)
 679  * @igp_system_mclk:    system clock Mhz (rs690,rs740,rs780,rs880)
 680  * @igp_ht_link_clk:    ht link clock Mhz (rs690,rs740,rs780,rs880)
 681  * @igp_ht_link_width:  ht link width in bits (rs690,rs740,rs780,rs880)
 682  * @k8_bandwidth:       k8 bandwidth the gpu has (MByte/s) (IGP)
 683  * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
 684  * @ht_bandwidth:       ht bandwidth the gpu has (MByte/s) (IGP)
 685  * @core_bandwidth:     core GPU bandwidth the gpu has (MByte/s) (IGP)
 686  * @sclk:               GPU clock Mhz (core bandwidth depends of this clock)
 687  * @needed_bandwidth:   current bandwidth needs
 688  *
 689  * It keeps track of various data needed to take powermanagement decision.
 690  * Bandwidth need is used to determine minimun clock of the GPU and memory.
 691  * Equation between gpu/memory clock and available bandwidth is hw dependent
 692  * (type of memory, bus size, efficiency, ...)
 693  */
 694
 695 enum radeon_pm_method {
 696         PM_METHOD_PROFILE,
 697         PM_METHOD_DYNPM,
 698 };
 699
 700 enum radeon_dynpm_state {
 701         DYNPM_STATE_DISABLED,
 702         DYNPM_STATE_MINIMUM,
 703         DYNPM_STATE_PAUSED,
 704         DYNPM_STATE_ACTIVE,
 705         DYNPM_STATE_SUSPENDED,
 706 };
 707 enum radeon_dynpm_action {
 708         DYNPM_ACTION_NONE,
 709         DYNPM_ACTION_MINIMUM,
 710         DYNPM_ACTION_DOWNCLOCK,
 711         DYNPM_ACTION_UPCLOCK,
 712         DYNPM_ACTION_DEFAULT
 713 };
 714
 715 enum radeon_voltage_type {
 716         VOLTAGE_NONE = 0,
 717         VOLTAGE_GPIO,
 718         VOLTAGE_VDDC,
 719         VOLTAGE_SW
 720 };
 721
 722 enum radeon_pm_state_type {
 723         POWER_STATE_TYPE_DEFAULT,
 724         POWER_STATE_TYPE_POWERSAVE,
 725         POWER_STATE_TYPE_BATTERY,
 726         POWER_STATE_TYPE_BALANCED,
 727         POWER_STATE_TYPE_PERFORMANCE,
 728 };
 729
 730 enum radeon_pm_profile_type {
 731         PM_PROFILE_DEFAULT,
 732         PM_PROFILE_AUTO,
 733         PM_PROFILE_LOW,
 734         PM_PROFILE_MID,
 735         PM_PROFILE_HIGH,
 736 };
 737
 738 #define PM_PROFILE_DEFAULT_IDX 0
 739 #define PM_PROFILE_LOW_SH_IDX  1
 740 #define PM_PROFILE_MID_SH_IDX  2
 741 #define PM_PROFILE_HIGH_SH_IDX 3
 742 #define PM_PROFILE_LOW_MH_IDX  4
 743 #define PM_PROFILE_MID_MH_IDX  5
 744 #define PM_PROFILE_HIGH_MH_IDX 6
 745 #define PM_PROFILE_MAX         7
 746
 747 struct radeon_pm_profile {
 748         int dpms_off_ps_idx;
 749         int dpms_on_ps_idx;
 750         int dpms_off_cm_idx;
 751         int dpms_on_cm_idx;
 752 };
 753
 754 enum radeon_int_thermal_type {
 755         THERMAL_TYPE_NONE,
 756         THERMAL_TYPE_RV6XX,
 757         THERMAL_TYPE_RV770,
 758         THERMAL_TYPE_EVERGREEN,
 759         THERMAL_TYPE_SUMO,
 760         THERMAL_TYPE_NI,
 761 };
 762
 763 struct radeon_voltage {
 764         enum radeon_voltage_type type;
 765         /* gpio voltage */
 766         struct radeon_gpio_rec gpio;
 767         u32 delay; /* delay in usec from voltage drop to sclk change */
 768         bool active_high; /* voltage drop is active when bit is high */
 769         /* VDDC voltage */
 770         u8 vddc_id; /* index into vddc voltage table */
 771         u8 vddci_id; /* index into vddci voltage table */
 772         bool vddci_enabled;
 773         /* r6xx+ sw */
 774         u16 voltage;
 775         /* evergreen+ vddci */
 776         u16 vddci;
 777 };
 778
 779 /* clock mode flags */
 780 #define RADEON_PM_MODE_NO_DISPLAY          (1 << 0)
 781
 782 struct radeon_pm_clock_info {
 783         /* memory clock */
 784         u32 mclk;
 785         /* engine clock */
 786         u32 sclk;
 787         /* voltage info */
 788         struct radeon_voltage voltage;
 789         /* standardized clock flags */
 790         u32 flags;
 791 };
 792
 793 /* state flags */
 794 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
 795
 796 struct radeon_power_state {
 797         enum radeon_pm_state_type type;
 798         /* XXX: use a define for num clock modes */
 799         struct radeon_pm_clock_info clock_info[8];
 800         /* number of valid clock modes in this power state */
 801         int num_clock_modes;
 802         struct radeon_pm_clock_info *default_clock_mode;
 803         /* standardized state flags */
 804         u32 flags;
 805         u32 misc; /* vbios specific flags */
 806         u32 misc2; /* vbios specific flags */
 807         int pcie_lanes; /* pcie lanes */
 808 };
 809
 810 /*
 811  * Some modes are overclocked by very low value, accept them
 812  */
 813 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
 814
 815 struct radeon_pm {
 816         struct mutex            mutex;
 817         u32                     active_crtcs;
 818         int                     active_crtc_count;
 819         int                     req_vblank;
 820         bool                    vblank_sync;
 821         bool                    gui_idle;
 822         fixed20_12              max_bandwidth;
 823         fixed20_12              igp_sideport_mclk;
 824         fixed20_12              igp_system_mclk;
 825         fixed20_12              igp_ht_link_clk;
 826         fixed20_12              igp_ht_link_width;
 827         fixed20_12              k8_bandwidth;
 828         fixed20_12              sideport_bandwidth;
 829         fixed20_12              ht_bandwidth;
 830         fixed20_12              core_bandwidth;
 831         fixed20_12              sclk;
 832         fixed20_12              mclk;
 833         fixed20_12              needed_bandwidth;
 834         struct radeon_power_state *power_state;
 835         /* number of valid power states */
 836         int                     num_power_states;
 837         int                     current_power_state_index;
 838         int                     current_clock_mode_index;
 839         int                     requested_power_state_index;
 840         int                     requested_clock_mode_index;
 841         int                     default_power_state_index;
 842         u32                     current_sclk;
 843         u32                     current_mclk;
 844         u16                     current_vddc;
 845         u16                     current_vddci;
 846         u32                     default_sclk;
 847         u32                     default_mclk;
 848         u16                     default_vddc;
 849         u16                     default_vddci;
 850         struct radeon_i2c_chan *i2c_bus;
 851         /* selected pm method */
 852         enum radeon_pm_method     pm_method;
 853         /* dynpm power management */
 854         struct delayed_work     dynpm_idle_work;
 855         enum radeon_dynpm_state dynpm_state;
 856         enum radeon_dynpm_action        dynpm_planned_action;
 857         unsigned long           dynpm_action_timeout;
 858         bool                    dynpm_can_upclock;
 859         bool                    dynpm_can_downclock;
 860         /* profile-based power management */
 861         enum radeon_pm_profile_type profile;
 862         int                     profile_index;
 863         struct radeon_pm_profile profiles[PM_PROFILE_MAX];
 864         /* internal thermal controller on rv6xx+ */
 865         enum radeon_int_thermal_type int_thermal_type;
 866         struct device           *int_hwmon_dev;
 867 };
 868
 869
 870 /*
 871  * Benchmarking
 872  */
 873 void radeon_benchmark(struct radeon_device *rdev);
 874
 875
 876 /*
 877  * Testing
 878  */
 879 void radeon_test_moves(struct radeon_device *rdev);
 880
 881
 882 /*
 883  * Debugfs
 884  */
 885 int radeon_debugfs_add_files(struct radeon_device *rdev,
 886                              struct drm_info_list *files,
 887                              unsigned nfiles);
 888 int radeon_debugfs_fence_init(struct radeon_device *rdev);
 889
 890
 891 /*
 892  * ASIC specific functions.
 893  */
 894 struct radeon_asic {
 895         int (*init)(struct radeon_device *rdev);
 896         void (*fini)(struct radeon_device *rdev);
 897         int (*resume)(struct radeon_device *rdev);
 898         int (*suspend)(struct radeon_device *rdev);
 899         void (*vga_set_state)(struct radeon_device *rdev, bool state);
 900         bool (*gpu_is_lockup)(struct radeon_device *rdev);
 901         int (*asic_reset)(struct radeon_device *rdev);
 902         void (*gart_tlb_flush)(struct radeon_device *rdev);
 903         int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr);
 904         int (*cp_init)(struct radeon_device *rdev, unsigned ring_size);
 905         void (*cp_fini)(struct radeon_device *rdev);
 906         void (*cp_disable)(struct radeon_device *rdev);
 907         void (*cp_commit)(struct radeon_device *rdev);
 908         void (*ring_start)(struct radeon_device *rdev);
 909         int (*ring_test)(struct radeon_device *rdev);
 910         void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
 911         int (*irq_set)(struct radeon_device *rdev);
 912         int (*irq_process)(struct radeon_device *rdev);
 913         u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
 914         void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence);
 915         int (*cs_parse)(struct radeon_cs_parser *p);
 916         int (*copy_blit)(struct radeon_device *rdev,
 917                          uint64_t src_offset,
 918                          uint64_t dst_offset,
 919                          unsigned num_gpu_pages,
 920                          struct radeon_fence *fence);
 921         int (*copy_dma)(struct radeon_device *rdev,
 922                         uint64_t src_offset,
 923                         uint64_t dst_offset,
 924                         unsigned num_gpu_pages,
 925                         struct radeon_fence *fence);
 926         int (*copy)(struct radeon_device *rdev,
 927                     uint64_t src_offset,
 928                     uint64_t dst_offset,
 929                     unsigned num_gpu_pages,
 930                     struct radeon_fence *fence);
 931         uint32_t (*get_engine_clock)(struct radeon_device *rdev);
 932         void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
 933         uint32_t (*get_memory_clock)(struct radeon_device *rdev);
 934         void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
 935         int (*get_pcie_lanes)(struct radeon_device *rdev);
 936         void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
 937         void (*set_clock_gating)(struct radeon_device *rdev, int enable);
 938         int (*set_surface_reg)(struct radeon_device *rdev, int reg,
 939                                uint32_t tiling_flags, uint32_t pitch,
 940                                uint32_t offset, uint32_t obj_size);
 941         void (*clear_surface_reg)(struct radeon_device *rdev, int reg);
 942         void (*bandwidth_update)(struct radeon_device *rdev);
 943         void (*hpd_init)(struct radeon_device *rdev);
 944         void (*hpd_fini)(struct radeon_device *rdev);
 945         bool (*hpd_sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
 946         void (*hpd_set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
 947         /* ioctl hw specific callback. Some hw might want to perform special
 948          * operation on specific ioctl. For instance on wait idle some hw
 949          * might want to perform and HDP flush through MMIO as it seems that
 950          * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
 951          * through ring.
 952          */
 953         void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
 954         bool (*gui_idle)(struct radeon_device *rdev);
 955         /* power management */
 956         void (*pm_misc)(struct radeon_device *rdev);
 957         void (*pm_prepare)(struct radeon_device *rdev);
 958         void (*pm_finish)(struct radeon_device *rdev);
 959         void (*pm_init_profile)(struct radeon_device *rdev);
 960         void (*pm_get_dynpm_state)(struct radeon_device *rdev);
 961         /* pageflipping */
 962         void (*pre_page_flip)(struct radeon_device *rdev, int crtc);
 963         u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
 964         void (*post_page_flip)(struct radeon_device *rdev, int crtc);
 965 };
 966
 967 /*
 968  * Asic structures
 969  */
 970 struct r100_gpu_lockup {
 971         unsigned long   last_jiffies;
 972         u32             last_cp_rptr;
 973 };
 974
 975 struct r100_asic {
 976         const unsigned          *reg_safe_bm;
 977         unsigned                reg_safe_bm_size;
 978         u32                     hdp_cntl;
 979         struct r100_gpu_lockup  lockup;
 980 };
 981
 982 struct r300_asic {
 983         const unsigned          *reg_safe_bm;
 984         unsigned                reg_safe_bm_size;
 985         u32                     resync_scratch;
 986         u32                     hdp_cntl;
 987         struct r100_gpu_lockup  lockup;
 988 };
 989
 990 struct r600_asic {
 991         unsigned                max_pipes;
 992         unsigned                max_tile_pipes;
 993         unsigned                max_simds;
 994         unsigned                max_backends;
 995         unsigned                max_gprs;
 996         unsigned                max_threads;
 997         unsigned                max_stack_entries;
 998         unsigned                max_hw_contexts;
 999         unsigned                max_gs_threads;
1000         unsigned                sx_max_export_size;
1001         unsigned                sx_max_export_pos_size;
1002         unsigned                sx_max_export_smx_size;
1003         unsigned                sq_num_cf_insts;
1004         unsigned                tiling_nbanks;
1005         unsigned                tiling_npipes;
1006         unsigned                tiling_group_size;
1007         unsigned                tile_config;
1008         unsigned                backend_map;
1009         struct r100_gpu_lockup  lockup;
1010 };
1011
1012 struct rv770_asic {
1013         unsigned                max_pipes;
1014         unsigned                max_tile_pipes;
1015         unsigned                max_simds;
1016         unsigned                max_backends;
1017         unsigned                max_gprs;
1018         unsigned                max_threads;
1019         unsigned                max_stack_entries;
1020         unsigned                max_hw_contexts;
1021         unsigned                max_gs_threads;
1022         unsigned                sx_max_export_size;
1023         unsigned                sx_max_export_pos_size;
1024         unsigned                sx_max_export_smx_size;
1025         unsigned                sq_num_cf_insts;
1026         unsigned                sx_num_of_sets;
1027         unsigned                sc_prim_fifo_size;
1028         unsigned                sc_hiz_tile_fifo_size;
1029         unsigned                sc_earlyz_tile_fifo_fize;
1030         unsigned                tiling_nbanks;
1031         unsigned                tiling_npipes;
1032         unsigned                tiling_group_size;
1033         unsigned                tile_config;
1034         unsigned                backend_map;
1035         struct r100_gpu_lockup  lockup;
1036 };
1037
1038 struct evergreen_asic {
1039         unsigned num_ses;
1040         unsigned max_pipes;
1041         unsigned max_tile_pipes;
1042         unsigned max_simds;
1043         unsigned max_backends;
1044         unsigned max_gprs;
1045         unsigned max_threads;
1046         unsigned max_stack_entries;
1047         unsigned max_hw_contexts;
1048         unsigned max_gs_threads;
1049         unsigned sx_max_export_size;
1050         unsigned sx_max_export_pos_size;
1051         unsigned sx_max_export_smx_size;
1052         unsigned sq_num_cf_insts;
1053         unsigned sx_num_of_sets;
1054         unsigned sc_prim_fifo_size;
1055         unsigned sc_hiz_tile_fifo_size;
1056         unsigned sc_earlyz_tile_fifo_size;
1057         unsigned tiling_nbanks;
1058         unsigned tiling_npipes;
1059         unsigned tiling_group_size;
1060         unsigned tile_config;
1061         unsigned backend_map;
1062         struct r100_gpu_lockup  lockup;
1063 };
1064
1065 struct cayman_asic {
1066         unsigned max_shader_engines;
1067         unsigned max_pipes_per_simd;
1068         unsigned max_tile_pipes;
1069         unsigned max_simds_per_se;
1070         unsigned max_backends_per_se;
1071         unsigned max_texture_channel_caches;
1072         unsigned max_gprs;
1073         unsigned max_threads;
1074         unsigned max_gs_threads;
1075         unsigned max_stack_entries;
1076         unsigned sx_num_of_sets;
1077         unsigned sx_max_export_size;
1078         unsigned sx_max_export_pos_size;
1079         unsigned sx_max_export_smx_size;
1080         unsigned max_hw_contexts;
1081         unsigned sq_num_cf_insts;
1082         unsigned sc_prim_fifo_size;
1083         unsigned sc_hiz_tile_fifo_size;
1084         unsigned sc_earlyz_tile_fifo_size;
1085
1086         unsigned num_shader_engines;
1087         unsigned num_shader_pipes_per_simd;
1088         unsigned num_tile_pipes;
1089         unsigned num_simds_per_se;
1090         unsigned num_backends_per_se;
1091         unsigned backend_disable_mask_per_asic;
1092         unsigned backend_map;
1093         unsigned num_texture_channel_caches;
1094         unsigned mem_max_burst_length_bytes;
1095         unsigned mem_row_size_in_kb;
1096         unsigned shader_engine_tile_size;
1097         unsigned num_gpus;
1098         unsigned multi_gpu_tile_size;
1099
1100         unsigned tile_config;
1101         struct r100_gpu_lockup  lockup;
1102 };
1103
1104 union radeon_asic_config {
1105         struct r300_asic        r300;
1106         struct r100_asic        r100;
1107         struct r600_asic        r600;
1108         struct rv770_asic       rv770;
1109         struct evergreen_asic   evergreen;
1110         struct cayman_asic      cayman;
1111 };
1112
1113 /*
1114  * asic initizalization from radeon_asic.c
1115  */
1116 void radeon_agp_disable(struct radeon_device *rdev);
1117 int radeon_asic_init(struct radeon_device *rdev);
1118
1119
1120 /*
1121  * IOCTL.
1122  */
1123 int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
1124                           struct drm_file *filp);
1125 int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
1126                             struct drm_file *filp);
1127 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
1128                          struct drm_file *file_priv);
1129 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
1130                            struct drm_file *file_priv);
1131 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1132                             struct drm_file *file_priv);
1133 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
1134                            struct drm_file *file_priv);
1135 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1136                                 struct drm_file *filp);
1137 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
1138                           struct drm_file *filp);
1139 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
1140                           struct drm_file *filp);
1141 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1142                               struct drm_file *filp);
1143 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1144 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
1145                                 struct drm_file *filp);
1146 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
1147                                 struct drm_file *filp);
1148
1149 /* VRAM scratch page for HDP bug */
1150 struct r700_vram_scratch {
1151         struct radeon_bo                *robj;
1152         volatile uint32_t               *ptr;
1153 };
1154
1155 /*
1156  * Core structure, functions and helpers.
1157  */
1158 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
1159 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
1160
1161 struct radeon_device {
1162         struct device                   *dev;
1163         struct drm_device               *ddev;
1164         struct pci_dev                  *pdev;
1165         /* ASIC */
1166         union radeon_asic_config        config;
1167         enum radeon_family              family;
1168         unsigned long                   flags;
1169         int                             usec_timeout;
1170         enum radeon_pll_errata          pll_errata;
1171         int                             num_gb_pipes;
1172         int                             num_z_pipes;
1173         int                             disp_priority;
1174         /* BIOS */
1175         uint8_t                         *bios;
1176         bool                            is_atom_bios;
1177         uint16_t                        bios_header_start;
1178         struct radeon_bo                *stollen_vga_memory;
1179         /* Register mmio */
1180         resource_size_t                 rmmio_base;
1181         resource_size_t                 rmmio_size;
1182         void __iomem                    *rmmio;
1183         radeon_rreg_t                   mc_rreg;
1184         radeon_wreg_t                   mc_wreg;
1185         radeon_rreg_t                   pll_rreg;
1186         radeon_wreg_t                   pll_wreg;
1187         uint32_t                        pcie_reg_mask;
1188         radeon_rreg_t                   pciep_rreg;
1189         radeon_wreg_t                   pciep_wreg;
1190         /* io port */
1191         void __iomem                    *rio_mem;
1192         resource_size_t                 rio_mem_size;
1193         struct radeon_clock             clock;
1194         struct radeon_mc                mc;
1195         struct radeon_gart              gart;
1196         struct radeon_mode_info         mode_info;
1197         struct radeon_scratch           scratch;
1198         struct radeon_mman              mman;
1199         struct radeon_fence_driver      fence_drv;
1200         struct radeon_cp                cp;
1201         /* cayman compute rings */
1202         struct radeon_cp                cp1;
1203         struct radeon_cp                cp2;
1204         struct radeon_ib_pool           ib_pool;
1205         struct radeon_irq               irq;
1206         struct radeon_asic              *asic;
1207         struct radeon_gem               gem;
1208         struct radeon_pm                pm;
1209         uint32_t                        bios_scratch[RADEON_BIOS_NUM_SCRATCH];
1210         struct mutex                    cs_mutex;
1211         struct radeon_wb                wb;
1212         struct radeon_dummy_page        dummy_page;
1213         bool                            gpu_lockup;
1214         bool                            shutdown;
1215         bool                            suspend;
1216         bool                            need_dma32;
1217         bool                            accel_working;
1218         struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
1219         const struct firmware *me_fw;   /* all family ME firmware */
1220         const struct firmware *pfp_fw;  /* r6/700 PFP firmware */
1221         const struct firmware *rlc_fw;  /* r6/700 RLC firmware */
1222         const struct firmware *mc_fw;   /* NI MC firmware */
1223         struct r600_blit r600_blit;
1224         struct r700_vram_scratch vram_scratch;
1225         int msi_enabled; /* msi enabled */
1226         struct r600_ih ih; /* r6/700 interrupt ring */
1227         struct work_struct hotplug_work;
1228         int num_crtc; /* number of crtcs */
1229         struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
1230         struct mutex vram_mutex;
1231
1232         /* audio stuff */
1233         bool                    audio_enabled;
1234         struct timer_list       audio_timer;
1235         int                     audio_channels;
1236         int                     audio_rate;
1237         int                     audio_bits_per_sample;
1238         uint8_t                 audio_status_bits;
1239         uint8_t                 audio_category_code;
1240
1241         struct notifier_block acpi_nb;
1242         /* only one userspace can use Hyperz features or CMASK at a time */
1243         struct drm_file *hyperz_filp;
1244         struct drm_file *cmask_filp;
1245         /* i2c buses */
1246         struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
1247 };
1248
1249 int radeon_device_init(struct radeon_device *rdev,
1250                        struct drm_device *ddev,
1251                        struct pci_dev *pdev,
1252                        uint32_t flags);
1253 void radeon_device_fini(struct radeon_device *rdev);
1254 int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
1255
1256 static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
1257 {
1258         if (reg < rdev->rmmio_size)
1259                 return readl((rdev->rmmio) + reg);
1260         else {
1261                 writel(reg, (rdev->rmmio) + RADEON_MM_INDEX);
1262                 return readl((rdev->rmmio) + RADEON_MM_DATA);
1263         }
1264 }
1265
1266 static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1267 {
1268         if (reg < rdev->rmmio_size)
1269                 writel(v, (rdev->rmmio) + reg);
1270         else {
1271                 writel(reg, (rdev->rmmio) + RADEON_MM_INDEX);
1272                 writel(v, (rdev->rmmio) + RADEON_MM_DATA);
1273         }
1274 }
1275
1276 static inline u32 r100_io_rreg(struct radeon_device *rdev, u32 reg)
1277 {
1278         if (reg < rdev->rio_mem_size)
1279                 return ioread32(rdev->rio_mem + reg);
1280         else {
1281                 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
1282                 return ioread32(rdev->rio_mem + RADEON_MM_DATA);
1283         }
1284 }
1285
1286 static inline void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v)
1287 {
1288         if (reg < rdev->rio_mem_size)
1289                 iowrite32(v, rdev->rio_mem + reg);
1290         else {
1291                 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
1292                 iowrite32(v, rdev->rio_mem + RADEON_MM_DATA);
1293         }
1294 }
1295
1296 /*
1297  * Cast helper
1298  */
1299 #define to_radeon_fence(p) ((struct radeon_fence *)(p))
1300
1301 /*
1302  * Registers read & write functions.
1303  */
1304 #define RREG8(reg) readb((rdev->rmmio) + (reg))
1305 #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg))
1306 #define RREG16(reg) readw((rdev->rmmio) + (reg))
1307 #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg))
1308 #define RREG32(reg) r100_mm_rreg(rdev, (reg))
1309 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg)))
1310 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v))
1311 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1312 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1313 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
1314 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
1315 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
1316 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
1317 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
1318 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
1319 #define RREG32_PCIE_P(reg) rdev->pciep_rreg(rdev, (reg))
1320 #define WREG32_PCIE_P(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
1321 #define WREG32_P(reg, val, mask)                                \
1322         do {                                                    \
1323                 uint32_t tmp_ = RREG32(reg);                    \
1324                 tmp_ &= (mask);                                 \
1325                 tmp_ |= ((val) & ~(mask));                      \
1326                 WREG32(reg, tmp_);                              \
1327         } while (0)
1328 #define WREG32_PLL_P(reg, val, mask)                            \
1329         do {                                                    \
1330                 uint32_t tmp_ = RREG32_PLL(reg);                \
1331                 tmp_ &= (mask);                                 \
1332                 tmp_ |= ((val) & ~(mask));                      \
1333                 WREG32_PLL(reg, tmp_);                          \
1334         } while (0)
1335 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg)))
1336 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
1337 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
1338
1339 /*
1340  * Indirect registers accessor
1341  */
1342 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
1343 {
1344         uint32_t r;
1345
1346         WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1347         r = RREG32(RADEON_PCIE_DATA);
1348         return r;
1349 }
1350
1351 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1352 {
1353         WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1354         WREG32(RADEON_PCIE_DATA, (v));
1355 }
1356
1357 void r100_pll_errata_after_index(struct radeon_device *rdev);
1358
1359
1360 /*
1361  * ASICs helpers.
1362  */
1363 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
1364                             (rdev->pdev->device == 0x5969))
1365 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
1366                 (rdev->family == CHIP_RV200) || \
1367                 (rdev->family == CHIP_RS100) || \
1368                 (rdev->family == CHIP_RS200) || \
1369                 (rdev->family == CHIP_RV250) || \
1370                 (rdev->family == CHIP_RV280) || \
1371                 (rdev->family == CHIP_RS300))
1372 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300)  ||     \
1373                 (rdev->family == CHIP_RV350) ||                 \
1374                 (rdev->family == CHIP_R350)  ||                 \
1375                 (rdev->family == CHIP_RV380) ||                 \
1376                 (rdev->family == CHIP_R420)  ||                 \
1377                 (rdev->family == CHIP_R423)  ||                 \
1378                 (rdev->family == CHIP_RV410) ||                 \
1379                 (rdev->family == CHIP_RS400) ||                 \
1380                 (rdev->family == CHIP_RS480))
1381 #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
1382                 (rdev->ddev->pdev->device == 0x9443) || \
1383                 (rdev->ddev->pdev->device == 0x944B) || \
1384                 (rdev->ddev->pdev->device == 0x9506) || \
1385                 (rdev->ddev->pdev->device == 0x9509) || \
1386                 (rdev->ddev->pdev->device == 0x950F) || \
1387                 (rdev->ddev->pdev->device == 0x689C) || \
1388                 (rdev->ddev->pdev->device == 0x689D))
1389 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
1390 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600)  ||    \
1391                             (rdev->family == CHIP_RS690)  ||    \
1392                             (rdev->family == CHIP_RS740)  ||    \
1393                             (rdev->family >= CHIP_R600))
1394 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
1395 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
1396 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
1397 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
1398                              (rdev->flags & RADEON_IS_IGP))
1399 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
1400
1401 /*
1402  * BIOS helpers.
1403  */
1404 #define RBIOS8(i) (rdev->bios[i])
1405 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1406 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1407
1408 int radeon_combios_init(struct radeon_device *rdev);
1409 void radeon_combios_fini(struct radeon_device *rdev);
1410 int radeon_atombios_init(struct radeon_device *rdev);
1411 void radeon_atombios_fini(struct radeon_device *rdev);
1412
1413
1414 /*
1415  * RING helpers.
1416  */
1417 static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
1418 {
1419 #if DRM_DEBUG_CODE
1420         if (rdev->cp.count_dw <= 0) {
1421                 DRM_ERROR("radeon: writting more dword to ring than expected !\n");
1422         }
1423 #endif
1424         rdev->cp.ring[rdev->cp.wptr++] = v;
1425         rdev->cp.wptr &= rdev->cp.ptr_mask;
1426         rdev->cp.count_dw--;
1427         rdev->cp.ring_free_dw--;
1428 }
1429
1430
1431 /*
1432  * ASICs macro.
1433  */
1434 #define radeon_init(rdev) (rdev)->asic->init((rdev))
1435 #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
1436 #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
1437 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
1438 #define radeon_cs_parse(p) rdev->asic->cs_parse((p))
1439 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
1440 #define radeon_gpu_is_lockup(rdev) (rdev)->asic->gpu_is_lockup((rdev))
1441 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
1442 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev))
1443 #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p))
1444 #define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev))
1445 #define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev))
1446 #define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev))
1447 #define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib))
1448 #define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev))
1449 #define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev))
1450 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc))
1451 #define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence))
1452 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f))
1453 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f))
1454 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f))
1455 #define radeon_get_engine_clock(rdev) (rdev)->asic->get_engine_clock((rdev))
1456 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
1457 #define radeon_get_memory_clock(rdev) (rdev)->asic->get_memory_clock((rdev))
1458 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_memory_clock((rdev), (e))
1459 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->get_pcie_lanes((rdev))
1460 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l))
1461 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e))
1462 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s)))
1463 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r)))
1464 #define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev))
1465 #define radeon_hpd_init(rdev) (rdev)->asic->hpd_init((rdev))
1466 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd_fini((rdev))
1467 #define radeon_hpd_sense(rdev, hpd) (rdev)->asic->hpd_sense((rdev), (hpd))
1468 #define radeon_hpd_set_polarity(rdev, hpd) (rdev)->asic->hpd_set_polarity((rdev), (hpd))
1469 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
1470 #define radeon_pm_misc(rdev) (rdev)->asic->pm_misc((rdev))
1471 #define radeon_pm_prepare(rdev) (rdev)->asic->pm_prepare((rdev))
1472 #define radeon_pm_finish(rdev) (rdev)->asic->pm_finish((rdev))
1473 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm_init_profile((rdev))
1474 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm_get_dynpm_state((rdev))
1475 #define radeon_pre_page_flip(rdev, crtc) rdev->asic->pre_page_flip((rdev), (crtc))
1476 #define radeon_page_flip(rdev, crtc, base) rdev->asic->page_flip((rdev), (crtc), (base))
1477 #define radeon_post_page_flip(rdev, crtc) rdev->asic->post_page_flip((rdev), (crtc))
1478
1479 /* Common functions */
1480 /* AGP */
1481 extern int radeon_gpu_reset(struct radeon_device *rdev);
1482 extern void radeon_agp_disable(struct radeon_device *rdev);
1483 extern int radeon_gart_table_vram_pin(struct radeon_device *rdev);
1484 extern void radeon_gart_restore(struct radeon_device *rdev);
1485 extern int radeon_modeset_init(struct radeon_device *rdev);
1486 extern void radeon_modeset_fini(struct radeon_device *rdev);
1487 extern bool radeon_card_posted(struct radeon_device *rdev);
1488 extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
1489 extern void radeon_update_display_priority(struct radeon_device *rdev);
1490 extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
1491 extern void radeon_scratch_init(struct radeon_device *rdev);
1492 extern void radeon_wb_fini(struct radeon_device *rdev);
1493 extern int radeon_wb_init(struct radeon_device *rdev);
1494 extern void radeon_wb_disable(struct radeon_device *rdev);
1495 extern void radeon_surface_init(struct radeon_device *rdev);
1496 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
1497 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
1498 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
1499 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
1500 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
1501 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
1502 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
1503 extern int radeon_resume_kms(struct drm_device *dev);
1504 extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state);
1505 extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size);
1506
1507 /*
1508  * r600 functions used by radeon_encoder.c
1509  */
1510 extern void r600_hdmi_enable(struct drm_encoder *encoder);
1511 extern void r600_hdmi_disable(struct drm_encoder *encoder);
1512 extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
1513
1514 extern int ni_init_microcode(struct radeon_device *rdev);
1515 extern int ni_mc_load_microcode(struct radeon_device *rdev);
1516
1517 /* radeon_acpi.c */
1518 #if defined(CONFIG_ACPI)
1519 extern int radeon_acpi_init(struct radeon_device *rdev);
1520 #else
1521 static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
1522 #endif
1523
1524 #include "radeon_object.h"
1525
1526 #endif