2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/slab.h>
35 #include <linux/swap.h>
36 #include <linux/pci.h>
37 #include <linux/intel-gtt.h>
39 static uint32_t i915_gem_get_gtt_alignment(struct drm_gem_object
*obj
);
41 static int i915_gem_object_flush_gpu_write_domain(struct drm_gem_object
*obj
,
43 static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object
*obj
);
44 static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object
*obj
);
45 static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object
*obj
,
47 static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object
*obj
,
50 static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object
*obj
);
51 static int i915_gem_object_wait_rendering(struct drm_gem_object
*obj
,
53 static int i915_gem_object_bind_to_gtt(struct drm_gem_object
*obj
,
54 unsigned alignment
, bool mappable
);
55 static void i915_gem_clear_fence_reg(struct drm_gem_object
*obj
);
56 static int i915_gem_phys_pwrite(struct drm_device
*dev
, struct drm_gem_object
*obj
,
57 struct drm_i915_gem_pwrite
*args
,
58 struct drm_file
*file_priv
);
59 static void i915_gem_free_object_tail(struct drm_gem_object
*obj
);
62 i915_gem_object_get_pages(struct drm_gem_object
*obj
,
66 i915_gem_object_put_pages(struct drm_gem_object
*obj
);
68 static LIST_HEAD(shrink_list
);
69 static DEFINE_SPINLOCK(shrink_list_lock
);
71 /* some bookkeeping */
72 static void i915_gem_info_add_obj(struct drm_i915_private
*dev_priv
,
75 dev_priv
->mm
.object_count
++;
76 dev_priv
->mm
.object_memory
+= size
;
79 static void i915_gem_info_remove_obj(struct drm_i915_private
*dev_priv
,
82 dev_priv
->mm
.object_count
--;
83 dev_priv
->mm
.object_memory
-= size
;
86 static void i915_gem_info_add_gtt(struct drm_i915_private
*dev_priv
,
89 dev_priv
->mm
.gtt_count
++;
90 dev_priv
->mm
.gtt_memory
+= size
;
93 static void i915_gem_info_remove_gtt(struct drm_i915_private
*dev_priv
,
96 dev_priv
->mm
.gtt_count
--;
97 dev_priv
->mm
.gtt_memory
-= size
;
100 static void i915_gem_info_add_pin(struct drm_i915_private
*dev_priv
,
103 dev_priv
->mm
.pin_count
++;
104 dev_priv
->mm
.pin_memory
+= size
;
107 static void i915_gem_info_remove_pin(struct drm_i915_private
*dev_priv
,
110 dev_priv
->mm
.pin_count
--;
111 dev_priv
->mm
.pin_memory
-= size
;
115 i915_gem_check_is_wedged(struct drm_device
*dev
)
117 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
118 struct completion
*x
= &dev_priv
->error_completion
;
122 if (!atomic_read(&dev_priv
->mm
.wedged
))
125 ret
= wait_for_completion_interruptible(x
);
129 /* Success, we reset the GPU! */
130 if (!atomic_read(&dev_priv
->mm
.wedged
))
133 /* GPU is hung, bump the completion count to account for
134 * the token we just consumed so that we never hit zero and
135 * end up waiting upon a subsequent completion event that
138 spin_lock_irqsave(&x
->wait
.lock
, flags
);
140 spin_unlock_irqrestore(&x
->wait
.lock
, flags
);
144 static int i915_mutex_lock_interruptible(struct drm_device
*dev
)
146 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
149 ret
= i915_gem_check_is_wedged(dev
);
153 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
157 if (atomic_read(&dev_priv
->mm
.wedged
)) {
158 mutex_unlock(&dev
->struct_mutex
);
162 WARN_ON(i915_verify_lists(dev
));
167 i915_gem_object_is_inactive(struct drm_i915_gem_object
*obj_priv
)
169 return obj_priv
->gtt_space
&&
171 obj_priv
->pin_count
== 0;
174 int i915_gem_do_init(struct drm_device
*dev
,
176 unsigned long mappable_end
,
179 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
182 (start
& (PAGE_SIZE
- 1)) != 0 ||
183 (end
& (PAGE_SIZE
- 1)) != 0) {
187 drm_mm_init(&dev_priv
->mm
.gtt_space
, start
,
190 dev_priv
->mm
.gtt_total
= end
- start
;
191 dev_priv
->mm
.gtt_mappable_end
= mappable_end
;
197 i915_gem_init_ioctl(struct drm_device
*dev
, void *data
,
198 struct drm_file
*file_priv
)
200 struct drm_i915_gem_init
*args
= data
;
203 mutex_lock(&dev
->struct_mutex
);
204 ret
= i915_gem_do_init(dev
, args
->gtt_start
, args
->gtt_end
, args
->gtt_end
);
205 mutex_unlock(&dev
->struct_mutex
);
211 i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
212 struct drm_file
*file_priv
)
214 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
215 struct drm_i915_gem_get_aperture
*args
= data
;
217 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
220 mutex_lock(&dev
->struct_mutex
);
221 args
->aper_size
= dev_priv
->mm
.gtt_total
;
222 args
->aper_available_size
= args
->aper_size
- dev_priv
->mm
.pin_memory
;
223 mutex_unlock(&dev
->struct_mutex
);
230 * Creates a new mm object and returns a handle to it.
233 i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
234 struct drm_file
*file_priv
)
236 struct drm_i915_gem_create
*args
= data
;
237 struct drm_gem_object
*obj
;
241 args
->size
= roundup(args
->size
, PAGE_SIZE
);
243 /* Allocate the new object */
244 obj
= i915_gem_alloc_object(dev
, args
->size
);
248 ret
= drm_gem_handle_create(file_priv
, obj
, &handle
);
250 drm_gem_object_release(obj
);
251 i915_gem_info_remove_obj(dev
->dev_private
, obj
->size
);
256 /* drop reference from allocate - handle holds it now */
257 drm_gem_object_unreference(obj
);
258 trace_i915_gem_object_create(obj
);
260 args
->handle
= handle
;
265 i915_gem_object_cpu_accessible(struct drm_i915_gem_object
*obj
)
267 struct drm_device
*dev
= obj
->base
.dev
;
268 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
270 return obj
->gtt_space
== NULL
||
271 obj
->gtt_offset
+ obj
->base
.size
<= dev_priv
->mm
.gtt_mappable_end
;
275 fast_shmem_read(struct page
**pages
,
276 loff_t page_base
, int page_offset
,
283 vaddr
= kmap_atomic(pages
[page_base
>> PAGE_SHIFT
]);
284 ret
= __copy_to_user_inatomic(data
, vaddr
+ page_offset
, length
);
285 kunmap_atomic(vaddr
);
290 static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object
*obj
)
292 drm_i915_private_t
*dev_priv
= obj
->dev
->dev_private
;
293 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
295 return dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_9_10_17
&&
296 obj_priv
->tiling_mode
!= I915_TILING_NONE
;
300 slow_shmem_copy(struct page
*dst_page
,
302 struct page
*src_page
,
306 char *dst_vaddr
, *src_vaddr
;
308 dst_vaddr
= kmap(dst_page
);
309 src_vaddr
= kmap(src_page
);
311 memcpy(dst_vaddr
+ dst_offset
, src_vaddr
+ src_offset
, length
);
318 slow_shmem_bit17_copy(struct page
*gpu_page
,
320 struct page
*cpu_page
,
325 char *gpu_vaddr
, *cpu_vaddr
;
327 /* Use the unswizzled path if this page isn't affected. */
328 if ((page_to_phys(gpu_page
) & (1 << 17)) == 0) {
330 return slow_shmem_copy(cpu_page
, cpu_offset
,
331 gpu_page
, gpu_offset
, length
);
333 return slow_shmem_copy(gpu_page
, gpu_offset
,
334 cpu_page
, cpu_offset
, length
);
337 gpu_vaddr
= kmap(gpu_page
);
338 cpu_vaddr
= kmap(cpu_page
);
340 /* Copy the data, XORing A6 with A17 (1). The user already knows he's
341 * XORing with the other bits (A9 for Y, A9 and A10 for X)
344 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
345 int this_length
= min(cacheline_end
- gpu_offset
, length
);
346 int swizzled_gpu_offset
= gpu_offset
^ 64;
349 memcpy(cpu_vaddr
+ cpu_offset
,
350 gpu_vaddr
+ swizzled_gpu_offset
,
353 memcpy(gpu_vaddr
+ swizzled_gpu_offset
,
354 cpu_vaddr
+ cpu_offset
,
357 cpu_offset
+= this_length
;
358 gpu_offset
+= this_length
;
359 length
-= this_length
;
367 * This is the fast shmem pread path, which attempts to copy_from_user directly
368 * from the backing pages of the object to the user's address space. On a
369 * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
372 i915_gem_shmem_pread_fast(struct drm_device
*dev
, struct drm_gem_object
*obj
,
373 struct drm_i915_gem_pread
*args
,
374 struct drm_file
*file_priv
)
376 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
378 loff_t offset
, page_base
;
379 char __user
*user_data
;
380 int page_offset
, page_length
;
382 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
385 obj_priv
= to_intel_bo(obj
);
386 offset
= args
->offset
;
389 /* Operation in this page
391 * page_base = page offset within aperture
392 * page_offset = offset within page
393 * page_length = bytes to copy for this page
395 page_base
= (offset
& ~(PAGE_SIZE
-1));
396 page_offset
= offset
& (PAGE_SIZE
-1);
397 page_length
= remain
;
398 if ((page_offset
+ remain
) > PAGE_SIZE
)
399 page_length
= PAGE_SIZE
- page_offset
;
401 if (fast_shmem_read(obj_priv
->pages
,
402 page_base
, page_offset
,
403 user_data
, page_length
))
406 remain
-= page_length
;
407 user_data
+= page_length
;
408 offset
+= page_length
;
415 i915_gem_object_get_pages_or_evict(struct drm_gem_object
*obj
)
419 ret
= i915_gem_object_get_pages(obj
, __GFP_NORETRY
| __GFP_NOWARN
);
421 /* If we've insufficient memory to map in the pages, attempt
422 * to make some space by throwing out some old buffers.
424 if (ret
== -ENOMEM
) {
425 struct drm_device
*dev
= obj
->dev
;
427 ret
= i915_gem_evict_something(dev
, obj
->size
,
428 i915_gem_get_gtt_alignment(obj
),
433 ret
= i915_gem_object_get_pages(obj
, 0);
440 * This is the fallback shmem pread path, which allocates temporary storage
441 * in kernel space to copy_to_user into outside of the struct_mutex, so we
442 * can copy out of the object's backing pages while holding the struct mutex
443 * and not take page faults.
446 i915_gem_shmem_pread_slow(struct drm_device
*dev
, struct drm_gem_object
*obj
,
447 struct drm_i915_gem_pread
*args
,
448 struct drm_file
*file_priv
)
450 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
451 struct mm_struct
*mm
= current
->mm
;
452 struct page
**user_pages
;
454 loff_t offset
, pinned_pages
, i
;
455 loff_t first_data_page
, last_data_page
, num_pages
;
456 int shmem_page_index
, shmem_page_offset
;
457 int data_page_index
, data_page_offset
;
460 uint64_t data_ptr
= args
->data_ptr
;
461 int do_bit17_swizzling
;
465 /* Pin the user pages containing the data. We can't fault while
466 * holding the struct mutex, yet we want to hold it while
467 * dereferencing the user data.
469 first_data_page
= data_ptr
/ PAGE_SIZE
;
470 last_data_page
= (data_ptr
+ args
->size
- 1) / PAGE_SIZE
;
471 num_pages
= last_data_page
- first_data_page
+ 1;
473 user_pages
= drm_malloc_ab(num_pages
, sizeof(struct page
*));
474 if (user_pages
== NULL
)
477 mutex_unlock(&dev
->struct_mutex
);
478 down_read(&mm
->mmap_sem
);
479 pinned_pages
= get_user_pages(current
, mm
, (uintptr_t)args
->data_ptr
,
480 num_pages
, 1, 0, user_pages
, NULL
);
481 up_read(&mm
->mmap_sem
);
482 mutex_lock(&dev
->struct_mutex
);
483 if (pinned_pages
< num_pages
) {
488 ret
= i915_gem_object_set_cpu_read_domain_range(obj
,
494 do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
496 obj_priv
= to_intel_bo(obj
);
497 offset
= args
->offset
;
500 /* Operation in this page
502 * shmem_page_index = page number within shmem file
503 * shmem_page_offset = offset within page in shmem file
504 * data_page_index = page number in get_user_pages return
505 * data_page_offset = offset with data_page_index page.
506 * page_length = bytes to copy for this page
508 shmem_page_index
= offset
/ PAGE_SIZE
;
509 shmem_page_offset
= offset
& ~PAGE_MASK
;
510 data_page_index
= data_ptr
/ PAGE_SIZE
- first_data_page
;
511 data_page_offset
= data_ptr
& ~PAGE_MASK
;
513 page_length
= remain
;
514 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
515 page_length
= PAGE_SIZE
- shmem_page_offset
;
516 if ((data_page_offset
+ page_length
) > PAGE_SIZE
)
517 page_length
= PAGE_SIZE
- data_page_offset
;
519 if (do_bit17_swizzling
) {
520 slow_shmem_bit17_copy(obj_priv
->pages
[shmem_page_index
],
522 user_pages
[data_page_index
],
527 slow_shmem_copy(user_pages
[data_page_index
],
529 obj_priv
->pages
[shmem_page_index
],
534 remain
-= page_length
;
535 data_ptr
+= page_length
;
536 offset
+= page_length
;
540 for (i
= 0; i
< pinned_pages
; i
++) {
541 SetPageDirty(user_pages
[i
]);
542 page_cache_release(user_pages
[i
]);
544 drm_free_large(user_pages
);
550 * Reads data from the object referenced by handle.
552 * On error, the contents of *data are undefined.
555 i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
556 struct drm_file
*file_priv
)
558 struct drm_i915_gem_pread
*args
= data
;
559 struct drm_gem_object
*obj
;
560 struct drm_i915_gem_object
*obj_priv
;
563 ret
= i915_mutex_lock_interruptible(dev
);
567 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
572 obj_priv
= to_intel_bo(obj
);
574 /* Bounds check source. */
575 if (args
->offset
> obj
->size
|| args
->size
> obj
->size
- args
->offset
) {
583 if (!access_ok(VERIFY_WRITE
,
584 (char __user
*)(uintptr_t)args
->data_ptr
,
590 ret
= fault_in_pages_writeable((char __user
*)(uintptr_t)args
->data_ptr
,
597 ret
= i915_gem_object_get_pages_or_evict(obj
);
601 ret
= i915_gem_object_set_cpu_read_domain_range(obj
,
608 if (!i915_gem_object_needs_bit17_swizzle(obj
))
609 ret
= i915_gem_shmem_pread_fast(dev
, obj
, args
, file_priv
);
611 ret
= i915_gem_shmem_pread_slow(dev
, obj
, args
, file_priv
);
614 i915_gem_object_put_pages(obj
);
616 drm_gem_object_unreference(obj
);
618 mutex_unlock(&dev
->struct_mutex
);
622 /* This is the fast write path which cannot handle
623 * page faults in the source data
627 fast_user_write(struct io_mapping
*mapping
,
628 loff_t page_base
, int page_offset
,
629 char __user
*user_data
,
633 unsigned long unwritten
;
635 vaddr_atomic
= io_mapping_map_atomic_wc(mapping
, page_base
);
636 unwritten
= __copy_from_user_inatomic_nocache(vaddr_atomic
+ page_offset
,
638 io_mapping_unmap_atomic(vaddr_atomic
);
642 /* Here's the write path which can sleep for
647 slow_kernel_write(struct io_mapping
*mapping
,
648 loff_t gtt_base
, int gtt_offset
,
649 struct page
*user_page
, int user_offset
,
652 char __iomem
*dst_vaddr
;
655 dst_vaddr
= io_mapping_map_wc(mapping
, gtt_base
);
656 src_vaddr
= kmap(user_page
);
658 memcpy_toio(dst_vaddr
+ gtt_offset
,
659 src_vaddr
+ user_offset
,
663 io_mapping_unmap(dst_vaddr
);
667 fast_shmem_write(struct page
**pages
,
668 loff_t page_base
, int page_offset
,
675 vaddr
= kmap_atomic(pages
[page_base
>> PAGE_SHIFT
]);
676 ret
= __copy_from_user_inatomic(vaddr
+ page_offset
, data
, length
);
677 kunmap_atomic(vaddr
);
683 * This is the fast pwrite path, where we copy the data directly from the
684 * user into the GTT, uncached.
687 i915_gem_gtt_pwrite_fast(struct drm_device
*dev
, struct drm_gem_object
*obj
,
688 struct drm_i915_gem_pwrite
*args
,
689 struct drm_file
*file_priv
)
691 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
692 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
694 loff_t offset
, page_base
;
695 char __user
*user_data
;
696 int page_offset
, page_length
;
698 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
701 obj_priv
= to_intel_bo(obj
);
702 offset
= obj_priv
->gtt_offset
+ args
->offset
;
705 /* Operation in this page
707 * page_base = page offset within aperture
708 * page_offset = offset within page
709 * page_length = bytes to copy for this page
711 page_base
= (offset
& ~(PAGE_SIZE
-1));
712 page_offset
= offset
& (PAGE_SIZE
-1);
713 page_length
= remain
;
714 if ((page_offset
+ remain
) > PAGE_SIZE
)
715 page_length
= PAGE_SIZE
- page_offset
;
717 /* If we get a fault while copying data, then (presumably) our
718 * source page isn't available. Return the error and we'll
719 * retry in the slow path.
721 if (fast_user_write(dev_priv
->mm
.gtt_mapping
, page_base
,
722 page_offset
, user_data
, page_length
))
726 remain
-= page_length
;
727 user_data
+= page_length
;
728 offset
+= page_length
;
735 * This is the fallback GTT pwrite path, which uses get_user_pages to pin
736 * the memory and maps it using kmap_atomic for copying.
738 * This code resulted in x11perf -rgb10text consuming about 10% more CPU
739 * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
742 i915_gem_gtt_pwrite_slow(struct drm_device
*dev
, struct drm_gem_object
*obj
,
743 struct drm_i915_gem_pwrite
*args
,
744 struct drm_file
*file_priv
)
746 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
747 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
749 loff_t gtt_page_base
, offset
;
750 loff_t first_data_page
, last_data_page
, num_pages
;
751 loff_t pinned_pages
, i
;
752 struct page
**user_pages
;
753 struct mm_struct
*mm
= current
->mm
;
754 int gtt_page_offset
, data_page_offset
, data_page_index
, page_length
;
756 uint64_t data_ptr
= args
->data_ptr
;
760 /* Pin the user pages containing the data. We can't fault while
761 * holding the struct mutex, and all of the pwrite implementations
762 * want to hold it while dereferencing the user data.
764 first_data_page
= data_ptr
/ PAGE_SIZE
;
765 last_data_page
= (data_ptr
+ args
->size
- 1) / PAGE_SIZE
;
766 num_pages
= last_data_page
- first_data_page
+ 1;
768 user_pages
= drm_malloc_ab(num_pages
, sizeof(struct page
*));
769 if (user_pages
== NULL
)
772 mutex_unlock(&dev
->struct_mutex
);
773 down_read(&mm
->mmap_sem
);
774 pinned_pages
= get_user_pages(current
, mm
, (uintptr_t)args
->data_ptr
,
775 num_pages
, 0, 0, user_pages
, NULL
);
776 up_read(&mm
->mmap_sem
);
777 mutex_lock(&dev
->struct_mutex
);
778 if (pinned_pages
< num_pages
) {
780 goto out_unpin_pages
;
783 ret
= i915_gem_object_set_to_gtt_domain(obj
, 1);
785 goto out_unpin_pages
;
787 obj_priv
= to_intel_bo(obj
);
788 offset
= obj_priv
->gtt_offset
+ args
->offset
;
791 /* Operation in this page
793 * gtt_page_base = page offset within aperture
794 * gtt_page_offset = offset within page in aperture
795 * data_page_index = page number in get_user_pages return
796 * data_page_offset = offset with data_page_index page.
797 * page_length = bytes to copy for this page
799 gtt_page_base
= offset
& PAGE_MASK
;
800 gtt_page_offset
= offset
& ~PAGE_MASK
;
801 data_page_index
= data_ptr
/ PAGE_SIZE
- first_data_page
;
802 data_page_offset
= data_ptr
& ~PAGE_MASK
;
804 page_length
= remain
;
805 if ((gtt_page_offset
+ page_length
) > PAGE_SIZE
)
806 page_length
= PAGE_SIZE
- gtt_page_offset
;
807 if ((data_page_offset
+ page_length
) > PAGE_SIZE
)
808 page_length
= PAGE_SIZE
- data_page_offset
;
810 slow_kernel_write(dev_priv
->mm
.gtt_mapping
,
811 gtt_page_base
, gtt_page_offset
,
812 user_pages
[data_page_index
],
816 remain
-= page_length
;
817 offset
+= page_length
;
818 data_ptr
+= page_length
;
822 for (i
= 0; i
< pinned_pages
; i
++)
823 page_cache_release(user_pages
[i
]);
824 drm_free_large(user_pages
);
830 * This is the fast shmem pwrite path, which attempts to directly
831 * copy_from_user into the kmapped pages backing the object.
834 i915_gem_shmem_pwrite_fast(struct drm_device
*dev
, struct drm_gem_object
*obj
,
835 struct drm_i915_gem_pwrite
*args
,
836 struct drm_file
*file_priv
)
838 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
840 loff_t offset
, page_base
;
841 char __user
*user_data
;
842 int page_offset
, page_length
;
844 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
847 obj_priv
= to_intel_bo(obj
);
848 offset
= args
->offset
;
852 /* Operation in this page
854 * page_base = page offset within aperture
855 * page_offset = offset within page
856 * page_length = bytes to copy for this page
858 page_base
= (offset
& ~(PAGE_SIZE
-1));
859 page_offset
= offset
& (PAGE_SIZE
-1);
860 page_length
= remain
;
861 if ((page_offset
+ remain
) > PAGE_SIZE
)
862 page_length
= PAGE_SIZE
- page_offset
;
864 if (fast_shmem_write(obj_priv
->pages
,
865 page_base
, page_offset
,
866 user_data
, page_length
))
869 remain
-= page_length
;
870 user_data
+= page_length
;
871 offset
+= page_length
;
878 * This is the fallback shmem pwrite path, which uses get_user_pages to pin
879 * the memory and maps it using kmap_atomic for copying.
881 * This avoids taking mmap_sem for faulting on the user's address while the
882 * struct_mutex is held.
885 i915_gem_shmem_pwrite_slow(struct drm_device
*dev
, struct drm_gem_object
*obj
,
886 struct drm_i915_gem_pwrite
*args
,
887 struct drm_file
*file_priv
)
889 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
890 struct mm_struct
*mm
= current
->mm
;
891 struct page
**user_pages
;
893 loff_t offset
, pinned_pages
, i
;
894 loff_t first_data_page
, last_data_page
, num_pages
;
895 int shmem_page_index
, shmem_page_offset
;
896 int data_page_index
, data_page_offset
;
899 uint64_t data_ptr
= args
->data_ptr
;
900 int do_bit17_swizzling
;
904 /* Pin the user pages containing the data. We can't fault while
905 * holding the struct mutex, and all of the pwrite implementations
906 * want to hold it while dereferencing the user data.
908 first_data_page
= data_ptr
/ PAGE_SIZE
;
909 last_data_page
= (data_ptr
+ args
->size
- 1) / PAGE_SIZE
;
910 num_pages
= last_data_page
- first_data_page
+ 1;
912 user_pages
= drm_malloc_ab(num_pages
, sizeof(struct page
*));
913 if (user_pages
== NULL
)
916 mutex_unlock(&dev
->struct_mutex
);
917 down_read(&mm
->mmap_sem
);
918 pinned_pages
= get_user_pages(current
, mm
, (uintptr_t)args
->data_ptr
,
919 num_pages
, 0, 0, user_pages
, NULL
);
920 up_read(&mm
->mmap_sem
);
921 mutex_lock(&dev
->struct_mutex
);
922 if (pinned_pages
< num_pages
) {
927 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
931 do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
933 obj_priv
= to_intel_bo(obj
);
934 offset
= args
->offset
;
938 /* Operation in this page
940 * shmem_page_index = page number within shmem file
941 * shmem_page_offset = offset within page in shmem file
942 * data_page_index = page number in get_user_pages return
943 * data_page_offset = offset with data_page_index page.
944 * page_length = bytes to copy for this page
946 shmem_page_index
= offset
/ PAGE_SIZE
;
947 shmem_page_offset
= offset
& ~PAGE_MASK
;
948 data_page_index
= data_ptr
/ PAGE_SIZE
- first_data_page
;
949 data_page_offset
= data_ptr
& ~PAGE_MASK
;
951 page_length
= remain
;
952 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
953 page_length
= PAGE_SIZE
- shmem_page_offset
;
954 if ((data_page_offset
+ page_length
) > PAGE_SIZE
)
955 page_length
= PAGE_SIZE
- data_page_offset
;
957 if (do_bit17_swizzling
) {
958 slow_shmem_bit17_copy(obj_priv
->pages
[shmem_page_index
],
960 user_pages
[data_page_index
],
965 slow_shmem_copy(obj_priv
->pages
[shmem_page_index
],
967 user_pages
[data_page_index
],
972 remain
-= page_length
;
973 data_ptr
+= page_length
;
974 offset
+= page_length
;
978 for (i
= 0; i
< pinned_pages
; i
++)
979 page_cache_release(user_pages
[i
]);
980 drm_free_large(user_pages
);
986 * Writes data to the object referenced by handle.
988 * On error, the contents of the buffer that were to be modified are undefined.
991 i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
992 struct drm_file
*file
)
994 struct drm_i915_gem_pwrite
*args
= data
;
995 struct drm_gem_object
*obj
;
996 struct drm_i915_gem_object
*obj_priv
;
999 ret
= i915_mutex_lock_interruptible(dev
);
1003 obj
= drm_gem_object_lookup(dev
, file
, args
->handle
);
1008 obj_priv
= to_intel_bo(obj
);
1011 /* Bounds check destination. */
1012 if (args
->offset
> obj
->size
|| args
->size
> obj
->size
- args
->offset
) {
1017 if (args
->size
== 0)
1020 if (!access_ok(VERIFY_READ
,
1021 (char __user
*)(uintptr_t)args
->data_ptr
,
1027 ret
= fault_in_pages_readable((char __user
*)(uintptr_t)args
->data_ptr
,
1034 /* We can only do the GTT pwrite on untiled buffers, as otherwise
1035 * it would end up going through the fenced access, and we'll get
1036 * different detiling behavior between reading and writing.
1037 * pread/pwrite currently are reading and writing from the CPU
1038 * perspective, requiring manual detiling by the client.
1040 if (obj_priv
->phys_obj
)
1041 ret
= i915_gem_phys_pwrite(dev
, obj
, args
, file
);
1042 else if (obj_priv
->tiling_mode
== I915_TILING_NONE
&&
1043 obj_priv
->gtt_space
&&
1044 obj
->write_domain
!= I915_GEM_DOMAIN_CPU
) {
1045 ret
= i915_gem_object_pin(obj
, 0, true);
1049 ret
= i915_gem_object_set_to_gtt_domain(obj
, 1);
1053 ret
= i915_gem_gtt_pwrite_fast(dev
, obj
, args
, file
);
1055 ret
= i915_gem_gtt_pwrite_slow(dev
, obj
, args
, file
);
1058 i915_gem_object_unpin(obj
);
1060 ret
= i915_gem_object_get_pages_or_evict(obj
);
1064 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
1069 if (!i915_gem_object_needs_bit17_swizzle(obj
))
1070 ret
= i915_gem_shmem_pwrite_fast(dev
, obj
, args
, file
);
1072 ret
= i915_gem_shmem_pwrite_slow(dev
, obj
, args
, file
);
1075 i915_gem_object_put_pages(obj
);
1079 drm_gem_object_unreference(obj
);
1081 mutex_unlock(&dev
->struct_mutex
);
1086 * Called when user space prepares to use an object with the CPU, either
1087 * through the mmap ioctl's mapping or a GTT mapping.
1090 i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
1091 struct drm_file
*file_priv
)
1093 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1094 struct drm_i915_gem_set_domain
*args
= data
;
1095 struct drm_gem_object
*obj
;
1096 struct drm_i915_gem_object
*obj_priv
;
1097 uint32_t read_domains
= args
->read_domains
;
1098 uint32_t write_domain
= args
->write_domain
;
1101 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1104 /* Only handle setting domains to types used by the CPU. */
1105 if (write_domain
& I915_GEM_GPU_DOMAINS
)
1108 if (read_domains
& I915_GEM_GPU_DOMAINS
)
1111 /* Having something in the write domain implies it's in the read
1112 * domain, and only that read domain. Enforce that in the request.
1114 if (write_domain
!= 0 && read_domains
!= write_domain
)
1117 ret
= i915_mutex_lock_interruptible(dev
);
1121 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1126 obj_priv
= to_intel_bo(obj
);
1128 intel_mark_busy(dev
, obj
);
1130 if (read_domains
& I915_GEM_DOMAIN_GTT
) {
1131 ret
= i915_gem_object_set_to_gtt_domain(obj
, write_domain
!= 0);
1133 /* Update the LRU on the fence for the CPU access that's
1136 if (obj_priv
->fence_reg
!= I915_FENCE_REG_NONE
) {
1137 struct drm_i915_fence_reg
*reg
=
1138 &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
1139 list_move_tail(®
->lru_list
,
1140 &dev_priv
->mm
.fence_list
);
1143 /* Silently promote "you're not bound, there was nothing to do"
1144 * to success, since the client was just asking us to
1145 * make sure everything was done.
1150 ret
= i915_gem_object_set_to_cpu_domain(obj
, write_domain
!= 0);
1153 /* Maintain LRU order of "inactive" objects */
1154 if (ret
== 0 && i915_gem_object_is_inactive(obj_priv
))
1155 list_move_tail(&obj_priv
->mm_list
, &dev_priv
->mm
.inactive_list
);
1157 drm_gem_object_unreference(obj
);
1159 mutex_unlock(&dev
->struct_mutex
);
1164 * Called when user space has done writes to this buffer
1167 i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
1168 struct drm_file
*file_priv
)
1170 struct drm_i915_gem_sw_finish
*args
= data
;
1171 struct drm_gem_object
*obj
;
1174 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1177 ret
= i915_mutex_lock_interruptible(dev
);
1181 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1187 /* Pinned buffers may be scanout, so flush the cache */
1188 if (to_intel_bo(obj
)->pin_count
)
1189 i915_gem_object_flush_cpu_write_domain(obj
);
1191 drm_gem_object_unreference(obj
);
1193 mutex_unlock(&dev
->struct_mutex
);
1198 * Maps the contents of an object, returning the address it is mapped
1201 * While the mapping holds a reference on the contents of the object, it doesn't
1202 * imply a ref on the object itself.
1205 i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1206 struct drm_file
*file_priv
)
1208 struct drm_i915_gem_mmap
*args
= data
;
1209 struct drm_gem_object
*obj
;
1213 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1216 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1220 offset
= args
->offset
;
1222 down_write(¤t
->mm
->mmap_sem
);
1223 addr
= do_mmap(obj
->filp
, 0, args
->size
,
1224 PROT_READ
| PROT_WRITE
, MAP_SHARED
,
1226 up_write(¤t
->mm
->mmap_sem
);
1227 drm_gem_object_unreference_unlocked(obj
);
1228 if (IS_ERR((void *)addr
))
1231 args
->addr_ptr
= (uint64_t) addr
;
1237 * i915_gem_fault - fault a page into the GTT
1238 * vma: VMA in question
1241 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1242 * from userspace. The fault handler takes care of binding the object to
1243 * the GTT (if needed), allocating and programming a fence register (again,
1244 * only if needed based on whether the old reg is still valid or the object
1245 * is tiled) and inserting a new PTE into the faulting process.
1247 * Note that the faulting process may involve evicting existing objects
1248 * from the GTT and/or fence registers to make room. So performance may
1249 * suffer if the GTT working set is large or there are few fence registers
1252 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
)
1254 struct drm_gem_object
*obj
= vma
->vm_private_data
;
1255 struct drm_device
*dev
= obj
->dev
;
1256 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1257 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1258 pgoff_t page_offset
;
1261 bool write
= !!(vmf
->flags
& FAULT_FLAG_WRITE
);
1263 /* We don't use vmf->pgoff since that has the fake offset */
1264 page_offset
= ((unsigned long)vmf
->virtual_address
- vma
->vm_start
) >>
1267 /* Now bind it into the GTT if needed */
1268 mutex_lock(&dev
->struct_mutex
);
1269 if (!i915_gem_object_cpu_accessible(obj_priv
))
1270 i915_gem_object_unbind(obj
);
1272 if (!obj_priv
->gtt_space
) {
1273 ret
= i915_gem_object_bind_to_gtt(obj
, 0, true);
1277 ret
= i915_gem_object_set_to_gtt_domain(obj
, write
);
1282 /* Need a new fence register? */
1283 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
) {
1284 ret
= i915_gem_object_get_fence_reg(obj
, true);
1289 if (i915_gem_object_is_inactive(obj_priv
))
1290 list_move_tail(&obj_priv
->mm_list
, &dev_priv
->mm
.inactive_list
);
1292 pfn
= ((dev
->agp
->base
+ obj_priv
->gtt_offset
) >> PAGE_SHIFT
) +
1295 /* Finally, remap it using the new GTT offset */
1296 ret
= vm_insert_pfn(vma
, (unsigned long)vmf
->virtual_address
, pfn
);
1298 mutex_unlock(&dev
->struct_mutex
);
1303 return VM_FAULT_NOPAGE
;
1306 return VM_FAULT_OOM
;
1308 return VM_FAULT_SIGBUS
;
1313 * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1314 * @obj: obj in question
1316 * GEM memory mapping works by handing back to userspace a fake mmap offset
1317 * it can use in a subsequent mmap(2) call. The DRM core code then looks
1318 * up the object based on the offset and sets up the various memory mapping
1321 * This routine allocates and attaches a fake offset for @obj.
1324 i915_gem_create_mmap_offset(struct drm_gem_object
*obj
)
1326 struct drm_device
*dev
= obj
->dev
;
1327 struct drm_gem_mm
*mm
= dev
->mm_private
;
1328 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1329 struct drm_map_list
*list
;
1330 struct drm_local_map
*map
;
1333 /* Set the object up for mmap'ing */
1334 list
= &obj
->map_list
;
1335 list
->map
= kzalloc(sizeof(struct drm_map_list
), GFP_KERNEL
);
1340 map
->type
= _DRM_GEM
;
1341 map
->size
= obj
->size
;
1344 /* Get a DRM GEM mmap offset allocated... */
1345 list
->file_offset_node
= drm_mm_search_free(&mm
->offset_manager
,
1346 obj
->size
/ PAGE_SIZE
, 0, 0);
1347 if (!list
->file_offset_node
) {
1348 DRM_ERROR("failed to allocate offset for bo %d\n", obj
->name
);
1353 list
->file_offset_node
= drm_mm_get_block(list
->file_offset_node
,
1354 obj
->size
/ PAGE_SIZE
, 0);
1355 if (!list
->file_offset_node
) {
1360 list
->hash
.key
= list
->file_offset_node
->start
;
1361 ret
= drm_ht_insert_item(&mm
->offset_hash
, &list
->hash
);
1363 DRM_ERROR("failed to add to map hash\n");
1367 /* By now we should be all set, any drm_mmap request on the offset
1368 * below will get to our mmap & fault handler */
1369 obj_priv
->mmap_offset
= ((uint64_t) list
->hash
.key
) << PAGE_SHIFT
;
1374 drm_mm_put_block(list
->file_offset_node
);
1382 * i915_gem_release_mmap - remove physical page mappings
1383 * @obj: obj in question
1385 * Preserve the reservation of the mmapping with the DRM core code, but
1386 * relinquish ownership of the pages back to the system.
1388 * It is vital that we remove the page mapping if we have mapped a tiled
1389 * object through the GTT and then lose the fence register due to
1390 * resource pressure. Similarly if the object has been moved out of the
1391 * aperture, than pages mapped into userspace must be revoked. Removing the
1392 * mapping will then trigger a page fault on the next user access, allowing
1393 * fixup by i915_gem_fault().
1396 i915_gem_release_mmap(struct drm_gem_object
*obj
)
1398 struct drm_device
*dev
= obj
->dev
;
1399 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1401 if (dev
->dev_mapping
)
1402 unmap_mapping_range(dev
->dev_mapping
,
1403 obj_priv
->mmap_offset
, obj
->size
, 1);
1407 i915_gem_free_mmap_offset(struct drm_gem_object
*obj
)
1409 struct drm_device
*dev
= obj
->dev
;
1410 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1411 struct drm_gem_mm
*mm
= dev
->mm_private
;
1412 struct drm_map_list
*list
;
1414 list
= &obj
->map_list
;
1415 drm_ht_remove_item(&mm
->offset_hash
, &list
->hash
);
1417 if (list
->file_offset_node
) {
1418 drm_mm_put_block(list
->file_offset_node
);
1419 list
->file_offset_node
= NULL
;
1427 obj_priv
->mmap_offset
= 0;
1431 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1432 * @obj: object to check
1434 * Return the required GTT alignment for an object, taking into account
1435 * potential fence register mapping if needed.
1438 i915_gem_get_gtt_alignment(struct drm_gem_object
*obj
)
1440 struct drm_device
*dev
= obj
->dev
;
1441 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1445 * Minimum alignment is 4k (GTT page size), but might be greater
1446 * if a fence register is needed for the object.
1448 if (INTEL_INFO(dev
)->gen
>= 4 || obj_priv
->tiling_mode
== I915_TILING_NONE
)
1452 * Previous chips need to be aligned to the size of the smallest
1453 * fence register that can contain the object.
1455 if (INTEL_INFO(dev
)->gen
== 3)
1460 for (i
= start
; i
< obj
->size
; i
<<= 1)
1467 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1469 * @data: GTT mapping ioctl data
1470 * @file_priv: GEM object info
1472 * Simply returns the fake offset to userspace so it can mmap it.
1473 * The mmap call will end up in drm_gem_mmap(), which will set things
1474 * up so we can get faults in the handler above.
1476 * The fault handler will take care of binding the object into the GTT
1477 * (since it may have been evicted to make room for something), allocating
1478 * a fence register, and mapping the appropriate aperture address into
1482 i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
1483 struct drm_file
*file_priv
)
1485 struct drm_i915_gem_mmap_gtt
*args
= data
;
1486 struct drm_gem_object
*obj
;
1487 struct drm_i915_gem_object
*obj_priv
;
1490 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1493 ret
= i915_mutex_lock_interruptible(dev
);
1497 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1502 obj_priv
= to_intel_bo(obj
);
1504 if (obj_priv
->madv
!= I915_MADV_WILLNEED
) {
1505 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1510 if (!obj_priv
->mmap_offset
) {
1511 ret
= i915_gem_create_mmap_offset(obj
);
1516 args
->offset
= obj_priv
->mmap_offset
;
1519 * Pull it into the GTT so that we have a page list (makes the
1520 * initial fault faster and any subsequent flushing possible).
1522 if (!obj_priv
->agp_mem
) {
1523 ret
= i915_gem_object_bind_to_gtt(obj
, 0, true);
1529 drm_gem_object_unreference(obj
);
1531 mutex_unlock(&dev
->struct_mutex
);
1536 i915_gem_object_put_pages(struct drm_gem_object
*obj
)
1538 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1539 int page_count
= obj
->size
/ PAGE_SIZE
;
1542 BUG_ON(obj_priv
->pages_refcount
== 0);
1543 BUG_ON(obj_priv
->madv
== __I915_MADV_PURGED
);
1545 if (--obj_priv
->pages_refcount
!= 0)
1548 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
)
1549 i915_gem_object_save_bit_17_swizzle(obj
);
1551 if (obj_priv
->madv
== I915_MADV_DONTNEED
)
1552 obj_priv
->dirty
= 0;
1554 for (i
= 0; i
< page_count
; i
++) {
1555 if (obj_priv
->dirty
)
1556 set_page_dirty(obj_priv
->pages
[i
]);
1558 if (obj_priv
->madv
== I915_MADV_WILLNEED
)
1559 mark_page_accessed(obj_priv
->pages
[i
]);
1561 page_cache_release(obj_priv
->pages
[i
]);
1563 obj_priv
->dirty
= 0;
1565 drm_free_large(obj_priv
->pages
);
1566 obj_priv
->pages
= NULL
;
1570 i915_gem_next_request_seqno(struct drm_device
*dev
,
1571 struct intel_ring_buffer
*ring
)
1573 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1575 ring
->outstanding_lazy_request
= true;
1576 return dev_priv
->next_seqno
;
1580 i915_gem_object_move_to_active(struct drm_gem_object
*obj
,
1581 struct intel_ring_buffer
*ring
)
1583 struct drm_device
*dev
= obj
->dev
;
1584 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1585 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1586 uint32_t seqno
= i915_gem_next_request_seqno(dev
, ring
);
1588 BUG_ON(ring
== NULL
);
1589 obj_priv
->ring
= ring
;
1591 /* Add a reference if we're newly entering the active list. */
1592 if (!obj_priv
->active
) {
1593 drm_gem_object_reference(obj
);
1594 obj_priv
->active
= 1;
1597 /* Move from whatever list we were on to the tail of execution. */
1598 list_move_tail(&obj_priv
->mm_list
, &dev_priv
->mm
.active_list
);
1599 list_move_tail(&obj_priv
->ring_list
, &ring
->active_list
);
1600 obj_priv
->last_rendering_seqno
= seqno
;
1604 i915_gem_object_move_to_flushing(struct drm_gem_object
*obj
)
1606 struct drm_device
*dev
= obj
->dev
;
1607 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1608 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1610 BUG_ON(!obj_priv
->active
);
1611 list_move_tail(&obj_priv
->mm_list
, &dev_priv
->mm
.flushing_list
);
1612 list_del_init(&obj_priv
->ring_list
);
1613 obj_priv
->last_rendering_seqno
= 0;
1616 /* Immediately discard the backing storage */
1618 i915_gem_object_truncate(struct drm_gem_object
*obj
)
1620 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1621 struct inode
*inode
;
1623 /* Our goal here is to return as much of the memory as
1624 * is possible back to the system as we are called from OOM.
1625 * To do this we must instruct the shmfs to drop all of its
1626 * backing pages, *now*. Here we mirror the actions taken
1627 * when by shmem_delete_inode() to release the backing store.
1629 inode
= obj
->filp
->f_path
.dentry
->d_inode
;
1630 truncate_inode_pages(inode
->i_mapping
, 0);
1631 if (inode
->i_op
->truncate_range
)
1632 inode
->i_op
->truncate_range(inode
, 0, (loff_t
)-1);
1634 obj_priv
->madv
= __I915_MADV_PURGED
;
1638 i915_gem_object_is_purgeable(struct drm_i915_gem_object
*obj_priv
)
1640 return obj_priv
->madv
== I915_MADV_DONTNEED
;
1644 i915_gem_object_move_to_inactive(struct drm_gem_object
*obj
)
1646 struct drm_device
*dev
= obj
->dev
;
1647 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1648 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1650 if (obj_priv
->pin_count
!= 0)
1651 list_move_tail(&obj_priv
->mm_list
, &dev_priv
->mm
.pinned_list
);
1653 list_move_tail(&obj_priv
->mm_list
, &dev_priv
->mm
.inactive_list
);
1654 list_del_init(&obj_priv
->ring_list
);
1656 BUG_ON(!list_empty(&obj_priv
->gpu_write_list
));
1658 obj_priv
->last_rendering_seqno
= 0;
1659 obj_priv
->ring
= NULL
;
1660 if (obj_priv
->active
) {
1661 obj_priv
->active
= 0;
1662 drm_gem_object_unreference(obj
);
1664 WARN_ON(i915_verify_lists(dev
));
1668 i915_gem_process_flushing_list(struct drm_device
*dev
,
1669 uint32_t flush_domains
,
1670 struct intel_ring_buffer
*ring
)
1672 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1673 struct drm_i915_gem_object
*obj_priv
, *next
;
1675 list_for_each_entry_safe(obj_priv
, next
,
1676 &ring
->gpu_write_list
,
1678 struct drm_gem_object
*obj
= &obj_priv
->base
;
1680 if (obj
->write_domain
& flush_domains
) {
1681 uint32_t old_write_domain
= obj
->write_domain
;
1683 obj
->write_domain
= 0;
1684 list_del_init(&obj_priv
->gpu_write_list
);
1685 i915_gem_object_move_to_active(obj
, ring
);
1687 /* update the fence lru list */
1688 if (obj_priv
->fence_reg
!= I915_FENCE_REG_NONE
) {
1689 struct drm_i915_fence_reg
*reg
=
1690 &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
1691 list_move_tail(®
->lru_list
,
1692 &dev_priv
->mm
.fence_list
);
1695 trace_i915_gem_object_change_domain(obj
,
1703 i915_add_request(struct drm_device
*dev
,
1704 struct drm_file
*file
,
1705 struct drm_i915_gem_request
*request
,
1706 struct intel_ring_buffer
*ring
)
1708 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1709 struct drm_i915_file_private
*file_priv
= NULL
;
1714 BUG_ON(request
== NULL
);
1717 file_priv
= file
->driver_priv
;
1719 ret
= ring
->add_request(ring
, &seqno
);
1723 ring
->outstanding_lazy_request
= false;
1725 request
->seqno
= seqno
;
1726 request
->ring
= ring
;
1727 request
->emitted_jiffies
= jiffies
;
1728 was_empty
= list_empty(&ring
->request_list
);
1729 list_add_tail(&request
->list
, &ring
->request_list
);
1732 spin_lock(&file_priv
->mm
.lock
);
1733 request
->file_priv
= file_priv
;
1734 list_add_tail(&request
->client_list
,
1735 &file_priv
->mm
.request_list
);
1736 spin_unlock(&file_priv
->mm
.lock
);
1739 if (!dev_priv
->mm
.suspended
) {
1740 mod_timer(&dev_priv
->hangcheck_timer
,
1741 jiffies
+ msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD
));
1743 queue_delayed_work(dev_priv
->wq
,
1744 &dev_priv
->mm
.retire_work
, HZ
);
1750 * Command execution barrier
1752 * Ensures that all commands in the ring are finished
1753 * before signalling the CPU
1756 i915_retire_commands(struct drm_device
*dev
, struct intel_ring_buffer
*ring
)
1758 uint32_t flush_domains
= 0;
1760 /* The sampler always gets flushed on i965 (sigh) */
1761 if (INTEL_INFO(dev
)->gen
>= 4)
1762 flush_domains
|= I915_GEM_DOMAIN_SAMPLER
;
1764 ring
->flush(ring
, I915_GEM_DOMAIN_COMMAND
, flush_domains
);
1768 i915_gem_request_remove_from_client(struct drm_i915_gem_request
*request
)
1770 struct drm_i915_file_private
*file_priv
= request
->file_priv
;
1775 spin_lock(&file_priv
->mm
.lock
);
1776 list_del(&request
->client_list
);
1777 request
->file_priv
= NULL
;
1778 spin_unlock(&file_priv
->mm
.lock
);
1781 static void i915_gem_reset_ring_lists(struct drm_i915_private
*dev_priv
,
1782 struct intel_ring_buffer
*ring
)
1784 while (!list_empty(&ring
->request_list
)) {
1785 struct drm_i915_gem_request
*request
;
1787 request
= list_first_entry(&ring
->request_list
,
1788 struct drm_i915_gem_request
,
1791 list_del(&request
->list
);
1792 i915_gem_request_remove_from_client(request
);
1796 while (!list_empty(&ring
->active_list
)) {
1797 struct drm_i915_gem_object
*obj_priv
;
1799 obj_priv
= list_first_entry(&ring
->active_list
,
1800 struct drm_i915_gem_object
,
1803 obj_priv
->base
.write_domain
= 0;
1804 list_del_init(&obj_priv
->gpu_write_list
);
1805 i915_gem_object_move_to_inactive(&obj_priv
->base
);
1809 void i915_gem_reset(struct drm_device
*dev
)
1811 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1812 struct drm_i915_gem_object
*obj_priv
;
1815 i915_gem_reset_ring_lists(dev_priv
, &dev_priv
->render_ring
);
1816 i915_gem_reset_ring_lists(dev_priv
, &dev_priv
->bsd_ring
);
1817 i915_gem_reset_ring_lists(dev_priv
, &dev_priv
->blt_ring
);
1819 /* Remove anything from the flushing lists. The GPU cache is likely
1820 * to be lost on reset along with the data, so simply move the
1821 * lost bo to the inactive list.
1823 while (!list_empty(&dev_priv
->mm
.flushing_list
)) {
1824 obj_priv
= list_first_entry(&dev_priv
->mm
.flushing_list
,
1825 struct drm_i915_gem_object
,
1828 obj_priv
->base
.write_domain
= 0;
1829 list_del_init(&obj_priv
->gpu_write_list
);
1830 i915_gem_object_move_to_inactive(&obj_priv
->base
);
1833 /* Move everything out of the GPU domains to ensure we do any
1834 * necessary invalidation upon reuse.
1836 list_for_each_entry(obj_priv
,
1837 &dev_priv
->mm
.inactive_list
,
1840 obj_priv
->base
.read_domains
&= ~I915_GEM_GPU_DOMAINS
;
1843 /* The fence registers are invalidated so clear them out */
1844 for (i
= 0; i
< 16; i
++) {
1845 struct drm_i915_fence_reg
*reg
;
1847 reg
= &dev_priv
->fence_regs
[i
];
1851 i915_gem_clear_fence_reg(reg
->obj
);
1856 * This function clears the request list as sequence numbers are passed.
1859 i915_gem_retire_requests_ring(struct drm_device
*dev
,
1860 struct intel_ring_buffer
*ring
)
1862 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1865 if (!ring
->status_page
.page_addr
||
1866 list_empty(&ring
->request_list
))
1869 WARN_ON(i915_verify_lists(dev
));
1871 seqno
= ring
->get_seqno(ring
);
1872 while (!list_empty(&ring
->request_list
)) {
1873 struct drm_i915_gem_request
*request
;
1875 request
= list_first_entry(&ring
->request_list
,
1876 struct drm_i915_gem_request
,
1879 if (!i915_seqno_passed(seqno
, request
->seqno
))
1882 trace_i915_gem_request_retire(dev
, request
->seqno
);
1884 list_del(&request
->list
);
1885 i915_gem_request_remove_from_client(request
);
1889 /* Move any buffers on the active list that are no longer referenced
1890 * by the ringbuffer to the flushing/inactive lists as appropriate.
1892 while (!list_empty(&ring
->active_list
)) {
1893 struct drm_gem_object
*obj
;
1894 struct drm_i915_gem_object
*obj_priv
;
1896 obj_priv
= list_first_entry(&ring
->active_list
,
1897 struct drm_i915_gem_object
,
1900 if (!i915_seqno_passed(seqno
, obj_priv
->last_rendering_seqno
))
1903 obj
= &obj_priv
->base
;
1904 if (obj
->write_domain
!= 0)
1905 i915_gem_object_move_to_flushing(obj
);
1907 i915_gem_object_move_to_inactive(obj
);
1910 if (unlikely (dev_priv
->trace_irq_seqno
&&
1911 i915_seqno_passed(dev_priv
->trace_irq_seqno
, seqno
))) {
1912 ring
->user_irq_put(ring
);
1913 dev_priv
->trace_irq_seqno
= 0;
1916 WARN_ON(i915_verify_lists(dev
));
1920 i915_gem_retire_requests(struct drm_device
*dev
)
1922 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1924 if (!list_empty(&dev_priv
->mm
.deferred_free_list
)) {
1925 struct drm_i915_gem_object
*obj_priv
, *tmp
;
1927 /* We must be careful that during unbind() we do not
1928 * accidentally infinitely recurse into retire requests.
1930 * retire -> free -> unbind -> wait -> retire_ring
1932 list_for_each_entry_safe(obj_priv
, tmp
,
1933 &dev_priv
->mm
.deferred_free_list
,
1935 i915_gem_free_object_tail(&obj_priv
->base
);
1938 i915_gem_retire_requests_ring(dev
, &dev_priv
->render_ring
);
1939 i915_gem_retire_requests_ring(dev
, &dev_priv
->bsd_ring
);
1940 i915_gem_retire_requests_ring(dev
, &dev_priv
->blt_ring
);
1944 i915_gem_retire_work_handler(struct work_struct
*work
)
1946 drm_i915_private_t
*dev_priv
;
1947 struct drm_device
*dev
;
1949 dev_priv
= container_of(work
, drm_i915_private_t
,
1950 mm
.retire_work
.work
);
1951 dev
= dev_priv
->dev
;
1953 /* Come back later if the device is busy... */
1954 if (!mutex_trylock(&dev
->struct_mutex
)) {
1955 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, HZ
);
1959 i915_gem_retire_requests(dev
);
1961 if (!dev_priv
->mm
.suspended
&&
1962 (!list_empty(&dev_priv
->render_ring
.request_list
) ||
1963 !list_empty(&dev_priv
->bsd_ring
.request_list
) ||
1964 !list_empty(&dev_priv
->blt_ring
.request_list
)))
1965 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, HZ
);
1966 mutex_unlock(&dev
->struct_mutex
);
1970 i915_do_wait_request(struct drm_device
*dev
, uint32_t seqno
,
1971 bool interruptible
, struct intel_ring_buffer
*ring
)
1973 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1979 if (atomic_read(&dev_priv
->mm
.wedged
))
1982 if (ring
->outstanding_lazy_request
) {
1983 struct drm_i915_gem_request
*request
;
1985 request
= kzalloc(sizeof(*request
), GFP_KERNEL
);
1986 if (request
== NULL
)
1989 ret
= i915_add_request(dev
, NULL
, request
, ring
);
1995 seqno
= request
->seqno
;
1997 BUG_ON(seqno
== dev_priv
->next_seqno
);
1999 if (!i915_seqno_passed(ring
->get_seqno(ring
), seqno
)) {
2000 if (HAS_PCH_SPLIT(dev
))
2001 ier
= I915_READ(DEIER
) | I915_READ(GTIER
);
2003 ier
= I915_READ(IER
);
2005 DRM_ERROR("something (likely vbetool) disabled "
2006 "interrupts, re-enabling\n");
2007 i915_driver_irq_preinstall(dev
);
2008 i915_driver_irq_postinstall(dev
);
2011 trace_i915_gem_request_wait_begin(dev
, seqno
);
2013 ring
->waiting_seqno
= seqno
;
2014 ring
->user_irq_get(ring
);
2016 ret
= wait_event_interruptible(ring
->irq_queue
,
2017 i915_seqno_passed(ring
->get_seqno(ring
), seqno
)
2018 || atomic_read(&dev_priv
->mm
.wedged
));
2020 wait_event(ring
->irq_queue
,
2021 i915_seqno_passed(ring
->get_seqno(ring
), seqno
)
2022 || atomic_read(&dev_priv
->mm
.wedged
));
2024 ring
->user_irq_put(ring
);
2025 ring
->waiting_seqno
= 0;
2027 trace_i915_gem_request_wait_end(dev
, seqno
);
2029 if (atomic_read(&dev_priv
->mm
.wedged
))
2032 if (ret
&& ret
!= -ERESTARTSYS
)
2033 DRM_ERROR("%s returns %d (awaiting %d at %d, next %d)\n",
2034 __func__
, ret
, seqno
, ring
->get_seqno(ring
),
2035 dev_priv
->next_seqno
);
2037 /* Directly dispatch request retiring. While we have the work queue
2038 * to handle this, the waiter on a request often wants an associated
2039 * buffer to have made it to the inactive list, and we would need
2040 * a separate wait queue to handle that.
2043 i915_gem_retire_requests_ring(dev
, ring
);
2049 * Waits for a sequence number to be signaled, and cleans up the
2050 * request and object lists appropriately for that event.
2053 i915_wait_request(struct drm_device
*dev
, uint32_t seqno
,
2054 struct intel_ring_buffer
*ring
)
2056 return i915_do_wait_request(dev
, seqno
, 1, ring
);
2060 i915_gem_flush_ring(struct drm_device
*dev
,
2061 struct drm_file
*file_priv
,
2062 struct intel_ring_buffer
*ring
,
2063 uint32_t invalidate_domains
,
2064 uint32_t flush_domains
)
2066 ring
->flush(ring
, invalidate_domains
, flush_domains
);
2067 i915_gem_process_flushing_list(dev
, flush_domains
, ring
);
2071 i915_gem_flush(struct drm_device
*dev
,
2072 struct drm_file
*file_priv
,
2073 uint32_t invalidate_domains
,
2074 uint32_t flush_domains
,
2075 uint32_t flush_rings
)
2077 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2079 if (flush_domains
& I915_GEM_DOMAIN_CPU
)
2080 drm_agp_chipset_flush(dev
);
2082 if ((flush_domains
| invalidate_domains
) & I915_GEM_GPU_DOMAINS
) {
2083 if (flush_rings
& RING_RENDER
)
2084 i915_gem_flush_ring(dev
, file_priv
,
2085 &dev_priv
->render_ring
,
2086 invalidate_domains
, flush_domains
);
2087 if (flush_rings
& RING_BSD
)
2088 i915_gem_flush_ring(dev
, file_priv
,
2089 &dev_priv
->bsd_ring
,
2090 invalidate_domains
, flush_domains
);
2091 if (flush_rings
& RING_BLT
)
2092 i915_gem_flush_ring(dev
, file_priv
,
2093 &dev_priv
->blt_ring
,
2094 invalidate_domains
, flush_domains
);
2099 * Ensures that all rendering to the object has completed and the object is
2100 * safe to unbind from the GTT or access from the CPU.
2103 i915_gem_object_wait_rendering(struct drm_gem_object
*obj
,
2106 struct drm_device
*dev
= obj
->dev
;
2107 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2110 /* This function only exists to support waiting for existing rendering,
2111 * not for emitting required flushes.
2113 BUG_ON((obj
->write_domain
& I915_GEM_GPU_DOMAINS
) != 0);
2115 /* If there is rendering queued on the buffer being evicted, wait for
2118 if (obj_priv
->active
) {
2119 ret
= i915_do_wait_request(dev
,
2120 obj_priv
->last_rendering_seqno
,
2131 * Unbinds an object from the GTT aperture.
2134 i915_gem_object_unbind(struct drm_gem_object
*obj
)
2136 struct drm_device
*dev
= obj
->dev
;
2137 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2138 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2141 if (obj_priv
->gtt_space
== NULL
)
2144 if (obj_priv
->pin_count
!= 0) {
2145 DRM_ERROR("Attempting to unbind pinned buffer\n");
2149 /* blow away mappings if mapped through GTT */
2150 i915_gem_release_mmap(obj
);
2152 /* Move the object to the CPU domain to ensure that
2153 * any possible CPU writes while it's not in the GTT
2154 * are flushed when we go to remap it. This will
2155 * also ensure that all pending GPU writes are finished
2158 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
2159 if (ret
== -ERESTARTSYS
)
2161 /* Continue on if we fail due to EIO, the GPU is hung so we
2162 * should be safe and we need to cleanup or else we might
2163 * cause memory corruption through use-after-free.
2166 i915_gem_clflush_object(obj
);
2167 obj
->read_domains
= obj
->write_domain
= I915_GEM_DOMAIN_CPU
;
2170 /* release the fence reg _after_ flushing */
2171 if (obj_priv
->fence_reg
!= I915_FENCE_REG_NONE
)
2172 i915_gem_clear_fence_reg(obj
);
2174 drm_unbind_agp(obj_priv
->agp_mem
);
2175 drm_free_agp(obj_priv
->agp_mem
, obj
->size
/ PAGE_SIZE
);
2177 i915_gem_object_put_pages(obj
);
2178 BUG_ON(obj_priv
->pages_refcount
);
2180 i915_gem_info_remove_gtt(dev_priv
, obj
->size
);
2181 list_del_init(&obj_priv
->mm_list
);
2183 drm_mm_put_block(obj_priv
->gtt_space
);
2184 obj_priv
->gtt_space
= NULL
;
2185 obj_priv
->gtt_offset
= 0;
2187 if (i915_gem_object_is_purgeable(obj_priv
))
2188 i915_gem_object_truncate(obj
);
2190 trace_i915_gem_object_unbind(obj
);
2195 static int i915_ring_idle(struct drm_device
*dev
,
2196 struct intel_ring_buffer
*ring
)
2198 if (list_empty(&ring
->gpu_write_list
))
2201 i915_gem_flush_ring(dev
, NULL
, ring
,
2202 I915_GEM_GPU_DOMAINS
, I915_GEM_GPU_DOMAINS
);
2203 return i915_wait_request(dev
,
2204 i915_gem_next_request_seqno(dev
, ring
),
2209 i915_gpu_idle(struct drm_device
*dev
)
2211 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2215 lists_empty
= (list_empty(&dev_priv
->mm
.flushing_list
) &&
2216 list_empty(&dev_priv
->render_ring
.active_list
) &&
2217 list_empty(&dev_priv
->bsd_ring
.active_list
) &&
2218 list_empty(&dev_priv
->blt_ring
.active_list
));
2222 /* Flush everything onto the inactive list. */
2223 ret
= i915_ring_idle(dev
, &dev_priv
->render_ring
);
2227 ret
= i915_ring_idle(dev
, &dev_priv
->bsd_ring
);
2231 ret
= i915_ring_idle(dev
, &dev_priv
->blt_ring
);
2239 i915_gem_object_get_pages(struct drm_gem_object
*obj
,
2242 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2244 struct address_space
*mapping
;
2245 struct inode
*inode
;
2248 BUG_ON(obj_priv
->pages_refcount
2249 == DRM_I915_GEM_OBJECT_MAX_PAGES_REFCOUNT
);
2251 if (obj_priv
->pages_refcount
++ != 0)
2254 /* Get the list of pages out of our struct file. They'll be pinned
2255 * at this point until we release them.
2257 page_count
= obj
->size
/ PAGE_SIZE
;
2258 BUG_ON(obj_priv
->pages
!= NULL
);
2259 obj_priv
->pages
= drm_calloc_large(page_count
, sizeof(struct page
*));
2260 if (obj_priv
->pages
== NULL
) {
2261 obj_priv
->pages_refcount
--;
2265 inode
= obj
->filp
->f_path
.dentry
->d_inode
;
2266 mapping
= inode
->i_mapping
;
2267 for (i
= 0; i
< page_count
; i
++) {
2268 page
= read_cache_page_gfp(mapping
, i
,
2276 obj_priv
->pages
[i
] = page
;
2279 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
)
2280 i915_gem_object_do_bit_17_swizzle(obj
);
2286 page_cache_release(obj_priv
->pages
[i
]);
2288 drm_free_large(obj_priv
->pages
);
2289 obj_priv
->pages
= NULL
;
2290 obj_priv
->pages_refcount
--;
2291 return PTR_ERR(page
);
2294 static void sandybridge_write_fence_reg(struct drm_i915_fence_reg
*reg
)
2296 struct drm_gem_object
*obj
= reg
->obj
;
2297 struct drm_device
*dev
= obj
->dev
;
2298 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2299 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2300 int regnum
= obj_priv
->fence_reg
;
2303 val
= (uint64_t)((obj_priv
->gtt_offset
+ obj
->size
- 4096) &
2305 val
|= obj_priv
->gtt_offset
& 0xfffff000;
2306 val
|= (uint64_t)((obj_priv
->stride
/ 128) - 1) <<
2307 SANDYBRIDGE_FENCE_PITCH_SHIFT
;
2309 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
2310 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
2311 val
|= I965_FENCE_REG_VALID
;
2313 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0
+ (regnum
* 8), val
);
2316 static void i965_write_fence_reg(struct drm_i915_fence_reg
*reg
)
2318 struct drm_gem_object
*obj
= reg
->obj
;
2319 struct drm_device
*dev
= obj
->dev
;
2320 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2321 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2322 int regnum
= obj_priv
->fence_reg
;
2325 val
= (uint64_t)((obj_priv
->gtt_offset
+ obj
->size
- 4096) &
2327 val
|= obj_priv
->gtt_offset
& 0xfffff000;
2328 val
|= ((obj_priv
->stride
/ 128) - 1) << I965_FENCE_PITCH_SHIFT
;
2329 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
2330 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
2331 val
|= I965_FENCE_REG_VALID
;
2333 I915_WRITE64(FENCE_REG_965_0
+ (regnum
* 8), val
);
2336 static void i915_write_fence_reg(struct drm_i915_fence_reg
*reg
)
2338 struct drm_gem_object
*obj
= reg
->obj
;
2339 struct drm_device
*dev
= obj
->dev
;
2340 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2341 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2342 int regnum
= obj_priv
->fence_reg
;
2344 uint32_t fence_reg
, val
;
2347 if ((obj_priv
->gtt_offset
& ~I915_FENCE_START_MASK
) ||
2348 (obj_priv
->gtt_offset
& (obj
->size
- 1))) {
2349 WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n",
2350 __func__
, obj_priv
->gtt_offset
, obj
->size
);
2354 if (obj_priv
->tiling_mode
== I915_TILING_Y
&&
2355 HAS_128_BYTE_Y_TILING(dev
))
2360 /* Note: pitch better be a power of two tile widths */
2361 pitch_val
= obj_priv
->stride
/ tile_width
;
2362 pitch_val
= ffs(pitch_val
) - 1;
2364 if (obj_priv
->tiling_mode
== I915_TILING_Y
&&
2365 HAS_128_BYTE_Y_TILING(dev
))
2366 WARN_ON(pitch_val
> I830_FENCE_MAX_PITCH_VAL
);
2368 WARN_ON(pitch_val
> I915_FENCE_MAX_PITCH_VAL
);
2370 val
= obj_priv
->gtt_offset
;
2371 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
2372 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2373 val
|= I915_FENCE_SIZE_BITS(obj
->size
);
2374 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2375 val
|= I830_FENCE_REG_VALID
;
2378 fence_reg
= FENCE_REG_830_0
+ (regnum
* 4);
2380 fence_reg
= FENCE_REG_945_8
+ ((regnum
- 8) * 4);
2381 I915_WRITE(fence_reg
, val
);
2384 static void i830_write_fence_reg(struct drm_i915_fence_reg
*reg
)
2386 struct drm_gem_object
*obj
= reg
->obj
;
2387 struct drm_device
*dev
= obj
->dev
;
2388 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2389 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2390 int regnum
= obj_priv
->fence_reg
;
2393 uint32_t fence_size_bits
;
2395 if ((obj_priv
->gtt_offset
& ~I830_FENCE_START_MASK
) ||
2396 (obj_priv
->gtt_offset
& (obj
->size
- 1))) {
2397 WARN(1, "%s: object 0x%08x not 512K or size aligned\n",
2398 __func__
, obj_priv
->gtt_offset
);
2402 pitch_val
= obj_priv
->stride
/ 128;
2403 pitch_val
= ffs(pitch_val
) - 1;
2404 WARN_ON(pitch_val
> I830_FENCE_MAX_PITCH_VAL
);
2406 val
= obj_priv
->gtt_offset
;
2407 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
2408 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2409 fence_size_bits
= I830_FENCE_SIZE_BITS(obj
->size
);
2410 WARN_ON(fence_size_bits
& ~0x00000f00);
2411 val
|= fence_size_bits
;
2412 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2413 val
|= I830_FENCE_REG_VALID
;
2415 I915_WRITE(FENCE_REG_830_0
+ (regnum
* 4), val
);
2418 static int i915_find_fence_reg(struct drm_device
*dev
,
2421 struct drm_i915_fence_reg
*reg
= NULL
;
2422 struct drm_i915_gem_object
*obj_priv
= NULL
;
2423 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2424 struct drm_gem_object
*obj
= NULL
;
2427 /* First try to find a free reg */
2429 for (i
= dev_priv
->fence_reg_start
; i
< dev_priv
->num_fence_regs
; i
++) {
2430 reg
= &dev_priv
->fence_regs
[i
];
2434 obj_priv
= to_intel_bo(reg
->obj
);
2435 if (!obj_priv
->pin_count
)
2442 /* None available, try to steal one or wait for a user to finish */
2443 i
= I915_FENCE_REG_NONE
;
2444 list_for_each_entry(reg
, &dev_priv
->mm
.fence_list
,
2447 obj_priv
= to_intel_bo(obj
);
2449 if (obj_priv
->pin_count
)
2453 i
= obj_priv
->fence_reg
;
2457 BUG_ON(i
== I915_FENCE_REG_NONE
);
2459 /* We only have a reference on obj from the active list. put_fence_reg
2460 * might drop that one, causing a use-after-free in it. So hold a
2461 * private reference to obj like the other callers of put_fence_reg
2462 * (set_tiling ioctl) do. */
2463 drm_gem_object_reference(obj
);
2464 ret
= i915_gem_object_put_fence_reg(obj
, interruptible
);
2465 drm_gem_object_unreference(obj
);
2473 * i915_gem_object_get_fence_reg - set up a fence reg for an object
2474 * @obj: object to map through a fence reg
2476 * When mapping objects through the GTT, userspace wants to be able to write
2477 * to them without having to worry about swizzling if the object is tiled.
2479 * This function walks the fence regs looking for a free one for @obj,
2480 * stealing one if it can't find any.
2482 * It then sets up the reg based on the object's properties: address, pitch
2483 * and tiling format.
2486 i915_gem_object_get_fence_reg(struct drm_gem_object
*obj
,
2489 struct drm_device
*dev
= obj
->dev
;
2490 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2491 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2492 struct drm_i915_fence_reg
*reg
= NULL
;
2495 /* Just update our place in the LRU if our fence is getting used. */
2496 if (obj_priv
->fence_reg
!= I915_FENCE_REG_NONE
) {
2497 reg
= &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
2498 list_move_tail(®
->lru_list
, &dev_priv
->mm
.fence_list
);
2502 switch (obj_priv
->tiling_mode
) {
2503 case I915_TILING_NONE
:
2504 WARN(1, "allocating a fence for non-tiled object?\n");
2507 if (!obj_priv
->stride
)
2509 WARN((obj_priv
->stride
& (512 - 1)),
2510 "object 0x%08x is X tiled but has non-512B pitch\n",
2511 obj_priv
->gtt_offset
);
2514 if (!obj_priv
->stride
)
2516 WARN((obj_priv
->stride
& (128 - 1)),
2517 "object 0x%08x is Y tiled but has non-128B pitch\n",
2518 obj_priv
->gtt_offset
);
2522 ret
= i915_find_fence_reg(dev
, interruptible
);
2526 obj_priv
->fence_reg
= ret
;
2527 reg
= &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
2528 list_add_tail(®
->lru_list
, &dev_priv
->mm
.fence_list
);
2532 switch (INTEL_INFO(dev
)->gen
) {
2534 sandybridge_write_fence_reg(reg
);
2538 i965_write_fence_reg(reg
);
2541 i915_write_fence_reg(reg
);
2544 i830_write_fence_reg(reg
);
2548 trace_i915_gem_object_get_fence(obj
, obj_priv
->fence_reg
,
2549 obj_priv
->tiling_mode
);
2555 * i915_gem_clear_fence_reg - clear out fence register info
2556 * @obj: object to clear
2558 * Zeroes out the fence register itself and clears out the associated
2559 * data structures in dev_priv and obj_priv.
2562 i915_gem_clear_fence_reg(struct drm_gem_object
*obj
)
2564 struct drm_device
*dev
= obj
->dev
;
2565 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2566 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2567 struct drm_i915_fence_reg
*reg
=
2568 &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
2571 switch (INTEL_INFO(dev
)->gen
) {
2573 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0
+
2574 (obj_priv
->fence_reg
* 8), 0);
2578 I915_WRITE64(FENCE_REG_965_0
+ (obj_priv
->fence_reg
* 8), 0);
2581 if (obj_priv
->fence_reg
>= 8)
2582 fence_reg
= FENCE_REG_945_8
+ (obj_priv
->fence_reg
- 8) * 4;
2585 fence_reg
= FENCE_REG_830_0
+ obj_priv
->fence_reg
* 4;
2587 I915_WRITE(fence_reg
, 0);
2592 obj_priv
->fence_reg
= I915_FENCE_REG_NONE
;
2593 list_del_init(®
->lru_list
);
2597 * i915_gem_object_put_fence_reg - waits on outstanding fenced access
2598 * to the buffer to finish, and then resets the fence register.
2599 * @obj: tiled object holding a fence register.
2600 * @bool: whether the wait upon the fence is interruptible
2602 * Zeroes out the fence register itself and clears out the associated
2603 * data structures in dev_priv and obj_priv.
2606 i915_gem_object_put_fence_reg(struct drm_gem_object
*obj
,
2609 struct drm_device
*dev
= obj
->dev
;
2610 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2611 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2612 struct drm_i915_fence_reg
*reg
;
2614 if (obj_priv
->fence_reg
== I915_FENCE_REG_NONE
)
2617 /* If we've changed tiling, GTT-mappings of the object
2618 * need to re-fault to ensure that the correct fence register
2619 * setup is in place.
2621 i915_gem_release_mmap(obj
);
2623 /* On the i915, GPU access to tiled buffers is via a fence,
2624 * therefore we must wait for any outstanding access to complete
2625 * before clearing the fence.
2627 reg
= &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
2631 ret
= i915_gem_object_flush_gpu_write_domain(obj
, true);
2635 ret
= i915_gem_object_wait_rendering(obj
, interruptible
);
2642 i915_gem_object_flush_gtt_write_domain(obj
);
2643 i915_gem_clear_fence_reg(obj
);
2649 * Finds free space in the GTT aperture and binds the object there.
2652 i915_gem_object_bind_to_gtt(struct drm_gem_object
*obj
,
2656 struct drm_device
*dev
= obj
->dev
;
2657 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2658 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2659 struct drm_mm_node
*free_space
;
2660 gfp_t gfpmask
= __GFP_NORETRY
| __GFP_NOWARN
;
2663 if (obj_priv
->madv
!= I915_MADV_WILLNEED
) {
2664 DRM_ERROR("Attempting to bind a purgeable object\n");
2669 alignment
= i915_gem_get_gtt_alignment(obj
);
2670 if (alignment
& (i915_gem_get_gtt_alignment(obj
) - 1)) {
2671 DRM_ERROR("Invalid object alignment requested %u\n", alignment
);
2675 /* If the object is bigger than the entire aperture, reject it early
2676 * before evicting everything in a vain attempt to find space.
2679 (mappable
? dev_priv
->mm
.gtt_mappable_end
: dev_priv
->mm
.gtt_total
)) {
2680 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
2687 drm_mm_search_free_in_range(&dev_priv
->mm
.gtt_space
,
2688 obj
->size
, alignment
, 0,
2689 dev_priv
->mm
.gtt_mappable_end
,
2692 free_space
= drm_mm_search_free(&dev_priv
->mm
.gtt_space
,
2693 obj
->size
, alignment
, 0);
2695 if (free_space
!= NULL
) {
2697 obj_priv
->gtt_space
=
2698 drm_mm_get_block_range_generic(free_space
,
2701 dev_priv
->mm
.gtt_mappable_end
,
2704 obj_priv
->gtt_space
=
2705 drm_mm_get_block(free_space
, obj
->size
,
2708 if (obj_priv
->gtt_space
== NULL
) {
2709 /* If the gtt is empty and we're still having trouble
2710 * fitting our object in, we're out of memory.
2712 ret
= i915_gem_evict_something(dev
, obj
->size
, alignment
,
2720 ret
= i915_gem_object_get_pages(obj
, gfpmask
);
2722 drm_mm_put_block(obj_priv
->gtt_space
);
2723 obj_priv
->gtt_space
= NULL
;
2725 if (ret
== -ENOMEM
) {
2726 /* first try to clear up some space from the GTT */
2727 ret
= i915_gem_evict_something(dev
, obj
->size
,
2728 alignment
, mappable
);
2730 /* now try to shrink everyone else */
2745 /* Create an AGP memory structure pointing at our pages, and bind it
2748 obj_priv
->agp_mem
= drm_agp_bind_pages(dev
,
2750 obj
->size
>> PAGE_SHIFT
,
2751 obj_priv
->gtt_space
->start
,
2752 obj_priv
->agp_type
);
2753 if (obj_priv
->agp_mem
== NULL
) {
2754 i915_gem_object_put_pages(obj
);
2755 drm_mm_put_block(obj_priv
->gtt_space
);
2756 obj_priv
->gtt_space
= NULL
;
2758 ret
= i915_gem_evict_something(dev
, obj
->size
, alignment
,
2766 /* keep track of bounds object by adding it to the inactive list */
2767 list_add_tail(&obj_priv
->mm_list
, &dev_priv
->mm
.inactive_list
);
2768 i915_gem_info_add_gtt(dev_priv
, obj
->size
);
2770 /* Assert that the object is not currently in any GPU domain. As it
2771 * wasn't in the GTT, there shouldn't be any way it could have been in
2774 BUG_ON(obj
->read_domains
& I915_GEM_GPU_DOMAINS
);
2775 BUG_ON(obj
->write_domain
& I915_GEM_GPU_DOMAINS
);
2777 obj_priv
->gtt_offset
= obj_priv
->gtt_space
->start
;
2778 trace_i915_gem_object_bind(obj
, obj_priv
->gtt_offset
);
2784 i915_gem_clflush_object(struct drm_gem_object
*obj
)
2786 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2788 /* If we don't have a page list set up, then we're not pinned
2789 * to GPU, and we can ignore the cache flush because it'll happen
2790 * again at bind time.
2792 if (obj_priv
->pages
== NULL
)
2795 trace_i915_gem_object_clflush(obj
);
2797 drm_clflush_pages(obj_priv
->pages
, obj
->size
/ PAGE_SIZE
);
2800 /** Flushes any GPU write domain for the object if it's dirty. */
2802 i915_gem_object_flush_gpu_write_domain(struct drm_gem_object
*obj
,
2805 struct drm_device
*dev
= obj
->dev
;
2806 uint32_t old_write_domain
;
2808 if ((obj
->write_domain
& I915_GEM_GPU_DOMAINS
) == 0)
2811 /* Queue the GPU write cache flushing we need. */
2812 old_write_domain
= obj
->write_domain
;
2813 i915_gem_flush_ring(dev
, NULL
,
2814 to_intel_bo(obj
)->ring
,
2815 0, obj
->write_domain
);
2816 BUG_ON(obj
->write_domain
);
2818 trace_i915_gem_object_change_domain(obj
,
2825 return i915_gem_object_wait_rendering(obj
, true);
2828 /** Flushes the GTT write domain for the object if it's dirty. */
2830 i915_gem_object_flush_gtt_write_domain(struct drm_gem_object
*obj
)
2832 uint32_t old_write_domain
;
2834 if (obj
->write_domain
!= I915_GEM_DOMAIN_GTT
)
2837 /* No actual flushing is required for the GTT write domain. Writes
2838 * to it immediately go to main memory as far as we know, so there's
2839 * no chipset flush. It also doesn't land in render cache.
2841 old_write_domain
= obj
->write_domain
;
2842 obj
->write_domain
= 0;
2844 trace_i915_gem_object_change_domain(obj
,
2849 /** Flushes the CPU write domain for the object if it's dirty. */
2851 i915_gem_object_flush_cpu_write_domain(struct drm_gem_object
*obj
)
2853 struct drm_device
*dev
= obj
->dev
;
2854 uint32_t old_write_domain
;
2856 if (obj
->write_domain
!= I915_GEM_DOMAIN_CPU
)
2859 i915_gem_clflush_object(obj
);
2860 drm_agp_chipset_flush(dev
);
2861 old_write_domain
= obj
->write_domain
;
2862 obj
->write_domain
= 0;
2864 trace_i915_gem_object_change_domain(obj
,
2870 * Moves a single object to the GTT read, and possibly write domain.
2872 * This function returns when the move is complete, including waiting on
2876 i915_gem_object_set_to_gtt_domain(struct drm_gem_object
*obj
, int write
)
2878 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2879 uint32_t old_write_domain
, old_read_domains
;
2882 /* Not valid to be called on unbound objects. */
2883 if (obj_priv
->gtt_space
== NULL
)
2886 ret
= i915_gem_object_flush_gpu_write_domain(obj
, false);
2890 i915_gem_object_flush_cpu_write_domain(obj
);
2893 ret
= i915_gem_object_wait_rendering(obj
, true);
2898 old_write_domain
= obj
->write_domain
;
2899 old_read_domains
= obj
->read_domains
;
2901 /* It should now be out of any other write domains, and we can update
2902 * the domain values for our changes.
2904 BUG_ON((obj
->write_domain
& ~I915_GEM_DOMAIN_GTT
) != 0);
2905 obj
->read_domains
|= I915_GEM_DOMAIN_GTT
;
2907 obj
->read_domains
= I915_GEM_DOMAIN_GTT
;
2908 obj
->write_domain
= I915_GEM_DOMAIN_GTT
;
2909 obj_priv
->dirty
= 1;
2912 trace_i915_gem_object_change_domain(obj
,
2920 * Prepare buffer for display plane. Use uninterruptible for possible flush
2921 * wait, as in modesetting process we're not supposed to be interrupted.
2924 i915_gem_object_set_to_display_plane(struct drm_gem_object
*obj
,
2927 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2928 uint32_t old_read_domains
;
2931 /* Not valid to be called on unbound objects. */
2932 if (obj_priv
->gtt_space
== NULL
)
2935 ret
= i915_gem_object_flush_gpu_write_domain(obj
, true);
2939 /* Currently, we are always called from an non-interruptible context. */
2941 ret
= i915_gem_object_wait_rendering(obj
, false);
2946 i915_gem_object_flush_cpu_write_domain(obj
);
2948 old_read_domains
= obj
->read_domains
;
2949 obj
->read_domains
|= I915_GEM_DOMAIN_GTT
;
2951 trace_i915_gem_object_change_domain(obj
,
2959 * Moves a single object to the CPU read, and possibly write domain.
2961 * This function returns when the move is complete, including waiting on
2965 i915_gem_object_set_to_cpu_domain(struct drm_gem_object
*obj
, int write
)
2967 uint32_t old_write_domain
, old_read_domains
;
2970 ret
= i915_gem_object_flush_gpu_write_domain(obj
, false);
2974 i915_gem_object_flush_gtt_write_domain(obj
);
2976 /* If we have a partially-valid cache of the object in the CPU,
2977 * finish invalidating it and free the per-page flags.
2979 i915_gem_object_set_to_full_cpu_read_domain(obj
);
2982 ret
= i915_gem_object_wait_rendering(obj
, true);
2987 old_write_domain
= obj
->write_domain
;
2988 old_read_domains
= obj
->read_domains
;
2990 /* Flush the CPU cache if it's still invalid. */
2991 if ((obj
->read_domains
& I915_GEM_DOMAIN_CPU
) == 0) {
2992 i915_gem_clflush_object(obj
);
2994 obj
->read_domains
|= I915_GEM_DOMAIN_CPU
;
2997 /* It should now be out of any other write domains, and we can update
2998 * the domain values for our changes.
3000 BUG_ON((obj
->write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
3002 /* If we're writing through the CPU, then the GPU read domains will
3003 * need to be invalidated at next use.
3006 obj
->read_domains
= I915_GEM_DOMAIN_CPU
;
3007 obj
->write_domain
= I915_GEM_DOMAIN_CPU
;
3010 trace_i915_gem_object_change_domain(obj
,
3018 * Set the next domain for the specified object. This
3019 * may not actually perform the necessary flushing/invaliding though,
3020 * as that may want to be batched with other set_domain operations
3022 * This is (we hope) the only really tricky part of gem. The goal
3023 * is fairly simple -- track which caches hold bits of the object
3024 * and make sure they remain coherent. A few concrete examples may
3025 * help to explain how it works. For shorthand, we use the notation
3026 * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
3027 * a pair of read and write domain masks.
3029 * Case 1: the batch buffer
3035 * 5. Unmapped from GTT
3038 * Let's take these a step at a time
3041 * Pages allocated from the kernel may still have
3042 * cache contents, so we set them to (CPU, CPU) always.
3043 * 2. Written by CPU (using pwrite)
3044 * The pwrite function calls set_domain (CPU, CPU) and
3045 * this function does nothing (as nothing changes)
3047 * This function asserts that the object is not
3048 * currently in any GPU-based read or write domains
3050 * i915_gem_execbuffer calls set_domain (COMMAND, 0).
3051 * As write_domain is zero, this function adds in the
3052 * current read domains (CPU+COMMAND, 0).
3053 * flush_domains is set to CPU.
3054 * invalidate_domains is set to COMMAND
3055 * clflush is run to get data out of the CPU caches
3056 * then i915_dev_set_domain calls i915_gem_flush to
3057 * emit an MI_FLUSH and drm_agp_chipset_flush
3058 * 5. Unmapped from GTT
3059 * i915_gem_object_unbind calls set_domain (CPU, CPU)
3060 * flush_domains and invalidate_domains end up both zero
3061 * so no flushing/invalidating happens
3065 * Case 2: The shared render buffer
3069 * 3. Read/written by GPU
3070 * 4. set_domain to (CPU,CPU)
3071 * 5. Read/written by CPU
3072 * 6. Read/written by GPU
3075 * Same as last example, (CPU, CPU)
3077 * Nothing changes (assertions find that it is not in the GPU)
3078 * 3. Read/written by GPU
3079 * execbuffer calls set_domain (RENDER, RENDER)
3080 * flush_domains gets CPU
3081 * invalidate_domains gets GPU
3083 * MI_FLUSH and drm_agp_chipset_flush
3084 * 4. set_domain (CPU, CPU)
3085 * flush_domains gets GPU
3086 * invalidate_domains gets CPU
3087 * wait_rendering (obj) to make sure all drawing is complete.
3088 * This will include an MI_FLUSH to get the data from GPU
3090 * clflush (obj) to invalidate the CPU cache
3091 * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
3092 * 5. Read/written by CPU
3093 * cache lines are loaded and dirtied
3094 * 6. Read written by GPU
3095 * Same as last GPU access
3097 * Case 3: The constant buffer
3102 * 4. Updated (written) by CPU again
3111 * flush_domains = CPU
3112 * invalidate_domains = RENDER
3115 * drm_agp_chipset_flush
3116 * 4. Updated (written) by CPU again
3118 * flush_domains = 0 (no previous write domain)
3119 * invalidate_domains = 0 (no new read domains)
3122 * flush_domains = CPU
3123 * invalidate_domains = RENDER
3126 * drm_agp_chipset_flush
3129 i915_gem_object_set_to_gpu_domain(struct drm_gem_object
*obj
,
3130 struct intel_ring_buffer
*ring
)
3132 struct drm_device
*dev
= obj
->dev
;
3133 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3134 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
3135 uint32_t invalidate_domains
= 0;
3136 uint32_t flush_domains
= 0;
3139 * If the object isn't moving to a new write domain,
3140 * let the object stay in multiple read domains
3142 if (obj
->pending_write_domain
== 0)
3143 obj
->pending_read_domains
|= obj
->read_domains
;
3146 * Flush the current write domain if
3147 * the new read domains don't match. Invalidate
3148 * any read domains which differ from the old
3151 if (obj
->write_domain
&&
3152 obj
->write_domain
!= obj
->pending_read_domains
) {
3153 flush_domains
|= obj
->write_domain
;
3154 invalidate_domains
|=
3155 obj
->pending_read_domains
& ~obj
->write_domain
;
3158 * Invalidate any read caches which may have
3159 * stale data. That is, any new read domains.
3161 invalidate_domains
|= obj
->pending_read_domains
& ~obj
->read_domains
;
3162 if ((flush_domains
| invalidate_domains
) & I915_GEM_DOMAIN_CPU
)
3163 i915_gem_clflush_object(obj
);
3165 /* The actual obj->write_domain will be updated with
3166 * pending_write_domain after we emit the accumulated flush for all
3167 * of our domain changes in execbuffers (which clears objects'
3168 * write_domains). So if we have a current write domain that we
3169 * aren't changing, set pending_write_domain to that.
3171 if (flush_domains
== 0 && obj
->pending_write_domain
== 0)
3172 obj
->pending_write_domain
= obj
->write_domain
;
3174 dev
->invalidate_domains
|= invalidate_domains
;
3175 dev
->flush_domains
|= flush_domains
;
3176 if (flush_domains
& I915_GEM_GPU_DOMAINS
)
3177 dev_priv
->mm
.flush_rings
|= obj_priv
->ring
->id
;
3178 if (invalidate_domains
& I915_GEM_GPU_DOMAINS
)
3179 dev_priv
->mm
.flush_rings
|= ring
->id
;
3183 * Moves the object from a partially CPU read to a full one.
3185 * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
3186 * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
3189 i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object
*obj
)
3191 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
3193 if (!obj_priv
->page_cpu_valid
)
3196 /* If we're partially in the CPU read domain, finish moving it in.
3198 if (obj
->read_domains
& I915_GEM_DOMAIN_CPU
) {
3201 for (i
= 0; i
<= (obj
->size
- 1) / PAGE_SIZE
; i
++) {
3202 if (obj_priv
->page_cpu_valid
[i
])
3204 drm_clflush_pages(obj_priv
->pages
+ i
, 1);
3208 /* Free the page_cpu_valid mappings which are now stale, whether
3209 * or not we've got I915_GEM_DOMAIN_CPU.
3211 kfree(obj_priv
->page_cpu_valid
);
3212 obj_priv
->page_cpu_valid
= NULL
;
3216 * Set the CPU read domain on a range of the object.
3218 * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
3219 * not entirely valid. The page_cpu_valid member of the object flags which
3220 * pages have been flushed, and will be respected by
3221 * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
3222 * of the whole object.
3224 * This function returns when the move is complete, including waiting on
3228 i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object
*obj
,
3229 uint64_t offset
, uint64_t size
)
3231 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
3232 uint32_t old_read_domains
;
3235 if (offset
== 0 && size
== obj
->size
)
3236 return i915_gem_object_set_to_cpu_domain(obj
, 0);
3238 ret
= i915_gem_object_flush_gpu_write_domain(obj
, false);
3241 i915_gem_object_flush_gtt_write_domain(obj
);
3243 /* If we're already fully in the CPU read domain, we're done. */
3244 if (obj_priv
->page_cpu_valid
== NULL
&&
3245 (obj
->read_domains
& I915_GEM_DOMAIN_CPU
) != 0)
3248 /* Otherwise, create/clear the per-page CPU read domain flag if we're
3249 * newly adding I915_GEM_DOMAIN_CPU
3251 if (obj_priv
->page_cpu_valid
== NULL
) {
3252 obj_priv
->page_cpu_valid
= kzalloc(obj
->size
/ PAGE_SIZE
,
3254 if (obj_priv
->page_cpu_valid
== NULL
)
3256 } else if ((obj
->read_domains
& I915_GEM_DOMAIN_CPU
) == 0)
3257 memset(obj_priv
->page_cpu_valid
, 0, obj
->size
/ PAGE_SIZE
);
3259 /* Flush the cache on any pages that are still invalid from the CPU's
3262 for (i
= offset
/ PAGE_SIZE
; i
<= (offset
+ size
- 1) / PAGE_SIZE
;
3264 if (obj_priv
->page_cpu_valid
[i
])
3267 drm_clflush_pages(obj_priv
->pages
+ i
, 1);
3269 obj_priv
->page_cpu_valid
[i
] = 1;
3272 /* It should now be out of any other write domains, and we can update
3273 * the domain values for our changes.
3275 BUG_ON((obj
->write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
3277 old_read_domains
= obj
->read_domains
;
3278 obj
->read_domains
|= I915_GEM_DOMAIN_CPU
;
3280 trace_i915_gem_object_change_domain(obj
,
3288 * Pin an object to the GTT and evaluate the relocations landing in it.
3291 i915_gem_execbuffer_relocate(struct drm_i915_gem_object
*obj
,
3292 struct drm_file
*file_priv
,
3293 struct drm_i915_gem_exec_object2
*entry
)
3295 struct drm_device
*dev
= obj
->base
.dev
;
3296 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3297 struct drm_i915_gem_relocation_entry __user
*user_relocs
;
3298 struct drm_gem_object
*target_obj
= NULL
;
3299 uint32_t target_handle
= 0;
3302 user_relocs
= (void __user
*)(uintptr_t)entry
->relocs_ptr
;
3303 for (i
= 0; i
< entry
->relocation_count
; i
++) {
3304 struct drm_i915_gem_relocation_entry reloc
;
3305 uint32_t target_offset
;
3307 if (__copy_from_user_inatomic(&reloc
,
3314 if (reloc
.target_handle
!= target_handle
) {
3315 drm_gem_object_unreference(target_obj
);
3317 target_obj
= drm_gem_object_lookup(dev
, file_priv
,
3318 reloc
.target_handle
);
3319 if (target_obj
== NULL
) {
3324 target_handle
= reloc
.target_handle
;
3326 target_offset
= to_intel_bo(target_obj
)->gtt_offset
;
3329 DRM_INFO("%s: obj %p offset %08x target %d "
3330 "read %08x write %08x gtt %08x "
3331 "presumed %08x delta %08x\n",
3335 (int) reloc
.target_handle
,
3336 (int) reloc
.read_domains
,
3337 (int) reloc
.write_domain
,
3338 (int) target_offset
,
3339 (int) reloc
.presumed_offset
,
3343 /* The target buffer should have appeared before us in the
3344 * exec_object list, so it should have a GTT space bound by now.
3346 if (target_offset
== 0) {
3347 DRM_ERROR("No GTT space found for object %d\n",
3348 reloc
.target_handle
);
3353 /* Validate that the target is in a valid r/w GPU domain */
3354 if (reloc
.write_domain
& (reloc
.write_domain
- 1)) {
3355 DRM_ERROR("reloc with multiple write domains: "
3356 "obj %p target %d offset %d "
3357 "read %08x write %08x",
3358 obj
, reloc
.target_handle
,
3361 reloc
.write_domain
);
3365 if (reloc
.write_domain
& I915_GEM_DOMAIN_CPU
||
3366 reloc
.read_domains
& I915_GEM_DOMAIN_CPU
) {
3367 DRM_ERROR("reloc with read/write CPU domains: "
3368 "obj %p target %d offset %d "
3369 "read %08x write %08x",
3370 obj
, reloc
.target_handle
,
3373 reloc
.write_domain
);
3377 if (reloc
.write_domain
&& target_obj
->pending_write_domain
&&
3378 reloc
.write_domain
!= target_obj
->pending_write_domain
) {
3379 DRM_ERROR("Write domain conflict: "
3380 "obj %p target %d offset %d "
3381 "new %08x old %08x\n",
3382 obj
, reloc
.target_handle
,
3385 target_obj
->pending_write_domain
);
3390 target_obj
->pending_read_domains
|= reloc
.read_domains
;
3391 target_obj
->pending_write_domain
|= reloc
.write_domain
;
3393 /* If the relocation already has the right value in it, no
3394 * more work needs to be done.
3396 if (target_offset
== reloc
.presumed_offset
)
3399 /* Check that the relocation address is valid... */
3400 if (reloc
.offset
> obj
->base
.size
- 4) {
3401 DRM_ERROR("Relocation beyond object bounds: "
3402 "obj %p target %d offset %d size %d.\n",
3403 obj
, reloc
.target_handle
,
3404 (int) reloc
.offset
, (int) obj
->base
.size
);
3408 if (reloc
.offset
& 3) {
3409 DRM_ERROR("Relocation not 4-byte aligned: "
3410 "obj %p target %d offset %d.\n",
3411 obj
, reloc
.target_handle
,
3412 (int) reloc
.offset
);
3417 /* and points to somewhere within the target object. */
3418 if (reloc
.delta
>= target_obj
->size
) {
3419 DRM_ERROR("Relocation beyond target object bounds: "
3420 "obj %p target %d delta %d size %d.\n",
3421 obj
, reloc
.target_handle
,
3422 (int) reloc
.delta
, (int) target_obj
->size
);
3427 reloc
.delta
+= target_offset
;
3428 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_CPU
) {
3429 uint32_t page_offset
= reloc
.offset
& ~PAGE_MASK
;
3432 vaddr
= kmap_atomic(obj
->pages
[reloc
.offset
>> PAGE_SHIFT
]);
3433 *(uint32_t *)(vaddr
+ page_offset
) = reloc
.delta
;
3434 kunmap_atomic(vaddr
);
3436 uint32_t __iomem
*reloc_entry
;
3437 void __iomem
*reloc_page
;
3439 ret
= i915_gem_object_set_to_gtt_domain(&obj
->base
, 1);
3443 /* Map the page containing the relocation we're going to perform. */
3444 reloc
.offset
+= obj
->gtt_offset
;
3445 reloc_page
= io_mapping_map_atomic_wc(dev_priv
->mm
.gtt_mapping
,
3446 reloc
.offset
& PAGE_MASK
);
3447 reloc_entry
= (uint32_t __iomem
*)
3448 (reloc_page
+ (reloc
.offset
& ~PAGE_MASK
));
3449 iowrite32(reloc
.delta
, reloc_entry
);
3450 io_mapping_unmap_atomic(reloc_page
);
3453 /* and update the user's relocation entry */
3454 reloc
.presumed_offset
= target_offset
;
3455 if (__copy_to_user_inatomic(&user_relocs
[i
].presumed_offset
,
3456 &reloc
.presumed_offset
,
3457 sizeof(reloc
.presumed_offset
))) {
3463 drm_gem_object_unreference(target_obj
);
3468 i915_gem_execbuffer_pin(struct drm_device
*dev
,
3469 struct drm_file
*file
,
3470 struct drm_gem_object
**object_list
,
3471 struct drm_i915_gem_exec_object2
*exec_list
,
3474 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3477 /* attempt to pin all of the buffers into the GTT */
3478 for (retry
= 0; retry
< 2; retry
++) {
3480 for (i
= 0; i
< count
; i
++) {
3481 struct drm_i915_gem_exec_object2
*entry
= &exec_list
[i
];
3482 struct drm_i915_gem_object
*obj
= to_intel_bo(object_list
[i
]);
3484 entry
->flags
& EXEC_OBJECT_NEEDS_FENCE
&&
3485 obj
->tiling_mode
!= I915_TILING_NONE
;
3487 /* g33/pnv can't fence buffers in the unmappable part */
3488 bool need_mappable
=
3489 entry
->relocation_count
? true : need_fence
;
3491 /* Check fence reg constraints and rebind if necessary */
3493 !i915_gem_object_fence_offset_ok(&obj
->base
,
3494 obj
->tiling_mode
)) {
3495 ret
= i915_gem_object_unbind(&obj
->base
);
3500 ret
= i915_gem_object_pin(&obj
->base
,
3507 * Pre-965 chips need a fence register set up in order
3508 * to properly handle blits to/from tiled surfaces.
3511 ret
= i915_gem_object_get_fence_reg(&obj
->base
, true);
3513 i915_gem_object_unpin(&obj
->base
);
3517 dev_priv
->fence_regs
[obj
->fence_reg
].gpu
= true;
3520 entry
->offset
= obj
->gtt_offset
;
3524 i915_gem_object_unpin(object_list
[i
]);
3529 if (ret
!= -ENOSPC
|| retry
)
3532 ret
= i915_gem_evict_everything(dev
);
3540 /* Throttle our rendering by waiting until the ring has completed our requests
3541 * emitted over 20 msec ago.
3543 * Note that if we were to use the current jiffies each time around the loop,
3544 * we wouldn't escape the function with any frames outstanding if the time to
3545 * render a frame was over 20ms.
3547 * This should get us reasonable parallelism between CPU and GPU but also
3548 * relatively low latency when blocking on a particular request to finish.
3551 i915_gem_ring_throttle(struct drm_device
*dev
, struct drm_file
*file
)
3553 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3554 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
3555 unsigned long recent_enough
= jiffies
- msecs_to_jiffies(20);
3556 struct drm_i915_gem_request
*request
;
3557 struct intel_ring_buffer
*ring
= NULL
;
3561 spin_lock(&file_priv
->mm
.lock
);
3562 list_for_each_entry(request
, &file_priv
->mm
.request_list
, client_list
) {
3563 if (time_after_eq(request
->emitted_jiffies
, recent_enough
))
3566 ring
= request
->ring
;
3567 seqno
= request
->seqno
;
3569 spin_unlock(&file_priv
->mm
.lock
);
3575 if (!i915_seqno_passed(ring
->get_seqno(ring
), seqno
)) {
3576 /* And wait for the seqno passing without holding any locks and
3577 * causing extra latency for others. This is safe as the irq
3578 * generation is designed to be run atomically and so is
3581 ring
->user_irq_get(ring
);
3582 ret
= wait_event_interruptible(ring
->irq_queue
,
3583 i915_seqno_passed(ring
->get_seqno(ring
), seqno
)
3584 || atomic_read(&dev_priv
->mm
.wedged
));
3585 ring
->user_irq_put(ring
);
3587 if (ret
== 0 && atomic_read(&dev_priv
->mm
.wedged
))
3592 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, 0);
3598 i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2
*exec
,
3599 uint64_t exec_offset
)
3601 uint32_t exec_start
, exec_len
;
3603 exec_start
= (uint32_t) exec_offset
+ exec
->batch_start_offset
;
3604 exec_len
= (uint32_t) exec
->batch_len
;
3606 if ((exec_start
| exec_len
) & 0x7)
3616 validate_exec_list(struct drm_i915_gem_exec_object2
*exec
,
3621 for (i
= 0; i
< count
; i
++) {
3622 char __user
*ptr
= (char __user
*)(uintptr_t)exec
[i
].relocs_ptr
;
3623 size_t length
= exec
[i
].relocation_count
* sizeof(struct drm_i915_gem_relocation_entry
);
3625 if (!access_ok(VERIFY_READ
, ptr
, length
))
3628 /* we may also need to update the presumed offsets */
3629 if (!access_ok(VERIFY_WRITE
, ptr
, length
))
3632 if (fault_in_pages_readable(ptr
, length
))
3640 i915_gem_do_execbuffer(struct drm_device
*dev
, void *data
,
3641 struct drm_file
*file
,
3642 struct drm_i915_gem_execbuffer2
*args
,
3643 struct drm_i915_gem_exec_object2
*exec_list
)
3645 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3646 struct drm_gem_object
**object_list
= NULL
;
3647 struct drm_gem_object
*batch_obj
;
3648 struct drm_clip_rect
*cliprects
= NULL
;
3649 struct drm_i915_gem_request
*request
= NULL
;
3651 uint64_t exec_offset
;
3653 struct intel_ring_buffer
*ring
= NULL
;
3655 ret
= i915_gem_check_is_wedged(dev
);
3659 ret
= validate_exec_list(exec_list
, args
->buffer_count
);
3664 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3665 (int) args
->buffers_ptr
, args
->buffer_count
, args
->batch_len
);
3667 switch (args
->flags
& I915_EXEC_RING_MASK
) {
3668 case I915_EXEC_DEFAULT
:
3669 case I915_EXEC_RENDER
:
3670 ring
= &dev_priv
->render_ring
;
3673 if (!HAS_BSD(dev
)) {
3674 DRM_ERROR("execbuf with invalid ring (BSD)\n");
3677 ring
= &dev_priv
->bsd_ring
;
3680 if (!HAS_BLT(dev
)) {
3681 DRM_ERROR("execbuf with invalid ring (BLT)\n");
3684 ring
= &dev_priv
->blt_ring
;
3687 DRM_ERROR("execbuf with unknown ring: %d\n",
3688 (int)(args
->flags
& I915_EXEC_RING_MASK
));
3692 if (args
->buffer_count
< 1) {
3693 DRM_ERROR("execbuf with %d buffers\n", args
->buffer_count
);
3696 object_list
= drm_malloc_ab(sizeof(*object_list
), args
->buffer_count
);
3697 if (object_list
== NULL
) {
3698 DRM_ERROR("Failed to allocate object list for %d buffers\n",
3699 args
->buffer_count
);
3704 if (args
->num_cliprects
!= 0) {
3705 cliprects
= kcalloc(args
->num_cliprects
, sizeof(*cliprects
),
3707 if (cliprects
== NULL
) {
3712 ret
= copy_from_user(cliprects
,
3713 (struct drm_clip_rect __user
*)
3714 (uintptr_t) args
->cliprects_ptr
,
3715 sizeof(*cliprects
) * args
->num_cliprects
);
3717 DRM_ERROR("copy %d cliprects failed: %d\n",
3718 args
->num_cliprects
, ret
);
3724 request
= kzalloc(sizeof(*request
), GFP_KERNEL
);
3725 if (request
== NULL
) {
3730 ret
= i915_mutex_lock_interruptible(dev
);
3734 if (dev_priv
->mm
.suspended
) {
3735 mutex_unlock(&dev
->struct_mutex
);
3740 /* Look up object handles */
3741 for (i
= 0; i
< args
->buffer_count
; i
++) {
3742 struct drm_i915_gem_object
*obj_priv
;
3744 object_list
[i
] = drm_gem_object_lookup(dev
, file
,
3745 exec_list
[i
].handle
);
3746 if (object_list
[i
] == NULL
) {
3747 DRM_ERROR("Invalid object handle %d at index %d\n",
3748 exec_list
[i
].handle
, i
);
3749 /* prevent error path from reading uninitialized data */
3750 args
->buffer_count
= i
+ 1;
3755 obj_priv
= to_intel_bo(object_list
[i
]);
3756 if (obj_priv
->in_execbuffer
) {
3757 DRM_ERROR("Object %p appears more than once in object list\n",
3759 /* prevent error path from reading uninitialized data */
3760 args
->buffer_count
= i
+ 1;
3764 obj_priv
->in_execbuffer
= true;
3767 /* Move the objects en-masse into the GTT, evicting if necessary. */
3768 ret
= i915_gem_execbuffer_pin(dev
, file
,
3769 object_list
, exec_list
,
3770 args
->buffer_count
);
3774 /* The objects are in their final locations, apply the relocations. */
3775 for (i
= 0; i
< args
->buffer_count
; i
++) {
3776 struct drm_i915_gem_object
*obj
= to_intel_bo(object_list
[i
]);
3777 obj
->base
.pending_read_domains
= 0;
3778 obj
->base
.pending_write_domain
= 0;
3779 ret
= i915_gem_execbuffer_relocate(obj
, file
, &exec_list
[i
]);
3784 /* Set the pending read domains for the batch buffer to COMMAND */
3785 batch_obj
= object_list
[args
->buffer_count
-1];
3786 if (batch_obj
->pending_write_domain
) {
3787 DRM_ERROR("Attempting to use self-modifying batch buffer\n");
3791 batch_obj
->pending_read_domains
|= I915_GEM_DOMAIN_COMMAND
;
3793 /* Sanity check the batch buffer */
3794 exec_offset
= to_intel_bo(batch_obj
)->gtt_offset
;
3795 ret
= i915_gem_check_execbuffer(args
, exec_offset
);
3797 DRM_ERROR("execbuf with invalid offset/length\n");
3801 /* Zero the global flush/invalidate flags. These
3802 * will be modified as new domains are computed
3805 dev
->invalidate_domains
= 0;
3806 dev
->flush_domains
= 0;
3807 dev_priv
->mm
.flush_rings
= 0;
3808 for (i
= 0; i
< args
->buffer_count
; i
++)
3809 i915_gem_object_set_to_gpu_domain(object_list
[i
], ring
);
3811 if (dev
->invalidate_domains
| dev
->flush_domains
) {
3813 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
3815 dev
->invalidate_domains
,
3816 dev
->flush_domains
);
3818 i915_gem_flush(dev
, file
,
3819 dev
->invalidate_domains
,
3821 dev_priv
->mm
.flush_rings
);
3825 for (i
= 0; i
< args
->buffer_count
; i
++) {
3826 i915_gem_object_check_coherency(object_list
[i
],
3827 exec_list
[i
].handle
);
3832 i915_gem_dump_object(batch_obj
,
3838 /* Check for any pending flips. As we only maintain a flip queue depth
3839 * of 1, we can simply insert a WAIT for the next display flip prior
3840 * to executing the batch and avoid stalling the CPU.
3843 for (i
= 0; i
< args
->buffer_count
; i
++) {
3844 if (object_list
[i
]->write_domain
)
3845 flips
|= atomic_read(&to_intel_bo(object_list
[i
])->pending_flip
);
3848 int plane
, flip_mask
;
3850 for (plane
= 0; flips
>> plane
; plane
++) {
3851 if (((flips
>> plane
) & 1) == 0)
3855 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
3857 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
3859 ret
= intel_ring_begin(ring
, 2);
3863 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
3864 intel_ring_emit(ring
, MI_NOOP
);
3865 intel_ring_advance(ring
);
3869 /* Exec the batchbuffer */
3870 ret
= ring
->dispatch_execbuffer(ring
, args
, cliprects
, exec_offset
);
3872 DRM_ERROR("dispatch failed %d\n", ret
);
3876 for (i
= 0; i
< args
->buffer_count
; i
++) {
3877 struct drm_gem_object
*obj
= object_list
[i
];
3879 obj
->read_domains
= obj
->pending_read_domains
;
3880 obj
->write_domain
= obj
->pending_write_domain
;
3882 i915_gem_object_move_to_active(obj
, ring
);
3883 if (obj
->write_domain
) {
3884 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
3885 obj_priv
->dirty
= 1;
3886 list_move_tail(&obj_priv
->gpu_write_list
,
3887 &ring
->gpu_write_list
);
3888 intel_mark_busy(dev
, obj
);
3891 trace_i915_gem_object_change_domain(obj
,
3897 * Ensure that the commands in the batch buffer are
3898 * finished before the interrupt fires
3900 i915_retire_commands(dev
, ring
);
3902 if (i915_add_request(dev
, file
, request
, ring
))
3903 ring
->outstanding_lazy_request
= true;
3908 for (i
= 0; i
< args
->buffer_count
; i
++) {
3909 if (object_list
[i
] == NULL
)
3912 to_intel_bo(object_list
[i
])->in_execbuffer
= false;
3913 drm_gem_object_unreference(object_list
[i
]);
3916 mutex_unlock(&dev
->struct_mutex
);
3919 drm_free_large(object_list
);
3927 * Legacy execbuffer just creates an exec2 list from the original exec object
3928 * list array and passes it to the real function.
3931 i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
3932 struct drm_file
*file_priv
)
3934 struct drm_i915_gem_execbuffer
*args
= data
;
3935 struct drm_i915_gem_execbuffer2 exec2
;
3936 struct drm_i915_gem_exec_object
*exec_list
= NULL
;
3937 struct drm_i915_gem_exec_object2
*exec2_list
= NULL
;
3941 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3942 (int) args
->buffers_ptr
, args
->buffer_count
, args
->batch_len
);
3945 if (args
->buffer_count
< 1) {
3946 DRM_ERROR("execbuf with %d buffers\n", args
->buffer_count
);
3950 /* Copy in the exec list from userland */
3951 exec_list
= drm_malloc_ab(sizeof(*exec_list
), args
->buffer_count
);
3952 exec2_list
= drm_malloc_ab(sizeof(*exec2_list
), args
->buffer_count
);
3953 if (exec_list
== NULL
|| exec2_list
== NULL
) {
3954 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
3955 args
->buffer_count
);
3956 drm_free_large(exec_list
);
3957 drm_free_large(exec2_list
);
3960 ret
= copy_from_user(exec_list
,
3961 (struct drm_i915_relocation_entry __user
*)
3962 (uintptr_t) args
->buffers_ptr
,
3963 sizeof(*exec_list
) * args
->buffer_count
);
3965 DRM_ERROR("copy %d exec entries failed %d\n",
3966 args
->buffer_count
, ret
);
3967 drm_free_large(exec_list
);
3968 drm_free_large(exec2_list
);
3972 for (i
= 0; i
< args
->buffer_count
; i
++) {
3973 exec2_list
[i
].handle
= exec_list
[i
].handle
;
3974 exec2_list
[i
].relocation_count
= exec_list
[i
].relocation_count
;
3975 exec2_list
[i
].relocs_ptr
= exec_list
[i
].relocs_ptr
;
3976 exec2_list
[i
].alignment
= exec_list
[i
].alignment
;
3977 exec2_list
[i
].offset
= exec_list
[i
].offset
;
3978 if (INTEL_INFO(dev
)->gen
< 4)
3979 exec2_list
[i
].flags
= EXEC_OBJECT_NEEDS_FENCE
;
3981 exec2_list
[i
].flags
= 0;
3984 exec2
.buffers_ptr
= args
->buffers_ptr
;
3985 exec2
.buffer_count
= args
->buffer_count
;
3986 exec2
.batch_start_offset
= args
->batch_start_offset
;
3987 exec2
.batch_len
= args
->batch_len
;
3988 exec2
.DR1
= args
->DR1
;
3989 exec2
.DR4
= args
->DR4
;
3990 exec2
.num_cliprects
= args
->num_cliprects
;
3991 exec2
.cliprects_ptr
= args
->cliprects_ptr
;
3992 exec2
.flags
= I915_EXEC_RENDER
;
3994 ret
= i915_gem_do_execbuffer(dev
, data
, file_priv
, &exec2
, exec2_list
);
3996 /* Copy the new buffer offsets back to the user's exec list. */
3997 for (i
= 0; i
< args
->buffer_count
; i
++)
3998 exec_list
[i
].offset
= exec2_list
[i
].offset
;
3999 /* ... and back out to userspace */
4000 ret
= copy_to_user((struct drm_i915_relocation_entry __user
*)
4001 (uintptr_t) args
->buffers_ptr
,
4003 sizeof(*exec_list
) * args
->buffer_count
);
4006 DRM_ERROR("failed to copy %d exec entries "
4007 "back to user (%d)\n",
4008 args
->buffer_count
, ret
);
4012 drm_free_large(exec_list
);
4013 drm_free_large(exec2_list
);
4018 i915_gem_execbuffer2(struct drm_device
*dev
, void *data
,
4019 struct drm_file
*file_priv
)
4021 struct drm_i915_gem_execbuffer2
*args
= data
;
4022 struct drm_i915_gem_exec_object2
*exec2_list
= NULL
;
4026 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
4027 (int) args
->buffers_ptr
, args
->buffer_count
, args
->batch_len
);
4030 if (args
->buffer_count
< 1) {
4031 DRM_ERROR("execbuf2 with %d buffers\n", args
->buffer_count
);
4035 exec2_list
= drm_malloc_ab(sizeof(*exec2_list
), args
->buffer_count
);
4036 if (exec2_list
== NULL
) {
4037 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
4038 args
->buffer_count
);
4041 ret
= copy_from_user(exec2_list
,
4042 (struct drm_i915_relocation_entry __user
*)
4043 (uintptr_t) args
->buffers_ptr
,
4044 sizeof(*exec2_list
) * args
->buffer_count
);
4046 DRM_ERROR("copy %d exec entries failed %d\n",
4047 args
->buffer_count
, ret
);
4048 drm_free_large(exec2_list
);
4052 ret
= i915_gem_do_execbuffer(dev
, data
, file_priv
, args
, exec2_list
);
4054 /* Copy the new buffer offsets back to the user's exec list. */
4055 ret
= copy_to_user((struct drm_i915_relocation_entry __user
*)
4056 (uintptr_t) args
->buffers_ptr
,
4058 sizeof(*exec2_list
) * args
->buffer_count
);
4061 DRM_ERROR("failed to copy %d exec entries "
4062 "back to user (%d)\n",
4063 args
->buffer_count
, ret
);
4067 drm_free_large(exec2_list
);
4072 i915_gem_object_pin(struct drm_gem_object
*obj
, uint32_t alignment
,
4075 struct drm_device
*dev
= obj
->dev
;
4076 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4077 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
4080 BUG_ON(obj_priv
->pin_count
== DRM_I915_GEM_OBJECT_MAX_PIN_COUNT
);
4081 WARN_ON(i915_verify_lists(dev
));
4083 if (obj_priv
->gtt_space
!= NULL
) {
4085 alignment
= i915_gem_get_gtt_alignment(obj
);
4086 if (obj_priv
->gtt_offset
& (alignment
- 1) ||
4087 (mappable
&& !i915_gem_object_cpu_accessible(obj_priv
))) {
4088 WARN(obj_priv
->pin_count
,
4089 "bo is already pinned with incorrect alignment:"
4090 " offset=%x, req.alignment=%x\n",
4091 obj_priv
->gtt_offset
, alignment
);
4092 ret
= i915_gem_object_unbind(obj
);
4098 if (obj_priv
->gtt_space
== NULL
) {
4099 ret
= i915_gem_object_bind_to_gtt(obj
, alignment
, mappable
);
4104 obj_priv
->pin_count
++;
4106 /* If the object is not active and not pending a flush,
4107 * remove it from the inactive list
4109 if (obj_priv
->pin_count
== 1) {
4110 i915_gem_info_add_pin(dev_priv
, obj
->size
);
4111 if (!obj_priv
->active
)
4112 list_move_tail(&obj_priv
->mm_list
,
4113 &dev_priv
->mm
.pinned_list
);
4116 WARN_ON(i915_verify_lists(dev
));
4121 i915_gem_object_unpin(struct drm_gem_object
*obj
)
4123 struct drm_device
*dev
= obj
->dev
;
4124 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4125 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
4127 WARN_ON(i915_verify_lists(dev
));
4128 obj_priv
->pin_count
--;
4129 BUG_ON(obj_priv
->pin_count
< 0);
4130 BUG_ON(obj_priv
->gtt_space
== NULL
);
4132 /* If the object is no longer pinned, and is
4133 * neither active nor being flushed, then stick it on
4136 if (obj_priv
->pin_count
== 0) {
4137 if (!obj_priv
->active
)
4138 list_move_tail(&obj_priv
->mm_list
,
4139 &dev_priv
->mm
.inactive_list
);
4140 i915_gem_info_remove_pin(dev_priv
, obj
->size
);
4142 WARN_ON(i915_verify_lists(dev
));
4146 i915_gem_pin_ioctl(struct drm_device
*dev
, void *data
,
4147 struct drm_file
*file_priv
)
4149 struct drm_i915_gem_pin
*args
= data
;
4150 struct drm_gem_object
*obj
;
4151 struct drm_i915_gem_object
*obj_priv
;
4154 ret
= i915_mutex_lock_interruptible(dev
);
4158 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
4163 obj_priv
= to_intel_bo(obj
);
4165 if (obj_priv
->madv
!= I915_MADV_WILLNEED
) {
4166 DRM_ERROR("Attempting to pin a purgeable buffer\n");
4171 if (obj_priv
->pin_filp
!= NULL
&& obj_priv
->pin_filp
!= file_priv
) {
4172 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
4178 obj_priv
->user_pin_count
++;
4179 obj_priv
->pin_filp
= file_priv
;
4180 if (obj_priv
->user_pin_count
== 1) {
4181 ret
= i915_gem_object_pin(obj
, args
->alignment
, true);
4186 /* XXX - flush the CPU caches for pinned objects
4187 * as the X server doesn't manage domains yet
4189 i915_gem_object_flush_cpu_write_domain(obj
);
4190 args
->offset
= obj_priv
->gtt_offset
;
4192 drm_gem_object_unreference(obj
);
4194 mutex_unlock(&dev
->struct_mutex
);
4199 i915_gem_unpin_ioctl(struct drm_device
*dev
, void *data
,
4200 struct drm_file
*file_priv
)
4202 struct drm_i915_gem_pin
*args
= data
;
4203 struct drm_gem_object
*obj
;
4204 struct drm_i915_gem_object
*obj_priv
;
4207 ret
= i915_mutex_lock_interruptible(dev
);
4211 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
4216 obj_priv
= to_intel_bo(obj
);
4218 if (obj_priv
->pin_filp
!= file_priv
) {
4219 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
4224 obj_priv
->user_pin_count
--;
4225 if (obj_priv
->user_pin_count
== 0) {
4226 obj_priv
->pin_filp
= NULL
;
4227 i915_gem_object_unpin(obj
);
4231 drm_gem_object_unreference(obj
);
4233 mutex_unlock(&dev
->struct_mutex
);
4238 i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
4239 struct drm_file
*file_priv
)
4241 struct drm_i915_gem_busy
*args
= data
;
4242 struct drm_gem_object
*obj
;
4243 struct drm_i915_gem_object
*obj_priv
;
4246 ret
= i915_mutex_lock_interruptible(dev
);
4250 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
4255 obj_priv
= to_intel_bo(obj
);
4257 /* Count all active objects as busy, even if they are currently not used
4258 * by the gpu. Users of this interface expect objects to eventually
4259 * become non-busy without any further actions, therefore emit any
4260 * necessary flushes here.
4262 args
->busy
= obj_priv
->active
;
4264 /* Unconditionally flush objects, even when the gpu still uses this
4265 * object. Userspace calling this function indicates that it wants to
4266 * use this buffer rather sooner than later, so issuing the required
4267 * flush earlier is beneficial.
4269 if (obj
->write_domain
& I915_GEM_GPU_DOMAINS
)
4270 i915_gem_flush_ring(dev
, file_priv
,
4272 0, obj
->write_domain
);
4274 /* Update the active list for the hardware's current position.
4275 * Otherwise this only updates on a delayed timer or when irqs
4276 * are actually unmasked, and our working set ends up being
4277 * larger than required.
4279 i915_gem_retire_requests_ring(dev
, obj_priv
->ring
);
4281 args
->busy
= obj_priv
->active
;
4284 drm_gem_object_unreference(obj
);
4286 mutex_unlock(&dev
->struct_mutex
);
4291 i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
4292 struct drm_file
*file_priv
)
4294 return i915_gem_ring_throttle(dev
, file_priv
);
4298 i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
4299 struct drm_file
*file_priv
)
4301 struct drm_i915_gem_madvise
*args
= data
;
4302 struct drm_gem_object
*obj
;
4303 struct drm_i915_gem_object
*obj_priv
;
4306 switch (args
->madv
) {
4307 case I915_MADV_DONTNEED
:
4308 case I915_MADV_WILLNEED
:
4314 ret
= i915_mutex_lock_interruptible(dev
);
4318 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
4323 obj_priv
= to_intel_bo(obj
);
4325 if (obj_priv
->pin_count
) {
4330 if (obj_priv
->madv
!= __I915_MADV_PURGED
)
4331 obj_priv
->madv
= args
->madv
;
4333 /* if the object is no longer bound, discard its backing storage */
4334 if (i915_gem_object_is_purgeable(obj_priv
) &&
4335 obj_priv
->gtt_space
== NULL
)
4336 i915_gem_object_truncate(obj
);
4338 args
->retained
= obj_priv
->madv
!= __I915_MADV_PURGED
;
4341 drm_gem_object_unreference(obj
);
4343 mutex_unlock(&dev
->struct_mutex
);
4347 struct drm_gem_object
* i915_gem_alloc_object(struct drm_device
*dev
,
4350 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4351 struct drm_i915_gem_object
*obj
;
4353 obj
= kzalloc(sizeof(*obj
), GFP_KERNEL
);
4357 if (drm_gem_object_init(dev
, &obj
->base
, size
) != 0) {
4362 i915_gem_info_add_obj(dev_priv
, size
);
4364 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
4365 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
4367 obj
->agp_type
= AGP_USER_MEMORY
;
4368 obj
->base
.driver_private
= NULL
;
4369 obj
->fence_reg
= I915_FENCE_REG_NONE
;
4370 INIT_LIST_HEAD(&obj
->mm_list
);
4371 INIT_LIST_HEAD(&obj
->ring_list
);
4372 INIT_LIST_HEAD(&obj
->gpu_write_list
);
4373 obj
->madv
= I915_MADV_WILLNEED
;
4378 int i915_gem_init_object(struct drm_gem_object
*obj
)
4385 static void i915_gem_free_object_tail(struct drm_gem_object
*obj
)
4387 struct drm_device
*dev
= obj
->dev
;
4388 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4389 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
4392 ret
= i915_gem_object_unbind(obj
);
4393 if (ret
== -ERESTARTSYS
) {
4394 list_move(&obj_priv
->mm_list
,
4395 &dev_priv
->mm
.deferred_free_list
);
4399 if (obj_priv
->mmap_offset
)
4400 i915_gem_free_mmap_offset(obj
);
4402 drm_gem_object_release(obj
);
4403 i915_gem_info_remove_obj(dev_priv
, obj
->size
);
4405 kfree(obj_priv
->page_cpu_valid
);
4406 kfree(obj_priv
->bit_17
);
4410 void i915_gem_free_object(struct drm_gem_object
*obj
)
4412 struct drm_device
*dev
= obj
->dev
;
4413 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
4415 trace_i915_gem_object_destroy(obj
);
4417 while (obj_priv
->pin_count
> 0)
4418 i915_gem_object_unpin(obj
);
4420 if (obj_priv
->phys_obj
)
4421 i915_gem_detach_phys_object(dev
, obj
);
4423 i915_gem_free_object_tail(obj
);
4427 i915_gem_idle(struct drm_device
*dev
)
4429 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4432 mutex_lock(&dev
->struct_mutex
);
4434 if (dev_priv
->mm
.suspended
) {
4435 mutex_unlock(&dev
->struct_mutex
);
4439 ret
= i915_gpu_idle(dev
);
4441 mutex_unlock(&dev
->struct_mutex
);
4445 /* Under UMS, be paranoid and evict. */
4446 if (!drm_core_check_feature(dev
, DRIVER_MODESET
)) {
4447 ret
= i915_gem_evict_inactive(dev
);
4449 mutex_unlock(&dev
->struct_mutex
);
4454 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4455 * We need to replace this with a semaphore, or something.
4456 * And not confound mm.suspended!
4458 dev_priv
->mm
.suspended
= 1;
4459 del_timer_sync(&dev_priv
->hangcheck_timer
);
4461 i915_kernel_lost_context(dev
);
4462 i915_gem_cleanup_ringbuffer(dev
);
4464 mutex_unlock(&dev
->struct_mutex
);
4466 /* Cancel the retire work handler, which should be idle now. */
4467 cancel_delayed_work_sync(&dev_priv
->mm
.retire_work
);
4473 * 965+ support PIPE_CONTROL commands, which provide finer grained control
4474 * over cache flushing.
4477 i915_gem_init_pipe_control(struct drm_device
*dev
)
4479 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4480 struct drm_gem_object
*obj
;
4481 struct drm_i915_gem_object
*obj_priv
;
4484 obj
= i915_gem_alloc_object(dev
, 4096);
4486 DRM_ERROR("Failed to allocate seqno page\n");
4490 obj_priv
= to_intel_bo(obj
);
4491 obj_priv
->agp_type
= AGP_USER_CACHED_MEMORY
;
4493 ret
= i915_gem_object_pin(obj
, 4096, true);
4497 dev_priv
->seqno_gfx_addr
= obj_priv
->gtt_offset
;
4498 dev_priv
->seqno_page
= kmap(obj_priv
->pages
[0]);
4499 if (dev_priv
->seqno_page
== NULL
)
4502 dev_priv
->seqno_obj
= obj
;
4503 memset(dev_priv
->seqno_page
, 0, PAGE_SIZE
);
4508 i915_gem_object_unpin(obj
);
4510 drm_gem_object_unreference(obj
);
4517 i915_gem_cleanup_pipe_control(struct drm_device
*dev
)
4519 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4520 struct drm_gem_object
*obj
;
4521 struct drm_i915_gem_object
*obj_priv
;
4523 obj
= dev_priv
->seqno_obj
;
4524 obj_priv
= to_intel_bo(obj
);
4525 kunmap(obj_priv
->pages
[0]);
4526 i915_gem_object_unpin(obj
);
4527 drm_gem_object_unreference(obj
);
4528 dev_priv
->seqno_obj
= NULL
;
4530 dev_priv
->seqno_page
= NULL
;
4534 i915_gem_init_ringbuffer(struct drm_device
*dev
)
4536 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4539 if (HAS_PIPE_CONTROL(dev
)) {
4540 ret
= i915_gem_init_pipe_control(dev
);
4545 ret
= intel_init_render_ring_buffer(dev
);
4547 goto cleanup_pipe_control
;
4550 ret
= intel_init_bsd_ring_buffer(dev
);
4552 goto cleanup_render_ring
;
4556 ret
= intel_init_blt_ring_buffer(dev
);
4558 goto cleanup_bsd_ring
;
4561 dev_priv
->next_seqno
= 1;
4566 intel_cleanup_ring_buffer(&dev_priv
->bsd_ring
);
4567 cleanup_render_ring
:
4568 intel_cleanup_ring_buffer(&dev_priv
->render_ring
);
4569 cleanup_pipe_control
:
4570 if (HAS_PIPE_CONTROL(dev
))
4571 i915_gem_cleanup_pipe_control(dev
);
4576 i915_gem_cleanup_ringbuffer(struct drm_device
*dev
)
4578 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4580 intel_cleanup_ring_buffer(&dev_priv
->render_ring
);
4581 intel_cleanup_ring_buffer(&dev_priv
->bsd_ring
);
4582 intel_cleanup_ring_buffer(&dev_priv
->blt_ring
);
4583 if (HAS_PIPE_CONTROL(dev
))
4584 i915_gem_cleanup_pipe_control(dev
);
4588 i915_gem_entervt_ioctl(struct drm_device
*dev
, void *data
,
4589 struct drm_file
*file_priv
)
4591 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4594 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4597 if (atomic_read(&dev_priv
->mm
.wedged
)) {
4598 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4599 atomic_set(&dev_priv
->mm
.wedged
, 0);
4602 mutex_lock(&dev
->struct_mutex
);
4603 dev_priv
->mm
.suspended
= 0;
4605 ret
= i915_gem_init_ringbuffer(dev
);
4607 mutex_unlock(&dev
->struct_mutex
);
4611 BUG_ON(!list_empty(&dev_priv
->mm
.active_list
));
4612 BUG_ON(!list_empty(&dev_priv
->render_ring
.active_list
));
4613 BUG_ON(!list_empty(&dev_priv
->bsd_ring
.active_list
));
4614 BUG_ON(!list_empty(&dev_priv
->blt_ring
.active_list
));
4615 BUG_ON(!list_empty(&dev_priv
->mm
.flushing_list
));
4616 BUG_ON(!list_empty(&dev_priv
->mm
.inactive_list
));
4617 BUG_ON(!list_empty(&dev_priv
->render_ring
.request_list
));
4618 BUG_ON(!list_empty(&dev_priv
->bsd_ring
.request_list
));
4619 BUG_ON(!list_empty(&dev_priv
->blt_ring
.request_list
));
4620 mutex_unlock(&dev
->struct_mutex
);
4622 ret
= drm_irq_install(dev
);
4624 goto cleanup_ringbuffer
;
4629 mutex_lock(&dev
->struct_mutex
);
4630 i915_gem_cleanup_ringbuffer(dev
);
4631 dev_priv
->mm
.suspended
= 1;
4632 mutex_unlock(&dev
->struct_mutex
);
4638 i915_gem_leavevt_ioctl(struct drm_device
*dev
, void *data
,
4639 struct drm_file
*file_priv
)
4641 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4644 drm_irq_uninstall(dev
);
4645 return i915_gem_idle(dev
);
4649 i915_gem_lastclose(struct drm_device
*dev
)
4653 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4656 ret
= i915_gem_idle(dev
);
4658 DRM_ERROR("failed to idle hardware: %d\n", ret
);
4662 init_ring_lists(struct intel_ring_buffer
*ring
)
4664 INIT_LIST_HEAD(&ring
->active_list
);
4665 INIT_LIST_HEAD(&ring
->request_list
);
4666 INIT_LIST_HEAD(&ring
->gpu_write_list
);
4670 i915_gem_load(struct drm_device
*dev
)
4673 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4675 INIT_LIST_HEAD(&dev_priv
->mm
.active_list
);
4676 INIT_LIST_HEAD(&dev_priv
->mm
.flushing_list
);
4677 INIT_LIST_HEAD(&dev_priv
->mm
.inactive_list
);
4678 INIT_LIST_HEAD(&dev_priv
->mm
.pinned_list
);
4679 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
4680 INIT_LIST_HEAD(&dev_priv
->mm
.deferred_free_list
);
4681 init_ring_lists(&dev_priv
->render_ring
);
4682 init_ring_lists(&dev_priv
->bsd_ring
);
4683 init_ring_lists(&dev_priv
->blt_ring
);
4684 for (i
= 0; i
< 16; i
++)
4685 INIT_LIST_HEAD(&dev_priv
->fence_regs
[i
].lru_list
);
4686 INIT_DELAYED_WORK(&dev_priv
->mm
.retire_work
,
4687 i915_gem_retire_work_handler
);
4688 init_completion(&dev_priv
->error_completion
);
4689 spin_lock(&shrink_list_lock
);
4690 list_add(&dev_priv
->mm
.shrink_list
, &shrink_list
);
4691 spin_unlock(&shrink_list_lock
);
4693 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4695 u32 tmp
= I915_READ(MI_ARB_STATE
);
4696 if (!(tmp
& MI_ARB_C3_LP_WRITE_ENABLE
)) {
4697 /* arb state is a masked write, so set bit + bit in mask */
4698 tmp
= MI_ARB_C3_LP_WRITE_ENABLE
| (MI_ARB_C3_LP_WRITE_ENABLE
<< MI_ARB_MASK_SHIFT
);
4699 I915_WRITE(MI_ARB_STATE
, tmp
);
4703 /* Old X drivers will take 0-2 for front, back, depth buffers */
4704 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
4705 dev_priv
->fence_reg_start
= 3;
4707 if (INTEL_INFO(dev
)->gen
>= 4 || IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
4708 dev_priv
->num_fence_regs
= 16;
4710 dev_priv
->num_fence_regs
= 8;
4712 /* Initialize fence registers to zero */
4713 switch (INTEL_INFO(dev
)->gen
) {
4715 for (i
= 0; i
< 16; i
++)
4716 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0
+ (i
* 8), 0);
4720 for (i
= 0; i
< 16; i
++)
4721 I915_WRITE64(FENCE_REG_965_0
+ (i
* 8), 0);
4724 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
4725 for (i
= 0; i
< 8; i
++)
4726 I915_WRITE(FENCE_REG_945_8
+ (i
* 4), 0);
4728 for (i
= 0; i
< 8; i
++)
4729 I915_WRITE(FENCE_REG_830_0
+ (i
* 4), 0);
4732 i915_gem_detect_bit_6_swizzle(dev
);
4733 init_waitqueue_head(&dev_priv
->pending_flip_queue
);
4737 * Create a physically contiguous memory object for this object
4738 * e.g. for cursor + overlay regs
4740 static int i915_gem_init_phys_object(struct drm_device
*dev
,
4741 int id
, int size
, int align
)
4743 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4744 struct drm_i915_gem_phys_object
*phys_obj
;
4747 if (dev_priv
->mm
.phys_objs
[id
- 1] || !size
)
4750 phys_obj
= kzalloc(sizeof(struct drm_i915_gem_phys_object
), GFP_KERNEL
);
4756 phys_obj
->handle
= drm_pci_alloc(dev
, size
, align
);
4757 if (!phys_obj
->handle
) {
4762 set_memory_wc((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
4765 dev_priv
->mm
.phys_objs
[id
- 1] = phys_obj
;
4773 static void i915_gem_free_phys_object(struct drm_device
*dev
, int id
)
4775 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4776 struct drm_i915_gem_phys_object
*phys_obj
;
4778 if (!dev_priv
->mm
.phys_objs
[id
- 1])
4781 phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
4782 if (phys_obj
->cur_obj
) {
4783 i915_gem_detach_phys_object(dev
, phys_obj
->cur_obj
);
4787 set_memory_wb((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
4789 drm_pci_free(dev
, phys_obj
->handle
);
4791 dev_priv
->mm
.phys_objs
[id
- 1] = NULL
;
4794 void i915_gem_free_all_phys_object(struct drm_device
*dev
)
4798 for (i
= I915_GEM_PHYS_CURSOR_0
; i
<= I915_MAX_PHYS_OBJECT
; i
++)
4799 i915_gem_free_phys_object(dev
, i
);
4802 void i915_gem_detach_phys_object(struct drm_device
*dev
,
4803 struct drm_gem_object
*obj
)
4805 struct drm_i915_gem_object
*obj_priv
;
4810 obj_priv
= to_intel_bo(obj
);
4811 if (!obj_priv
->phys_obj
)
4814 ret
= i915_gem_object_get_pages(obj
, 0);
4818 page_count
= obj
->size
/ PAGE_SIZE
;
4820 for (i
= 0; i
< page_count
; i
++) {
4821 char *dst
= kmap_atomic(obj_priv
->pages
[i
]);
4822 char *src
= obj_priv
->phys_obj
->handle
->vaddr
+ (i
* PAGE_SIZE
);
4824 memcpy(dst
, src
, PAGE_SIZE
);
4827 drm_clflush_pages(obj_priv
->pages
, page_count
);
4828 drm_agp_chipset_flush(dev
);
4830 i915_gem_object_put_pages(obj
);
4832 obj_priv
->phys_obj
->cur_obj
= NULL
;
4833 obj_priv
->phys_obj
= NULL
;
4837 i915_gem_attach_phys_object(struct drm_device
*dev
,
4838 struct drm_gem_object
*obj
,
4842 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4843 struct drm_i915_gem_object
*obj_priv
;
4848 if (id
> I915_MAX_PHYS_OBJECT
)
4851 obj_priv
= to_intel_bo(obj
);
4853 if (obj_priv
->phys_obj
) {
4854 if (obj_priv
->phys_obj
->id
== id
)
4856 i915_gem_detach_phys_object(dev
, obj
);
4859 /* create a new object */
4860 if (!dev_priv
->mm
.phys_objs
[id
- 1]) {
4861 ret
= i915_gem_init_phys_object(dev
, id
,
4864 DRM_ERROR("failed to init phys object %d size: %zu\n", id
, obj
->size
);
4869 /* bind to the object */
4870 obj_priv
->phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
4871 obj_priv
->phys_obj
->cur_obj
= obj
;
4873 ret
= i915_gem_object_get_pages(obj
, 0);
4875 DRM_ERROR("failed to get page list\n");
4879 page_count
= obj
->size
/ PAGE_SIZE
;
4881 for (i
= 0; i
< page_count
; i
++) {
4882 char *src
= kmap_atomic(obj_priv
->pages
[i
]);
4883 char *dst
= obj_priv
->phys_obj
->handle
->vaddr
+ (i
* PAGE_SIZE
);
4885 memcpy(dst
, src
, PAGE_SIZE
);
4889 i915_gem_object_put_pages(obj
);
4897 i915_gem_phys_pwrite(struct drm_device
*dev
, struct drm_gem_object
*obj
,
4898 struct drm_i915_gem_pwrite
*args
,
4899 struct drm_file
*file_priv
)
4901 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
4904 char __user
*user_data
;
4906 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
4907 obj_addr
= obj_priv
->phys_obj
->handle
->vaddr
+ args
->offset
;
4909 DRM_DEBUG_DRIVER("obj_addr %p, %lld\n", obj_addr
, args
->size
);
4910 ret
= copy_from_user(obj_addr
, user_data
, args
->size
);
4914 drm_agp_chipset_flush(dev
);
4918 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
)
4920 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
4922 /* Clean up our request list when the client is going away, so that
4923 * later retire_requests won't dereference our soon-to-be-gone
4926 spin_lock(&file_priv
->mm
.lock
);
4927 while (!list_empty(&file_priv
->mm
.request_list
)) {
4928 struct drm_i915_gem_request
*request
;
4930 request
= list_first_entry(&file_priv
->mm
.request_list
,
4931 struct drm_i915_gem_request
,
4933 list_del(&request
->client_list
);
4934 request
->file_priv
= NULL
;
4936 spin_unlock(&file_priv
->mm
.lock
);
4940 i915_gpu_is_active(struct drm_device
*dev
)
4942 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4945 lists_empty
= list_empty(&dev_priv
->mm
.flushing_list
) &&
4946 list_empty(&dev_priv
->render_ring
.active_list
) &&
4947 list_empty(&dev_priv
->bsd_ring
.active_list
) &&
4948 list_empty(&dev_priv
->blt_ring
.active_list
);
4950 return !lists_empty
;
4954 i915_gem_shrink(struct shrinker
*shrink
, int nr_to_scan
, gfp_t gfp_mask
)
4956 drm_i915_private_t
*dev_priv
, *next_dev
;
4957 struct drm_i915_gem_object
*obj_priv
, *next_obj
;
4959 int would_deadlock
= 1;
4961 /* "fast-path" to count number of available objects */
4962 if (nr_to_scan
== 0) {
4963 spin_lock(&shrink_list_lock
);
4964 list_for_each_entry(dev_priv
, &shrink_list
, mm
.shrink_list
) {
4965 struct drm_device
*dev
= dev_priv
->dev
;
4967 if (mutex_trylock(&dev
->struct_mutex
)) {
4968 list_for_each_entry(obj_priv
,
4969 &dev_priv
->mm
.inactive_list
,
4972 mutex_unlock(&dev
->struct_mutex
);
4975 spin_unlock(&shrink_list_lock
);
4977 return (cnt
/ 100) * sysctl_vfs_cache_pressure
;
4980 spin_lock(&shrink_list_lock
);
4983 /* first scan for clean buffers */
4984 list_for_each_entry_safe(dev_priv
, next_dev
,
4985 &shrink_list
, mm
.shrink_list
) {
4986 struct drm_device
*dev
= dev_priv
->dev
;
4988 if (! mutex_trylock(&dev
->struct_mutex
))
4991 spin_unlock(&shrink_list_lock
);
4992 i915_gem_retire_requests(dev
);
4994 list_for_each_entry_safe(obj_priv
, next_obj
,
4995 &dev_priv
->mm
.inactive_list
,
4997 if (i915_gem_object_is_purgeable(obj_priv
)) {
4998 i915_gem_object_unbind(&obj_priv
->base
);
4999 if (--nr_to_scan
<= 0)
5004 spin_lock(&shrink_list_lock
);
5005 mutex_unlock(&dev
->struct_mutex
);
5009 if (nr_to_scan
<= 0)
5013 /* second pass, evict/count anything still on the inactive list */
5014 list_for_each_entry_safe(dev_priv
, next_dev
,
5015 &shrink_list
, mm
.shrink_list
) {
5016 struct drm_device
*dev
= dev_priv
->dev
;
5018 if (! mutex_trylock(&dev
->struct_mutex
))
5021 spin_unlock(&shrink_list_lock
);
5023 list_for_each_entry_safe(obj_priv
, next_obj
,
5024 &dev_priv
->mm
.inactive_list
,
5026 if (nr_to_scan
> 0) {
5027 i915_gem_object_unbind(&obj_priv
->base
);
5033 spin_lock(&shrink_list_lock
);
5034 mutex_unlock(&dev
->struct_mutex
);
5043 * We are desperate for pages, so as a last resort, wait
5044 * for the GPU to finish and discard whatever we can.
5045 * This has a dramatic impact to reduce the number of
5046 * OOM-killer events whilst running the GPU aggressively.
5048 list_for_each_entry(dev_priv
, &shrink_list
, mm
.shrink_list
) {
5049 struct drm_device
*dev
= dev_priv
->dev
;
5051 if (!mutex_trylock(&dev
->struct_mutex
))
5054 spin_unlock(&shrink_list_lock
);
5056 if (i915_gpu_is_active(dev
)) {
5061 spin_lock(&shrink_list_lock
);
5062 mutex_unlock(&dev
->struct_mutex
);
5069 spin_unlock(&shrink_list_lock
);
5074 return (cnt
/ 100) * sysctl_vfs_cache_pressure
;
5079 static struct shrinker shrinker
= {
5080 .shrink
= i915_gem_shrink
,
5081 .seeks
= DEFAULT_SEEKS
,
5085 i915_gem_shrinker_init(void)
5087 register_shrinker(&shrinker
);
5091 i915_gem_shrinker_exit(void)
5093 unregister_shrinker(&shrinker
);