2 * Copyright (c) 2000-2004 by David Brownell
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
11 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software Foundation,
16 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 #include <linux/module.h>
20 #include <linux/pci.h>
21 #include <linux/dmapool.h>
22 #include <linux/kernel.h>
23 #include <linux/delay.h>
24 #include <linux/ioport.h>
25 #include <linux/sched.h>
26 #include <linux/slab.h>
27 #include <linux/vmalloc.h>
28 #include <linux/errno.h>
29 #include <linux/init.h>
30 #include <linux/timer.h>
31 #include <linux/list.h>
32 #include <linux/interrupt.h>
33 #include <linux/reboot.h>
34 #include <linux/usb.h>
35 #include <linux/moduleparam.h>
36 #include <linux/dma-mapping.h>
37 #include <linux/debugfs.h>
39 #include "../core/hcd.h"
41 #include <asm/byteorder.h>
44 #include <asm/system.h>
45 #include <asm/unaligned.h>
47 /*-------------------------------------------------------------------------*/
50 * EHCI hc_driver implementation ... experimental, incomplete.
51 * Based on the final 1.0 register interface specification.
53 * USB 2.0 shows up in upcoming www.pcmcia.org technology.
54 * First was PCMCIA, like ISA; then CardBus, which is PCI.
55 * Next comes "CardBay", using USB 2.0 signals.
57 * Contains additional contributions by Brad Hards, Rory Bolt, and others.
58 * Special thanks to Intel and VIA for providing host controllers to
59 * test this driver on, and Cypress (including In-System Design) for
60 * providing early devices for those host controllers to talk to!
63 #define DRIVER_AUTHOR "David Brownell"
64 #define DRIVER_DESC "USB 2.0 'Enhanced' Host Controller (EHCI) Driver"
66 static const char hcd_name
[] = "ehci_hcd";
76 /* magic numbers that can affect system performance */
77 #define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */
78 #define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */
79 #define EHCI_TUNE_RL_TT 0
80 #define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */
81 #define EHCI_TUNE_MULT_TT 1
82 #define EHCI_TUNE_FLS 2 /* (small) 256 frame schedule */
84 #define EHCI_IAA_MSECS 10 /* arbitrary */
85 #define EHCI_IO_JIFFIES (HZ/10) /* io watchdog > irq_thresh */
86 #define EHCI_ASYNC_JIFFIES (HZ/20) /* async idle timeout */
87 #define EHCI_SHRINK_FRAMES 5 /* async qh unlink delay */
89 /* Initial IRQ latency: faster than hw default */
90 static int log2_irq_thresh
= 0; // 0 to 6
91 module_param (log2_irq_thresh
, int, S_IRUGO
);
92 MODULE_PARM_DESC (log2_irq_thresh
, "log2 IRQ latency, 1-64 microframes");
94 /* initial park setting: slower than hw default */
95 static unsigned park
= 0;
96 module_param (park
, uint
, S_IRUGO
);
97 MODULE_PARM_DESC (park
, "park setting; 1-3 back-to-back async packets");
99 /* for flakey hardware, ignore overcurrent indicators */
100 static int ignore_oc
= 0;
101 module_param (ignore_oc
, bool, S_IRUGO
);
102 MODULE_PARM_DESC (ignore_oc
, "ignore bogus hardware overcurrent indications");
104 #define INTR_MASK (STS_IAA | STS_FATAL | STS_PCD | STS_ERR | STS_INT)
106 /*-------------------------------------------------------------------------*/
109 #include "ehci-dbg.c"
111 /*-------------------------------------------------------------------------*/
114 timer_action(struct ehci_hcd
*ehci
, enum ehci_timer_action action
)
116 /* Don't override timeouts which shrink or (later) disable
117 * the async ring; just the I/O watchdog. Note that if a
118 * SHRINK were pending, OFF would never be requested.
120 if (timer_pending(&ehci
->watchdog
)
121 && ((BIT(TIMER_ASYNC_SHRINK
) | BIT(TIMER_ASYNC_OFF
))
125 if (!test_and_set_bit(action
, &ehci
->actions
)) {
129 case TIMER_IO_WATCHDOG
:
130 if (!ehci
->need_io_watchdog
)
134 case TIMER_ASYNC_OFF
:
135 t
= EHCI_ASYNC_JIFFIES
;
137 /* case TIMER_ASYNC_SHRINK: */
139 /* add a jiffie since we synch against the
140 * 8 KHz uframe counter.
142 t
= DIV_ROUND_UP(EHCI_SHRINK_FRAMES
* HZ
, 1000) + 1;
145 mod_timer(&ehci
->watchdog
, t
+ jiffies
);
149 /*-------------------------------------------------------------------------*/
152 * handshake - spin reading hc until handshake completes or fails
153 * @ptr: address of hc register to be read
154 * @mask: bits to look at in result of read
155 * @done: value of those bits when handshake succeeds
156 * @usec: timeout in microseconds
158 * Returns negative errno, or zero on success
160 * Success happens when the "mask" bits have the specified value (hardware
161 * handshake done). There are two failure modes: "usec" have passed (major
162 * hardware flakeout), or the register reads as all-ones (hardware removed).
164 * That last failure should_only happen in cases like physical cardbus eject
165 * before driver shutdown. But it also seems to be caused by bugs in cardbus
166 * bridge shutdown: shutting down the bridge before the devices using it.
168 static int handshake (struct ehci_hcd
*ehci
, void __iomem
*ptr
,
169 u32 mask
, u32 done
, int usec
)
174 result
= ehci_readl(ehci
, ptr
);
175 if (result
== ~(u32
)0) /* card removed */
186 /* force HC to halt state from unknown (EHCI spec section 2.3) */
187 static int ehci_halt (struct ehci_hcd
*ehci
)
189 u32 temp
= ehci_readl(ehci
, &ehci
->regs
->status
);
191 /* disable any irqs left enabled by previous code */
192 ehci_writel(ehci
, 0, &ehci
->regs
->intr_enable
);
194 if ((temp
& STS_HALT
) != 0)
197 temp
= ehci_readl(ehci
, &ehci
->regs
->command
);
199 ehci_writel(ehci
, temp
, &ehci
->regs
->command
);
200 return handshake (ehci
, &ehci
->regs
->status
,
201 STS_HALT
, STS_HALT
, 16 * 125);
204 static int handshake_on_error_set_halt(struct ehci_hcd
*ehci
, void __iomem
*ptr
,
205 u32 mask
, u32 done
, int usec
)
209 error
= handshake(ehci
, ptr
, mask
, done
, usec
);
212 ehci_to_hcd(ehci
)->state
= HC_STATE_HALT
;
213 ehci_err(ehci
, "force halt; handhake %p %08x %08x -> %d\n",
214 ptr
, mask
, done
, error
);
220 /* put TDI/ARC silicon into EHCI mode */
221 static void tdi_reset (struct ehci_hcd
*ehci
)
223 u32 __iomem
*reg_ptr
;
226 reg_ptr
= (u32 __iomem
*)(((u8 __iomem
*)ehci
->regs
) + USBMODE
);
227 tmp
= ehci_readl(ehci
, reg_ptr
);
228 tmp
|= USBMODE_CM_HC
;
229 /* The default byte access to MMR space is LE after
230 * controller reset. Set the required endian mode
231 * for transfer buffers to match the host microprocessor
233 if (ehci_big_endian_mmio(ehci
))
235 ehci_writel(ehci
, tmp
, reg_ptr
);
238 /* reset a non-running (STS_HALT == 1) controller */
239 static int ehci_reset (struct ehci_hcd
*ehci
)
242 u32 command
= ehci_readl(ehci
, &ehci
->regs
->command
);
244 command
|= CMD_RESET
;
245 dbg_cmd (ehci
, "reset", command
);
246 ehci_writel(ehci
, command
, &ehci
->regs
->command
);
247 ehci_to_hcd(ehci
)->state
= HC_STATE_HALT
;
248 ehci
->next_statechange
= jiffies
;
249 retval
= handshake (ehci
, &ehci
->regs
->command
,
250 CMD_RESET
, 0, 250 * 1000);
252 if (ehci
->has_hostpc
) {
253 ehci_writel(ehci
, USBMODE_EX_HC
| USBMODE_EX_VBPS
,
254 (u32 __iomem
*)(((u8
*)ehci
->regs
) + USBMODE_EX
));
255 ehci_writel(ehci
, TXFIFO_DEFAULT
,
256 (u32 __iomem
*)(((u8
*)ehci
->regs
) + TXFILLTUNING
));
261 if (ehci_is_TDI(ehci
))
267 /* idle the controller (from running) */
268 static void ehci_quiesce (struct ehci_hcd
*ehci
)
273 if (!HC_IS_RUNNING (ehci_to_hcd(ehci
)->state
))
277 /* wait for any schedule enables/disables to take effect */
278 temp
= ehci_readl(ehci
, &ehci
->regs
->command
) << 10;
279 temp
&= STS_ASS
| STS_PSS
;
280 if (handshake_on_error_set_halt(ehci
, &ehci
->regs
->status
,
281 STS_ASS
| STS_PSS
, temp
, 16 * 125))
284 /* then disable anything that's still active */
285 temp
= ehci_readl(ehci
, &ehci
->regs
->command
);
286 temp
&= ~(CMD_ASE
| CMD_IAAD
| CMD_PSE
);
287 ehci_writel(ehci
, temp
, &ehci
->regs
->command
);
289 /* hardware can take 16 microframes to turn off ... */
290 handshake_on_error_set_halt(ehci
, &ehci
->regs
->status
,
291 STS_ASS
| STS_PSS
, 0, 16 * 125);
294 /*-------------------------------------------------------------------------*/
296 static void end_unlink_async(struct ehci_hcd
*ehci
);
297 static void ehci_work(struct ehci_hcd
*ehci
);
299 #include "ehci-hub.c"
300 #include "ehci-mem.c"
302 #include "ehci-sched.c"
304 /*-------------------------------------------------------------------------*/
306 static void ehci_iaa_watchdog(unsigned long param
)
308 struct ehci_hcd
*ehci
= (struct ehci_hcd
*) param
;
311 spin_lock_irqsave (&ehci
->lock
, flags
);
313 /* Lost IAA irqs wedge things badly; seen first with a vt8235.
314 * So we need this watchdog, but must protect it against both
315 * (a) SMP races against real IAA firing and retriggering, and
316 * (b) clean HC shutdown, when IAA watchdog was pending.
319 && !timer_pending(&ehci
->iaa_watchdog
)
320 && HC_IS_RUNNING(ehci_to_hcd(ehci
)->state
)) {
323 /* If we get here, IAA is *REALLY* late. It's barely
324 * conceivable that the system is so busy that CMD_IAAD
325 * is still legitimately set, so let's be sure it's
326 * clear before we read STS_IAA. (The HC should clear
327 * CMD_IAAD when it sets STS_IAA.)
329 cmd
= ehci_readl(ehci
, &ehci
->regs
->command
);
331 ehci_writel(ehci
, cmd
& ~CMD_IAAD
,
332 &ehci
->regs
->command
);
334 /* If IAA is set here it either legitimately triggered
335 * before we cleared IAAD above (but _way_ late, so we'll
336 * still count it as lost) ... or a silicon erratum:
337 * - VIA seems to set IAA without triggering the IRQ;
338 * - IAAD potentially cleared without setting IAA.
340 status
= ehci_readl(ehci
, &ehci
->regs
->status
);
341 if ((status
& STS_IAA
) || !(cmd
& CMD_IAAD
)) {
342 COUNT (ehci
->stats
.lost_iaa
);
343 ehci_writel(ehci
, STS_IAA
, &ehci
->regs
->status
);
346 ehci_vdbg(ehci
, "IAA watchdog: status %x cmd %x\n",
348 end_unlink_async(ehci
);
351 spin_unlock_irqrestore(&ehci
->lock
, flags
);
354 static void ehci_watchdog(unsigned long param
)
356 struct ehci_hcd
*ehci
= (struct ehci_hcd
*) param
;
359 spin_lock_irqsave(&ehci
->lock
, flags
);
361 /* stop async processing after it's idled a bit */
362 if (test_bit (TIMER_ASYNC_OFF
, &ehci
->actions
))
363 start_unlink_async (ehci
, ehci
->async
);
365 /* ehci could run by timer, without IRQs ... */
368 spin_unlock_irqrestore (&ehci
->lock
, flags
);
371 /* On some systems, leaving remote wakeup enabled prevents system shutdown.
372 * The firmware seems to think that powering off is a wakeup event!
373 * This routine turns off remote wakeup and everything else, on all ports.
375 static void ehci_turn_off_all_ports(struct ehci_hcd
*ehci
)
377 int port
= HCS_N_PORTS(ehci
->hcs_params
);
380 ehci_writel(ehci
, PORT_RWC_BITS
,
381 &ehci
->regs
->port_status
[port
]);
385 * Halt HC, turn off all ports, and let the BIOS use the companion controllers.
386 * Should be called with ehci->lock held.
388 static void ehci_silence_controller(struct ehci_hcd
*ehci
)
391 ehci_turn_off_all_ports(ehci
);
393 /* make BIOS/etc use companion controller during reboot */
394 ehci_writel(ehci
, 0, &ehci
->regs
->configured_flag
);
396 /* unblock posted writes */
397 ehci_readl(ehci
, &ehci
->regs
->configured_flag
);
400 /* ehci_shutdown kick in for silicon on any bus (not just pci, etc).
401 * This forcibly disables dma and IRQs, helping kexec and other cases
402 * where the next system software may expect clean state.
404 static void ehci_shutdown(struct usb_hcd
*hcd
)
406 struct ehci_hcd
*ehci
= hcd_to_ehci(hcd
);
408 del_timer_sync(&ehci
->watchdog
);
409 del_timer_sync(&ehci
->iaa_watchdog
);
411 spin_lock_irq(&ehci
->lock
);
412 ehci_silence_controller(ehci
);
413 spin_unlock_irq(&ehci
->lock
);
416 static void ehci_port_power (struct ehci_hcd
*ehci
, int is_on
)
420 if (!HCS_PPC (ehci
->hcs_params
))
423 ehci_dbg (ehci
, "...power%s ports...\n", is_on
? "up" : "down");
424 for (port
= HCS_N_PORTS (ehci
->hcs_params
); port
> 0; )
425 (void) ehci_hub_control(ehci_to_hcd(ehci
),
426 is_on
? SetPortFeature
: ClearPortFeature
,
429 /* Flush those writes */
430 ehci_readl(ehci
, &ehci
->regs
->command
);
434 /*-------------------------------------------------------------------------*/
437 * ehci_work is called from some interrupts, timers, and so on.
438 * it calls driver completion functions, after dropping ehci->lock.
440 static void ehci_work (struct ehci_hcd
*ehci
)
442 timer_action_done (ehci
, TIMER_IO_WATCHDOG
);
444 /* another CPU may drop ehci->lock during a schedule scan while
445 * it reports urb completions. this flag guards against bogus
446 * attempts at re-entrant schedule scanning.
452 if (ehci
->next_uframe
!= -1)
453 scan_periodic (ehci
);
456 /* the IO watchdog guards against hardware or driver bugs that
457 * misplace IRQs, and should let us run completely without IRQs.
458 * such lossage has been observed on both VT6202 and VT8235.
460 if (HC_IS_RUNNING (ehci_to_hcd(ehci
)->state
) &&
461 (ehci
->async
->qh_next
.ptr
!= NULL
||
462 ehci
->periodic_sched
!= 0))
463 timer_action (ehci
, TIMER_IO_WATCHDOG
);
467 * Called when the ehci_hcd module is removed.
469 static void ehci_stop (struct usb_hcd
*hcd
)
471 struct ehci_hcd
*ehci
= hcd_to_ehci (hcd
);
473 ehci_dbg (ehci
, "stop\n");
475 /* no more interrupts ... */
476 del_timer_sync (&ehci
->watchdog
);
477 del_timer_sync(&ehci
->iaa_watchdog
);
479 spin_lock_irq(&ehci
->lock
);
480 if (HC_IS_RUNNING (hcd
->state
))
483 ehci_silence_controller(ehci
);
485 spin_unlock_irq(&ehci
->lock
);
487 remove_companion_file(ehci
);
488 remove_debug_files (ehci
);
490 /* root hub is shut down separately (first, when possible) */
491 spin_lock_irq (&ehci
->lock
);
494 spin_unlock_irq (&ehci
->lock
);
495 ehci_mem_cleanup (ehci
);
498 ehci_dbg (ehci
, "irq normal %ld err %ld reclaim %ld (lost %ld)\n",
499 ehci
->stats
.normal
, ehci
->stats
.error
, ehci
->stats
.reclaim
,
500 ehci
->stats
.lost_iaa
);
501 ehci_dbg (ehci
, "complete %ld unlink %ld\n",
502 ehci
->stats
.complete
, ehci
->stats
.unlink
);
505 dbg_status (ehci
, "ehci_stop completed",
506 ehci_readl(ehci
, &ehci
->regs
->status
));
509 /* one-time init, only for memory state */
510 static int ehci_init(struct usb_hcd
*hcd
)
512 struct ehci_hcd
*ehci
= hcd_to_ehci(hcd
);
516 struct ehci_qh_hw
*hw
;
518 spin_lock_init(&ehci
->lock
);
521 * keep io watchdog by default, those good HCDs could turn off it later
523 ehci
->need_io_watchdog
= 1;
524 init_timer(&ehci
->watchdog
);
525 ehci
->watchdog
.function
= ehci_watchdog
;
526 ehci
->watchdog
.data
= (unsigned long) ehci
;
528 init_timer(&ehci
->iaa_watchdog
);
529 ehci
->iaa_watchdog
.function
= ehci_iaa_watchdog
;
530 ehci
->iaa_watchdog
.data
= (unsigned long) ehci
;
533 * hw default: 1K periodic list heads, one per frame.
534 * periodic_size can shrink by USBCMD update if hcc_params allows.
536 ehci
->periodic_size
= DEFAULT_I_TDPS
;
537 INIT_LIST_HEAD(&ehci
->cached_itd_list
);
538 if ((retval
= ehci_mem_init(ehci
, GFP_KERNEL
)) < 0)
541 /* controllers may cache some of the periodic schedule ... */
542 hcc_params
= ehci_readl(ehci
, &ehci
->caps
->hcc_params
);
543 if (HCC_ISOC_CACHE(hcc_params
)) // full frame cache
545 else // N microframes cached
546 ehci
->i_thresh
= 2 + HCC_ISOC_THRES(hcc_params
);
548 ehci
->reclaim
= NULL
;
549 ehci
->next_uframe
= -1;
550 ehci
->clock_frame
= -1;
553 * dedicate a qh for the async ring head, since we couldn't unlink
554 * a 'real' qh without stopping the async schedule [4.8]. use it
555 * as the 'reclamation list head' too.
556 * its dummy is used in hw_alt_next of many tds, to prevent the qh
557 * from automatically advancing to the next td after short reads.
559 ehci
->async
->qh_next
.qh
= NULL
;
560 hw
= ehci
->async
->hw
;
561 hw
->hw_next
= QH_NEXT(ehci
, ehci
->async
->qh_dma
);
562 hw
->hw_info1
= cpu_to_hc32(ehci
, QH_HEAD
);
563 hw
->hw_token
= cpu_to_hc32(ehci
, QTD_STS_HALT
);
564 hw
->hw_qtd_next
= EHCI_LIST_END(ehci
);
565 ehci
->async
->qh_state
= QH_STATE_LINKED
;
566 hw
->hw_alt_next
= QTD_NEXT(ehci
, ehci
->async
->dummy
->qtd_dma
);
568 /* clear interrupt enables, set irq latency */
569 if (log2_irq_thresh
< 0 || log2_irq_thresh
> 6)
571 temp
= 1 << (16 + log2_irq_thresh
);
572 if (HCC_CANPARK(hcc_params
)) {
573 /* HW default park == 3, on hardware that supports it (like
574 * NVidia and ALI silicon), maximizes throughput on the async
575 * schedule by avoiding QH fetches between transfers.
577 * With fast usb storage devices and NForce2, "park" seems to
578 * make problems: throughput reduction (!), data errors...
581 park
= min(park
, (unsigned) 3);
585 ehci_dbg(ehci
, "park %d\n", park
);
587 if (HCC_PGM_FRAMELISTLEN(hcc_params
)) {
588 /* periodic schedule size can be smaller than default */
590 temp
|= (EHCI_TUNE_FLS
<< 2);
591 switch (EHCI_TUNE_FLS
) {
592 case 0: ehci
->periodic_size
= 1024; break;
593 case 1: ehci
->periodic_size
= 512; break;
594 case 2: ehci
->periodic_size
= 256; break;
598 ehci
->command
= temp
;
603 /* start HC running; it's halted, ehci_init() has been run (once) */
604 static int ehci_run (struct usb_hcd
*hcd
)
606 struct ehci_hcd
*ehci
= hcd_to_ehci (hcd
);
611 hcd
->uses_new_polling
= 1;
614 /* EHCI spec section 4.1 */
615 if ((retval
= ehci_reset(ehci
)) != 0) {
616 ehci_mem_cleanup(ehci
);
619 ehci_writel(ehci
, ehci
->periodic_dma
, &ehci
->regs
->frame_list
);
620 ehci_writel(ehci
, (u32
)ehci
->async
->qh_dma
, &ehci
->regs
->async_next
);
623 * hcc_params controls whether ehci->regs->segment must (!!!)
624 * be used; it constrains QH/ITD/SITD and QTD locations.
625 * pci_pool consistent memory always uses segment zero.
626 * streaming mappings for I/O buffers, like pci_map_single(),
627 * can return segments above 4GB, if the device allows.
629 * NOTE: the dma mask is visible through dma_supported(), so
630 * drivers can pass this info along ... like NETIF_F_HIGHDMA,
631 * Scsi_Host.highmem_io, and so forth. It's readonly to all
632 * host side drivers though.
634 hcc_params
= ehci_readl(ehci
, &ehci
->caps
->hcc_params
);
635 if (HCC_64BIT_ADDR(hcc_params
)) {
636 ehci_writel(ehci
, 0, &ehci
->regs
->segment
);
638 // this is deeply broken on almost all architectures
639 if (!dma_set_mask(hcd
->self
.controller
, DMA_BIT_MASK(64)))
640 ehci_info(ehci
, "enabled 64bit DMA\n");
645 // Philips, Intel, and maybe others need CMD_RUN before the
646 // root hub will detect new devices (why?); NEC doesn't
647 ehci
->command
&= ~(CMD_LRESET
|CMD_IAAD
|CMD_PSE
|CMD_ASE
|CMD_RESET
);
648 ehci
->command
|= CMD_RUN
;
649 ehci_writel(ehci
, ehci
->command
, &ehci
->regs
->command
);
650 dbg_cmd (ehci
, "init", ehci
->command
);
653 * Start, enabling full USB 2.0 functionality ... usb 1.1 devices
654 * are explicitly handed to companion controller(s), so no TT is
655 * involved with the root hub. (Except where one is integrated,
656 * and there's no companion controller unless maybe for USB OTG.)
658 * Turning on the CF flag will transfer ownership of all ports
659 * from the companions to the EHCI controller. If any of the
660 * companions are in the middle of a port reset at the time, it
661 * could cause trouble. Write-locking ehci_cf_port_reset_rwsem
662 * guarantees that no resets are in progress. After we set CF,
663 * a short delay lets the hardware catch up; new resets shouldn't
664 * be started before the port switching actions could complete.
666 down_write(&ehci_cf_port_reset_rwsem
);
667 hcd
->state
= HC_STATE_RUNNING
;
668 ehci_writel(ehci
, FLAG_CF
, &ehci
->regs
->configured_flag
);
669 ehci_readl(ehci
, &ehci
->regs
->command
); /* unblock posted writes */
671 up_write(&ehci_cf_port_reset_rwsem
);
673 temp
= HC_VERSION(ehci_readl(ehci
, &ehci
->caps
->hc_capbase
));
675 "USB %x.%x started, EHCI %x.%02x%s\n",
676 ((ehci
->sbrn
& 0xf0)>>4), (ehci
->sbrn
& 0x0f),
677 temp
>> 8, temp
& 0xff,
678 ignore_oc
? ", overcurrent ignored" : "");
680 ehci_writel(ehci
, INTR_MASK
,
681 &ehci
->regs
->intr_enable
); /* Turn On Interrupts */
683 /* GRR this is run-once init(), being done every time the HC starts.
684 * So long as they're part of class devices, we can't do it init()
685 * since the class device isn't created that early.
687 create_debug_files(ehci
);
688 create_companion_file(ehci
);
693 /*-------------------------------------------------------------------------*/
695 static irqreturn_t
ehci_irq (struct usb_hcd
*hcd
)
697 struct ehci_hcd
*ehci
= hcd_to_ehci (hcd
);
698 u32 status
, masked_status
, pcd_status
= 0, cmd
;
701 spin_lock (&ehci
->lock
);
703 status
= ehci_readl(ehci
, &ehci
->regs
->status
);
705 /* e.g. cardbus physical eject */
706 if (status
== ~(u32
) 0) {
707 ehci_dbg (ehci
, "device removed\n");
711 masked_status
= status
& INTR_MASK
;
712 if (!masked_status
) { /* irq sharing? */
713 spin_unlock(&ehci
->lock
);
717 /* clear (just) interrupts */
718 ehci_writel(ehci
, masked_status
, &ehci
->regs
->status
);
719 cmd
= ehci_readl(ehci
, &ehci
->regs
->command
);
723 /* unrequested/ignored: Frame List Rollover */
724 dbg_status (ehci
, "irq", status
);
727 /* INT, ERR, and IAA interrupt rates can be throttled */
729 /* normal [4.15.1.2] or error [4.15.1.1] completion */
730 if (likely ((status
& (STS_INT
|STS_ERR
)) != 0)) {
731 if (likely ((status
& STS_ERR
) == 0))
732 COUNT (ehci
->stats
.normal
);
734 COUNT (ehci
->stats
.error
);
738 /* complete the unlinking of some qh [4.15.2.3] */
739 if (status
& STS_IAA
) {
740 /* guard against (alleged) silicon errata */
741 if (cmd
& CMD_IAAD
) {
742 ehci_writel(ehci
, cmd
& ~CMD_IAAD
,
743 &ehci
->regs
->command
);
744 ehci_dbg(ehci
, "IAA with IAAD still set?\n");
747 COUNT(ehci
->stats
.reclaim
);
748 end_unlink_async(ehci
);
750 ehci_dbg(ehci
, "IAA with nothing to reclaim?\n");
753 /* remote wakeup [4.3.1] */
754 if (status
& STS_PCD
) {
755 unsigned i
= HCS_N_PORTS (ehci
->hcs_params
);
757 /* kick root hub later */
760 /* resume root hub? */
761 if (!(cmd
& CMD_RUN
))
762 usb_hcd_resume_root_hub(hcd
);
765 int pstatus
= ehci_readl(ehci
,
766 &ehci
->regs
->port_status
[i
]);
768 if (pstatus
& PORT_OWNER
)
770 if (!(test_bit(i
, &ehci
->suspended_ports
) &&
771 ((pstatus
& PORT_RESUME
) ||
772 !(pstatus
& PORT_SUSPEND
)) &&
773 (pstatus
& PORT_PE
) &&
774 ehci
->reset_done
[i
] == 0))
777 /* start 20 msec resume signaling from this port,
778 * and make khubd collect PORT_STAT_C_SUSPEND to
779 * stop that signaling.
781 ehci
->reset_done
[i
] = jiffies
+ msecs_to_jiffies (20);
782 ehci_dbg (ehci
, "port %d remote wakeup\n", i
+ 1);
783 mod_timer(&hcd
->rh_timer
, ehci
->reset_done
[i
]);
787 /* PCI errors [4.15.2.4] */
788 if (unlikely ((status
& STS_FATAL
) != 0)) {
789 ehci_err(ehci
, "fatal error\n");
790 dbg_cmd(ehci
, "fatal", cmd
);
791 dbg_status(ehci
, "fatal", status
);
795 ehci_writel(ehci
, 0, &ehci
->regs
->configured_flag
);
796 /* generic layer kills/unlinks all urbs, then
797 * uses ehci_stop to clean up the rest
804 spin_unlock (&ehci
->lock
);
806 usb_hcd_poll_rh_status(hcd
);
810 /*-------------------------------------------------------------------------*/
813 * non-error returns are a promise to giveback() the urb later
814 * we drop ownership so next owner (or urb unlink) can get it
816 * urb + dev is in hcd.self.controller.urb_list
817 * we're queueing TDs onto software and hardware lists
819 * hcd-specific init for hcpriv hasn't been done yet
821 * NOTE: control, bulk, and interrupt share the same code to append TDs
822 * to a (possibly active) QH, and the same QH scanning code.
824 static int ehci_urb_enqueue (
829 struct ehci_hcd
*ehci
= hcd_to_ehci (hcd
);
830 struct list_head qtd_list
;
832 INIT_LIST_HEAD (&qtd_list
);
834 switch (usb_pipetype (urb
->pipe
)) {
836 /* qh_completions() code doesn't handle all the fault cases
837 * in multi-TD control transfers. Even 1KB is rare anyway.
839 if (urb
->transfer_buffer_length
> (16 * 1024))
842 /* case PIPE_BULK: */
844 if (!qh_urb_transaction (ehci
, urb
, &qtd_list
, mem_flags
))
846 return submit_async(ehci
, urb
, &qtd_list
, mem_flags
);
849 if (!qh_urb_transaction (ehci
, urb
, &qtd_list
, mem_flags
))
851 return intr_submit(ehci
, urb
, &qtd_list
, mem_flags
);
853 case PIPE_ISOCHRONOUS
:
854 if (urb
->dev
->speed
== USB_SPEED_HIGH
)
855 return itd_submit (ehci
, urb
, mem_flags
);
857 return sitd_submit (ehci
, urb
, mem_flags
);
861 static void unlink_async (struct ehci_hcd
*ehci
, struct ehci_qh
*qh
)
864 if (!HC_IS_RUNNING(ehci_to_hcd(ehci
)->state
) && ehci
->reclaim
)
865 end_unlink_async(ehci
);
867 /* if it's not linked then there's nothing to do */
868 if (qh
->qh_state
!= QH_STATE_LINKED
)
871 /* defer till later if busy */
872 else if (ehci
->reclaim
) {
873 struct ehci_qh
*last
;
875 for (last
= ehci
->reclaim
;
877 last
= last
->reclaim
)
879 qh
->qh_state
= QH_STATE_UNLINK_WAIT
;
882 /* start IAA cycle */
884 start_unlink_async (ehci
, qh
);
887 /* remove from hardware lists
888 * completions normally happen asynchronously
891 static int ehci_urb_dequeue(struct usb_hcd
*hcd
, struct urb
*urb
, int status
)
893 struct ehci_hcd
*ehci
= hcd_to_ehci (hcd
);
898 spin_lock_irqsave (&ehci
->lock
, flags
);
899 rc
= usb_hcd_check_unlink_urb(hcd
, urb
, status
);
903 switch (usb_pipetype (urb
->pipe
)) {
904 // case PIPE_CONTROL:
907 qh
= (struct ehci_qh
*) urb
->hcpriv
;
910 switch (qh
->qh_state
) {
911 case QH_STATE_LINKED
:
912 case QH_STATE_COMPLETING
:
913 unlink_async(ehci
, qh
);
915 case QH_STATE_UNLINK
:
916 case QH_STATE_UNLINK_WAIT
:
917 /* already started */
920 /* QH might be waiting for a Clear-TT-Buffer */
921 qh_completions(ehci
, qh
);
927 qh
= (struct ehci_qh
*) urb
->hcpriv
;
930 switch (qh
->qh_state
) {
931 case QH_STATE_LINKED
:
932 intr_deschedule (ehci
, qh
);
935 qh_completions (ehci
, qh
);
938 ehci_dbg (ehci
, "bogus qh %p state %d\n",
943 /* reschedule QH iff another request is queued */
944 if (!list_empty (&qh
->qtd_list
)
945 && HC_IS_RUNNING (hcd
->state
)) {
946 rc
= qh_schedule(ehci
, qh
);
948 /* An error here likely indicates handshake failure
949 * or no space left in the schedule. Neither fault
950 * should happen often ...
952 * FIXME kill the now-dysfunctional queued urbs
956 "can't reschedule qh %p, err %d",
961 case PIPE_ISOCHRONOUS
:
964 // wait till next completion, do it then.
965 // completion irqs can wait up to 1024 msec,
969 spin_unlock_irqrestore (&ehci
->lock
, flags
);
973 /*-------------------------------------------------------------------------*/
975 // bulk qh holds the data toggle
978 ehci_endpoint_disable (struct usb_hcd
*hcd
, struct usb_host_endpoint
*ep
)
980 struct ehci_hcd
*ehci
= hcd_to_ehci (hcd
);
982 struct ehci_qh
*qh
, *tmp
;
984 /* ASSERT: any requests/urbs are being unlinked */
985 /* ASSERT: nobody can be submitting urbs for this any more */
988 spin_lock_irqsave (&ehci
->lock
, flags
);
993 /* endpoints can be iso streams. for now, we don't
994 * accelerate iso completions ... so spin a while.
996 if (qh
->hw
->hw_info1
== 0) {
997 ehci_vdbg (ehci
, "iso delay\n");
1001 if (!HC_IS_RUNNING (hcd
->state
))
1002 qh
->qh_state
= QH_STATE_IDLE
;
1003 switch (qh
->qh_state
) {
1004 case QH_STATE_LINKED
:
1005 for (tmp
= ehci
->async
->qh_next
.qh
;
1007 tmp
= tmp
->qh_next
.qh
)
1009 /* periodic qh self-unlinks on empty */
1012 unlink_async (ehci
, qh
);
1014 case QH_STATE_UNLINK
: /* wait for hw to finish? */
1015 case QH_STATE_UNLINK_WAIT
:
1017 spin_unlock_irqrestore (&ehci
->lock
, flags
);
1018 schedule_timeout_uninterruptible(1);
1020 case QH_STATE_IDLE
: /* fully unlinked */
1021 if (qh
->clearing_tt
)
1023 if (list_empty (&qh
->qtd_list
)) {
1027 /* else FALL THROUGH */
1030 /* caller was supposed to have unlinked any requests;
1031 * that's not our job. just leak this memory.
1033 ehci_err (ehci
, "qh %p (#%02x) state %d%s\n",
1034 qh
, ep
->desc
.bEndpointAddress
, qh
->qh_state
,
1035 list_empty (&qh
->qtd_list
) ? "" : "(has tds)");
1040 spin_unlock_irqrestore (&ehci
->lock
, flags
);
1045 ehci_endpoint_reset(struct usb_hcd
*hcd
, struct usb_host_endpoint
*ep
)
1047 struct ehci_hcd
*ehci
= hcd_to_ehci(hcd
);
1049 int eptype
= usb_endpoint_type(&ep
->desc
);
1050 int epnum
= usb_endpoint_num(&ep
->desc
);
1051 int is_out
= usb_endpoint_dir_out(&ep
->desc
);
1052 unsigned long flags
;
1054 if (eptype
!= USB_ENDPOINT_XFER_BULK
&& eptype
!= USB_ENDPOINT_XFER_INT
)
1057 spin_lock_irqsave(&ehci
->lock
, flags
);
1060 /* For Bulk and Interrupt endpoints we maintain the toggle state
1061 * in the hardware; the toggle bits in udev aren't used at all.
1062 * When an endpoint is reset by usb_clear_halt() we must reset
1063 * the toggle bit in the QH.
1066 usb_settoggle(qh
->dev
, epnum
, is_out
, 0);
1067 if (!list_empty(&qh
->qtd_list
)) {
1068 WARN_ONCE(1, "clear_halt for a busy endpoint\n");
1069 } else if (qh
->qh_state
== QH_STATE_LINKED
) {
1071 /* The toggle value in the QH can't be updated
1072 * while the QH is active. Unlink it now;
1073 * re-linking will call qh_refresh().
1075 if (eptype
== USB_ENDPOINT_XFER_BULK
) {
1076 unlink_async(ehci
, qh
);
1078 intr_deschedule(ehci
, qh
);
1079 (void) qh_schedule(ehci
, qh
);
1083 spin_unlock_irqrestore(&ehci
->lock
, flags
);
1086 static int ehci_get_frame (struct usb_hcd
*hcd
)
1088 struct ehci_hcd
*ehci
= hcd_to_ehci (hcd
);
1089 return (ehci_readl(ehci
, &ehci
->regs
->frame_index
) >> 3) %
1090 ehci
->periodic_size
;
1093 /*-------------------------------------------------------------------------*/
1095 MODULE_DESCRIPTION(DRIVER_DESC
);
1096 MODULE_AUTHOR (DRIVER_AUTHOR
);
1097 MODULE_LICENSE ("GPL");
1100 #include "ehci-pci.c"
1101 #define PCI_DRIVER ehci_pci_driver
1104 #ifdef CONFIG_USB_EHCI_FSL
1105 #include "ehci-fsl.c"
1106 #define PLATFORM_DRIVER ehci_fsl_driver
1109 #ifdef CONFIG_SOC_AU1200
1110 #include "ehci-au1xxx.c"
1111 #define PLATFORM_DRIVER ehci_hcd_au1xxx_driver
1114 #ifdef CONFIG_PPC_PS3
1115 #include "ehci-ps3.c"
1116 #define PS3_SYSTEM_BUS_DRIVER ps3_ehci_driver
1119 #ifdef CONFIG_USB_EHCI_HCD_PPC_OF
1120 #include "ehci-ppc-of.c"
1121 #define OF_PLATFORM_DRIVER ehci_hcd_ppc_of_driver
1124 #ifdef CONFIG_PLAT_ORION
1125 #include "ehci-orion.c"
1126 #define PLATFORM_DRIVER ehci_orion_driver
1129 #ifdef CONFIG_ARCH_IXP4XX
1130 #include "ehci-ixp4xx.c"
1131 #define PLATFORM_DRIVER ixp4xx_ehci_driver
1134 #ifdef CONFIG_USB_W90X900_EHCI
1135 #include "ehci-w90x900.c"
1136 #define PLATFORM_DRIVER ehci_hcd_w90x900_driver
1139 #ifdef CONFIG_ARCH_AT91
1140 #include "ehci-atmel.c"
1141 #define PLATFORM_DRIVER ehci_atmel_driver
1144 #if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER) && \
1145 !defined(PS3_SYSTEM_BUS_DRIVER) && !defined(OF_PLATFORM_DRIVER)
1146 #error "missing bus glue for ehci-hcd"
1149 static int __init
ehci_hcd_init(void)
1156 printk(KERN_INFO
"%s: " DRIVER_DESC
"\n", hcd_name
);
1157 set_bit(USB_EHCI_LOADED
, &usb_hcds_loaded
);
1158 if (test_bit(USB_UHCI_LOADED
, &usb_hcds_loaded
) ||
1159 test_bit(USB_OHCI_LOADED
, &usb_hcds_loaded
))
1160 printk(KERN_WARNING
"Warning! ehci_hcd should always be loaded"
1161 " before uhci_hcd and ohci_hcd, not after\n");
1163 pr_debug("%s: block sizes: qh %Zd qtd %Zd itd %Zd sitd %Zd\n",
1165 sizeof(struct ehci_qh
), sizeof(struct ehci_qtd
),
1166 sizeof(struct ehci_itd
), sizeof(struct ehci_sitd
));
1169 ehci_debug_root
= debugfs_create_dir("ehci", usb_debug_root
);
1170 if (!ehci_debug_root
) {
1176 #ifdef PLATFORM_DRIVER
1177 retval
= platform_driver_register(&PLATFORM_DRIVER
);
1183 retval
= pci_register_driver(&PCI_DRIVER
);
1188 #ifdef PS3_SYSTEM_BUS_DRIVER
1189 retval
= ps3_ehci_driver_register(&PS3_SYSTEM_BUS_DRIVER
);
1194 #ifdef OF_PLATFORM_DRIVER
1195 retval
= of_register_platform_driver(&OF_PLATFORM_DRIVER
);
1201 #ifdef OF_PLATFORM_DRIVER
1202 /* of_unregister_platform_driver(&OF_PLATFORM_DRIVER); */
1205 #ifdef PS3_SYSTEM_BUS_DRIVER
1206 ps3_ehci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER
);
1210 pci_unregister_driver(&PCI_DRIVER
);
1213 #ifdef PLATFORM_DRIVER
1214 platform_driver_unregister(&PLATFORM_DRIVER
);
1218 debugfs_remove(ehci_debug_root
);
1219 ehci_debug_root
= NULL
;
1222 clear_bit(USB_EHCI_LOADED
, &usb_hcds_loaded
);
1225 module_init(ehci_hcd_init
);
1227 static void __exit
ehci_hcd_cleanup(void)
1229 #ifdef OF_PLATFORM_DRIVER
1230 of_unregister_platform_driver(&OF_PLATFORM_DRIVER
);
1232 #ifdef PLATFORM_DRIVER
1233 platform_driver_unregister(&PLATFORM_DRIVER
);
1236 pci_unregister_driver(&PCI_DRIVER
);
1238 #ifdef PS3_SYSTEM_BUS_DRIVER
1239 ps3_ehci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER
);
1242 debugfs_remove(ehci_debug_root
);
1244 clear_bit(USB_EHCI_LOADED
, &usb_hcds_loaded
);
1246 module_exit(ehci_hcd_cleanup
);