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iwlwifi: move rx handlers code to iwl-rx.c
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / wireless / iwlwifi / iwl-agn-lib.c
blob25fccf9a3001374c0cadf899d3a0023eef38b693
1 /******************************************************************************
2 *
3 * GPL LICENSE SUMMARY
4 *
5 * Copyright(c) 2008 - 2010 Intel Corporation. All rights reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of version 2 of the GNU General Public License as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
19 * USA
20 *
21 * The full GNU General Public License is included in this distribution
22 * in the file called LICENSE.GPL.
23 *
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29 #include <linux/etherdevice.h>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/init.h>
33 #include <linux/sched.h>
34
35 #include "iwl-dev.h"
36 #include "iwl-core.h"
37 #include "iwl-io.h"
38 #include "iwl-helpers.h"
39 #include "iwl-agn-hw.h"
40 #include "iwl-agn.h"
41 #include "iwl-sta.h"
42
43 static inline u32 iwlagn_get_scd_ssn(struct iwlagn_tx_resp *tx_resp)
44 {
45 return le32_to_cpup((__le32 *)&tx_resp->status +
46 tx_resp->frame_count) & MAX_SN;
47 }
48
49 static void iwlagn_count_tx_err_status(struct iwl_priv *priv, u16 status)
50 {
51 status &= TX_STATUS_MSK;
52
53 switch (status) {
54 case TX_STATUS_POSTPONE_DELAY:
55 priv->_agn.reply_tx_stats.pp_delay++;
56 break;
57 case TX_STATUS_POSTPONE_FEW_BYTES:
58 priv->_agn.reply_tx_stats.pp_few_bytes++;
59 break;
60 case TX_STATUS_POSTPONE_BT_PRIO:
61 priv->_agn.reply_tx_stats.pp_bt_prio++;
62 break;
63 case TX_STATUS_POSTPONE_QUIET_PERIOD:
64 priv->_agn.reply_tx_stats.pp_quiet_period++;
65 break;
66 case TX_STATUS_POSTPONE_CALC_TTAK:
67 priv->_agn.reply_tx_stats.pp_calc_ttak++;
68 break;
69 case TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY:
70 priv->_agn.reply_tx_stats.int_crossed_retry++;
71 break;
72 case TX_STATUS_FAIL_SHORT_LIMIT:
73 priv->_agn.reply_tx_stats.short_limit++;
74 break;
75 case TX_STATUS_FAIL_LONG_LIMIT:
76 priv->_agn.reply_tx_stats.long_limit++;
77 break;
78 case TX_STATUS_FAIL_FIFO_UNDERRUN:
79 priv->_agn.reply_tx_stats.fifo_underrun++;
80 break;
81 case TX_STATUS_FAIL_DRAIN_FLOW:
82 priv->_agn.reply_tx_stats.drain_flow++;
83 break;
84 case TX_STATUS_FAIL_RFKILL_FLUSH:
85 priv->_agn.reply_tx_stats.rfkill_flush++;
86 break;
87 case TX_STATUS_FAIL_LIFE_EXPIRE:
88 priv->_agn.reply_tx_stats.life_expire++;
89 break;
90 case TX_STATUS_FAIL_DEST_PS:
91 priv->_agn.reply_tx_stats.dest_ps++;
92 break;
93 case TX_STATUS_FAIL_HOST_ABORTED:
94 priv->_agn.reply_tx_stats.host_abort++;
95 break;
96 case TX_STATUS_FAIL_BT_RETRY:
97 priv->_agn.reply_tx_stats.bt_retry++;
98 break;
99 case TX_STATUS_FAIL_STA_INVALID:
100 priv->_agn.reply_tx_stats.sta_invalid++;
101 break;
102 case TX_STATUS_FAIL_FRAG_DROPPED:
103 priv->_agn.reply_tx_stats.frag_drop++;
104 break;
105 case TX_STATUS_FAIL_TID_DISABLE:
106 priv->_agn.reply_tx_stats.tid_disable++;
107 break;
108 case TX_STATUS_FAIL_FIFO_FLUSHED:
109 priv->_agn.reply_tx_stats.fifo_flush++;
110 break;
111 case TX_STATUS_FAIL_INSUFFICIENT_CF_POLL:
112 priv->_agn.reply_tx_stats.insuff_cf_poll++;
113 break;
114 case TX_STATUS_FAIL_PASSIVE_NO_RX:
115 priv->_agn.reply_tx_stats.fail_hw_drop++;
116 break;
117 case TX_STATUS_FAIL_NO_BEACON_ON_RADAR:
118 priv->_agn.reply_tx_stats.sta_color_mismatch++;
119 break;
120 default:
121 priv->_agn.reply_tx_stats.unknown++;
122 break;
123 }
124 }
125
126 static void iwlagn_count_agg_tx_err_status(struct iwl_priv *priv, u16 status)
127 {
128 status &= AGG_TX_STATUS_MSK;
129
130 switch (status) {
131 case AGG_TX_STATE_UNDERRUN_MSK:
132 priv->_agn.reply_agg_tx_stats.underrun++;
133 break;
134 case AGG_TX_STATE_BT_PRIO_MSK:
135 priv->_agn.reply_agg_tx_stats.bt_prio++;
136 break;
137 case AGG_TX_STATE_FEW_BYTES_MSK:
138 priv->_agn.reply_agg_tx_stats.few_bytes++;
139 break;
140 case AGG_TX_STATE_ABORT_MSK:
141 priv->_agn.reply_agg_tx_stats.abort++;
142 break;
143 case AGG_TX_STATE_LAST_SENT_TTL_MSK:
144 priv->_agn.reply_agg_tx_stats.last_sent_ttl++;
145 break;
146 case AGG_TX_STATE_LAST_SENT_TRY_CNT_MSK:
147 priv->_agn.reply_agg_tx_stats.last_sent_try++;
148 break;
149 case AGG_TX_STATE_LAST_SENT_BT_KILL_MSK:
150 priv->_agn.reply_agg_tx_stats.last_sent_bt_kill++;
151 break;
152 case AGG_TX_STATE_SCD_QUERY_MSK:
153 priv->_agn.reply_agg_tx_stats.scd_query++;
154 break;
155 case AGG_TX_STATE_TEST_BAD_CRC32_MSK:
156 priv->_agn.reply_agg_tx_stats.bad_crc32++;
157 break;
158 case AGG_TX_STATE_RESPONSE_MSK:
159 priv->_agn.reply_agg_tx_stats.response++;
160 break;
161 case AGG_TX_STATE_DUMP_TX_MSK:
162 priv->_agn.reply_agg_tx_stats.dump_tx++;
163 break;
164 case AGG_TX_STATE_DELAY_TX_MSK:
165 priv->_agn.reply_agg_tx_stats.delay_tx++;
166 break;
167 default:
168 priv->_agn.reply_agg_tx_stats.unknown++;
169 break;
170 }
171 }
172
173 static void iwlagn_set_tx_status(struct iwl_priv *priv,
174 struct ieee80211_tx_info *info,
175 struct iwlagn_tx_resp *tx_resp,
176 int txq_id, bool is_agg)
177 {
178 u16 status = le16_to_cpu(tx_resp->status.status);
179
180 info->status.rates[0].count = tx_resp->failure_frame + 1;
181 if (is_agg)
182 info->flags &= ~IEEE80211_TX_CTL_AMPDU;
183 info->flags |= iwl_tx_status_to_mac80211(status);
184 iwlagn_hwrate_to_tx_control(priv, le32_to_cpu(tx_resp->rate_n_flags),
185 info);
186 if (!iwl_is_tx_success(status))
187 iwlagn_count_tx_err_status(priv, status);
188
189 IWL_DEBUG_TX_REPLY(priv, "TXQ %d status %s (0x%08x) rate_n_flags "
190 "0x%x retries %d\n",
191 txq_id,
192 iwl_get_tx_fail_reason(status), status,
193 le32_to_cpu(tx_resp->rate_n_flags),
194 tx_resp->failure_frame);
195 }
196
197 #ifdef CONFIG_IWLWIFI_DEBUG
198 #define AGG_TX_STATE_FAIL(x) case AGG_TX_STATE_ ## x: return #x
199
200 const char *iwl_get_agg_tx_fail_reason(u16 status)
201 {
202 status &= AGG_TX_STATUS_MSK;
203 switch (status) {
204 case AGG_TX_STATE_TRANSMITTED:
205 return "SUCCESS";
206 AGG_TX_STATE_FAIL(UNDERRUN_MSK);
207 AGG_TX_STATE_FAIL(BT_PRIO_MSK);
208 AGG_TX_STATE_FAIL(FEW_BYTES_MSK);
209 AGG_TX_STATE_FAIL(ABORT_MSK);
210 AGG_TX_STATE_FAIL(LAST_SENT_TTL_MSK);
211 AGG_TX_STATE_FAIL(LAST_SENT_TRY_CNT_MSK);
212 AGG_TX_STATE_FAIL(LAST_SENT_BT_KILL_MSK);
213 AGG_TX_STATE_FAIL(SCD_QUERY_MSK);
214 AGG_TX_STATE_FAIL(TEST_BAD_CRC32_MSK);
215 AGG_TX_STATE_FAIL(RESPONSE_MSK);
216 AGG_TX_STATE_FAIL(DUMP_TX_MSK);
217 AGG_TX_STATE_FAIL(DELAY_TX_MSK);
218 }
219
220 return "UNKNOWN";
221 }
222 #endif /* CONFIG_IWLWIFI_DEBUG */
223
224 static int iwlagn_tx_status_reply_tx(struct iwl_priv *priv,
225 struct iwl_ht_agg *agg,
226 struct iwlagn_tx_resp *tx_resp,
227 int txq_id, u16 start_idx)
228 {
229 u16 status;
230 struct agg_tx_status *frame_status = &tx_resp->status;
231 struct ieee80211_hdr *hdr = NULL;
232 int i, sh, idx;
233 u16 seq;
234
235 if (agg->wait_for_ba)
236 IWL_DEBUG_TX_REPLY(priv, "got tx response w/o block-ack\n");
237
238 agg->frame_count = tx_resp->frame_count;
239 agg->start_idx = start_idx;
240 agg->rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
241 agg->bitmap = 0;
242
243 /* # frames attempted by Tx command */
244 if (agg->frame_count == 1) {
245 /* Only one frame was attempted; no block-ack will arrive */
246 idx = start_idx;
247
248 IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, StartIdx=%d idx=%d\n",
249 agg->frame_count, agg->start_idx, idx);
250 iwlagn_set_tx_status(priv,
251 IEEE80211_SKB_CB(
252 priv->txq[txq_id].txb[idx].skb),
253 tx_resp, txq_id, true);
254 agg->wait_for_ba = 0;
255 } else {
256 /* Two or more frames were attempted; expect block-ack */
257 u64 bitmap = 0;
258
259 /*
260 * Start is the lowest frame sent. It may not be the first
261 * frame in the batch; we figure this out dynamically during
262 * the following loop.
263 */
264 int start = agg->start_idx;
265
266 /* Construct bit-map of pending frames within Tx window */
267 for (i = 0; i < agg->frame_count; i++) {
268 u16 sc;
269 status = le16_to_cpu(frame_status[i].status);
270 seq = le16_to_cpu(frame_status[i].sequence);
271 idx = SEQ_TO_INDEX(seq);
272 txq_id = SEQ_TO_QUEUE(seq);
273
274 if (status & AGG_TX_STATUS_MSK)
275 iwlagn_count_agg_tx_err_status(priv, status);
276
277 if (status & (AGG_TX_STATE_FEW_BYTES_MSK |
278 AGG_TX_STATE_ABORT_MSK))
279 continue;
280
281 IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, txq_id=%d idx=%d\n",
282 agg->frame_count, txq_id, idx);
283 IWL_DEBUG_TX_REPLY(priv, "status %s (0x%08x), "
284 "try-count (0x%08x)\n",
285 iwl_get_agg_tx_fail_reason(status),
286 status & AGG_TX_STATUS_MSK,
287 status & AGG_TX_TRY_MSK);
288
289 hdr = iwl_tx_queue_get_hdr(priv, txq_id, idx);
290 if (!hdr) {
291 IWL_ERR(priv,
292 "BUG_ON idx doesn't point to valid skb"
293 " idx=%d, txq_id=%d\n", idx, txq_id);
294 return -1;
295 }
296
297 sc = le16_to_cpu(hdr->seq_ctrl);
298 if (idx != (SEQ_TO_SN(sc) & 0xff)) {
299 IWL_ERR(priv,
300 "BUG_ON idx doesn't match seq control"
301 " idx=%d, seq_idx=%d, seq=%d\n",
302 idx, SEQ_TO_SN(sc),
303 hdr->seq_ctrl);
304 return -1;
305 }
306
307 IWL_DEBUG_TX_REPLY(priv, "AGG Frame i=%d idx %d seq=%d\n",
308 i, idx, SEQ_TO_SN(sc));
309
310 /*
311 * sh -> how many frames ahead of the starting frame is
312 * the current one?
313 *
314 * Note that all frames sent in the batch must be in a
315 * 64-frame window, so this number should be in [0,63].
316 * If outside of this window, then we've found a new
317 * "first" frame in the batch and need to change start.
318 */
319 sh = idx - start;
320
321 /*
322 * If >= 64, out of window. start must be at the front
323 * of the circular buffer, idx must be near the end of
324 * the buffer, and idx is the new "first" frame. Shift
325 * the indices around.
326 */
327 if (sh >= 64) {
328 /* Shift bitmap by start - idx, wrapped */
329 sh = 0x100 - idx + start;
330 bitmap = bitmap << sh;
331 /* Now idx is the new start so sh = 0 */
332 sh = 0;
333 start = idx;
334 /*
335 * If <= -64 then wraps the 256-pkt circular buffer
336 * (e.g., start = 255 and idx = 0, sh should be 1)
337 */
338 } else if (sh <= -64) {
339 sh = 0x100 - start + idx;
340 /*
341 * If < 0 but > -64, out of window. idx is before start
342 * but not wrapped. Shift the indices around.
343 */
344 } else if (sh < 0) {
345 /* Shift by how far start is ahead of idx */
346 sh = start - idx;
347 bitmap = bitmap << sh;
348 /* Now idx is the new start so sh = 0 */
349 start = idx;
350 sh = 0;
351 }
352 /* Sequence number start + sh was sent in this batch */
353 bitmap |= 1ULL << sh;
354 IWL_DEBUG_TX_REPLY(priv, "start=%d bitmap=0x%llx\n",
355 start, (unsigned long long)bitmap);
356 }
357
358 /*
359 * Store the bitmap and possibly the new start, if we wrapped
360 * the buffer above
361 */
362 agg->bitmap = bitmap;
363 agg->start_idx = start;
364 IWL_DEBUG_TX_REPLY(priv, "Frames %d start_idx=%d bitmap=0x%llx\n",
365 agg->frame_count, agg->start_idx,
366 (unsigned long long)agg->bitmap);
367
368 if (bitmap)
369 agg->wait_for_ba = 1;
370 }
371 return 0;
372 }
373
374 void iwl_check_abort_status(struct iwl_priv *priv,
375 u8 frame_count, u32 status)
376 {
377 if (frame_count == 1 && status == TX_STATUS_FAIL_RFKILL_FLUSH) {
378 IWL_ERR(priv, "Tx flush command to flush out all frames\n");
379 if (!test_bit(STATUS_EXIT_PENDING, &priv->status))
380 queue_work(priv->workqueue, &priv->tx_flush);
381 }
382 }
383
384 static void iwlagn_rx_reply_tx(struct iwl_priv *priv,
385 struct iwl_rx_mem_buffer *rxb)
386 {
387 struct iwl_rx_packet *pkt = rxb_addr(rxb);
388 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
389 int txq_id = SEQ_TO_QUEUE(sequence);
390 int index = SEQ_TO_INDEX(sequence);
391 struct iwl_tx_queue *txq = &priv->txq[txq_id];
392 struct ieee80211_tx_info *info;
393 struct iwlagn_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
394 u32 status = le16_to_cpu(tx_resp->status.status);
395 int tid;
396 int sta_id;
397 int freed;
398 unsigned long flags;
399
400 if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
401 IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d "
402 "is out of range [0-%d] %d %d\n", txq_id,
403 index, txq->q.n_bd, txq->q.write_ptr,
404 txq->q.read_ptr);
405 return;
406 }
407
408 txq->time_stamp = jiffies;
409 info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb);
410 memset(&info->status, 0, sizeof(info->status));
411
412 tid = (tx_resp->ra_tid & IWLAGN_TX_RES_TID_MSK) >>
413 IWLAGN_TX_RES_TID_POS;
414 sta_id = (tx_resp->ra_tid & IWLAGN_TX_RES_RA_MSK) >>
415 IWLAGN_TX_RES_RA_POS;
416
417 spin_lock_irqsave(&priv->sta_lock, flags);
418 if (txq->sched_retry) {
419 const u32 scd_ssn = iwlagn_get_scd_ssn(tx_resp);
420 struct iwl_ht_agg *agg;
421
422 agg = &priv->stations[sta_id].tid[tid].agg;
423 /*
424 * If the BT kill count is non-zero, we'll get this
425 * notification again.
426 */
427 if (tx_resp->bt_kill_count && tx_resp->frame_count == 1 &&
428 priv->cfg->bt_params &&
429 priv->cfg->bt_params->advanced_bt_coexist) {
430 IWL_WARN(priv, "receive reply tx with bt_kill\n");
431 }
432 iwlagn_tx_status_reply_tx(priv, agg, tx_resp, txq_id, index);
433
434 /* check if BAR is needed */
435 if ((tx_resp->frame_count == 1) && !iwl_is_tx_success(status))
436 info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
437
438 if (txq->q.read_ptr != (scd_ssn & 0xff)) {
439 index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd);
440 IWL_DEBUG_TX_REPLY(priv, "Retry scheduler reclaim "
441 "scd_ssn=%d idx=%d txq=%d swq=%d\n",
442 scd_ssn , index, txq_id, txq->swq_id);
443
444 freed = iwlagn_tx_queue_reclaim(priv, txq_id, index);
445 iwl_free_tfds_in_queue(priv, sta_id, tid, freed);
446
447 if (priv->mac80211_registered &&
448 (iwl_queue_space(&txq->q) > txq->q.low_mark) &&
449 (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA))
450 iwl_wake_queue(priv, txq);
451 }
452 } else {
453 iwlagn_set_tx_status(priv, info, tx_resp, txq_id, false);
454 freed = iwlagn_tx_queue_reclaim(priv, txq_id, index);
455 iwl_free_tfds_in_queue(priv, sta_id, tid, freed);
456
457 if (priv->mac80211_registered &&
458 (iwl_queue_space(&txq->q) > txq->q.low_mark))
459 iwl_wake_queue(priv, txq);
460 }
461
462 iwlagn_txq_check_empty(priv, sta_id, tid, txq_id);
463
464 iwl_check_abort_status(priv, tx_resp->frame_count, status);
465 spin_unlock_irqrestore(&priv->sta_lock, flags);
466 }
467
468 void iwlagn_rx_handler_setup(struct iwl_priv *priv)
469 {
470 /* init calibration handlers */
471 priv->rx_handlers[CALIBRATION_RES_NOTIFICATION] =
472 iwlagn_rx_calib_result;
473 priv->rx_handlers[CALIBRATION_COMPLETE_NOTIFICATION] =
474 iwlagn_rx_calib_complete;
475 priv->rx_handlers[REPLY_TX] = iwlagn_rx_reply_tx;
476
477 /* set up notification wait support */
478 spin_lock_init(&priv->_agn.notif_wait_lock);
479 INIT_LIST_HEAD(&priv->_agn.notif_waits);
480 init_waitqueue_head(&priv->_agn.notif_waitq);
481 }
482
483 void iwlagn_setup_deferred_work(struct iwl_priv *priv)
484 {
485 /* in agn, the tx power calibration is done in uCode */
486 priv->disable_tx_power_cal = 1;
487 }
488
489 int iwlagn_hw_valid_rtc_data_addr(u32 addr)
490 {
491 return (addr >= IWLAGN_RTC_DATA_LOWER_BOUND) &&
492 (addr < IWLAGN_RTC_DATA_UPPER_BOUND);
493 }
494
495 int iwlagn_send_tx_power(struct iwl_priv *priv)
496 {
497 struct iwlagn_tx_power_dbm_cmd tx_power_cmd;
498 u8 tx_ant_cfg_cmd;
499
500 if (WARN_ONCE(test_bit(STATUS_SCAN_HW, &priv->status),
501 "TX Power requested while scanning!\n"))
502 return -EAGAIN;
503
504 /* half dBm need to multiply */
505 tx_power_cmd.global_lmt = (s8)(2 * priv->tx_power_user_lmt);
506
507 if (priv->tx_power_lmt_in_half_dbm &&
508 priv->tx_power_lmt_in_half_dbm < tx_power_cmd.global_lmt) {
509 /*
510 * For the newer devices which using enhanced/extend tx power
511 * table in EEPROM, the format is in half dBm. driver need to
512 * convert to dBm format before report to mac80211.
513 * By doing so, there is a possibility of 1/2 dBm resolution
514 * lost. driver will perform "round-up" operation before
515 * reporting, but it will cause 1/2 dBm tx power over the
516 * regulatory limit. Perform the checking here, if the
517 * "tx_power_user_lmt" is higher than EEPROM value (in
518 * half-dBm format), lower the tx power based on EEPROM
519 */
520 tx_power_cmd.global_lmt = priv->tx_power_lmt_in_half_dbm;
521 }
522 tx_power_cmd.flags = IWLAGN_TX_POWER_NO_CLOSED;
523 tx_power_cmd.srv_chan_lmt = IWLAGN_TX_POWER_AUTO;
524
525 if (IWL_UCODE_API(priv->ucode_ver) == 1)
526 tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD_V1;
527 else
528 tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD;
529
530 return iwl_send_cmd_pdu(priv, tx_ant_cfg_cmd, sizeof(tx_power_cmd),
531 &tx_power_cmd);
532 }
533
534 void iwlagn_temperature(struct iwl_priv *priv)
535 {
536 /* store temperature from correct statistics (in Celsius) */
537 priv->temperature = le32_to_cpu((iwl_bt_statistics(priv)) ?
538 priv->_agn.statistics_bt.general.common.temperature :
539 priv->_agn.statistics.general.common.temperature);
540 iwl_tt_handler(priv);
541 }
542
543 u16 iwlagn_eeprom_calib_version(struct iwl_priv *priv)
544 {
545 struct iwl_eeprom_calib_hdr {
546 u8 version;
547 u8 pa_type;
548 u16 voltage;
549 } *hdr;
550
551 hdr = (struct iwl_eeprom_calib_hdr *)iwl_eeprom_query_addr(priv,
552 EEPROM_CALIB_ALL);
553 return hdr->version;
554
555 }
556
557 /*
558 * EEPROM
559 */
560 static u32 eeprom_indirect_address(const struct iwl_priv *priv, u32 address)
561 {
562 u16 offset = 0;
563
564 if ((address & INDIRECT_ADDRESS) == 0)
565 return address;
566
567 switch (address & INDIRECT_TYPE_MSK) {
568 case INDIRECT_HOST:
569 offset = iwl_eeprom_query16(priv, EEPROM_LINK_HOST);
570 break;
571 case INDIRECT_GENERAL:
572 offset = iwl_eeprom_query16(priv, EEPROM_LINK_GENERAL);
573 break;
574 case INDIRECT_REGULATORY:
575 offset = iwl_eeprom_query16(priv, EEPROM_LINK_REGULATORY);
576 break;
577 case INDIRECT_TXP_LIMIT:
578 offset = iwl_eeprom_query16(priv, EEPROM_LINK_TXP_LIMIT);
579 break;
580 case INDIRECT_TXP_LIMIT_SIZE:
581 offset = iwl_eeprom_query16(priv, EEPROM_LINK_TXP_LIMIT_SIZE);
582 break;
583 case INDIRECT_CALIBRATION:
584 offset = iwl_eeprom_query16(priv, EEPROM_LINK_CALIBRATION);
585 break;
586 case INDIRECT_PROCESS_ADJST:
587 offset = iwl_eeprom_query16(priv, EEPROM_LINK_PROCESS_ADJST);
588 break;
589 case INDIRECT_OTHERS:
590 offset = iwl_eeprom_query16(priv, EEPROM_LINK_OTHERS);
591 break;
592 default:
593 IWL_ERR(priv, "illegal indirect type: 0x%X\n",
594 address & INDIRECT_TYPE_MSK);
595 break;
596 }
597
598 /* translate the offset from words to byte */
599 return (address & ADDRESS_MSK) + (offset << 1);
600 }
601
602 const u8 *iwlagn_eeprom_query_addr(const struct iwl_priv *priv,
603 size_t offset)
604 {
605 u32 address = eeprom_indirect_address(priv, offset);
606 BUG_ON(address >= priv->cfg->base_params->eeprom_size);
607 return &priv->eeprom[address];
608 }
609
610 struct iwl_mod_params iwlagn_mod_params = {
611 .amsdu_size_8K = 1,
612 .restart_fw = 1,
613 .plcp_check = true,
614 /* the rest are 0 by default */
615 };
616
617 void iwlagn_rx_queue_reset(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
618 {
619 unsigned long flags;
620 int i;
621 spin_lock_irqsave(&rxq->lock, flags);
622 INIT_LIST_HEAD(&rxq->rx_free);
623 INIT_LIST_HEAD(&rxq->rx_used);
624 /* Fill the rx_used queue with _all_ of the Rx buffers */
625 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
626 /* In the reset function, these buffers may have been allocated
627 * to an SKB, so we need to unmap and free potential storage */
628 if (rxq->pool[i].page != NULL) {
629 pci_unmap_page(priv->pci_dev, rxq->pool[i].page_dma,
630 PAGE_SIZE << priv->hw_params.rx_page_order,
631 PCI_DMA_FROMDEVICE);
632 __iwl_free_pages(priv, rxq->pool[i].page);
633 rxq->pool[i].page = NULL;
634 }
635 list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
636 }
637
638 for (i = 0; i < RX_QUEUE_SIZE; i++)
639 rxq->queue[i] = NULL;
640
641 /* Set us so that we have processed and used all buffers, but have
642 * not restocked the Rx queue with fresh buffers */
643 rxq->read = rxq->write = 0;
644 rxq->write_actual = 0;
645 rxq->free_count = 0;
646 spin_unlock_irqrestore(&rxq->lock, flags);
647 }
648
649 int iwlagn_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
650 {
651 u32 rb_size;
652 const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
653 u32 rb_timeout = 0; /* FIXME: RX_RB_TIMEOUT for all devices? */
654
655 if (!priv->cfg->base_params->use_isr_legacy)
656 rb_timeout = RX_RB_TIMEOUT;
657
658 if (priv->cfg->mod_params->amsdu_size_8K)
659 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
660 else
661 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
662
663 /* Stop Rx DMA */
664 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
665
666 /* Reset driver's Rx queue write index */
667 iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
668
669 /* Tell device where to find RBD circular buffer in DRAM */
670 iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
671 (u32)(rxq->bd_dma >> 8));
672
673 /* Tell device where in DRAM to update its Rx status */
674 iwl_write_direct32(priv, FH_RSCSR_CHNL0_STTS_WPTR_REG,
675 rxq->rb_stts_dma >> 4);
676
677 /* Enable Rx DMA
678 * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
679 * the credit mechanism in 5000 HW RX FIFO
680 * Direct rx interrupts to hosts
681 * Rx buffer size 4 or 8k
682 * RB timeout 0x10
683 * 256 RBDs
684 */
685 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG,
686 FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
687 FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |
688 FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
689 FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK |
690 rb_size|
691 (rb_timeout << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)|
692 (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
693
694 /* Set interrupt coalescing timer to default (2048 usecs) */
695 iwl_write8(priv, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
696
697 return 0;
698 }
699
700 static void iwlagn_set_pwr_vmain(struct iwl_priv *priv)
701 {
702 /*
703 * (for documentation purposes)
704 * to set power to V_AUX, do:
705
706 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
707 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
708 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
709 ~APMG_PS_CTRL_MSK_PWR_SRC);
710 */
711
712 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
713 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
714 ~APMG_PS_CTRL_MSK_PWR_SRC);
715 }
716
717 int iwlagn_hw_nic_init(struct iwl_priv *priv)
718 {
719 unsigned long flags;
720 struct iwl_rx_queue *rxq = &priv->rxq;
721 int ret;
722
723 /* nic_init */
724 spin_lock_irqsave(&priv->lock, flags);
725 priv->cfg->ops->lib->apm_ops.init(priv);
726
727 /* Set interrupt coalescing calibration timer to default (512 usecs) */
728 iwl_write8(priv, CSR_INT_COALESCING, IWL_HOST_INT_CALIB_TIMEOUT_DEF);
729
730 spin_unlock_irqrestore(&priv->lock, flags);
731
732 iwlagn_set_pwr_vmain(priv);
733
734 priv->cfg->ops->lib->apm_ops.config(priv);
735
736 /* Allocate the RX queue, or reset if it is already allocated */
737 if (!rxq->bd) {
738 ret = iwl_rx_queue_alloc(priv);
739 if (ret) {
740 IWL_ERR(priv, "Unable to initialize Rx queue\n");
741 return -ENOMEM;
742 }
743 } else
744 iwlagn_rx_queue_reset(priv, rxq);
745
746 iwlagn_rx_replenish(priv);
747
748 iwlagn_rx_init(priv, rxq);
749
750 spin_lock_irqsave(&priv->lock, flags);
751
752 rxq->need_update = 1;
753 iwl_rx_queue_update_write_ptr(priv, rxq);
754
755 spin_unlock_irqrestore(&priv->lock, flags);
756
757 /* Allocate or reset and init all Tx and Command queues */
758 if (!priv->txq) {
759 ret = iwlagn_txq_ctx_alloc(priv);
760 if (ret)
761 return ret;
762 } else
763 iwlagn_txq_ctx_reset(priv);
764
765 if (priv->cfg->base_params->shadow_reg_enable) {
766 /* enable shadow regs in HW */
767 iwl_set_bit(priv, CSR_MAC_SHADOW_REG_CTRL,
768 0x800FFFFF);
769 }
770
771 set_bit(STATUS_INIT, &priv->status);
772
773 return 0;
774 }
775
776 /**
777 * iwlagn_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
778 */
779 static inline __le32 iwlagn_dma_addr2rbd_ptr(struct iwl_priv *priv,
780 dma_addr_t dma_addr)
781 {
782 return cpu_to_le32((u32)(dma_addr >> 8));
783 }
784
785 /**
786 * iwlagn_rx_queue_restock - refill RX queue from pre-allocated pool
787 *
788 * If there are slots in the RX queue that need to be restocked,
789 * and we have free pre-allocated buffers, fill the ranks as much
790 * as we can, pulling from rx_free.
791 *
792 * This moves the 'write' index forward to catch up with 'processed', and
793 * also updates the memory address in the firmware to reference the new
794 * target buffer.
795 */
796 void iwlagn_rx_queue_restock(struct iwl_priv *priv)
797 {
798 struct iwl_rx_queue *rxq = &priv->rxq;
799 struct list_head *element;
800 struct iwl_rx_mem_buffer *rxb;
801 unsigned long flags;
802
803 spin_lock_irqsave(&rxq->lock, flags);
804 while ((iwl_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
805 /* The overwritten rxb must be a used one */
806 rxb = rxq->queue[rxq->write];
807 BUG_ON(rxb && rxb->page);
808
809 /* Get next free Rx buffer, remove from free list */
810 element = rxq->rx_free.next;
811 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
812 list_del(element);
813
814 /* Point to Rx buffer via next RBD in circular buffer */
815 rxq->bd[rxq->write] = iwlagn_dma_addr2rbd_ptr(priv,
816 rxb->page_dma);
817 rxq->queue[rxq->write] = rxb;
818 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
819 rxq->free_count--;
820 }
821 spin_unlock_irqrestore(&rxq->lock, flags);
822 /* If the pre-allocated buffer pool is dropping low, schedule to
823 * refill it */
824 if (rxq->free_count <= RX_LOW_WATERMARK)
825 queue_work(priv->workqueue, &priv->rx_replenish);
826
827
828 /* If we've added more space for the firmware to place data, tell it.
829 * Increment device's write pointer in multiples of 8. */
830 if (rxq->write_actual != (rxq->write & ~0x7)) {
831 spin_lock_irqsave(&rxq->lock, flags);
832 rxq->need_update = 1;
833 spin_unlock_irqrestore(&rxq->lock, flags);
834 iwl_rx_queue_update_write_ptr(priv, rxq);
835 }
836 }
837
838 /**
839 * iwlagn_rx_replenish - Move all used packet from rx_used to rx_free
840 *
841 * When moving to rx_free an SKB is allocated for the slot.
842 *
843 * Also restock the Rx queue via iwl_rx_queue_restock.
844 * This is called as a scheduled work item (except for during initialization)
845 */
846 void iwlagn_rx_allocate(struct iwl_priv *priv, gfp_t priority)
847 {
848 struct iwl_rx_queue *rxq = &priv->rxq;
849 struct list_head *element;
850 struct iwl_rx_mem_buffer *rxb;
851 struct page *page;
852 unsigned long flags;
853 gfp_t gfp_mask = priority;
854
855 while (1) {
856 spin_lock_irqsave(&rxq->lock, flags);
857 if (list_empty(&rxq->rx_used)) {
858 spin_unlock_irqrestore(&rxq->lock, flags);
859 return;
860 }
861 spin_unlock_irqrestore(&rxq->lock, flags);
862
863 if (rxq->free_count > RX_LOW_WATERMARK)
864 gfp_mask |= __GFP_NOWARN;
865
866 if (priv->hw_params.rx_page_order > 0)
867 gfp_mask |= __GFP_COMP;
868
869 /* Alloc a new receive buffer */
870 page = alloc_pages(gfp_mask, priv->hw_params.rx_page_order);
871 if (!page) {
872 if (net_ratelimit())
873 IWL_DEBUG_INFO(priv, "alloc_pages failed, "
874 "order: %d\n",
875 priv->hw_params.rx_page_order);
876
877 if ((rxq->free_count <= RX_LOW_WATERMARK) &&
878 net_ratelimit())
879 IWL_CRIT(priv, "Failed to alloc_pages with %s. Only %u free buffers remaining.\n",
880 priority == GFP_ATOMIC ? "GFP_ATOMIC" : "GFP_KERNEL",
881 rxq->free_count);
882 /* We don't reschedule replenish work here -- we will
883 * call the restock method and if it still needs
884 * more buffers it will schedule replenish */
885 return;
886 }
887
888 spin_lock_irqsave(&rxq->lock, flags);
889
890 if (list_empty(&rxq->rx_used)) {
891 spin_unlock_irqrestore(&rxq->lock, flags);
892 __free_pages(page, priv->hw_params.rx_page_order);
893 return;
894 }
895 element = rxq->rx_used.next;
896 rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
897 list_del(element);
898
899 spin_unlock_irqrestore(&rxq->lock, flags);
900
901 BUG_ON(rxb->page);
902 rxb->page = page;
903 /* Get physical address of the RB */
904 rxb->page_dma = pci_map_page(priv->pci_dev, page, 0,
905 PAGE_SIZE << priv->hw_params.rx_page_order,
906 PCI_DMA_FROMDEVICE);
907 /* dma address must be no more than 36 bits */
908 BUG_ON(rxb->page_dma & ~DMA_BIT_MASK(36));
909 /* and also 256 byte aligned! */
910 BUG_ON(rxb->page_dma & DMA_BIT_MASK(8));
911
912 spin_lock_irqsave(&rxq->lock, flags);
913
914 list_add_tail(&rxb->list, &rxq->rx_free);
915 rxq->free_count++;
916 priv->alloc_rxb_page++;
917
918 spin_unlock_irqrestore(&rxq->lock, flags);
919 }
920 }
921
922 void iwlagn_rx_replenish(struct iwl_priv *priv)
923 {
924 unsigned long flags;
925
926 iwlagn_rx_allocate(priv, GFP_KERNEL);
927
928 spin_lock_irqsave(&priv->lock, flags);
929 iwlagn_rx_queue_restock(priv);
930 spin_unlock_irqrestore(&priv->lock, flags);
931 }
932
933 void iwlagn_rx_replenish_now(struct iwl_priv *priv)
934 {
935 iwlagn_rx_allocate(priv, GFP_ATOMIC);
936
937 iwlagn_rx_queue_restock(priv);
938 }
939
940 /* Assumes that the skb field of the buffers in 'pool' is kept accurate.
941 * If an SKB has been detached, the POOL needs to have its SKB set to NULL
942 * This free routine walks the list of POOL entries and if SKB is set to
943 * non NULL it is unmapped and freed
944 */
945 void iwlagn_rx_queue_free(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
946 {
947 int i;
948 for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
949 if (rxq->pool[i].page != NULL) {
950 pci_unmap_page(priv->pci_dev, rxq->pool[i].page_dma,
951 PAGE_SIZE << priv->hw_params.rx_page_order,
952 PCI_DMA_FROMDEVICE);
953 __iwl_free_pages(priv, rxq->pool[i].page);
954 rxq->pool[i].page = NULL;
955 }
956 }
957
958 dma_free_coherent(&priv->pci_dev->dev, 4 * RX_QUEUE_SIZE, rxq->bd,
959 rxq->bd_dma);
960 dma_free_coherent(&priv->pci_dev->dev, sizeof(struct iwl_rb_status),
961 rxq->rb_stts, rxq->rb_stts_dma);
962 rxq->bd = NULL;
963 rxq->rb_stts = NULL;
964 }
965
966 int iwlagn_rxq_stop(struct iwl_priv *priv)
967 {
968
969 /* stop Rx DMA */
970 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
971 iwl_poll_direct_bit(priv, FH_MEM_RSSR_RX_STATUS_REG,
972 FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
973
974 return 0;
975 }
976
977 int iwlagn_hwrate_to_mac80211_idx(u32 rate_n_flags, enum ieee80211_band band)
978 {
979 int idx = 0;
980 int band_offset = 0;
981
982 /* HT rate format: mac80211 wants an MCS number, which is just LSB */
983 if (rate_n_flags & RATE_MCS_HT_MSK) {
984 idx = (rate_n_flags & 0xff);
985 return idx;
986 /* Legacy rate format, search for match in table */
987 } else {
988 if (band == IEEE80211_BAND_5GHZ)
989 band_offset = IWL_FIRST_OFDM_RATE;
990 for (idx = band_offset; idx < IWL_RATE_COUNT_LEGACY; idx++)
991 if (iwl_rates[idx].plcp == (rate_n_flags & 0xFF))
992 return idx - band_offset;
993 }
994
995 return -1;
996 }
997
998 static int iwl_get_single_channel_for_scan(struct iwl_priv *priv,
999 struct ieee80211_vif *vif,
1000 enum ieee80211_band band,
1001 struct iwl_scan_channel *scan_ch)
1002 {
1003 const struct ieee80211_supported_band *sband;
1004 u16 passive_dwell = 0;
1005 u16 active_dwell = 0;
1006 int added = 0;
1007 u16 channel = 0;
1008
1009 sband = iwl_get_hw_mode(priv, band);
1010 if (!sband) {
1011 IWL_ERR(priv, "invalid band\n");
1012 return added;
1013 }
1014
1015 active_dwell = iwl_get_active_dwell_time(priv, band, 0);
1016 passive_dwell = iwl_get_passive_dwell_time(priv, band, vif);
1017
1018 if (passive_dwell <= active_dwell)
1019 passive_dwell = active_dwell + 1;
1020
1021 channel = iwl_get_single_channel_number(priv, band);
1022 if (channel) {
1023 scan_ch->channel = cpu_to_le16(channel);
1024 scan_ch->type = SCAN_CHANNEL_TYPE_PASSIVE;
1025 scan_ch->active_dwell = cpu_to_le16(active_dwell);
1026 scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
1027 /* Set txpower levels to defaults */
1028 scan_ch->dsp_atten = 110;
1029 if (band == IEEE80211_BAND_5GHZ)
1030 scan_ch->tx_gain = ((1 << 5) | (3 << 3)) | 3;
1031 else
1032 scan_ch->tx_gain = ((1 << 5) | (5 << 3));
1033 added++;
1034 } else
1035 IWL_ERR(priv, "no valid channel found\n");
1036 return added;
1037 }
1038
1039 static int iwl_get_channels_for_scan(struct iwl_priv *priv,
1040 struct ieee80211_vif *vif,
1041 enum ieee80211_band band,
1042 u8 is_active, u8 n_probes,
1043 struct iwl_scan_channel *scan_ch)
1044 {
1045 struct ieee80211_channel *chan;
1046 const struct ieee80211_supported_band *sband;
1047 const struct iwl_channel_info *ch_info;
1048 u16 passive_dwell = 0;
1049 u16 active_dwell = 0;
1050 int added, i;
1051 u16 channel;
1052
1053 sband = iwl_get_hw_mode(priv, band);
1054 if (!sband)
1055 return 0;
1056
1057 active_dwell = iwl_get_active_dwell_time(priv, band, n_probes);
1058 passive_dwell = iwl_get_passive_dwell_time(priv, band, vif);
1059
1060 if (passive_dwell <= active_dwell)
1061 passive_dwell = active_dwell + 1;
1062
1063 for (i = 0, added = 0; i < priv->scan_request->n_channels; i++) {
1064 chan = priv->scan_request->channels[i];
1065
1066 if (chan->band != band)
1067 continue;
1068
1069 channel = chan->hw_value;
1070 scan_ch->channel = cpu_to_le16(channel);
1071
1072 ch_info = iwl_get_channel_info(priv, band, channel);
1073 if (!is_channel_valid(ch_info)) {
1074 IWL_DEBUG_SCAN(priv, "Channel %d is INVALID for this band.\n",
1075 channel);
1076 continue;
1077 }
1078
1079 if (!is_active || is_channel_passive(ch_info) ||
1080 (chan->flags & IEEE80211_CHAN_PASSIVE_SCAN))
1081 scan_ch->type = SCAN_CHANNEL_TYPE_PASSIVE;
1082 else
1083 scan_ch->type = SCAN_CHANNEL_TYPE_ACTIVE;
1084
1085 if (n_probes)
1086 scan_ch->type |= IWL_SCAN_PROBE_MASK(n_probes);
1087
1088 scan_ch->active_dwell = cpu_to_le16(active_dwell);
1089 scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
1090
1091 /* Set txpower levels to defaults */
1092 scan_ch->dsp_atten = 110;
1093
1094 /* NOTE: if we were doing 6Mb OFDM for scans we'd use
1095 * power level:
1096 * scan_ch->tx_gain = ((1 << 5) | (2 << 3)) | 3;
1097 */
1098 if (band == IEEE80211_BAND_5GHZ)
1099 scan_ch->tx_gain = ((1 << 5) | (3 << 3)) | 3;
1100 else
1101 scan_ch->tx_gain = ((1 << 5) | (5 << 3));
1102
1103 IWL_DEBUG_SCAN(priv, "Scanning ch=%d prob=0x%X [%s %d]\n",
1104 channel, le32_to_cpu(scan_ch->type),
1105 (scan_ch->type & SCAN_CHANNEL_TYPE_ACTIVE) ?
1106 "ACTIVE" : "PASSIVE",
1107 (scan_ch->type & SCAN_CHANNEL_TYPE_ACTIVE) ?
1108 active_dwell : passive_dwell);
1109
1110 scan_ch++;
1111 added++;
1112 }
1113
1114 IWL_DEBUG_SCAN(priv, "total channels to scan %d\n", added);
1115 return added;
1116 }
1117
1118 int iwlagn_request_scan(struct iwl_priv *priv, struct ieee80211_vif *vif)
1119 {
1120 struct iwl_host_cmd cmd = {
1121 .id = REPLY_SCAN_CMD,
1122 .len = sizeof(struct iwl_scan_cmd),
1123 .flags = CMD_SIZE_HUGE,
1124 };
1125 struct iwl_scan_cmd *scan;
1126 struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
1127 u32 rate_flags = 0;
1128 u16 cmd_len;
1129 u16 rx_chain = 0;
1130 enum ieee80211_band band;
1131 u8 n_probes = 0;
1132 u8 rx_ant = priv->hw_params.valid_rx_ant;
1133 u8 rate;
1134 bool is_active = false;
1135 int chan_mod;
1136 u8 active_chains;
1137 u8 scan_tx_antennas = priv->hw_params.valid_tx_ant;
1138 int ret;
1139
1140 lockdep_assert_held(&priv->mutex);
1141
1142 if (vif)
1143 ctx = iwl_rxon_ctx_from_vif(vif);
1144
1145 if (!priv->scan_cmd) {
1146 priv->scan_cmd = kmalloc(sizeof(struct iwl_scan_cmd) +
1147 IWL_MAX_SCAN_SIZE, GFP_KERNEL);
1148 if (!priv->scan_cmd) {
1149 IWL_DEBUG_SCAN(priv,
1150 "fail to allocate memory for scan\n");
1151 return -ENOMEM;
1152 }
1153 }
1154 scan = priv->scan_cmd;
1155 memset(scan, 0, sizeof(struct iwl_scan_cmd) + IWL_MAX_SCAN_SIZE);
1156
1157 scan->quiet_plcp_th = IWL_PLCP_QUIET_THRESH;
1158 scan->quiet_time = IWL_ACTIVE_QUIET_TIME;
1159
1160 if (iwl_is_any_associated(priv)) {
1161 u16 interval = 0;
1162 u32 extra;
1163 u32 suspend_time = 100;
1164 u32 scan_suspend_time = 100;
1165
1166 IWL_DEBUG_INFO(priv, "Scanning while associated...\n");
1167 if (priv->is_internal_short_scan)
1168 interval = 0;
1169 else
1170 interval = vif->bss_conf.beacon_int;
1171
1172 scan->suspend_time = 0;
1173 scan->max_out_time = cpu_to_le32(200 * 1024);
1174 if (!interval)
1175 interval = suspend_time;
1176
1177 extra = (suspend_time / interval) << 22;
1178 scan_suspend_time = (extra |
1179 ((suspend_time % interval) * 1024));
1180 scan->suspend_time = cpu_to_le32(scan_suspend_time);
1181 IWL_DEBUG_SCAN(priv, "suspend_time 0x%X beacon interval %d\n",
1182 scan_suspend_time, interval);
1183 }
1184
1185 if (priv->is_internal_short_scan) {
1186 IWL_DEBUG_SCAN(priv, "Start internal passive scan.\n");
1187 } else if (priv->scan_request->n_ssids) {
1188 int i, p = 0;
1189 IWL_DEBUG_SCAN(priv, "Kicking off active scan\n");
1190 for (i = 0; i < priv->scan_request->n_ssids; i++) {
1191 /* always does wildcard anyway */
1192 if (!priv->scan_request->ssids[i].ssid_len)
1193 continue;
1194 scan->direct_scan[p].id = WLAN_EID_SSID;
1195 scan->direct_scan[p].len =
1196 priv->scan_request->ssids[i].ssid_len;
1197 memcpy(scan->direct_scan[p].ssid,
1198 priv->scan_request->ssids[i].ssid,
1199 priv->scan_request->ssids[i].ssid_len);
1200 n_probes++;
1201 p++;
1202 }
1203 is_active = true;
1204 } else
1205 IWL_DEBUG_SCAN(priv, "Start passive scan.\n");
1206
1207 scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
1208 scan->tx_cmd.sta_id = ctx->bcast_sta_id;
1209 scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
1210
1211 switch (priv->scan_band) {
1212 case IEEE80211_BAND_2GHZ:
1213 scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
1214 chan_mod = le32_to_cpu(
1215 priv->contexts[IWL_RXON_CTX_BSS].active.flags &
1216 RXON_FLG_CHANNEL_MODE_MSK)
1217 >> RXON_FLG_CHANNEL_MODE_POS;
1218 if (chan_mod == CHANNEL_MODE_PURE_40) {
1219 rate = IWL_RATE_6M_PLCP;
1220 } else {
1221 rate = IWL_RATE_1M_PLCP;
1222 rate_flags = RATE_MCS_CCK_MSK;
1223 }
1224 /*
1225 * Internal scans are passive, so we can indiscriminately set
1226 * the BT ignore flag on 2.4 GHz since it applies to TX only.
1227 */
1228 if (priv->cfg->bt_params &&
1229 priv->cfg->bt_params->advanced_bt_coexist)
1230 scan->tx_cmd.tx_flags |= TX_CMD_FLG_IGNORE_BT;
1231 break;
1232 case IEEE80211_BAND_5GHZ:
1233 rate = IWL_RATE_6M_PLCP;
1234 break;
1235 default:
1236 IWL_WARN(priv, "Invalid scan band\n");
1237 return -EIO;
1238 }
1239
1240 /*
1241 * If active scanning is requested but a certain channel is
1242 * marked passive, we can do active scanning if we detect
1243 * transmissions.
1244 *
1245 * There is an issue with some firmware versions that triggers
1246 * a sysassert on a "good CRC threshold" of zero (== disabled),
1247 * on a radar channel even though this means that we should NOT
1248 * send probes.
1249 *
1250 * The "good CRC threshold" is the number of frames that we
1251 * need to receive during our dwell time on a channel before
1252 * sending out probes -- setting this to a huge value will
1253 * mean we never reach it, but at the same time work around
1254 * the aforementioned issue. Thus use IWL_GOOD_CRC_TH_NEVER
1255 * here instead of IWL_GOOD_CRC_TH_DISABLED.
1256 */
1257 scan->good_CRC_th = is_active ? IWL_GOOD_CRC_TH_DEFAULT :
1258 IWL_GOOD_CRC_TH_NEVER;
1259
1260 band = priv->scan_band;
1261
1262 if (priv->cfg->scan_rx_antennas[band])
1263 rx_ant = priv->cfg->scan_rx_antennas[band];
1264
1265 if (band == IEEE80211_BAND_2GHZ &&
1266 priv->cfg->bt_params &&
1267 priv->cfg->bt_params->advanced_bt_coexist) {
1268 /* transmit 2.4 GHz probes only on first antenna */
1269 scan_tx_antennas = first_antenna(scan_tx_antennas);
1270 }
1271
1272 priv->scan_tx_ant[band] = iwl_toggle_tx_ant(priv, priv->scan_tx_ant[band],
1273 scan_tx_antennas);
1274 rate_flags |= iwl_ant_idx_to_flags(priv->scan_tx_ant[band]);
1275 scan->tx_cmd.rate_n_flags = iwl_hw_set_rate_n_flags(rate, rate_flags);
1276
1277 /* In power save mode use one chain, otherwise use all chains */
1278 if (test_bit(STATUS_POWER_PMI, &priv->status)) {
1279 /* rx_ant has been set to all valid chains previously */
1280 active_chains = rx_ant &
1281 ((u8)(priv->chain_noise_data.active_chains));
1282 if (!active_chains)
1283 active_chains = rx_ant;
1284
1285 IWL_DEBUG_SCAN(priv, "chain_noise_data.active_chains: %u\n",
1286 priv->chain_noise_data.active_chains);
1287
1288 rx_ant = first_antenna(active_chains);
1289 }
1290 if (priv->cfg->bt_params &&
1291 priv->cfg->bt_params->advanced_bt_coexist &&
1292 priv->bt_full_concurrent) {
1293 /* operated as 1x1 in full concurrency mode */
1294 rx_ant = first_antenna(rx_ant);
1295 }
1296
1297 /* MIMO is not used here, but value is required */
1298 rx_chain |= priv->hw_params.valid_rx_ant << RXON_RX_CHAIN_VALID_POS;
1299 rx_chain |= rx_ant << RXON_RX_CHAIN_FORCE_MIMO_SEL_POS;
1300 rx_chain |= rx_ant << RXON_RX_CHAIN_FORCE_SEL_POS;
1301 rx_chain |= 0x1 << RXON_RX_CHAIN_DRIVER_FORCE_POS;
1302 scan->rx_chain = cpu_to_le16(rx_chain);
1303 if (!priv->is_internal_short_scan) {
1304 cmd_len = iwl_fill_probe_req(priv,
1305 (struct ieee80211_mgmt *)scan->data,
1306 vif->addr,
1307 priv->scan_request->ie,
1308 priv->scan_request->ie_len,
1309 IWL_MAX_SCAN_SIZE - sizeof(*scan));
1310 } else {
1311 /* use bcast addr, will not be transmitted but must be valid */
1312 cmd_len = iwl_fill_probe_req(priv,
1313 (struct ieee80211_mgmt *)scan->data,
1314 iwl_bcast_addr, NULL, 0,
1315 IWL_MAX_SCAN_SIZE - sizeof(*scan));
1316
1317 }
1318 scan->tx_cmd.len = cpu_to_le16(cmd_len);
1319
1320 scan->filter_flags |= (RXON_FILTER_ACCEPT_GRP_MSK |
1321 RXON_FILTER_BCON_AWARE_MSK);
1322
1323 if (priv->is_internal_short_scan) {
1324 scan->channel_count =
1325 iwl_get_single_channel_for_scan(priv, vif, band,
1326 (void *)&scan->data[le16_to_cpu(
1327 scan->tx_cmd.len)]);
1328 } else {
1329 scan->channel_count =
1330 iwl_get_channels_for_scan(priv, vif, band,
1331 is_active, n_probes,
1332 (void *)&scan->data[le16_to_cpu(
1333 scan->tx_cmd.len)]);
1334 }
1335 if (scan->channel_count == 0) {
1336 IWL_DEBUG_SCAN(priv, "channel count %d\n", scan->channel_count);
1337 return -EIO;
1338 }
1339
1340 cmd.len += le16_to_cpu(scan->tx_cmd.len) +
1341 scan->channel_count * sizeof(struct iwl_scan_channel);
1342 cmd.data = scan;
1343 scan->len = cpu_to_le16(cmd.len);
1344
1345 /* set scan bit here for PAN params */
1346 set_bit(STATUS_SCAN_HW, &priv->status);
1347
1348 if (priv->cfg->ops->hcmd->set_pan_params) {
1349 ret = priv->cfg->ops->hcmd->set_pan_params(priv);
1350 if (ret)
1351 return ret;
1352 }
1353
1354 ret = iwl_send_cmd_sync(priv, &cmd);
1355 if (ret) {
1356 clear_bit(STATUS_SCAN_HW, &priv->status);
1357 if (priv->cfg->ops->hcmd->set_pan_params)
1358 priv->cfg->ops->hcmd->set_pan_params(priv);
1359 }
1360
1361 return ret;
1362 }
1363
1364 int iwlagn_manage_ibss_station(struct iwl_priv *priv,
1365 struct ieee80211_vif *vif, bool add)
1366 {
1367 struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
1368
1369 if (add)
1370 return iwlagn_add_bssid_station(priv, vif_priv->ctx,
1371 vif->bss_conf.bssid,
1372 &vif_priv->ibss_bssid_sta_id);
1373 return iwl_remove_station(priv, vif_priv->ibss_bssid_sta_id,
1374 vif->bss_conf.bssid);
1375 }
1376
1377 void iwl_free_tfds_in_queue(struct iwl_priv *priv,
1378 int sta_id, int tid, int freed)
1379 {
1380 lockdep_assert_held(&priv->sta_lock);
1381
1382 if (priv->stations[sta_id].tid[tid].tfds_in_queue >= freed)
1383 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1384 else {
1385 IWL_DEBUG_TX(priv, "free more than tfds_in_queue (%u:%d)\n",
1386 priv->stations[sta_id].tid[tid].tfds_in_queue,
1387 freed);
1388 priv->stations[sta_id].tid[tid].tfds_in_queue = 0;
1389 }
1390 }
1391
1392 #define IWL_FLUSH_WAIT_MS 2000
1393
1394 int iwlagn_wait_tx_queue_empty(struct iwl_priv *priv)
1395 {
1396 struct iwl_tx_queue *txq;
1397 struct iwl_queue *q;
1398 int cnt;
1399 unsigned long now = jiffies;
1400 int ret = 0;
1401
1402 /* waiting for all the tx frames complete might take a while */
1403 for (cnt = 0; cnt < priv->hw_params.max_txq_num; cnt++) {
1404 if (cnt == priv->cmd_queue)
1405 continue;
1406 txq = &priv->txq[cnt];
1407 q = &txq->q;
1408 while (q->read_ptr != q->write_ptr && !time_after(jiffies,
1409 now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS)))
1410 msleep(1);
1411
1412 if (q->read_ptr != q->write_ptr) {
1413 IWL_ERR(priv, "fail to flush all tx fifo queues\n");
1414 ret = -ETIMEDOUT;
1415 break;
1416 }
1417 }
1418 return ret;
1419 }
1420
1421 #define IWL_TX_QUEUE_MSK 0xfffff
1422
1423 /**
1424 * iwlagn_txfifo_flush: send REPLY_TXFIFO_FLUSH command to uCode
1425 *
1426 * pre-requirements:
1427 * 1. acquire mutex before calling
1428 * 2. make sure rf is on and not in exit state
1429 */
1430 int iwlagn_txfifo_flush(struct iwl_priv *priv, u16 flush_control)
1431 {
1432 struct iwl_txfifo_flush_cmd flush_cmd;
1433 struct iwl_host_cmd cmd = {
1434 .id = REPLY_TXFIFO_FLUSH,
1435 .len = sizeof(struct iwl_txfifo_flush_cmd),
1436 .flags = CMD_SYNC,
1437 .data = &flush_cmd,
1438 };
1439
1440 might_sleep();
1441
1442 memset(&flush_cmd, 0, sizeof(flush_cmd));
1443 flush_cmd.fifo_control = IWL_TX_FIFO_VO_MSK | IWL_TX_FIFO_VI_MSK |
1444 IWL_TX_FIFO_BE_MSK | IWL_TX_FIFO_BK_MSK;
1445 if (priv->cfg->sku & IWL_SKU_N)
1446 flush_cmd.fifo_control |= IWL_AGG_TX_QUEUE_MSK;
1447
1448 IWL_DEBUG_INFO(priv, "fifo queue control: 0X%x\n",
1449 flush_cmd.fifo_control);
1450 flush_cmd.flush_control = cpu_to_le16(flush_control);
1451
1452 return iwl_send_cmd(priv, &cmd);
1453 }
1454
1455 void iwlagn_dev_txfifo_flush(struct iwl_priv *priv, u16 flush_control)
1456 {
1457 mutex_lock(&priv->mutex);
1458 ieee80211_stop_queues(priv->hw);
1459 if (priv->cfg->ops->lib->txfifo_flush(priv, IWL_DROP_ALL)) {
1460 IWL_ERR(priv, "flush request fail\n");
1461 goto done;
1462 }
1463 IWL_DEBUG_INFO(priv, "wait transmit/flush all frames\n");
1464 iwlagn_wait_tx_queue_empty(priv);
1465 done:
1466 ieee80211_wake_queues(priv->hw);
1467 mutex_unlock(&priv->mutex);
1468 }
1469
1470 /*
1471 * BT coex
1472 */
1473 /*
1474 * Macros to access the lookup table.
1475 *
1476 * The lookup table has 7 inputs: bt3_prio, bt3_txrx, bt_rf_act, wifi_req,
1477 * wifi_prio, wifi_txrx and wifi_sh_ant_req.
1478 *
1479 * It has three outputs: WLAN_ACTIVE, WLAN_KILL and ANT_SWITCH
1480 *
1481 * The format is that "registers" 8 through 11 contain the WLAN_ACTIVE bits
1482 * one after another in 32-bit registers, and "registers" 0 through 7 contain
1483 * the WLAN_KILL and ANT_SWITCH bits interleaved (in that order).
1484 *
1485 * These macros encode that format.
1486 */
1487 #define LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, wifi_req, wifi_prio, \
1488 wifi_txrx, wifi_sh_ant_req) \
1489 (bt3_prio | (bt3_txrx << 1) | (bt_rf_act << 2) | (wifi_req << 3) | \
1490 (wifi_prio << 4) | (wifi_txrx << 5) | (wifi_sh_ant_req << 6))
1491
1492 #define LUT_PTA_WLAN_ACTIVE_OP(lut, op, val) \
1493 lut[8 + ((val) >> 5)] op (cpu_to_le32(BIT((val) & 0x1f)))
1494 #define LUT_TEST_PTA_WLAN_ACTIVE(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1495 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1496 (!!(LUT_PTA_WLAN_ACTIVE_OP(lut, &, LUT_VALUE(bt3_prio, bt3_txrx, \
1497 bt_rf_act, wifi_req, wifi_prio, wifi_txrx, \
1498 wifi_sh_ant_req))))
1499 #define LUT_SET_PTA_WLAN_ACTIVE(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1500 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1501 LUT_PTA_WLAN_ACTIVE_OP(lut, |=, LUT_VALUE(bt3_prio, bt3_txrx, \
1502 bt_rf_act, wifi_req, wifi_prio, wifi_txrx, \
1503 wifi_sh_ant_req))
1504 #define LUT_CLEAR_PTA_WLAN_ACTIVE(lut, bt3_prio, bt3_txrx, bt_rf_act, \
1505 wifi_req, wifi_prio, wifi_txrx, \
1506 wifi_sh_ant_req) \
1507 LUT_PTA_WLAN_ACTIVE_OP(lut, &= ~, LUT_VALUE(bt3_prio, bt3_txrx, \
1508 bt_rf_act, wifi_req, wifi_prio, wifi_txrx, \
1509 wifi_sh_ant_req))
1510
1511 #define LUT_WLAN_KILL_OP(lut, op, val) \
1512 lut[(val) >> 4] op (cpu_to_le32(BIT(((val) << 1) & 0x1e)))
1513 #define LUT_TEST_WLAN_KILL(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1514 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1515 (!!(LUT_WLAN_KILL_OP(lut, &, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1516 wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))))
1517 #define LUT_SET_WLAN_KILL(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1518 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1519 LUT_WLAN_KILL_OP(lut, |=, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1520 wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))
1521 #define LUT_CLEAR_WLAN_KILL(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1522 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1523 LUT_WLAN_KILL_OP(lut, &= ~, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1524 wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))
1525
1526 #define LUT_ANT_SWITCH_OP(lut, op, val) \
1527 lut[(val) >> 4] op (cpu_to_le32(BIT((((val) << 1) & 0x1e) + 1)))
1528 #define LUT_TEST_ANT_SWITCH(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1529 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1530 (!!(LUT_ANT_SWITCH_OP(lut, &, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1531 wifi_req, wifi_prio, wifi_txrx, \
1532 wifi_sh_ant_req))))
1533 #define LUT_SET_ANT_SWITCH(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1534 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1535 LUT_ANT_SWITCH_OP(lut, |=, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1536 wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))
1537 #define LUT_CLEAR_ANT_SWITCH(lut, bt3_prio, bt3_txrx, bt_rf_act, wifi_req, \
1538 wifi_prio, wifi_txrx, wifi_sh_ant_req) \
1539 LUT_ANT_SWITCH_OP(lut, &= ~, LUT_VALUE(bt3_prio, bt3_txrx, bt_rf_act, \
1540 wifi_req, wifi_prio, wifi_txrx, wifi_sh_ant_req))
1541
1542 static const __le32 iwlagn_def_3w_lookup[12] = {
1543 cpu_to_le32(0xaaaaaaaa),
1544 cpu_to_le32(0xaaaaaaaa),
1545 cpu_to_le32(0xaeaaaaaa),
1546 cpu_to_le32(0xaaaaaaaa),
1547 cpu_to_le32(0xcc00ff28),
1548 cpu_to_le32(0x0000aaaa),
1549 cpu_to_le32(0xcc00aaaa),
1550 cpu_to_le32(0x0000aaaa),
1551 cpu_to_le32(0xc0004000),
1552 cpu_to_le32(0x00004000),
1553 cpu_to_le32(0xf0005000),
1554 cpu_to_le32(0xf0005000),
1555 };
1556
1557 static const __le32 iwlagn_concurrent_lookup[12] = {
1558 cpu_to_le32(0xaaaaaaaa),
1559 cpu_to_le32(0xaaaaaaaa),
1560 cpu_to_le32(0xaaaaaaaa),
1561 cpu_to_le32(0xaaaaaaaa),
1562 cpu_to_le32(0xaaaaaaaa),
1563 cpu_to_le32(0xaaaaaaaa),
1564 cpu_to_le32(0xaaaaaaaa),
1565 cpu_to_le32(0xaaaaaaaa),
1566 cpu_to_le32(0x00000000),
1567 cpu_to_le32(0x00000000),
1568 cpu_to_le32(0x00000000),
1569 cpu_to_le32(0x00000000),
1570 };
1571
1572 void iwlagn_send_advance_bt_config(struct iwl_priv *priv)
1573 {
1574 struct iwl_basic_bt_cmd basic = {
1575 .max_kill = IWLAGN_BT_MAX_KILL_DEFAULT,
1576 .bt3_timer_t7_value = IWLAGN_BT3_T7_DEFAULT,
1577 .bt3_prio_sample_time = IWLAGN_BT3_PRIO_SAMPLE_DEFAULT,
1578 .bt3_timer_t2_value = IWLAGN_BT3_T2_DEFAULT,
1579 };
1580 struct iwl6000_bt_cmd bt_cmd_6000;
1581 struct iwl2000_bt_cmd bt_cmd_2000;
1582 int ret;
1583
1584 BUILD_BUG_ON(sizeof(iwlagn_def_3w_lookup) !=
1585 sizeof(basic.bt3_lookup_table));
1586
1587 if (priv->cfg->bt_params) {
1588 if (priv->cfg->bt_params->bt_session_2) {
1589 bt_cmd_2000.prio_boost = cpu_to_le32(
1590 priv->cfg->bt_params->bt_prio_boost);
1591 bt_cmd_2000.tx_prio_boost = 0;
1592 bt_cmd_2000.rx_prio_boost = 0;
1593 } else {
1594 bt_cmd_6000.prio_boost =
1595 priv->cfg->bt_params->bt_prio_boost;
1596 bt_cmd_6000.tx_prio_boost = 0;
1597 bt_cmd_6000.rx_prio_boost = 0;
1598 }
1599 } else {
1600 IWL_ERR(priv, "failed to construct BT Coex Config\n");
1601 return;
1602 }
1603
1604 basic.kill_ack_mask = priv->kill_ack_mask;
1605 basic.kill_cts_mask = priv->kill_cts_mask;
1606 basic.valid = priv->bt_valid;
1607
1608 /*
1609 * Configure BT coex mode to "no coexistence" when the
1610 * user disabled BT coexistence, we have no interface
1611 * (might be in monitor mode), or the interface is in
1612 * IBSS mode (no proper uCode support for coex then).
1613 */
1614 if (!bt_coex_active || priv->iw_mode == NL80211_IFTYPE_ADHOC) {
1615 basic.flags = IWLAGN_BT_FLAG_COEX_MODE_DISABLED;
1616 } else {
1617 basic.flags = IWLAGN_BT_FLAG_COEX_MODE_3W <<
1618 IWLAGN_BT_FLAG_COEX_MODE_SHIFT;
1619 if (priv->cfg->bt_params &&
1620 priv->cfg->bt_params->bt_sco_disable)
1621 basic.flags |= IWLAGN_BT_FLAG_SYNC_2_BT_DISABLE;
1622
1623 if (priv->bt_ch_announce)
1624 basic.flags |= IWLAGN_BT_FLAG_CHANNEL_INHIBITION;
1625 IWL_DEBUG_INFO(priv, "BT coex flag: 0X%x\n", basic.flags);
1626 }
1627 priv->bt_enable_flag = basic.flags;
1628 if (priv->bt_full_concurrent)
1629 memcpy(basic.bt3_lookup_table, iwlagn_concurrent_lookup,
1630 sizeof(iwlagn_concurrent_lookup));
1631 else
1632 memcpy(basic.bt3_lookup_table, iwlagn_def_3w_lookup,
1633 sizeof(iwlagn_def_3w_lookup));
1634
1635 IWL_DEBUG_INFO(priv, "BT coex %s in %s mode\n",
1636 basic.flags ? "active" : "disabled",
1637 priv->bt_full_concurrent ?
1638 "full concurrency" : "3-wire");
1639
1640 if (priv->cfg->bt_params->bt_session_2) {
1641 memcpy(&bt_cmd_2000.basic, &basic,
1642 sizeof(basic));
1643 ret = iwl_send_cmd_pdu(priv, REPLY_BT_CONFIG,
1644 sizeof(bt_cmd_2000), &bt_cmd_2000);
1645 } else {
1646 memcpy(&bt_cmd_6000.basic, &basic,
1647 sizeof(basic));
1648 ret = iwl_send_cmd_pdu(priv, REPLY_BT_CONFIG,
1649 sizeof(bt_cmd_6000), &bt_cmd_6000);
1650 }
1651 if (ret)
1652 IWL_ERR(priv, "failed to send BT Coex Config\n");
1653
1654 }
1655
1656 static void iwlagn_bt_traffic_change_work(struct work_struct *work)
1657 {
1658 struct iwl_priv *priv =
1659 container_of(work, struct iwl_priv, bt_traffic_change_work);
1660 struct iwl_rxon_context *ctx;
1661 int smps_request = -1;
1662
1663 if (priv->bt_enable_flag == IWLAGN_BT_FLAG_COEX_MODE_DISABLED) {
1664 /* bt coex disabled */
1665 return;
1666 }
1667
1668 /*
1669 * Note: bt_traffic_load can be overridden by scan complete and
1670 * coex profile notifications. Ignore that since only bad consequence
1671 * can be not matching debug print with actual state.
1672 */
1673 IWL_DEBUG_INFO(priv, "BT traffic load changes: %d\n",
1674 priv->bt_traffic_load);
1675
1676 switch (priv->bt_traffic_load) {
1677 case IWL_BT_COEX_TRAFFIC_LOAD_NONE:
1678 if (priv->bt_status)
1679 smps_request = IEEE80211_SMPS_DYNAMIC;
1680 else
1681 smps_request = IEEE80211_SMPS_AUTOMATIC;
1682 break;
1683 case IWL_BT_COEX_TRAFFIC_LOAD_LOW:
1684 smps_request = IEEE80211_SMPS_DYNAMIC;
1685 break;
1686 case IWL_BT_COEX_TRAFFIC_LOAD_HIGH:
1687 case IWL_BT_COEX_TRAFFIC_LOAD_CONTINUOUS:
1688 smps_request = IEEE80211_SMPS_STATIC;
1689 break;
1690 default:
1691 IWL_ERR(priv, "Invalid BT traffic load: %d\n",
1692 priv->bt_traffic_load);
1693 break;
1694 }
1695
1696 mutex_lock(&priv->mutex);
1697
1698 /*
1699 * We can not send command to firmware while scanning. When the scan
1700 * complete we will schedule this work again. We do check with mutex
1701 * locked to prevent new scan request to arrive. We do not check
1702 * STATUS_SCANNING to avoid race when queue_work two times from
1703 * different notifications, but quit and not perform any work at all.
1704 */
1705 if (test_bit(STATUS_SCAN_HW, &priv->status))
1706 goto out;
1707
1708 if (priv->cfg->ops->lib->update_chain_flags)
1709 priv->cfg->ops->lib->update_chain_flags(priv);
1710
1711 if (smps_request != -1) {
1712 for_each_context(priv, ctx) {
1713 if (ctx->vif && ctx->vif->type == NL80211_IFTYPE_STATION)
1714 ieee80211_request_smps(ctx->vif, smps_request);
1715 }
1716 }
1717 out:
1718 mutex_unlock(&priv->mutex);
1719 }
1720
1721 static void iwlagn_print_uartmsg(struct iwl_priv *priv,
1722 struct iwl_bt_uart_msg *uart_msg)
1723 {
1724 IWL_DEBUG_NOTIF(priv, "Message Type = 0x%X, SSN = 0x%X, "
1725 "Update Req = 0x%X",
1726 (BT_UART_MSG_FRAME1MSGTYPE_MSK & uart_msg->frame1) >>
1727 BT_UART_MSG_FRAME1MSGTYPE_POS,
1728 (BT_UART_MSG_FRAME1SSN_MSK & uart_msg->frame1) >>
1729 BT_UART_MSG_FRAME1SSN_POS,
1730 (BT_UART_MSG_FRAME1UPDATEREQ_MSK & uart_msg->frame1) >>
1731 BT_UART_MSG_FRAME1UPDATEREQ_POS);
1732
1733 IWL_DEBUG_NOTIF(priv, "Open connections = 0x%X, Traffic load = 0x%X, "
1734 "Chl_SeqN = 0x%X, In band = 0x%X",
1735 (BT_UART_MSG_FRAME2OPENCONNECTIONS_MSK & uart_msg->frame2) >>
1736 BT_UART_MSG_FRAME2OPENCONNECTIONS_POS,
1737 (BT_UART_MSG_FRAME2TRAFFICLOAD_MSK & uart_msg->frame2) >>
1738 BT_UART_MSG_FRAME2TRAFFICLOAD_POS,
1739 (BT_UART_MSG_FRAME2CHLSEQN_MSK & uart_msg->frame2) >>
1740 BT_UART_MSG_FRAME2CHLSEQN_POS,
1741 (BT_UART_MSG_FRAME2INBAND_MSK & uart_msg->frame2) >>
1742 BT_UART_MSG_FRAME2INBAND_POS);
1743
1744 IWL_DEBUG_NOTIF(priv, "SCO/eSCO = 0x%X, Sniff = 0x%X, A2DP = 0x%X, "
1745 "ACL = 0x%X, Master = 0x%X, OBEX = 0x%X",
1746 (BT_UART_MSG_FRAME3SCOESCO_MSK & uart_msg->frame3) >>
1747 BT_UART_MSG_FRAME3SCOESCO_POS,
1748 (BT_UART_MSG_FRAME3SNIFF_MSK & uart_msg->frame3) >>
1749 BT_UART_MSG_FRAME3SNIFF_POS,
1750 (BT_UART_MSG_FRAME3A2DP_MSK & uart_msg->frame3) >>
1751 BT_UART_MSG_FRAME3A2DP_POS,
1752 (BT_UART_MSG_FRAME3ACL_MSK & uart_msg->frame3) >>
1753 BT_UART_MSG_FRAME3ACL_POS,
1754 (BT_UART_MSG_FRAME3MASTER_MSK & uart_msg->frame3) >>
1755 BT_UART_MSG_FRAME3MASTER_POS,
1756 (BT_UART_MSG_FRAME3OBEX_MSK & uart_msg->frame3) >>
1757 BT_UART_MSG_FRAME3OBEX_POS);
1758
1759 IWL_DEBUG_NOTIF(priv, "Idle duration = 0x%X",
1760 (BT_UART_MSG_FRAME4IDLEDURATION_MSK & uart_msg->frame4) >>
1761 BT_UART_MSG_FRAME4IDLEDURATION_POS);
1762
1763 IWL_DEBUG_NOTIF(priv, "Tx Activity = 0x%X, Rx Activity = 0x%X, "
1764 "eSCO Retransmissions = 0x%X",
1765 (BT_UART_MSG_FRAME5TXACTIVITY_MSK & uart_msg->frame5) >>
1766 BT_UART_MSG_FRAME5TXACTIVITY_POS,
1767 (BT_UART_MSG_FRAME5RXACTIVITY_MSK & uart_msg->frame5) >>
1768 BT_UART_MSG_FRAME5RXACTIVITY_POS,
1769 (BT_UART_MSG_FRAME5ESCORETRANSMIT_MSK & uart_msg->frame5) >>
1770 BT_UART_MSG_FRAME5ESCORETRANSMIT_POS);
1771
1772 IWL_DEBUG_NOTIF(priv, "Sniff Interval = 0x%X, Discoverable = 0x%X",
1773 (BT_UART_MSG_FRAME6SNIFFINTERVAL_MSK & uart_msg->frame6) >>
1774 BT_UART_MSG_FRAME6SNIFFINTERVAL_POS,
1775 (BT_UART_MSG_FRAME6DISCOVERABLE_MSK & uart_msg->frame6) >>
1776 BT_UART_MSG_FRAME6DISCOVERABLE_POS);
1777
1778 IWL_DEBUG_NOTIF(priv, "Sniff Activity = 0x%X, Page = "
1779 "0x%X, Inquiry = 0x%X, Connectable = 0x%X",
1780 (BT_UART_MSG_FRAME7SNIFFACTIVITY_MSK & uart_msg->frame7) >>
1781 BT_UART_MSG_FRAME7SNIFFACTIVITY_POS,
1782 (BT_UART_MSG_FRAME7PAGE_MSK & uart_msg->frame7) >>
1783 BT_UART_MSG_FRAME7PAGE_POS,
1784 (BT_UART_MSG_FRAME7INQUIRY_MSK & uart_msg->frame7) >>
1785 BT_UART_MSG_FRAME7INQUIRY_POS,
1786 (BT_UART_MSG_FRAME7CONNECTABLE_MSK & uart_msg->frame7) >>
1787 BT_UART_MSG_FRAME7CONNECTABLE_POS);
1788 }
1789
1790 static void iwlagn_set_kill_msk(struct iwl_priv *priv,
1791 struct iwl_bt_uart_msg *uart_msg)
1792 {
1793 u8 kill_msk;
1794 static const __le32 bt_kill_ack_msg[2] = {
1795 IWLAGN_BT_KILL_ACK_MASK_DEFAULT,
1796 IWLAGN_BT_KILL_ACK_CTS_MASK_SCO };
1797 static const __le32 bt_kill_cts_msg[2] = {
1798 IWLAGN_BT_KILL_CTS_MASK_DEFAULT,
1799 IWLAGN_BT_KILL_ACK_CTS_MASK_SCO };
1800
1801 kill_msk = (BT_UART_MSG_FRAME3SCOESCO_MSK & uart_msg->frame3)
1802 ? 1 : 0;
1803 if (priv->kill_ack_mask != bt_kill_ack_msg[kill_msk] ||
1804 priv->kill_cts_mask != bt_kill_cts_msg[kill_msk]) {
1805 priv->bt_valid |= IWLAGN_BT_VALID_KILL_ACK_MASK;
1806 priv->kill_ack_mask = bt_kill_ack_msg[kill_msk];
1807 priv->bt_valid |= IWLAGN_BT_VALID_KILL_CTS_MASK;
1808 priv->kill_cts_mask = bt_kill_cts_msg[kill_msk];
1809
1810 /* schedule to send runtime bt_config */
1811 queue_work(priv->workqueue, &priv->bt_runtime_config);
1812 }
1813 }
1814
1815 void iwlagn_bt_coex_profile_notif(struct iwl_priv *priv,
1816 struct iwl_rx_mem_buffer *rxb)
1817 {
1818 unsigned long flags;
1819 struct iwl_rx_packet *pkt = rxb_addr(rxb);
1820 struct iwl_bt_coex_profile_notif *coex = &pkt->u.bt_coex_profile_notif;
1821 struct iwl_bt_uart_msg *uart_msg = &coex->last_bt_uart_msg;
1822
1823 if (priv->bt_enable_flag == IWLAGN_BT_FLAG_COEX_MODE_DISABLED) {
1824 /* bt coex disabled */
1825 return;
1826 }
1827
1828 IWL_DEBUG_NOTIF(priv, "BT Coex notification:\n");
1829 IWL_DEBUG_NOTIF(priv, " status: %d\n", coex->bt_status);
1830 IWL_DEBUG_NOTIF(priv, " traffic load: %d\n", coex->bt_traffic_load);
1831 IWL_DEBUG_NOTIF(priv, " CI compliance: %d\n",
1832 coex->bt_ci_compliance);
1833 iwlagn_print_uartmsg(priv, uart_msg);
1834
1835 priv->last_bt_traffic_load = priv->bt_traffic_load;
1836 if (priv->iw_mode != NL80211_IFTYPE_ADHOC) {
1837 if (priv->bt_status != coex->bt_status ||
1838 priv->last_bt_traffic_load != coex->bt_traffic_load) {
1839 if (coex->bt_status) {
1840 /* BT on */
1841 if (!priv->bt_ch_announce)
1842 priv->bt_traffic_load =
1843 IWL_BT_COEX_TRAFFIC_LOAD_HIGH;
1844 else
1845 priv->bt_traffic_load =
1846 coex->bt_traffic_load;
1847 } else {
1848 /* BT off */
1849 priv->bt_traffic_load =
1850 IWL_BT_COEX_TRAFFIC_LOAD_NONE;
1851 }
1852 priv->bt_status = coex->bt_status;
1853 queue_work(priv->workqueue,
1854 &priv->bt_traffic_change_work);
1855 }
1856 }
1857
1858 iwlagn_set_kill_msk(priv, uart_msg);
1859
1860 /* FIXME: based on notification, adjust the prio_boost */
1861
1862 spin_lock_irqsave(&priv->lock, flags);
1863 priv->bt_ci_compliance = coex->bt_ci_compliance;
1864 spin_unlock_irqrestore(&priv->lock, flags);
1865 }
1866
1867 void iwlagn_bt_rx_handler_setup(struct iwl_priv *priv)
1868 {
1869 iwlagn_rx_handler_setup(priv);
1870 priv->rx_handlers[REPLY_BT_COEX_PROFILE_NOTIF] =
1871 iwlagn_bt_coex_profile_notif;
1872 }
1873
1874 void iwlagn_bt_setup_deferred_work(struct iwl_priv *priv)
1875 {
1876 iwlagn_setup_deferred_work(priv);
1877
1878 INIT_WORK(&priv->bt_traffic_change_work,
1879 iwlagn_bt_traffic_change_work);
1880 }
1881
1882 void iwlagn_bt_cancel_deferred_work(struct iwl_priv *priv)
1883 {
1884 cancel_work_sync(&priv->bt_traffic_change_work);
1885 }
1886
1887 static bool is_single_rx_stream(struct iwl_priv *priv)
1888 {
1889 return priv->current_ht_config.smps == IEEE80211_SMPS_STATIC ||
1890 priv->current_ht_config.single_chain_sufficient;
1891 }
1892
1893 #define IWL_NUM_RX_CHAINS_MULTIPLE 3
1894 #define IWL_NUM_RX_CHAINS_SINGLE 2
1895 #define IWL_NUM_IDLE_CHAINS_DUAL 2
1896 #define IWL_NUM_IDLE_CHAINS_SINGLE 1
1897
1898 /*
1899 * Determine how many receiver/antenna chains to use.
1900 *
1901 * More provides better reception via diversity. Fewer saves power
1902 * at the expense of throughput, but only when not in powersave to
1903 * start with.
1904 *
1905 * MIMO (dual stream) requires at least 2, but works better with 3.
1906 * This does not determine *which* chains to use, just how many.
1907 */
1908 static int iwl_get_active_rx_chain_count(struct iwl_priv *priv)
1909 {
1910 if (priv->cfg->bt_params &&
1911 priv->cfg->bt_params->advanced_bt_coexist &&
1912 (priv->bt_full_concurrent ||
1913 priv->bt_traffic_load >= IWL_BT_COEX_TRAFFIC_LOAD_HIGH)) {
1914 /*
1915 * only use chain 'A' in bt high traffic load or
1916 * full concurrency mode
1917 */
1918 return IWL_NUM_RX_CHAINS_SINGLE;
1919 }
1920 /* # of Rx chains to use when expecting MIMO. */
1921 if (is_single_rx_stream(priv))
1922 return IWL_NUM_RX_CHAINS_SINGLE;
1923 else
1924 return IWL_NUM_RX_CHAINS_MULTIPLE;
1925 }
1926
1927 /*
1928 * When we are in power saving mode, unless device support spatial
1929 * multiplexing power save, use the active count for rx chain count.
1930 */
1931 static int iwl_get_idle_rx_chain_count(struct iwl_priv *priv, int active_cnt)
1932 {
1933 /* # Rx chains when idling, depending on SMPS mode */
1934 switch (priv->current_ht_config.smps) {
1935 case IEEE80211_SMPS_STATIC:
1936 case IEEE80211_SMPS_DYNAMIC:
1937 return IWL_NUM_IDLE_CHAINS_SINGLE;
1938 case IEEE80211_SMPS_OFF:
1939 return active_cnt;
1940 default:
1941 WARN(1, "invalid SMPS mode %d",
1942 priv->current_ht_config.smps);
1943 return active_cnt;
1944 }
1945 }
1946
1947 /* up to 4 chains */
1948 static u8 iwl_count_chain_bitmap(u32 chain_bitmap)
1949 {
1950 u8 res;
1951 res = (chain_bitmap & BIT(0)) >> 0;
1952 res += (chain_bitmap & BIT(1)) >> 1;
1953 res += (chain_bitmap & BIT(2)) >> 2;
1954 res += (chain_bitmap & BIT(3)) >> 3;
1955 return res;
1956 }
1957
1958 /**
1959 * iwlagn_set_rxon_chain - Set up Rx chain usage in "staging" RXON image
1960 *
1961 * Selects how many and which Rx receivers/antennas/chains to use.
1962 * This should not be used for scan command ... it puts data in wrong place.
1963 */
1964 void iwlagn_set_rxon_chain(struct iwl_priv *priv, struct iwl_rxon_context *ctx)
1965 {
1966 bool is_single = is_single_rx_stream(priv);
1967 bool is_cam = !test_bit(STATUS_POWER_PMI, &priv->status);
1968 u8 idle_rx_cnt, active_rx_cnt, valid_rx_cnt;
1969 u32 active_chains;
1970 u16 rx_chain;
1971
1972 /* Tell uCode which antennas are actually connected.
1973 * Before first association, we assume all antennas are connected.
1974 * Just after first association, iwl_chain_noise_calibration()
1975 * checks which antennas actually *are* connected. */
1976 if (priv->chain_noise_data.active_chains)
1977 active_chains = priv->chain_noise_data.active_chains;
1978 else
1979 active_chains = priv->hw_params.valid_rx_ant;
1980
1981 if (priv->cfg->bt_params &&
1982 priv->cfg->bt_params->advanced_bt_coexist &&
1983 (priv->bt_full_concurrent ||
1984 priv->bt_traffic_load >= IWL_BT_COEX_TRAFFIC_LOAD_HIGH)) {
1985 /*
1986 * only use chain 'A' in bt high traffic load or
1987 * full concurrency mode
1988 */
1989 active_chains = first_antenna(active_chains);
1990 }
1991
1992 rx_chain = active_chains << RXON_RX_CHAIN_VALID_POS;
1993
1994 /* How many receivers should we use? */
1995 active_rx_cnt = iwl_get_active_rx_chain_count(priv);
1996 idle_rx_cnt = iwl_get_idle_rx_chain_count(priv, active_rx_cnt);
1997
1998
1999 /* correct rx chain count according hw settings
2000 * and chain noise calibration
2001 */
2002 valid_rx_cnt = iwl_count_chain_bitmap(active_chains);
2003 if (valid_rx_cnt < active_rx_cnt)
2004 active_rx_cnt = valid_rx_cnt;
2005
2006 if (valid_rx_cnt < idle_rx_cnt)
2007 idle_rx_cnt = valid_rx_cnt;
2008
2009 rx_chain |= active_rx_cnt << RXON_RX_CHAIN_MIMO_CNT_POS;
2010 rx_chain |= idle_rx_cnt << RXON_RX_CHAIN_CNT_POS;
2011
2012 ctx->staging.rx_chain = cpu_to_le16(rx_chain);
2013
2014 if (!is_single && (active_rx_cnt >= IWL_NUM_RX_CHAINS_SINGLE) && is_cam)
2015 ctx->staging.rx_chain |= RXON_RX_CHAIN_MIMO_FORCE_MSK;
2016 else
2017 ctx->staging.rx_chain &= ~RXON_RX_CHAIN_MIMO_FORCE_MSK;
2018
2019 IWL_DEBUG_ASSOC(priv, "rx_chain=0x%X active=%d idle=%d\n",
2020 ctx->staging.rx_chain,
2021 active_rx_cnt, idle_rx_cnt);
2022
2023 WARN_ON(active_rx_cnt == 0 || idle_rx_cnt == 0 ||
2024 active_rx_cnt < idle_rx_cnt);
2025 }
2026
2027 u8 iwl_toggle_tx_ant(struct iwl_priv *priv, u8 ant, u8 valid)
2028 {
2029 int i;
2030 u8 ind = ant;
2031
2032 if (priv->band == IEEE80211_BAND_2GHZ &&
2033 priv->bt_traffic_load >= IWL_BT_COEX_TRAFFIC_LOAD_HIGH)
2034 return 0;
2035
2036 for (i = 0; i < RATE_ANT_NUM - 1; i++) {
2037 ind = (ind + 1) < RATE_ANT_NUM ? ind + 1 : 0;
2038 if (valid & BIT(ind))
2039 return ind;
2040 }
2041 return ant;
2042 }
2043
2044 static const char *get_csr_string(int cmd)
2045 {
2046 switch (cmd) {
2047 IWL_CMD(CSR_HW_IF_CONFIG_REG);
2048 IWL_CMD(CSR_INT_COALESCING);
2049 IWL_CMD(CSR_INT);
2050 IWL_CMD(CSR_INT_MASK);
2051 IWL_CMD(CSR_FH_INT_STATUS);
2052 IWL_CMD(CSR_GPIO_IN);
2053 IWL_CMD(CSR_RESET);
2054 IWL_CMD(CSR_GP_CNTRL);
2055 IWL_CMD(CSR_HW_REV);
2056 IWL_CMD(CSR_EEPROM_REG);
2057 IWL_CMD(CSR_EEPROM_GP);
2058 IWL_CMD(CSR_OTP_GP_REG);
2059 IWL_CMD(CSR_GIO_REG);
2060 IWL_CMD(CSR_GP_UCODE_REG);
2061 IWL_CMD(CSR_GP_DRIVER_REG);
2062 IWL_CMD(CSR_UCODE_DRV_GP1);
2063 IWL_CMD(CSR_UCODE_DRV_GP2);
2064 IWL_CMD(CSR_LED_REG);
2065 IWL_CMD(CSR_DRAM_INT_TBL_REG);
2066 IWL_CMD(CSR_GIO_CHICKEN_BITS);
2067 IWL_CMD(CSR_ANA_PLL_CFG);
2068 IWL_CMD(CSR_HW_REV_WA_REG);
2069 IWL_CMD(CSR_DBG_HPET_MEM_REG);
2070 default:
2071 return "UNKNOWN";
2072 }
2073 }
2074
2075 void iwl_dump_csr(struct iwl_priv *priv)
2076 {
2077 int i;
2078 static const u32 csr_tbl[] = {
2079 CSR_HW_IF_CONFIG_REG,
2080 CSR_INT_COALESCING,
2081 CSR_INT,
2082 CSR_INT_MASK,
2083 CSR_FH_INT_STATUS,
2084 CSR_GPIO_IN,
2085 CSR_RESET,
2086 CSR_GP_CNTRL,
2087 CSR_HW_REV,
2088 CSR_EEPROM_REG,
2089 CSR_EEPROM_GP,
2090 CSR_OTP_GP_REG,
2091 CSR_GIO_REG,
2092 CSR_GP_UCODE_REG,
2093 CSR_GP_DRIVER_REG,
2094 CSR_UCODE_DRV_GP1,
2095 CSR_UCODE_DRV_GP2,
2096 CSR_LED_REG,
2097 CSR_DRAM_INT_TBL_REG,
2098 CSR_GIO_CHICKEN_BITS,
2099 CSR_ANA_PLL_CFG,
2100 CSR_HW_REV_WA_REG,
2101 CSR_DBG_HPET_MEM_REG
2102 };
2103 IWL_ERR(priv, "CSR values:\n");
2104 IWL_ERR(priv, "(2nd byte of CSR_INT_COALESCING is "
2105 "CSR_INT_PERIODIC_REG)\n");
2106 for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) {
2107 IWL_ERR(priv, " %25s: 0X%08x\n",
2108 get_csr_string(csr_tbl[i]),
2109 iwl_read32(priv, csr_tbl[i]));
2110 }
2111 }
2112
2113 static const char *get_fh_string(int cmd)
2114 {
2115 switch (cmd) {
2116 IWL_CMD(FH_RSCSR_CHNL0_STTS_WPTR_REG);
2117 IWL_CMD(FH_RSCSR_CHNL0_RBDCB_BASE_REG);
2118 IWL_CMD(FH_RSCSR_CHNL0_WPTR);
2119 IWL_CMD(FH_MEM_RCSR_CHNL0_CONFIG_REG);
2120 IWL_CMD(FH_MEM_RSSR_SHARED_CTRL_REG);
2121 IWL_CMD(FH_MEM_RSSR_RX_STATUS_REG);
2122 IWL_CMD(FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV);
2123 IWL_CMD(FH_TSSR_TX_STATUS_REG);
2124 IWL_CMD(FH_TSSR_TX_ERROR_REG);
2125 default:
2126 return "UNKNOWN";
2127 }
2128 }
2129
2130 int iwl_dump_fh(struct iwl_priv *priv, char **buf, bool display)
2131 {
2132 int i;
2133 #ifdef CONFIG_IWLWIFI_DEBUG
2134 int pos = 0;
2135 size_t bufsz = 0;
2136 #endif
2137 static const u32 fh_tbl[] = {
2138 FH_RSCSR_CHNL0_STTS_WPTR_REG,
2139 FH_RSCSR_CHNL0_RBDCB_BASE_REG,
2140 FH_RSCSR_CHNL0_WPTR,
2141 FH_MEM_RCSR_CHNL0_CONFIG_REG,
2142 FH_MEM_RSSR_SHARED_CTRL_REG,
2143 FH_MEM_RSSR_RX_STATUS_REG,
2144 FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV,
2145 FH_TSSR_TX_STATUS_REG,
2146 FH_TSSR_TX_ERROR_REG
2147 };
2148 #ifdef CONFIG_IWLWIFI_DEBUG
2149 if (display) {
2150 bufsz = ARRAY_SIZE(fh_tbl) * 48 + 40;
2151 *buf = kmalloc(bufsz, GFP_KERNEL);
2152 if (!*buf)
2153 return -ENOMEM;
2154 pos += scnprintf(*buf + pos, bufsz - pos,
2155 "FH register values:\n");
2156 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
2157 pos += scnprintf(*buf + pos, bufsz - pos,
2158 " %34s: 0X%08x\n",
2159 get_fh_string(fh_tbl[i]),
2160 iwl_read_direct32(priv, fh_tbl[i]));
2161 }
2162 return pos;
2163 }
2164 #endif
2165 IWL_ERR(priv, "FH register values:\n");
2166 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) {
2167 IWL_ERR(priv, " %34s: 0X%08x\n",
2168 get_fh_string(fh_tbl[i]),
2169 iwl_read_direct32(priv, fh_tbl[i]));
2170 }
2171 return 0;
2172 }
2173
2174 /* notification wait support */
2175 void iwlagn_init_notification_wait(struct iwl_priv *priv,
2176 struct iwl_notification_wait *wait_entry,
2177 void (*fn)(struct iwl_priv *priv,
2178 struct iwl_rx_packet *pkt),
2179 u8 cmd)
2180 {
2181 wait_entry->fn = fn;
2182 wait_entry->cmd = cmd;
2183 wait_entry->triggered = false;
2184
2185 spin_lock_bh(&priv->_agn.notif_wait_lock);
2186 list_add(&wait_entry->list, &priv->_agn.notif_waits);
2187 spin_unlock_bh(&priv->_agn.notif_wait_lock);
2188 }
2189
2190 signed long iwlagn_wait_notification(struct iwl_priv *priv,
2191 struct iwl_notification_wait *wait_entry,
2192 unsigned long timeout)
2193 {
2194 int ret;
2195
2196 ret = wait_event_timeout(priv->_agn.notif_waitq,
2197 &wait_entry->triggered,
2198 timeout);
2199
2200 spin_lock_bh(&priv->_agn.notif_wait_lock);
2201 list_del(&wait_entry->list);
2202 spin_unlock_bh(&priv->_agn.notif_wait_lock);
2203
2204 return ret;
2205 }
2206
2207 void iwlagn_remove_notification(struct iwl_priv *priv,
2208 struct iwl_notification_wait *wait_entry)
2209 {
2210 spin_lock_bh(&priv->_agn.notif_wait_lock);
2211 list_del(&wait_entry->list);
2212 spin_unlock_bh(&priv->_agn.notif_wait_lock);
2213 }
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree