drivers/gpu/drm/radeon/radeon.h

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #ifndef __RADEON_H__
  29 #define __RADEON_H__
  30
  31 /* TODO: Here are things that needs to be done :
  32  *      - surface allocator & initializer : (bit like scratch reg) should
  33  *        initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
  34  *        related to surface
  35  *      - WB : write back stuff (do it bit like scratch reg things)
  36  *      - Vblank : look at Jesse's rework and what we should do
  37  *      - r600/r700: gart & cp
  38  *      - cs : clean cs ioctl use bitmap & things like that.
  39  *      - power management stuff
  40  *      - Barrier in gart code
  41  *      - Unmappabled vram ?
  42  *      - TESTING, TESTING, TESTING
  43  */
  44
  45 /* Initialization path:
  46  *  We expect that acceleration initialization might fail for various
  47  *  reasons even thought we work hard to make it works on most
  48  *  configurations. In order to still have a working userspace in such
  49  *  situation the init path must succeed up to the memory controller
  50  *  initialization point. Failure before this point are considered as
  51  *  fatal error. Here is the init callchain :
  52  *      radeon_device_init  perform common structure, mutex initialization
  53  *      asic_init           setup the GPU memory layout and perform all
  54  *                          one time initialization (failure in this
  55  *                          function are considered fatal)
  56  *      asic_startup        setup the GPU acceleration, in order to
  57  *                          follow guideline the first thing this
  58  *                          function should do is setting the GPU
  59  *                          memory controller (only MC setup failure
  60  *                          are considered as fatal)
  61  */
  62
  63 #include <asm/atomic.h>
  64 #include <linux/wait.h>
  65 #include <linux/list.h>
  66 #include <linux/kref.h>
  67
  68 #include <ttm/ttm_bo_api.h>
  69 #include <ttm/ttm_bo_driver.h>
  70 #include <ttm/ttm_placement.h>
  71 #include <ttm/ttm_module.h>
  72 #include <ttm/ttm_execbuf_util.h>
  73
  74 #include "radeon_family.h"
  75 #include "radeon_mode.h"
  76 #include "radeon_reg.h"
  77
  78 /*
  79  * Modules parameters.
  80  */
  81 extern int radeon_no_wb;
  82 extern int radeon_modeset;
  83 extern int radeon_dynclks;
  84 extern int radeon_r4xx_atom;
  85 extern int radeon_agpmode;
  86 extern int radeon_vram_limit;
  87 extern int radeon_gart_size;
  88 extern int radeon_benchmarking;
  89 extern int radeon_testing;
  90 extern int radeon_connector_table;
  91 extern int radeon_tv;
  92 extern int radeon_audio;
  93 extern int radeon_disp_priority;
  94 extern int radeon_hw_i2c;
  95 extern int radeon_pcie_gen2;
  96
  97 /*
  98  * Copy from radeon_drv.h so we don't have to include both and have conflicting
  99  * symbol;
 100  */
 101 #define RADEON_MAX_USEC_TIMEOUT         100000  /* 100 ms */
 102 #define RADEON_FENCE_JIFFIES_TIMEOUT    (HZ / 2)
 103 /* RADEON_IB_POOL_SIZE must be a power of 2 */
 104 #define RADEON_IB_POOL_SIZE             16
 105 #define RADEON_DEBUGFS_MAX_NUM_FILES    32
 106 #define RADEONFB_CONN_LIMIT             4
 107 #define RADEON_BIOS_NUM_SCRATCH         8
 108
 109 /*
 110  * Errata workarounds.
 111  */
 112 enum radeon_pll_errata {
 113         CHIP_ERRATA_R300_CG             = 0x00000001,
 114         CHIP_ERRATA_PLL_DUMMYREADS      = 0x00000002,
 115         CHIP_ERRATA_PLL_DELAY           = 0x00000004
 116 };
 117
 118
 119 struct radeon_device;
 120
 121
 122 /*
 123  * BIOS.
 124  */
 125 #define ATRM_BIOS_PAGE 4096
 126
 127 #if defined(CONFIG_VGA_SWITCHEROO)
 128 bool radeon_atrm_supported(struct pci_dev *pdev);
 129 int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len);
 130 #else
 131 static inline bool radeon_atrm_supported(struct pci_dev *pdev)
 132 {
 133         return false;
 134 }
 135
 136 static inline int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len){
 137         return -EINVAL;
 138 }
 139 #endif
 140 bool radeon_get_bios(struct radeon_device *rdev);
 141
 142
 143 /*
 144  * Dummy page
 145  */
 146 struct radeon_dummy_page {
 147         struct page     *page;
 148         dma_addr_t      addr;
 149 };
 150 int radeon_dummy_page_init(struct radeon_device *rdev);
 151 void radeon_dummy_page_fini(struct radeon_device *rdev);
 152
 153
 154 /*
 155  * Clocks
 156  */
 157 struct radeon_clock {
 158         struct radeon_pll p1pll;
 159         struct radeon_pll p2pll;
 160         struct radeon_pll dcpll;
 161         struct radeon_pll spll;
 162         struct radeon_pll mpll;
 163         /* 10 Khz units */
 164         uint32_t default_mclk;
 165         uint32_t default_sclk;
 166         uint32_t default_dispclk;
 167         uint32_t dp_extclk;
 168 };
 169
 170 /*
 171  * Power management
 172  */
 173 int radeon_pm_init(struct radeon_device *rdev);
 174 void radeon_pm_fini(struct radeon_device *rdev);
 175 void radeon_pm_compute_clocks(struct radeon_device *rdev);
 176 void radeon_pm_suspend(struct radeon_device *rdev);
 177 void radeon_pm_resume(struct radeon_device *rdev);
 178 void radeon_combios_get_power_modes(struct radeon_device *rdev);
 179 void radeon_atombios_get_power_modes(struct radeon_device *rdev);
 180 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 level);
 181 void rs690_pm_info(struct radeon_device *rdev);
 182 extern int rv6xx_get_temp(struct radeon_device *rdev);
 183 extern int rv770_get_temp(struct radeon_device *rdev);
 184 extern int evergreen_get_temp(struct radeon_device *rdev);
 185 extern int sumo_get_temp(struct radeon_device *rdev);
 186
 187 /*
 188  * Fences.
 189  */
 190 struct radeon_fence_driver {
 191         uint32_t                        scratch_reg;
 192         atomic_t                        seq;
 193         uint32_t                        last_seq;
 194         unsigned long                   last_jiffies;
 195         unsigned long                   last_timeout;
 196         wait_queue_head_t               queue;
 197         rwlock_t                        lock;
 198         struct list_head                created;
 199         struct list_head                emited;
 200         struct list_head                signaled;
 201         bool                            initialized;
 202 };
 203
 204 struct radeon_fence {
 205         struct radeon_device            *rdev;
 206         struct kref                     kref;
 207         struct list_head                list;
 208         /* protected by radeon_fence.lock */
 209         uint32_t                        seq;
 210         bool                            emited;
 211         bool                            signaled;
 212 };
 213
 214 int radeon_fence_driver_init(struct radeon_device *rdev);
 215 void radeon_fence_driver_fini(struct radeon_device *rdev);
 216 int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence);
 217 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence);
 218 void radeon_fence_process(struct radeon_device *rdev);
 219 bool radeon_fence_signaled(struct radeon_fence *fence);
 220 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
 221 int radeon_fence_wait_next(struct radeon_device *rdev);
 222 int radeon_fence_wait_last(struct radeon_device *rdev);
 223 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
 224 void radeon_fence_unref(struct radeon_fence **fence);
 225
 226 /*
 227  * Tiling registers
 228  */
 229 struct radeon_surface_reg {
 230         struct radeon_bo *bo;
 231 };
 232
 233 #define RADEON_GEM_MAX_SURFACES 8
 234
 235 /*
 236  * TTM.
 237  */
 238 struct radeon_mman {
 239         struct ttm_bo_global_ref        bo_global_ref;
 240         struct drm_global_reference     mem_global_ref;
 241         struct ttm_bo_device            bdev;
 242         bool                            mem_global_referenced;
 243         bool                            initialized;
 244 };
 245
 246 struct radeon_bo {
 247         /* Protected by gem.mutex */
 248         struct list_head                list;
 249         /* Protected by tbo.reserved */
 250         u32                             placements[3];
 251         struct ttm_placement            placement;
 252         struct ttm_buffer_object        tbo;
 253         struct ttm_bo_kmap_obj          kmap;
 254         unsigned                        pin_count;
 255         void                            *kptr;
 256         u32                             tiling_flags;
 257         u32                             pitch;
 258         int                             surface_reg;
 259         /* Constant after initialization */
 260         struct radeon_device            *rdev;
 261         struct drm_gem_object           gem_base;
 262 };
 263 #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base)
 264
 265 struct radeon_bo_list {
 266         struct ttm_validate_buffer tv;
 267         struct radeon_bo        *bo;
 268         uint64_t                gpu_offset;
 269         unsigned                rdomain;
 270         unsigned                wdomain;
 271         u32                     tiling_flags;
 272 };
 273
 274 /*
 275  * GEM objects.
 276  */
 277 struct radeon_gem {
 278         struct mutex            mutex;
 279         struct list_head        objects;
 280 };
 281
 282 int radeon_gem_init(struct radeon_device *rdev);
 283 void radeon_gem_fini(struct radeon_device *rdev);
 284 int radeon_gem_object_create(struct radeon_device *rdev, int size,
 285                                 int alignment, int initial_domain,
 286                                 bool discardable, bool kernel,
 287                                 struct drm_gem_object **obj);
 288 int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain,
 289                           uint64_t *gpu_addr);
 290 void radeon_gem_object_unpin(struct drm_gem_object *obj);
 291
 292 int radeon_mode_dumb_create(struct drm_file *file_priv,
 293                             struct drm_device *dev,
 294                             struct drm_mode_create_dumb *args);
 295 int radeon_mode_dumb_mmap(struct drm_file *filp,
 296                           struct drm_device *dev,
 297                           uint32_t handle, uint64_t *offset_p);
 298 int radeon_mode_dumb_destroy(struct drm_file *file_priv,
 299                              struct drm_device *dev,
 300                              uint32_t handle);
 301
 302 /*
 303  * GART structures, functions & helpers
 304  */
 305 struct radeon_mc;
 306
 307 struct radeon_gart_table_ram {
 308         volatile uint32_t               *ptr;
 309 };
 310
 311 struct radeon_gart_table_vram {
 312         struct radeon_bo                *robj;
 313         volatile uint32_t               *ptr;
 314 };
 315
 316 union radeon_gart_table {
 317         struct radeon_gart_table_ram    ram;
 318         struct radeon_gart_table_vram   vram;
 319 };
 320
 321 #define RADEON_GPU_PAGE_SIZE 4096
 322 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
 323
 324 struct radeon_gart {
 325         dma_addr_t                      table_addr;
 326         unsigned                        num_gpu_pages;
 327         unsigned                        num_cpu_pages;
 328         unsigned                        table_size;
 329         union radeon_gart_table         table;
 330         struct page                     **pages;
 331         dma_addr_t                      *pages_addr;
 332         bool                            ready;
 333 };
 334
 335 int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
 336 void radeon_gart_table_ram_free(struct radeon_device *rdev);
 337 int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
 338 void radeon_gart_table_vram_free(struct radeon_device *rdev);
 339 int radeon_gart_init(struct radeon_device *rdev);
 340 void radeon_gart_fini(struct radeon_device *rdev);
 341 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
 342                         int pages);
 343 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
 344                      int pages, struct page **pagelist);
 345
 346
 347 /*
 348  * GPU MC structures, functions & helpers
 349  */
 350 struct radeon_mc {
 351         resource_size_t         aper_size;
 352         resource_size_t         aper_base;
 353         resource_size_t         agp_base;
 354         /* for some chips with <= 32MB we need to lie
 355          * about vram size near mc fb location */
 356         u64                     mc_vram_size;
 357         u64                     visible_vram_size;
 358         u64                     active_vram_size;
 359         u64                     gtt_size;
 360         u64                     gtt_start;
 361         u64                     gtt_end;
 362         u64                     vram_start;
 363         u64                     vram_end;
 364         unsigned                vram_width;
 365         u64                     real_vram_size;
 366         int                     vram_mtrr;
 367         bool                    vram_is_ddr;
 368         bool                    igp_sideport_enabled;
 369         u64                     gtt_base_align;
 370 };
 371
 372 bool radeon_combios_sideport_present(struct radeon_device *rdev);
 373 bool radeon_atombios_sideport_present(struct radeon_device *rdev);
 374
 375 /*
 376  * GPU scratch registers structures, functions & helpers
 377  */
 378 struct radeon_scratch {
 379         unsigned                num_reg;
 380         uint32_t                reg_base;
 381         bool                    free[32];
 382         uint32_t                reg[32];
 383 };
 384
 385 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
 386 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
 387
 388
 389 /*
 390  * IRQS.
 391  */
 392
 393 struct radeon_unpin_work {
 394         struct work_struct work;
 395         struct radeon_device *rdev;
 396         int crtc_id;
 397         struct radeon_fence *fence;
 398         struct drm_pending_vblank_event *event;
 399         struct radeon_bo *old_rbo;
 400         u64 new_crtc_base;
 401 };
 402
 403 struct r500_irq_stat_regs {
 404         u32 disp_int;
 405 };
 406
 407 struct r600_irq_stat_regs {
 408         u32 disp_int;
 409         u32 disp_int_cont;
 410         u32 disp_int_cont2;
 411         u32 d1grph_int;
 412         u32 d2grph_int;
 413 };
 414
 415 struct evergreen_irq_stat_regs {
 416         u32 disp_int;
 417         u32 disp_int_cont;
 418         u32 disp_int_cont2;
 419         u32 disp_int_cont3;
 420         u32 disp_int_cont4;
 421         u32 disp_int_cont5;
 422         u32 d1grph_int;
 423         u32 d2grph_int;
 424         u32 d3grph_int;
 425         u32 d4grph_int;
 426         u32 d5grph_int;
 427         u32 d6grph_int;
 428 };
 429
 430 union radeon_irq_stat_regs {
 431         struct r500_irq_stat_regs r500;
 432         struct r600_irq_stat_regs r600;
 433         struct evergreen_irq_stat_regs evergreen;
 434 };
 435
 436 struct radeon_irq {
 437         bool            installed;
 438         bool            sw_int;
 439         /* FIXME: use a define max crtc rather than hardcode it */
 440         bool            crtc_vblank_int[6];
 441         bool            pflip[6];
 442         wait_queue_head_t       vblank_queue;
 443         /* FIXME: use defines for max hpd/dacs */
 444         bool            hpd[6];
 445         bool            gui_idle;
 446         bool            gui_idle_acked;
 447         wait_queue_head_t       idle_queue;
 448         /* FIXME: use defines for max HDMI blocks */
 449         bool            hdmi[2];
 450         spinlock_t sw_lock;
 451         int sw_refcount;
 452         union radeon_irq_stat_regs stat_regs;
 453         spinlock_t pflip_lock[6];
 454         int pflip_refcount[6];
 455 };
 456
 457 int radeon_irq_kms_init(struct radeon_device *rdev);
 458 void radeon_irq_kms_fini(struct radeon_device *rdev);
 459 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev);
 460 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev);
 461 void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc);
 462 void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc);
 463
 464 /*
 465  * CP & ring.
 466  */
 467 struct radeon_ib {
 468         struct list_head        list;
 469         unsigned                idx;
 470         uint64_t                gpu_addr;
 471         struct radeon_fence     *fence;
 472         uint32_t                *ptr;
 473         uint32_t                length_dw;
 474         bool                    free;
 475 };
 476
 477 /*
 478  * locking -
 479  * mutex protects scheduled_ibs, ready, alloc_bm
 480  */
 481 struct radeon_ib_pool {
 482         struct mutex            mutex;
 483         struct radeon_bo        *robj;
 484         struct list_head        bogus_ib;
 485         struct radeon_ib        ibs[RADEON_IB_POOL_SIZE];
 486         bool                    ready;
 487         unsigned                head_id;
 488 };
 489
 490 struct radeon_cp {
 491         struct radeon_bo        *ring_obj;
 492         volatile uint32_t       *ring;
 493         unsigned                rptr;
 494         unsigned                wptr;
 495         unsigned                wptr_old;
 496         unsigned                ring_size;
 497         unsigned                ring_free_dw;
 498         int                     count_dw;
 499         uint64_t                gpu_addr;
 500         uint32_t                align_mask;
 501         uint32_t                ptr_mask;
 502         struct mutex            mutex;
 503         bool                    ready;
 504 };
 505
 506 /*
 507  * R6xx+ IH ring
 508  */
 509 struct r600_ih {
 510         struct radeon_bo        *ring_obj;
 511         volatile uint32_t       *ring;
 512         unsigned                rptr;
 513         unsigned                wptr;
 514         unsigned                wptr_old;
 515         unsigned                ring_size;
 516         uint64_t                gpu_addr;
 517         uint32_t                ptr_mask;
 518         spinlock_t              lock;
 519         bool                    enabled;
 520 };
 521
 522 struct r600_blit {
 523         struct mutex            mutex;
 524         struct radeon_bo        *shader_obj;
 525         u64 shader_gpu_addr;
 526         u32 vs_offset, ps_offset;
 527         u32 state_offset;
 528         u32 state_len;
 529         u32 vb_used, vb_total;
 530         struct radeon_ib *vb_ib;
 531 };
 532
 533 int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib);
 534 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib);
 535 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib);
 536 int radeon_ib_pool_init(struct radeon_device *rdev);
 537 void radeon_ib_pool_fini(struct radeon_device *rdev);
 538 int radeon_ib_test(struct radeon_device *rdev);
 539 extern void radeon_ib_bogus_add(struct radeon_device *rdev, struct radeon_ib *ib);
 540 /* Ring access between begin & end cannot sleep */
 541 void radeon_ring_free_size(struct radeon_device *rdev);
 542 int radeon_ring_alloc(struct radeon_device *rdev, unsigned ndw);
 543 int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw);
 544 void radeon_ring_commit(struct radeon_device *rdev);
 545 void radeon_ring_unlock_commit(struct radeon_device *rdev);
 546 void radeon_ring_unlock_undo(struct radeon_device *rdev);
 547 int radeon_ring_test(struct radeon_device *rdev);
 548 int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size);
 549 void radeon_ring_fini(struct radeon_device *rdev);
 550
 551
 552 /*
 553  * CS.
 554  */
 555 struct radeon_cs_reloc {
 556         struct drm_gem_object           *gobj;
 557         struct radeon_bo                *robj;
 558         struct radeon_bo_list           lobj;
 559         uint32_t                        handle;
 560         uint32_t                        flags;
 561 };
 562
 563 struct radeon_cs_chunk {
 564         uint32_t                chunk_id;
 565         uint32_t                length_dw;
 566         int kpage_idx[2];
 567         uint32_t                *kpage[2];
 568         uint32_t                *kdata;
 569         void __user *user_ptr;
 570         int last_copied_page;
 571         int last_page_index;
 572 };
 573
 574 struct radeon_cs_parser {
 575         struct device           *dev;
 576         struct radeon_device    *rdev;
 577         struct drm_file         *filp;
 578         /* chunks */
 579         unsigned                nchunks;
 580         struct radeon_cs_chunk  *chunks;
 581         uint64_t                *chunks_array;
 582         /* IB */
 583         unsigned                idx;
 584         /* relocations */
 585         unsigned                nrelocs;
 586         struct radeon_cs_reloc  *relocs;
 587         struct radeon_cs_reloc  **relocs_ptr;
 588         struct list_head        validated;
 589         /* indices of various chunks */
 590         int                     chunk_ib_idx;
 591         int                     chunk_relocs_idx;
 592         struct radeon_ib        *ib;
 593         void                    *track;
 594         unsigned                family;
 595         int parser_error;
 596 };
 597
 598 extern int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx);
 599 extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
 600
 601
 602 static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
 603 {
 604         struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
 605         u32 pg_idx, pg_offset;
 606         u32 idx_value = 0;
 607         int new_page;
 608
 609         pg_idx = (idx * 4) / PAGE_SIZE;
 610         pg_offset = (idx * 4) % PAGE_SIZE;
 611
 612         if (ibc->kpage_idx[0] == pg_idx)
 613                 return ibc->kpage[0][pg_offset/4];
 614         if (ibc->kpage_idx[1] == pg_idx)
 615                 return ibc->kpage[1][pg_offset/4];
 616
 617         new_page = radeon_cs_update_pages(p, pg_idx);
 618         if (new_page < 0) {
 619                 p->parser_error = new_page;
 620                 return 0;
 621         }
 622
 623         idx_value = ibc->kpage[new_page][pg_offset/4];
 624         return idx_value;
 625 }
 626
 627 struct radeon_cs_packet {
 628         unsigned        idx;
 629         unsigned        type;
 630         unsigned        reg;
 631         unsigned        opcode;
 632         int             count;
 633         unsigned        one_reg_wr;
 634 };
 635
 636 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
 637                                       struct radeon_cs_packet *pkt,
 638                                       unsigned idx, unsigned reg);
 639 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
 640                                       struct radeon_cs_packet *pkt);
 641
 642
 643 /*
 644  * AGP
 645  */
 646 int radeon_agp_init(struct radeon_device *rdev);
 647 void radeon_agp_resume(struct radeon_device *rdev);
 648 void radeon_agp_suspend(struct radeon_device *rdev);
 649 void radeon_agp_fini(struct radeon_device *rdev);
 650
 651
 652 /*
 653  * Writeback
 654  */
 655 struct radeon_wb {
 656         struct radeon_bo        *wb_obj;
 657         volatile uint32_t       *wb;
 658         uint64_t                gpu_addr;
 659         bool                    enabled;
 660         bool                    use_event;
 661 };
 662
 663 #define RADEON_WB_SCRATCH_OFFSET 0
 664 #define RADEON_WB_CP_RPTR_OFFSET 1024
 665 #define R600_WB_IH_WPTR_OFFSET   2048
 666 #define R600_WB_EVENT_OFFSET     3072
 667
 668 /**
 669  * struct radeon_pm - power management datas
 670  * @max_bandwidth:      maximum bandwidth the gpu has (MByte/s)
 671  * @igp_sideport_mclk:  sideport memory clock Mhz (rs690,rs740,rs780,rs880)
 672  * @igp_system_mclk:    system clock Mhz (rs690,rs740,rs780,rs880)
 673  * @igp_ht_link_clk:    ht link clock Mhz (rs690,rs740,rs780,rs880)
 674  * @igp_ht_link_width:  ht link width in bits (rs690,rs740,rs780,rs880)
 675  * @k8_bandwidth:       k8 bandwidth the gpu has (MByte/s) (IGP)
 676  * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
 677  * @ht_bandwidth:       ht bandwidth the gpu has (MByte/s) (IGP)
 678  * @core_bandwidth:     core GPU bandwidth the gpu has (MByte/s) (IGP)
 679  * @sclk:               GPU clock Mhz (core bandwith depends of this clock)
 680  * @needed_bandwidth:   current bandwidth needs
 681  *
 682  * It keeps track of various data needed to take powermanagement decision.
 683  * Bandwith need is used to determine minimun clock of the GPU and memory.
 684  * Equation between gpu/memory clock and available bandwidth is hw dependent
 685  * (type of memory, bus size, efficiency, ...)
 686  */
 687
 688 enum radeon_pm_method {
 689         PM_METHOD_PROFILE,
 690         PM_METHOD_DYNPM,
 691 };
 692
 693 enum radeon_dynpm_state {
 694         DYNPM_STATE_DISABLED,
 695         DYNPM_STATE_MINIMUM,
 696         DYNPM_STATE_PAUSED,
 697         DYNPM_STATE_ACTIVE,
 698         DYNPM_STATE_SUSPENDED,
 699 };
 700 enum radeon_dynpm_action {
 701         DYNPM_ACTION_NONE,
 702         DYNPM_ACTION_MINIMUM,
 703         DYNPM_ACTION_DOWNCLOCK,
 704         DYNPM_ACTION_UPCLOCK,
 705         DYNPM_ACTION_DEFAULT
 706 };
 707
 708 enum radeon_voltage_type {
 709         VOLTAGE_NONE = 0,
 710         VOLTAGE_GPIO,
 711         VOLTAGE_VDDC,
 712         VOLTAGE_SW
 713 };
 714
 715 enum radeon_pm_state_type {
 716         POWER_STATE_TYPE_DEFAULT,
 717         POWER_STATE_TYPE_POWERSAVE,
 718         POWER_STATE_TYPE_BATTERY,
 719         POWER_STATE_TYPE_BALANCED,
 720         POWER_STATE_TYPE_PERFORMANCE,
 721 };
 722
 723 enum radeon_pm_profile_type {
 724         PM_PROFILE_DEFAULT,
 725         PM_PROFILE_AUTO,
 726         PM_PROFILE_LOW,
 727         PM_PROFILE_MID,
 728         PM_PROFILE_HIGH,
 729 };
 730
 731 #define PM_PROFILE_DEFAULT_IDX 0
 732 #define PM_PROFILE_LOW_SH_IDX  1
 733 #define PM_PROFILE_MID_SH_IDX  2
 734 #define PM_PROFILE_HIGH_SH_IDX 3
 735 #define PM_PROFILE_LOW_MH_IDX  4
 736 #define PM_PROFILE_MID_MH_IDX  5
 737 #define PM_PROFILE_HIGH_MH_IDX 6
 738 #define PM_PROFILE_MAX         7
 739
 740 struct radeon_pm_profile {
 741         int dpms_off_ps_idx;
 742         int dpms_on_ps_idx;
 743         int dpms_off_cm_idx;
 744         int dpms_on_cm_idx;
 745 };
 746
 747 enum radeon_int_thermal_type {
 748         THERMAL_TYPE_NONE,
 749         THERMAL_TYPE_RV6XX,
 750         THERMAL_TYPE_RV770,
 751         THERMAL_TYPE_EVERGREEN,
 752         THERMAL_TYPE_SUMO,
 753         THERMAL_TYPE_NI,
 754 };
 755
 756 struct radeon_voltage {
 757         enum radeon_voltage_type type;
 758         /* gpio voltage */
 759         struct radeon_gpio_rec gpio;
 760         u32 delay; /* delay in usec from voltage drop to sclk change */
 761         bool active_high; /* voltage drop is active when bit is high */
 762         /* VDDC voltage */
 763         u8 vddc_id; /* index into vddc voltage table */
 764         u8 vddci_id; /* index into vddci voltage table */
 765         bool vddci_enabled;
 766         /* r6xx+ sw */
 767         u32 voltage;
 768 };
 769
 770 /* clock mode flags */
 771 #define RADEON_PM_MODE_NO_DISPLAY          (1 << 0)
 772
 773 struct radeon_pm_clock_info {
 774         /* memory clock */
 775         u32 mclk;
 776         /* engine clock */
 777         u32 sclk;
 778         /* voltage info */
 779         struct radeon_voltage voltage;
 780         /* standardized clock flags */
 781         u32 flags;
 782 };
 783
 784 /* state flags */
 785 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
 786
 787 struct radeon_power_state {
 788         enum radeon_pm_state_type type;
 789         /* XXX: use a define for num clock modes */
 790         struct radeon_pm_clock_info clock_info[8];
 791         /* number of valid clock modes in this power state */
 792         int num_clock_modes;
 793         struct radeon_pm_clock_info *default_clock_mode;
 794         /* standardized state flags */
 795         u32 flags;
 796         u32 misc; /* vbios specific flags */
 797         u32 misc2; /* vbios specific flags */
 798         int pcie_lanes; /* pcie lanes */
 799 };
 800
 801 /*
 802  * Some modes are overclocked by very low value, accept them
 803  */
 804 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
 805
 806 struct radeon_pm {
 807         struct mutex            mutex;
 808         u32                     active_crtcs;
 809         int                     active_crtc_count;
 810         int                     req_vblank;
 811         bool                    vblank_sync;
 812         bool                    gui_idle;
 813         fixed20_12              max_bandwidth;
 814         fixed20_12              igp_sideport_mclk;
 815         fixed20_12              igp_system_mclk;
 816         fixed20_12              igp_ht_link_clk;
 817         fixed20_12              igp_ht_link_width;
 818         fixed20_12              k8_bandwidth;
 819         fixed20_12              sideport_bandwidth;
 820         fixed20_12              ht_bandwidth;
 821         fixed20_12              core_bandwidth;
 822         fixed20_12              sclk;
 823         fixed20_12              mclk;
 824         fixed20_12              needed_bandwidth;
 825         struct radeon_power_state *power_state;
 826         /* number of valid power states */
 827         int                     num_power_states;
 828         int                     current_power_state_index;
 829         int                     current_clock_mode_index;
 830         int                     requested_power_state_index;
 831         int                     requested_clock_mode_index;
 832         int                     default_power_state_index;
 833         u32                     current_sclk;
 834         u32                     current_mclk;
 835         u32                     current_vddc;
 836         u32                     default_sclk;
 837         u32                     default_mclk;
 838         u32                     default_vddc;
 839         struct radeon_i2c_chan *i2c_bus;
 840         /* selected pm method */
 841         enum radeon_pm_method     pm_method;
 842         /* dynpm power management */
 843         struct delayed_work     dynpm_idle_work;
 844         enum radeon_dynpm_state dynpm_state;
 845         enum radeon_dynpm_action        dynpm_planned_action;
 846         unsigned long           dynpm_action_timeout;
 847         bool                    dynpm_can_upclock;
 848         bool                    dynpm_can_downclock;
 849         /* profile-based power management */
 850         enum radeon_pm_profile_type profile;
 851         int                     profile_index;
 852         struct radeon_pm_profile profiles[PM_PROFILE_MAX];
 853         /* internal thermal controller on rv6xx+ */
 854         enum radeon_int_thermal_type int_thermal_type;
 855         struct device           *int_hwmon_dev;
 856 };
 857
 858
 859 /*
 860  * Benchmarking
 861  */
 862 void radeon_benchmark(struct radeon_device *rdev);
 863
 864
 865 /*
 866  * Testing
 867  */
 868 void radeon_test_moves(struct radeon_device *rdev);
 869
 870
 871 /*
 872  * Debugfs
 873  */
 874 int radeon_debugfs_add_files(struct radeon_device *rdev,
 875                              struct drm_info_list *files,
 876                              unsigned nfiles);
 877 int radeon_debugfs_fence_init(struct radeon_device *rdev);
 878
 879
 880 /*
 881  * ASIC specific functions.
 882  */
 883 struct radeon_asic {
 884         int (*init)(struct radeon_device *rdev);
 885         void (*fini)(struct radeon_device *rdev);
 886         int (*resume)(struct radeon_device *rdev);
 887         int (*suspend)(struct radeon_device *rdev);
 888         void (*vga_set_state)(struct radeon_device *rdev, bool state);
 889         bool (*gpu_is_lockup)(struct radeon_device *rdev);
 890         int (*asic_reset)(struct radeon_device *rdev);
 891         void (*gart_tlb_flush)(struct radeon_device *rdev);
 892         int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr);
 893         int (*cp_init)(struct radeon_device *rdev, unsigned ring_size);
 894         void (*cp_fini)(struct radeon_device *rdev);
 895         void (*cp_disable)(struct radeon_device *rdev);
 896         void (*cp_commit)(struct radeon_device *rdev);
 897         void (*ring_start)(struct radeon_device *rdev);
 898         int (*ring_test)(struct radeon_device *rdev);
 899         void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
 900         int (*irq_set)(struct radeon_device *rdev);
 901         int (*irq_process)(struct radeon_device *rdev);
 902         u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
 903         void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence);
 904         int (*cs_parse)(struct radeon_cs_parser *p);
 905         int (*copy_blit)(struct radeon_device *rdev,
 906                          uint64_t src_offset,
 907                          uint64_t dst_offset,
 908                          unsigned num_pages,
 909                          struct radeon_fence *fence);
 910         int (*copy_dma)(struct radeon_device *rdev,
 911                         uint64_t src_offset,
 912                         uint64_t dst_offset,
 913                         unsigned num_pages,
 914                         struct radeon_fence *fence);
 915         int (*copy)(struct radeon_device *rdev,
 916                     uint64_t src_offset,
 917                     uint64_t dst_offset,
 918                     unsigned num_pages,
 919                     struct radeon_fence *fence);
 920         uint32_t (*get_engine_clock)(struct radeon_device *rdev);
 921         void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
 922         uint32_t (*get_memory_clock)(struct radeon_device *rdev);
 923         void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
 924         int (*get_pcie_lanes)(struct radeon_device *rdev);
 925         void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
 926         void (*set_clock_gating)(struct radeon_device *rdev, int enable);
 927         int (*set_surface_reg)(struct radeon_device *rdev, int reg,
 928                                uint32_t tiling_flags, uint32_t pitch,
 929                                uint32_t offset, uint32_t obj_size);
 930         void (*clear_surface_reg)(struct radeon_device *rdev, int reg);
 931         void (*bandwidth_update)(struct radeon_device *rdev);
 932         void (*hpd_init)(struct radeon_device *rdev);
 933         void (*hpd_fini)(struct radeon_device *rdev);
 934         bool (*hpd_sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
 935         void (*hpd_set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
 936         /* ioctl hw specific callback. Some hw might want to perform special
 937          * operation on specific ioctl. For instance on wait idle some hw
 938          * might want to perform and HDP flush through MMIO as it seems that
 939          * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
 940          * through ring.
 941          */
 942         void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
 943         bool (*gui_idle)(struct radeon_device *rdev);
 944         /* power management */
 945         void (*pm_misc)(struct radeon_device *rdev);
 946         void (*pm_prepare)(struct radeon_device *rdev);
 947         void (*pm_finish)(struct radeon_device *rdev);
 948         void (*pm_init_profile)(struct radeon_device *rdev);
 949         void (*pm_get_dynpm_state)(struct radeon_device *rdev);
 950         /* pageflipping */
 951         void (*pre_page_flip)(struct radeon_device *rdev, int crtc);
 952         u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base);
 953         void (*post_page_flip)(struct radeon_device *rdev, int crtc);
 954 };
 955
 956 /*
 957  * Asic structures
 958  */
 959 struct r100_gpu_lockup {
 960         unsigned long   last_jiffies;
 961         u32             last_cp_rptr;
 962 };
 963
 964 struct r100_asic {
 965         const unsigned          *reg_safe_bm;
 966         unsigned                reg_safe_bm_size;
 967         u32                     hdp_cntl;
 968         struct r100_gpu_lockup  lockup;
 969 };
 970
 971 struct r300_asic {
 972         const unsigned          *reg_safe_bm;
 973         unsigned                reg_safe_bm_size;
 974         u32                     resync_scratch;
 975         u32                     hdp_cntl;
 976         struct r100_gpu_lockup  lockup;
 977 };
 978
 979 struct r600_asic {
 980         unsigned                max_pipes;
 981         unsigned                max_tile_pipes;
 982         unsigned                max_simds;
 983         unsigned                max_backends;
 984         unsigned                max_gprs;
 985         unsigned                max_threads;
 986         unsigned                max_stack_entries;
 987         unsigned                max_hw_contexts;
 988         unsigned                max_gs_threads;
 989         unsigned                sx_max_export_size;
 990         unsigned                sx_max_export_pos_size;
 991         unsigned                sx_max_export_smx_size;
 992         unsigned                sq_num_cf_insts;
 993         unsigned                tiling_nbanks;
 994         unsigned                tiling_npipes;
 995         unsigned                tiling_group_size;
 996         unsigned                tile_config;
 997         struct r100_gpu_lockup  lockup;
 998 };
 999
1000 struct rv770_asic {
1001         unsigned                max_pipes;
1002         unsigned                max_tile_pipes;
1003         unsigned                max_simds;
1004         unsigned                max_backends;
1005         unsigned                max_gprs;
1006         unsigned                max_threads;
1007         unsigned                max_stack_entries;
1008         unsigned                max_hw_contexts;
1009         unsigned                max_gs_threads;
1010         unsigned                sx_max_export_size;
1011         unsigned                sx_max_export_pos_size;
1012         unsigned                sx_max_export_smx_size;
1013         unsigned                sq_num_cf_insts;
1014         unsigned                sx_num_of_sets;
1015         unsigned                sc_prim_fifo_size;
1016         unsigned                sc_hiz_tile_fifo_size;
1017         unsigned                sc_earlyz_tile_fifo_fize;
1018         unsigned                tiling_nbanks;
1019         unsigned                tiling_npipes;
1020         unsigned                tiling_group_size;
1021         unsigned                tile_config;
1022         struct r100_gpu_lockup  lockup;
1023 };
1024
1025 struct evergreen_asic {
1026         unsigned num_ses;
1027         unsigned max_pipes;
1028         unsigned max_tile_pipes;
1029         unsigned max_simds;
1030         unsigned max_backends;
1031         unsigned max_gprs;
1032         unsigned max_threads;
1033         unsigned max_stack_entries;
1034         unsigned max_hw_contexts;
1035         unsigned max_gs_threads;
1036         unsigned sx_max_export_size;
1037         unsigned sx_max_export_pos_size;
1038         unsigned sx_max_export_smx_size;
1039         unsigned sq_num_cf_insts;
1040         unsigned sx_num_of_sets;
1041         unsigned sc_prim_fifo_size;
1042         unsigned sc_hiz_tile_fifo_size;
1043         unsigned sc_earlyz_tile_fifo_size;
1044         unsigned tiling_nbanks;
1045         unsigned tiling_npipes;
1046         unsigned tiling_group_size;
1047         unsigned tile_config;
1048         struct r100_gpu_lockup  lockup;
1049 };
1050
1051 union radeon_asic_config {
1052         struct r300_asic        r300;
1053         struct r100_asic        r100;
1054         struct r600_asic        r600;
1055         struct rv770_asic       rv770;
1056         struct evergreen_asic   evergreen;
1057 };
1058
1059 /*
1060  * asic initizalization from radeon_asic.c
1061  */
1062 void radeon_agp_disable(struct radeon_device *rdev);
1063 int radeon_asic_init(struct radeon_device *rdev);
1064
1065
1066 /*
1067  * IOCTL.
1068  */
1069 int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
1070                           struct drm_file *filp);
1071 int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
1072                             struct drm_file *filp);
1073 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
1074                          struct drm_file *file_priv);
1075 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
1076                            struct drm_file *file_priv);
1077 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1078                             struct drm_file *file_priv);
1079 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
1080                            struct drm_file *file_priv);
1081 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1082                                 struct drm_file *filp);
1083 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
1084                           struct drm_file *filp);
1085 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
1086                           struct drm_file *filp);
1087 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1088                               struct drm_file *filp);
1089 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1090 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
1091                                 struct drm_file *filp);
1092 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
1093                                 struct drm_file *filp);
1094
1095 /* VRAM scratch page for HDP bug */
1096 struct r700_vram_scratch {
1097         struct radeon_bo                *robj;
1098         volatile uint32_t               *ptr;
1099 };
1100
1101 /*
1102  * Core structure, functions and helpers.
1103  */
1104 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
1105 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
1106
1107 struct radeon_device {
1108         struct device                   *dev;
1109         struct drm_device               *ddev;
1110         struct pci_dev                  *pdev;
1111         /* ASIC */
1112         union radeon_asic_config        config;
1113         enum radeon_family              family;
1114         unsigned long                   flags;
1115         int                             usec_timeout;
1116         enum radeon_pll_errata          pll_errata;
1117         int                             num_gb_pipes;
1118         int                             num_z_pipes;
1119         int                             disp_priority;
1120         /* BIOS */
1121         uint8_t                         *bios;
1122         bool                            is_atom_bios;
1123         uint16_t                        bios_header_start;
1124         struct radeon_bo                *stollen_vga_memory;
1125         /* Register mmio */
1126         resource_size_t                 rmmio_base;
1127         resource_size_t                 rmmio_size;
1128         void                            *rmmio;
1129         radeon_rreg_t                   mc_rreg;
1130         radeon_wreg_t                   mc_wreg;
1131         radeon_rreg_t                   pll_rreg;
1132         radeon_wreg_t                   pll_wreg;
1133         uint32_t                        pcie_reg_mask;
1134         radeon_rreg_t                   pciep_rreg;
1135         radeon_wreg_t                   pciep_wreg;
1136         /* io port */
1137         void __iomem                    *rio_mem;
1138         resource_size_t                 rio_mem_size;
1139         struct radeon_clock             clock;
1140         struct radeon_mc                mc;
1141         struct radeon_gart              gart;
1142         struct radeon_mode_info         mode_info;
1143         struct radeon_scratch           scratch;
1144         struct radeon_mman              mman;
1145         struct radeon_fence_driver      fence_drv;
1146         struct radeon_cp                cp;
1147         struct radeon_ib_pool           ib_pool;
1148         struct radeon_irq               irq;
1149         struct radeon_asic              *asic;
1150         struct radeon_gem               gem;
1151         struct radeon_pm                pm;
1152         uint32_t                        bios_scratch[RADEON_BIOS_NUM_SCRATCH];
1153         struct mutex                    cs_mutex;
1154         struct radeon_wb                wb;
1155         struct radeon_dummy_page        dummy_page;
1156         bool                            gpu_lockup;
1157         bool                            shutdown;
1158         bool                            suspend;
1159         bool                            need_dma32;
1160         bool                            accel_working;
1161         struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
1162         const struct firmware *me_fw;   /* all family ME firmware */
1163         const struct firmware *pfp_fw;  /* r6/700 PFP firmware */
1164         const struct firmware *rlc_fw;  /* r6/700 RLC firmware */
1165         const struct firmware *mc_fw;   /* NI MC firmware */
1166         struct r600_blit r600_blit;
1167         struct r700_vram_scratch vram_scratch;
1168         int msi_enabled; /* msi enabled */
1169         struct r600_ih ih; /* r6/700 interrupt ring */
1170         struct work_struct hotplug_work;
1171         int num_crtc; /* number of crtcs */
1172         struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
1173         struct mutex vram_mutex;
1174
1175         /* audio stuff */
1176         bool                    audio_enabled;
1177         struct timer_list       audio_timer;
1178         int                     audio_channels;
1179         int                     audio_rate;
1180         int                     audio_bits_per_sample;
1181         uint8_t                 audio_status_bits;
1182         uint8_t                 audio_category_code;
1183
1184         struct notifier_block acpi_nb;
1185         /* only one userspace can use Hyperz features or CMASK at a time */
1186         struct drm_file *hyperz_filp;
1187         struct drm_file *cmask_filp;
1188         /* i2c buses */
1189         struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS];
1190 };
1191
1192 int radeon_device_init(struct radeon_device *rdev,
1193                        struct drm_device *ddev,
1194                        struct pci_dev *pdev,
1195                        uint32_t flags);
1196 void radeon_device_fini(struct radeon_device *rdev);
1197 int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
1198
1199 static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
1200 {
1201         if (reg < rdev->rmmio_size)
1202                 return readl(((void __iomem *)rdev->rmmio) + reg);
1203         else {
1204                 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
1205                 return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
1206         }
1207 }
1208
1209 static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1210 {
1211         if (reg < rdev->rmmio_size)
1212                 writel(v, ((void __iomem *)rdev->rmmio) + reg);
1213         else {
1214                 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
1215                 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
1216         }
1217 }
1218
1219 static inline u32 r100_io_rreg(struct radeon_device *rdev, u32 reg)
1220 {
1221         if (reg < rdev->rio_mem_size)
1222                 return ioread32(rdev->rio_mem + reg);
1223         else {
1224                 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
1225                 return ioread32(rdev->rio_mem + RADEON_MM_DATA);
1226         }
1227 }
1228
1229 static inline void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v)
1230 {
1231         if (reg < rdev->rio_mem_size)
1232                 iowrite32(v, rdev->rio_mem + reg);
1233         else {
1234                 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
1235                 iowrite32(v, rdev->rio_mem + RADEON_MM_DATA);
1236         }
1237 }
1238
1239 /*
1240  * Cast helper
1241  */
1242 #define to_radeon_fence(p) ((struct radeon_fence *)(p))
1243
1244 /*
1245  * Registers read & write functions.
1246  */
1247 #define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg))
1248 #define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg))
1249 #define RREG16(reg) readw(((void __iomem *)rdev->rmmio) + (reg))
1250 #define WREG16(reg, v) writew(v, ((void __iomem *)rdev->rmmio) + (reg))
1251 #define RREG32(reg) r100_mm_rreg(rdev, (reg))
1252 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg)))
1253 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v))
1254 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1255 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1256 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
1257 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
1258 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
1259 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
1260 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
1261 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
1262 #define RREG32_PCIE_P(reg) rdev->pciep_rreg(rdev, (reg))
1263 #define WREG32_PCIE_P(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
1264 #define WREG32_P(reg, val, mask)                                \
1265         do {                                                    \
1266                 uint32_t tmp_ = RREG32(reg);                    \
1267                 tmp_ &= (mask);                                 \
1268                 tmp_ |= ((val) & ~(mask));                      \
1269                 WREG32(reg, tmp_);                              \
1270         } while (0)
1271 #define WREG32_PLL_P(reg, val, mask)                            \
1272         do {                                                    \
1273                 uint32_t tmp_ = RREG32_PLL(reg);                \
1274                 tmp_ &= (mask);                                 \
1275                 tmp_ |= ((val) & ~(mask));                      \
1276                 WREG32_PLL(reg, tmp_);                          \
1277         } while (0)
1278 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg)))
1279 #define RREG32_IO(reg) r100_io_rreg(rdev, (reg))
1280 #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v))
1281
1282 /*
1283  * Indirect registers accessor
1284  */
1285 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
1286 {
1287         uint32_t r;
1288
1289         WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1290         r = RREG32(RADEON_PCIE_DATA);
1291         return r;
1292 }
1293
1294 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1295 {
1296         WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1297         WREG32(RADEON_PCIE_DATA, (v));
1298 }
1299
1300 void r100_pll_errata_after_index(struct radeon_device *rdev);
1301
1302
1303 /*
1304  * ASICs helpers.
1305  */
1306 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
1307                             (rdev->pdev->device == 0x5969))
1308 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
1309                 (rdev->family == CHIP_RV200) || \
1310                 (rdev->family == CHIP_RS100) || \
1311                 (rdev->family == CHIP_RS200) || \
1312                 (rdev->family == CHIP_RV250) || \
1313                 (rdev->family == CHIP_RV280) || \
1314                 (rdev->family == CHIP_RS300))
1315 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300)  ||     \
1316                 (rdev->family == CHIP_RV350) ||                 \
1317                 (rdev->family == CHIP_R350)  ||                 \
1318                 (rdev->family == CHIP_RV380) ||                 \
1319                 (rdev->family == CHIP_R420)  ||                 \
1320                 (rdev->family == CHIP_R423)  ||                 \
1321                 (rdev->family == CHIP_RV410) ||                 \
1322                 (rdev->family == CHIP_RS400) ||                 \
1323                 (rdev->family == CHIP_RS480))
1324 #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \
1325                 (rdev->ddev->pdev->device == 0x9443) || \
1326                 (rdev->ddev->pdev->device == 0x944B) || \
1327                 (rdev->ddev->pdev->device == 0x9506) || \
1328                 (rdev->ddev->pdev->device == 0x9509) || \
1329                 (rdev->ddev->pdev->device == 0x950F) || \
1330                 (rdev->ddev->pdev->device == 0x689C) || \
1331                 (rdev->ddev->pdev->device == 0x689D))
1332 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
1333 #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600)  ||    \
1334                             (rdev->family == CHIP_RS690)  ||    \
1335                             (rdev->family == CHIP_RS740)  ||    \
1336                             (rdev->family >= CHIP_R600))
1337 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
1338 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
1339 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
1340 #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \
1341                              (rdev->flags & RADEON_IS_IGP))
1342 #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS))
1343
1344 /*
1345  * BIOS helpers.
1346  */
1347 #define RBIOS8(i) (rdev->bios[i])
1348 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1349 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1350
1351 int radeon_combios_init(struct radeon_device *rdev);
1352 void radeon_combios_fini(struct radeon_device *rdev);
1353 int radeon_atombios_init(struct radeon_device *rdev);
1354 void radeon_atombios_fini(struct radeon_device *rdev);
1355
1356
1357 /*
1358  * RING helpers.
1359  */
1360 static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
1361 {
1362 #if DRM_DEBUG_CODE
1363         if (rdev->cp.count_dw <= 0) {
1364                 DRM_ERROR("radeon: writting more dword to ring than expected !\n");
1365         }
1366 #endif
1367         rdev->cp.ring[rdev->cp.wptr++] = v;
1368         rdev->cp.wptr &= rdev->cp.ptr_mask;
1369         rdev->cp.count_dw--;
1370         rdev->cp.ring_free_dw--;
1371 }
1372
1373
1374 /*
1375  * ASICs macro.
1376  */
1377 #define radeon_init(rdev) (rdev)->asic->init((rdev))
1378 #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
1379 #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
1380 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
1381 #define radeon_cs_parse(p) rdev->asic->cs_parse((p))
1382 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
1383 #define radeon_gpu_is_lockup(rdev) (rdev)->asic->gpu_is_lockup((rdev))
1384 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
1385 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev))
1386 #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p))
1387 #define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev))
1388 #define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev))
1389 #define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev))
1390 #define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib))
1391 #define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev))
1392 #define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev))
1393 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc))
1394 #define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence))
1395 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f))
1396 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f))
1397 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f))
1398 #define radeon_get_engine_clock(rdev) (rdev)->asic->get_engine_clock((rdev))
1399 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
1400 #define radeon_get_memory_clock(rdev) (rdev)->asic->get_memory_clock((rdev))
1401 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_memory_clock((rdev), (e))
1402 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->get_pcie_lanes((rdev))
1403 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l))
1404 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e))
1405 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s)))
1406 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r)))
1407 #define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev))
1408 #define radeon_hpd_init(rdev) (rdev)->asic->hpd_init((rdev))
1409 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd_fini((rdev))
1410 #define radeon_hpd_sense(rdev, hpd) (rdev)->asic->hpd_sense((rdev), (hpd))
1411 #define radeon_hpd_set_polarity(rdev, hpd) (rdev)->asic->hpd_set_polarity((rdev), (hpd))
1412 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
1413 #define radeon_pm_misc(rdev) (rdev)->asic->pm_misc((rdev))
1414 #define radeon_pm_prepare(rdev) (rdev)->asic->pm_prepare((rdev))
1415 #define radeon_pm_finish(rdev) (rdev)->asic->pm_finish((rdev))
1416 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm_init_profile((rdev))
1417 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm_get_dynpm_state((rdev))
1418 #define radeon_pre_page_flip(rdev, crtc) rdev->asic->pre_page_flip((rdev), (crtc))
1419 #define radeon_page_flip(rdev, crtc, base) rdev->asic->page_flip((rdev), (crtc), (base))
1420 #define radeon_post_page_flip(rdev, crtc) rdev->asic->post_page_flip((rdev), (crtc))
1421
1422 /* Common functions */
1423 /* AGP */
1424 extern int radeon_gpu_reset(struct radeon_device *rdev);
1425 extern void radeon_agp_disable(struct radeon_device *rdev);
1426 extern int radeon_gart_table_vram_pin(struct radeon_device *rdev);
1427 extern void radeon_gart_restore(struct radeon_device *rdev);
1428 extern int radeon_modeset_init(struct radeon_device *rdev);
1429 extern void radeon_modeset_fini(struct radeon_device *rdev);
1430 extern bool radeon_card_posted(struct radeon_device *rdev);
1431 extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
1432 extern void radeon_update_display_priority(struct radeon_device *rdev);
1433 extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
1434 extern void radeon_scratch_init(struct radeon_device *rdev);
1435 extern void radeon_wb_fini(struct radeon_device *rdev);
1436 extern int radeon_wb_init(struct radeon_device *rdev);
1437 extern void radeon_wb_disable(struct radeon_device *rdev);
1438 extern void radeon_surface_init(struct radeon_device *rdev);
1439 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
1440 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
1441 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
1442 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
1443 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
1444 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
1445 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
1446 extern int radeon_resume_kms(struct drm_device *dev);
1447 extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state);
1448
1449 /*
1450  * r600 functions used by radeon_encoder.c
1451  */
1452 extern void r600_hdmi_enable(struct drm_encoder *encoder);
1453 extern void r600_hdmi_disable(struct drm_encoder *encoder);
1454 extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
1455
1456 extern int ni_init_microcode(struct radeon_device *rdev);
1457 extern int btc_mc_load_microcode(struct radeon_device *rdev);
1458
1459 /* radeon_acpi.c */
1460 #if defined(CONFIG_ACPI)
1461 extern int radeon_acpi_init(struct radeon_device *rdev);
1462 #else
1463 static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; }
1464 #endif
1465
1466 #include "radeon_object.h"
1467
1468 #endif