arch/blackfin/mach-bf561/smp.c

   1 /*
   2  * Copyright 2007-2009 Analog Devices Inc.
   3  *               Philippe Gerum <rpm@xenomai.org>
   4  *
   5  * Licensed under the GPL-2 or later.
   6  */
   7
   8 #include <linux/init.h>
   9 #include <linux/kernel.h>
  10 #include <linux/sched.h>
  11 #include <linux/delay.h>
  12 #include <asm/smp.h>
  13 #include <asm/dma.h>
  14 #include <asm/time.h>
  15
  16 static DEFINE_SPINLOCK(boot_lock);
  17
  18 /*
  19  * platform_init_cpus() - Tell the world about how many cores we
  20  * have. This is called while setting up the architecture support
  21  * (setup_arch()), so don't be too demanding here with respect to
  22  * available kernel services.
  23  */
  24
  25 void __init platform_init_cpus(void)
  26 {
  27         cpu_set(0, cpu_possible_map); /* CoreA */
  28         cpu_set(1, cpu_possible_map); /* CoreB */
  29 }
  30
  31 void __init platform_prepare_cpus(unsigned int max_cpus)
  32 {
  33         bfin_relocate_coreb_l1_mem();
  34
  35         /* Both cores ought to be present on a bf561! */
  36         cpu_set(0, cpu_present_map); /* CoreA */
  37         cpu_set(1, cpu_present_map); /* CoreB */
  38 }
  39
  40 int __init setup_profiling_timer(unsigned int multiplier) /* not supported */
  41 {
  42         return -EINVAL;
  43 }
  44
  45 void __cpuinit platform_secondary_init(unsigned int cpu)
  46 {
  47         /* Clone setup for peripheral interrupt sources from CoreA. */
  48         bfin_write_SICB_IMASK0(bfin_read_SIC_IMASK0());
  49         bfin_write_SICB_IMASK1(bfin_read_SIC_IMASK1());
  50         SSYNC();
  51
  52         /* Clone setup for IARs from CoreA. */
  53         bfin_write_SICB_IAR0(bfin_read_SIC_IAR0());
  54         bfin_write_SICB_IAR1(bfin_read_SIC_IAR1());
  55         bfin_write_SICB_IAR2(bfin_read_SIC_IAR2());
  56         bfin_write_SICB_IAR3(bfin_read_SIC_IAR3());
  57         bfin_write_SICB_IAR4(bfin_read_SIC_IAR4());
  58         bfin_write_SICB_IAR5(bfin_read_SIC_IAR5());
  59         bfin_write_SICB_IAR6(bfin_read_SIC_IAR6());
  60         bfin_write_SICB_IAR7(bfin_read_SIC_IAR7());
  61         bfin_write_SICB_IWR0(IWR_DISABLE_ALL);
  62         bfin_write_SICB_IWR1(IWR_DISABLE_ALL);
  63         SSYNC();
  64
  65         /* We are done with local CPU inits, unblock the boot CPU. */
  66         set_cpu_online(cpu, true);
  67         spin_lock(&boot_lock);
  68         spin_unlock(&boot_lock);
  69 }
  70
  71 int __cpuinit platform_boot_secondary(unsigned int cpu, struct task_struct *idle)
  72 {
  73         unsigned long timeout;
  74
  75         printk(KERN_INFO "Booting Core B.\n");
  76
  77         spin_lock(&boot_lock);
  78
  79         if ((bfin_read_SYSCR() & COREB_SRAM_INIT) == 0) {
  80                 /* CoreB already running, sending ipi to wakeup it */
  81                 platform_send_ipi_cpu(cpu, IRQ_SUPPLE_0);
  82         } else {
  83                 /* Kick CoreB, which should start execution from CORE_SRAM_BASE. */
  84                 bfin_write_SYSCR(bfin_read_SYSCR() & ~COREB_SRAM_INIT);
  85                 SSYNC();
  86         }
  87
  88         timeout = jiffies + 1 * HZ;
  89         while (time_before(jiffies, timeout)) {
  90                 if (cpu_online(cpu))
  91                         break;
  92                 udelay(100);
  93                 barrier();
  94         }
  95
  96         if (cpu_online(cpu)) {
  97                 /* release the lock and let coreb run */
  98                 spin_unlock(&boot_lock);
  99                 return 0;
 100         } else
 101                 panic("CPU%u: processor failed to boot\n", cpu);
 102 }
 103
 104 static const char supple0[] = "IRQ_SUPPLE_0";
 105 static const char supple1[] = "IRQ_SUPPLE_1";
 106 void __init platform_request_ipi(int irq, void *handler)
 107 {
 108         int ret;
 109         const char *name = (irq == IRQ_SUPPLE_0) ? supple0 : supple1;
 110
 111         ret = request_irq(irq, handler, IRQF_DISABLED | IRQF_PERCPU, name, handler);
 112         if (ret)
 113                 panic("Cannot request %s for IPI service", name);
 114 }
 115
 116 void platform_send_ipi(cpumask_t callmap, int irq)
 117 {
 118         unsigned int cpu;
 119         int offset = (irq == IRQ_SUPPLE_0) ? 6 : 8;
 120
 121         for_each_cpu_mask(cpu, callmap) {
 122                 BUG_ON(cpu >= 2);
 123                 SSYNC();
 124                 bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (offset + cpu)));
 125                 SSYNC();
 126         }
 127 }
 128
 129 void platform_send_ipi_cpu(unsigned int cpu, int irq)
 130 {
 131         int offset = (irq == IRQ_SUPPLE_0) ? 6 : 8;
 132         BUG_ON(cpu >= 2);
 133         SSYNC();
 134         bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (offset + cpu)));
 135         SSYNC();
 136 }
 137
 138 void platform_clear_ipi(unsigned int cpu, int irq)
 139 {
 140         int offset = (irq == IRQ_SUPPLE_0) ? 10 : 12;
 141         BUG_ON(cpu >= 2);
 142         SSYNC();
 143         bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (offset + cpu)));
 144         SSYNC();
 145 }
 146
 147 /*
 148  * Setup core B's local core timer.
 149  * In SMP, core timer is used for clock event device.
 150  */
 151 void __cpuinit bfin_local_timer_setup(void)
 152 {
 153 #if defined(CONFIG_TICKSOURCE_CORETMR)
 154         struct irq_data *data = irq_get_irq_data(IRQ_CORETMR);
 155         struct irq_chip *chip = irq_data_get_irq_chip(data);
 156
 157         bfin_coretmr_init();
 158         bfin_coretmr_clockevent_init();
 159
 160         chip->irq_unmask(data);
 161 #else
 162         /* Power down the core timer, just to play safe. */
 163         bfin_write_TCNTL(0);
 164 #endif
 165
 166 }