2 * Copyright 2004-2010 Analog Devices Inc.
4 * Licensed under the GPL-2 or later.
7 #include <linux/delay.h>
8 #include <linux/console.h>
9 #include <linux/bootmem.h>
10 #include <linux/seq_file.h>
11 #include <linux/cpu.h>
13 #include <linux/module.h>
14 #include <linux/tty.h>
15 #include <linux/pfn.h>
17 #ifdef CONFIG_MTD_UCLINUX
18 #include <linux/mtd/map.h>
19 #include <linux/ext2_fs.h>
20 #include <linux/cramfs_fs.h>
21 #include <linux/romfs_fs.h>
25 #include <asm/cacheflush.h>
26 #include <asm/blackfin.h>
27 #include <asm/cplbinit.h>
28 #include <asm/div64.h>
30 #include <asm/fixed_code.h>
31 #include <asm/early_printk.h>
34 EXPORT_SYMBOL(_bfin_swrst
);
36 unsigned long memory_start
, memory_end
, physical_mem_end
;
37 unsigned long _rambase
, _ramstart
, _ramend
;
38 unsigned long reserved_mem_dcache_on
;
39 unsigned long reserved_mem_icache_on
;
40 EXPORT_SYMBOL(memory_start
);
41 EXPORT_SYMBOL(memory_end
);
42 EXPORT_SYMBOL(physical_mem_end
);
43 EXPORT_SYMBOL(_ramend
);
44 EXPORT_SYMBOL(reserved_mem_dcache_on
);
46 #ifdef CONFIG_MTD_UCLINUX
47 extern struct map_info uclinux_ram_map
;
48 unsigned long memory_mtd_end
, memory_mtd_start
, mtd_size
;
50 EXPORT_SYMBOL(memory_mtd_end
);
51 EXPORT_SYMBOL(memory_mtd_start
);
52 EXPORT_SYMBOL(mtd_size
);
55 char __initdata command_line
[COMMAND_LINE_SIZE
];
56 void __initdata
*init_retx
, *init_saved_retx
, *init_saved_seqstat
,
57 *init_saved_icplb_fault_addr
, *init_saved_dcplb_fault_addr
;
59 /* boot memmap, for parsing "memmap=" */
60 #define BFIN_MEMMAP_MAX 128 /* number of entries in bfin_memmap */
61 #define BFIN_MEMMAP_RAM 1
62 #define BFIN_MEMMAP_RESERVED 2
63 static struct bfin_memmap
{
65 struct bfin_memmap_entry
{
66 unsigned long long addr
; /* start of memory segment */
67 unsigned long long size
;
69 } map
[BFIN_MEMMAP_MAX
];
70 } bfin_memmap __initdata
;
72 /* for memmap sanitization */
73 struct change_member
{
74 struct bfin_memmap_entry
*pentry
; /* pointer to original entry */
75 unsigned long long addr
; /* address for this change point */
77 static struct change_member change_point_list
[2*BFIN_MEMMAP_MAX
] __initdata
;
78 static struct change_member
*change_point
[2*BFIN_MEMMAP_MAX
] __initdata
;
79 static struct bfin_memmap_entry
*overlap_list
[BFIN_MEMMAP_MAX
] __initdata
;
80 static struct bfin_memmap_entry new_map
[BFIN_MEMMAP_MAX
] __initdata
;
82 DEFINE_PER_CPU(struct blackfin_cpudata
, cpu_data
);
84 static int early_init_clkin_hz(char *buf
);
86 #if defined(CONFIG_BFIN_DCACHE) || defined(CONFIG_BFIN_ICACHE)
87 void __init
generate_cplb_tables(void)
91 generate_cplb_tables_all();
92 /* Generate per-CPU I&D CPLB tables */
93 for (cpu
= 0; cpu
< num_possible_cpus(); ++cpu
)
94 generate_cplb_tables_cpu(cpu
);
98 void __cpuinit
bfin_setup_caches(unsigned int cpu
)
100 #ifdef CONFIG_BFIN_ICACHE
101 bfin_icache_init(icplb_tbl
[cpu
]);
104 #ifdef CONFIG_BFIN_DCACHE
105 bfin_dcache_init(dcplb_tbl
[cpu
]);
108 bfin_setup_cpudata(cpu
);
111 * In cache coherence emulation mode, we need to have the
112 * D-cache enabled before running any atomic operation which
113 * might involve cache invalidation (i.e. spinlock, rwlock).
114 * So printk's are deferred until then.
116 #ifdef CONFIG_BFIN_ICACHE
117 printk(KERN_INFO
"Instruction Cache Enabled for CPU%u\n", cpu
);
118 printk(KERN_INFO
" External memory:"
119 # ifdef CONFIG_BFIN_EXTMEM_ICACHEABLE
124 " in instruction cache\n");
126 printk(KERN_INFO
" L2 SRAM :"
127 # ifdef CONFIG_BFIN_L2_ICACHEABLE
132 " in instruction cache\n");
135 printk(KERN_INFO
"Instruction Cache Disabled for CPU%u\n", cpu
);
138 #ifdef CONFIG_BFIN_DCACHE
139 printk(KERN_INFO
"Data Cache Enabled for CPU%u\n", cpu
);
140 printk(KERN_INFO
" External memory:"
141 # if defined CONFIG_BFIN_EXTMEM_WRITEBACK
142 " cacheable (write-back)"
143 # elif defined CONFIG_BFIN_EXTMEM_WRITETHROUGH
144 " cacheable (write-through)"
150 printk(KERN_INFO
" L2 SRAM :"
151 # if defined CONFIG_BFIN_L2_WRITEBACK
152 " cacheable (write-back)"
153 # elif defined CONFIG_BFIN_L2_WRITETHROUGH
154 " cacheable (write-through)"
160 printk(KERN_INFO
"Data Cache Disabled for CPU%u\n", cpu
);
164 void __cpuinit
bfin_setup_cpudata(unsigned int cpu
)
166 struct blackfin_cpudata
*cpudata
= &per_cpu(cpu_data
, cpu
);
168 cpudata
->idle
= current
;
169 cpudata
->imemctl
= bfin_read_IMEM_CONTROL();
170 cpudata
->dmemctl
= bfin_read_DMEM_CONTROL();
173 void __init
bfin_cache_init(void)
175 #if defined(CONFIG_BFIN_DCACHE) || defined(CONFIG_BFIN_ICACHE)
176 generate_cplb_tables();
178 bfin_setup_caches(0);
181 void __init
bfin_relocate_l1_mem(void)
183 unsigned long text_l1_len
= (unsigned long)_text_l1_len
;
184 unsigned long data_l1_len
= (unsigned long)_data_l1_len
;
185 unsigned long data_b_l1_len
= (unsigned long)_data_b_l1_len
;
186 unsigned long l2_len
= (unsigned long)_l2_len
;
188 early_shadow_stamp();
191 * due to the ALIGN(4) in the arch/blackfin/kernel/vmlinux.lds.S
192 * we know that everything about l1 text/data is nice and aligned,
193 * so copy by 4 byte chunks, and don't worry about overlapping
196 * We can't use the dma_memcpy functions, since they can call
197 * scheduler functions which might be in L1 :( and core writes
198 * into L1 instruction cause bad access errors, so we are stuck,
199 * we are required to use DMA, but can't use the common dma
200 * functions. We can't use memcpy either - since that might be
201 * going to be in the relocated L1
204 blackfin_dma_early_init();
206 /* if necessary, copy L1 text to L1 instruction SRAM */
207 if (L1_CODE_LENGTH
&& text_l1_len
)
208 early_dma_memcpy(_stext_l1
, _text_l1_lma
, text_l1_len
);
210 /* if necessary, copy L1 data to L1 data bank A SRAM */
211 if (L1_DATA_A_LENGTH
&& data_l1_len
)
212 early_dma_memcpy(_sdata_l1
, _data_l1_lma
, data_l1_len
);
214 /* if necessary, copy L1 data B to L1 data bank B SRAM */
215 if (L1_DATA_B_LENGTH
&& data_b_l1_len
)
216 early_dma_memcpy(_sdata_b_l1
, _data_b_l1_lma
, data_b_l1_len
);
218 early_dma_memcpy_done();
220 #if defined(CONFIG_SMP) && defined(CONFIG_ICACHE_FLUSH_L1)
221 blackfin_iflush_l1_entry
[0] = (unsigned long)blackfin_icache_flush_range_l1
;
224 /* if necessary, copy L2 text/data to L2 SRAM */
225 if (L2_LENGTH
&& l2_len
)
226 memcpy(_stext_l2
, _l2_lma
, l2_len
);
230 void __init
bfin_relocate_coreb_l1_mem(void)
232 unsigned long text_l1_len
= (unsigned long)_text_l1_len
;
233 unsigned long data_l1_len
= (unsigned long)_data_l1_len
;
234 unsigned long data_b_l1_len
= (unsigned long)_data_b_l1_len
;
236 blackfin_dma_early_init();
238 /* if necessary, copy L1 text to L1 instruction SRAM */
239 if (L1_CODE_LENGTH
&& text_l1_len
)
240 early_dma_memcpy((void *)COREB_L1_CODE_START
, _text_l1_lma
,
243 /* if necessary, copy L1 data to L1 data bank A SRAM */
244 if (L1_DATA_A_LENGTH
&& data_l1_len
)
245 early_dma_memcpy((void *)COREB_L1_DATA_A_START
, _data_l1_lma
,
248 /* if necessary, copy L1 data B to L1 data bank B SRAM */
249 if (L1_DATA_B_LENGTH
&& data_b_l1_len
)
250 early_dma_memcpy((void *)COREB_L1_DATA_B_START
, _data_b_l1_lma
,
253 early_dma_memcpy_done();
255 #ifdef CONFIG_ICACHE_FLUSH_L1
256 blackfin_iflush_l1_entry
[1] = (unsigned long)blackfin_icache_flush_range_l1
-
257 (unsigned long)_stext_l1
+ COREB_L1_CODE_START
;
262 #ifdef CONFIG_ROMKERNEL
263 void __init
bfin_relocate_xip_data(void)
265 early_shadow_stamp();
267 memcpy(_sdata
, _data_lma
, (unsigned long)_data_len
- THREAD_SIZE
+ sizeof(struct thread_info
));
268 memcpy(_sinitdata
, _init_data_lma
, (unsigned long)_init_data_len
);
272 /* add_memory_region to memmap */
273 static void __init
add_memory_region(unsigned long long start
,
274 unsigned long long size
, int type
)
278 i
= bfin_memmap
.nr_map
;
280 if (i
== BFIN_MEMMAP_MAX
) {
281 printk(KERN_ERR
"Ooops! Too many entries in the memory map!\n");
285 bfin_memmap
.map
[i
].addr
= start
;
286 bfin_memmap
.map
[i
].size
= size
;
287 bfin_memmap
.map
[i
].type
= type
;
288 bfin_memmap
.nr_map
++;
292 * Sanitize the boot memmap, removing overlaps.
294 static int __init
sanitize_memmap(struct bfin_memmap_entry
*map
, int *pnr_map
)
296 struct change_member
*change_tmp
;
297 unsigned long current_type
, last_type
;
298 unsigned long long last_addr
;
299 int chgidx
, still_changing
;
302 int old_nr
, new_nr
, chg_nr
;
306 Visually we're performing the following (1,2,3,4 = memory types)
308 Sample memory map (w/overlaps):
309 ____22__________________
310 ______________________4_
311 ____1111________________
312 _44_____________________
313 11111111________________
314 ____________________33__
315 ___________44___________
316 __________33333_________
317 ______________22________
318 ___________________2222_
319 _________111111111______
320 _____________________11_
321 _________________4______
323 Sanitized equivalent (no overlap):
324 1_______________________
325 _44_____________________
326 ___1____________________
327 ____22__________________
328 ______11________________
329 _________1______________
330 __________3_____________
331 ___________44___________
332 _____________33_________
333 _______________2________
334 ________________1_______
335 _________________4______
336 ___________________2____
337 ____________________33__
338 ______________________4_
340 /* if there's only one memory region, don't bother */
346 /* bail out if we find any unreasonable addresses in memmap */
347 for (i
= 0; i
< old_nr
; i
++)
348 if (map
[i
].addr
+ map
[i
].size
< map
[i
].addr
)
351 /* create pointers for initial change-point information (for sorting) */
352 for (i
= 0; i
< 2*old_nr
; i
++)
353 change_point
[i
] = &change_point_list
[i
];
355 /* record all known change-points (starting and ending addresses),
356 omitting those that are for empty memory regions */
358 for (i
= 0; i
< old_nr
; i
++) {
359 if (map
[i
].size
!= 0) {
360 change_point
[chgidx
]->addr
= map
[i
].addr
;
361 change_point
[chgidx
++]->pentry
= &map
[i
];
362 change_point
[chgidx
]->addr
= map
[i
].addr
+ map
[i
].size
;
363 change_point
[chgidx
++]->pentry
= &map
[i
];
366 chg_nr
= chgidx
; /* true number of change-points */
368 /* sort change-point list by memory addresses (low -> high) */
370 while (still_changing
) {
372 for (i
= 1; i
< chg_nr
; i
++) {
373 /* if <current_addr> > <last_addr>, swap */
374 /* or, if current=<start_addr> & last=<end_addr>, swap */
375 if ((change_point
[i
]->addr
< change_point
[i
-1]->addr
) ||
376 ((change_point
[i
]->addr
== change_point
[i
-1]->addr
) &&
377 (change_point
[i
]->addr
== change_point
[i
]->pentry
->addr
) &&
378 (change_point
[i
-1]->addr
!= change_point
[i
-1]->pentry
->addr
))
380 change_tmp
= change_point
[i
];
381 change_point
[i
] = change_point
[i
-1];
382 change_point
[i
-1] = change_tmp
;
388 /* create a new memmap, removing overlaps */
389 overlap_entries
= 0; /* number of entries in the overlap table */
390 new_entry
= 0; /* index for creating new memmap entries */
391 last_type
= 0; /* start with undefined memory type */
392 last_addr
= 0; /* start with 0 as last starting address */
393 /* loop through change-points, determining affect on the new memmap */
394 for (chgidx
= 0; chgidx
< chg_nr
; chgidx
++) {
395 /* keep track of all overlapping memmap entries */
396 if (change_point
[chgidx
]->addr
== change_point
[chgidx
]->pentry
->addr
) {
397 /* add map entry to overlap list (> 1 entry implies an overlap) */
398 overlap_list
[overlap_entries
++] = change_point
[chgidx
]->pentry
;
400 /* remove entry from list (order independent, so swap with last) */
401 for (i
= 0; i
< overlap_entries
; i
++) {
402 if (overlap_list
[i
] == change_point
[chgidx
]->pentry
)
403 overlap_list
[i
] = overlap_list
[overlap_entries
-1];
407 /* if there are overlapping entries, decide which "type" to use */
408 /* (larger value takes precedence -- 1=usable, 2,3,4,4+=unusable) */
410 for (i
= 0; i
< overlap_entries
; i
++)
411 if (overlap_list
[i
]->type
> current_type
)
412 current_type
= overlap_list
[i
]->type
;
413 /* continue building up new memmap based on this information */
414 if (current_type
!= last_type
) {
415 if (last_type
!= 0) {
416 new_map
[new_entry
].size
=
417 change_point
[chgidx
]->addr
- last_addr
;
418 /* move forward only if the new size was non-zero */
419 if (new_map
[new_entry
].size
!= 0)
420 if (++new_entry
>= BFIN_MEMMAP_MAX
)
421 break; /* no more space left for new entries */
423 if (current_type
!= 0) {
424 new_map
[new_entry
].addr
= change_point
[chgidx
]->addr
;
425 new_map
[new_entry
].type
= current_type
;
426 last_addr
= change_point
[chgidx
]->addr
;
428 last_type
= current_type
;
431 new_nr
= new_entry
; /* retain count for new entries */
433 /* copy new mapping into original location */
434 memcpy(map
, new_map
, new_nr
*sizeof(struct bfin_memmap_entry
));
440 static void __init
print_memory_map(char *who
)
444 for (i
= 0; i
< bfin_memmap
.nr_map
; i
++) {
445 printk(KERN_DEBUG
" %s: %016Lx - %016Lx ", who
,
446 bfin_memmap
.map
[i
].addr
,
447 bfin_memmap
.map
[i
].addr
+ bfin_memmap
.map
[i
].size
);
448 switch (bfin_memmap
.map
[i
].type
) {
449 case BFIN_MEMMAP_RAM
:
450 printk(KERN_CONT
"(usable)\n");
452 case BFIN_MEMMAP_RESERVED
:
453 printk(KERN_CONT
"(reserved)\n");
456 printk(KERN_CONT
"type %lu\n", bfin_memmap
.map
[i
].type
);
462 static __init
int parse_memmap(char *arg
)
464 unsigned long long start_at
, mem_size
;
469 mem_size
= memparse(arg
, &arg
);
471 start_at
= memparse(arg
+1, &arg
);
472 add_memory_region(start_at
, mem_size
, BFIN_MEMMAP_RAM
);
473 } else if (*arg
== '$') {
474 start_at
= memparse(arg
+1, &arg
);
475 add_memory_region(start_at
, mem_size
, BFIN_MEMMAP_RESERVED
);
482 * Initial parsing of the command line. Currently, we support:
483 * - Controlling the linux memory size: mem=xxx[KMG]
484 * - Controlling the physical memory size: max_mem=xxx[KMG][$][#]
485 * $ -> reserved memory is dcacheable
486 * # -> reserved memory is icacheable
487 * - "memmap=XXX[KkmM][@][$]XXX[KkmM]" defines a memory region
488 * @ from <start> to <start>+<mem>, type RAM
489 * $ from <start> to <start>+<mem>, type RESERVED
491 static __init
void parse_cmdline_early(char *cmdline_p
)
493 char c
= ' ', *to
= cmdline_p
;
494 unsigned int memsize
;
497 if (!memcmp(to
, "mem=", 4)) {
499 memsize
= memparse(to
, &to
);
503 } else if (!memcmp(to
, "max_mem=", 8)) {
505 memsize
= memparse(to
, &to
);
507 physical_mem_end
= memsize
;
511 reserved_mem_dcache_on
= 1;
514 reserved_mem_icache_on
= 1;
517 } else if (!memcmp(to
, "clkin_hz=", 9)) {
519 early_init_clkin_hz(to
);
520 #ifdef CONFIG_EARLY_PRINTK
521 } else if (!memcmp(to
, "earlyprintk=", 12)) {
523 setup_early_printk(to
);
525 } else if (!memcmp(to
, "memmap=", 7)) {
537 * Setup memory defaults from user config.
538 * The physical memory layout looks like:
540 * [_rambase, _ramstart]: kernel image
541 * [memory_start, memory_end]: dynamic memory managed by kernel
542 * [memory_end, _ramend]: reserved memory
543 * [memory_mtd_start(memory_end),
544 * memory_mtd_start + mtd_size]: rootfs (if any)
545 * [_ramend - DMA_UNCACHED_REGION,
546 * _ramend]: uncached DMA region
547 * [_ramend, physical_mem_end]: memory not managed by kernel
549 static __init
void memory_setup(void)
551 #ifdef CONFIG_MTD_UCLINUX
552 unsigned long mtd_phys
= 0;
554 unsigned long max_mem
;
556 _rambase
= CONFIG_BOOT_LOAD
;
557 _ramstart
= (unsigned long)_end
;
559 if (DMA_UNCACHED_REGION
> (_ramend
- _ramstart
)) {
561 panic("DMA region exceeds memory limit: %lu.",
562 _ramend
- _ramstart
);
564 max_mem
= memory_end
= _ramend
- DMA_UNCACHED_REGION
;
566 #if (defined(CONFIG_BFIN_EXTMEM_ICACHEABLE) && ANOMALY_05000263)
567 /* Due to a Hardware Anomaly we need to limit the size of usable
568 * instruction memory to max 60MB, 56 if HUNT_FOR_ZERO is on
569 * 05000263 - Hardware loop corrupted when taking an ICPLB exception
571 # if (defined(CONFIG_DEBUG_HUNT_FOR_ZERO))
572 if (max_mem
>= 56 * 1024 * 1024)
573 max_mem
= 56 * 1024 * 1024;
575 if (max_mem
>= 60 * 1024 * 1024)
576 max_mem
= 60 * 1024 * 1024;
577 # endif /* CONFIG_DEBUG_HUNT_FOR_ZERO */
578 #endif /* ANOMALY_05000263 */
582 /* Round up to multiple of 4MB */
583 memory_start
= (_ramstart
+ 0x3fffff) & ~0x3fffff;
585 memory_start
= PAGE_ALIGN(_ramstart
);
588 #if defined(CONFIG_MTD_UCLINUX)
589 /* generic memory mapped MTD driver */
590 memory_mtd_end
= memory_end
;
592 mtd_phys
= _ramstart
;
593 mtd_size
= PAGE_ALIGN(*((unsigned long *)(mtd_phys
+ 8)));
595 # if defined(CONFIG_EXT2_FS) || defined(CONFIG_EXT3_FS)
596 if (*((unsigned short *)(mtd_phys
+ 0x438)) == EXT2_SUPER_MAGIC
)
598 PAGE_ALIGN(*((unsigned long *)(mtd_phys
+ 0x404)) << 10);
601 # if defined(CONFIG_CRAMFS)
602 if (*((unsigned long *)(mtd_phys
)) == CRAMFS_MAGIC
)
603 mtd_size
= PAGE_ALIGN(*((unsigned long *)(mtd_phys
+ 0x4)));
606 # if defined(CONFIG_ROMFS_FS)
607 if (((unsigned long *)mtd_phys
)[0] == ROMSB_WORD0
608 && ((unsigned long *)mtd_phys
)[1] == ROMSB_WORD1
) {
610 PAGE_ALIGN(be32_to_cpu(((unsigned long *)mtd_phys
)[2]));
612 /* ROM_FS is XIP, so if we found it, we need to limit memory */
613 if (memory_end
> max_mem
) {
614 pr_info("Limiting kernel memory to %liMB due to anomaly 05000263\n", max_mem
>> 20);
615 memory_end
= max_mem
;
618 # endif /* CONFIG_ROMFS_FS */
620 /* Since the default MTD_UCLINUX has no magic number, we just blindly
621 * read 8 past the end of the kernel's image, and look at it.
622 * When no image is attached, mtd_size is set to a random number
623 * Do some basic sanity checks before operating on things
625 if (mtd_size
== 0 || memory_end
<= mtd_size
) {
626 pr_emerg("Could not find valid ram mtd attached.\n");
628 memory_end
-= mtd_size
;
630 /* Relocate MTD image to the top of memory after the uncached memory area */
631 uclinux_ram_map
.phys
= memory_mtd_start
= memory_end
;
632 uclinux_ram_map
.size
= mtd_size
;
633 pr_info("Found mtd parition at 0x%p, (len=0x%lx), moving to 0x%p\n",
634 _end
, mtd_size
, (void *)memory_mtd_start
);
635 dma_memcpy((void *)uclinux_ram_map
.phys
, _end
, uclinux_ram_map
.size
);
637 #endif /* CONFIG_MTD_UCLINUX */
639 /* We need lo limit memory, since everything could have a text section
640 * of userspace in it, and expose anomaly 05000263. If the anomaly
641 * doesn't exist, or we don't need to - then dont.
643 if (memory_end
> max_mem
) {
644 pr_info("Limiting kernel memory to %liMB due to anomaly 05000263\n", max_mem
>> 20);
645 memory_end
= max_mem
;
649 #if defined(CONFIG_ROMFS_ON_MTD) && defined(CONFIG_MTD_ROM)
650 page_mask_nelts
= (((_ramend
+ ASYNC_BANK3_BASE
+ ASYNC_BANK3_SIZE
-
651 ASYNC_BANK0_BASE
) >> PAGE_SHIFT
) + 31) / 32;
653 page_mask_nelts
= ((_ramend
>> PAGE_SHIFT
) + 31) / 32;
655 page_mask_order
= get_order(3 * page_mask_nelts
* sizeof(long));
658 init_mm
.start_code
= (unsigned long)_stext
;
659 init_mm
.end_code
= (unsigned long)_etext
;
660 init_mm
.end_data
= (unsigned long)_edata
;
661 init_mm
.brk
= (unsigned long)0;
663 printk(KERN_INFO
"Board Memory: %ldMB\n", physical_mem_end
>> 20);
664 printk(KERN_INFO
"Kernel Managed Memory: %ldMB\n", _ramend
>> 20);
666 printk(KERN_INFO
"Memory map:\n"
667 " fixedcode = 0x%p-0x%p\n"
668 " text = 0x%p-0x%p\n"
669 " rodata = 0x%p-0x%p\n"
671 " data = 0x%p-0x%p\n"
672 " stack = 0x%p-0x%p\n"
673 " init = 0x%p-0x%p\n"
674 " available = 0x%p-0x%p\n"
675 #ifdef CONFIG_MTD_UCLINUX
676 " rootfs = 0x%p-0x%p\n"
678 #if DMA_UNCACHED_REGION > 0
679 " DMA Zone = 0x%p-0x%p\n"
681 , (void *)FIXED_CODE_START
, (void *)FIXED_CODE_END
,
683 __start_rodata
, __end_rodata
,
684 __bss_start
, __bss_stop
,
686 (void *)&init_thread_union
,
687 (void *)((int)(&init_thread_union
) + THREAD_SIZE
),
688 __init_begin
, __init_end
,
689 (void *)_ramstart
, (void *)memory_end
690 #ifdef CONFIG_MTD_UCLINUX
691 , (void *)memory_mtd_start
, (void *)(memory_mtd_start
+ mtd_size
)
693 #if DMA_UNCACHED_REGION > 0
694 , (void *)(_ramend
- DMA_UNCACHED_REGION
), (void *)(_ramend
)
700 * Find the lowest, highest page frame number we have available
702 void __init
find_min_max_pfn(void)
707 min_low_pfn
= memory_end
;
709 for (i
= 0; i
< bfin_memmap
.nr_map
; i
++) {
710 unsigned long start
, end
;
712 if (bfin_memmap
.map
[i
].type
!= BFIN_MEMMAP_RAM
)
714 start
= PFN_UP(bfin_memmap
.map
[i
].addr
);
715 end
= PFN_DOWN(bfin_memmap
.map
[i
].addr
+
716 bfin_memmap
.map
[i
].size
);
721 if (start
< min_low_pfn
)
726 static __init
void setup_bootmem_allocator(void)
730 unsigned long start_pfn
, end_pfn
;
731 unsigned long curr_pfn
, last_pfn
, size
;
733 /* mark memory between memory_start and memory_end usable */
734 add_memory_region(memory_start
,
735 memory_end
- memory_start
, BFIN_MEMMAP_RAM
);
736 /* sanity check for overlap */
737 sanitize_memmap(bfin_memmap
.map
, &bfin_memmap
.nr_map
);
738 print_memory_map("boot memmap");
740 /* initialize globals in linux/bootmem.h */
742 /* pfn of the last usable page frame */
743 if (max_pfn
> memory_end
>> PAGE_SHIFT
)
744 max_pfn
= memory_end
>> PAGE_SHIFT
;
745 /* pfn of last page frame directly mapped by kernel */
746 max_low_pfn
= max_pfn
;
747 /* pfn of the first usable page frame after kernel image*/
748 if (min_low_pfn
< memory_start
>> PAGE_SHIFT
)
749 min_low_pfn
= memory_start
>> PAGE_SHIFT
;
751 start_pfn
= PAGE_OFFSET
>> PAGE_SHIFT
;
752 end_pfn
= memory_end
>> PAGE_SHIFT
;
755 * give all the memory to the bootmap allocator, tell it to put the
756 * boot mem_map at the start of memory.
758 bootmap_size
= init_bootmem_node(NODE_DATA(0),
759 memory_start
>> PAGE_SHIFT
, /* map goes here */
762 /* register the memmap regions with the bootmem allocator */
763 for (i
= 0; i
< bfin_memmap
.nr_map
; i
++) {
765 * Reserve usable memory
767 if (bfin_memmap
.map
[i
].type
!= BFIN_MEMMAP_RAM
)
770 * We are rounding up the start address of usable memory:
772 curr_pfn
= PFN_UP(bfin_memmap
.map
[i
].addr
);
773 if (curr_pfn
>= end_pfn
)
776 * ... and at the end of the usable range downwards:
778 last_pfn
= PFN_DOWN(bfin_memmap
.map
[i
].addr
+
779 bfin_memmap
.map
[i
].size
);
781 if (last_pfn
> end_pfn
)
785 * .. finally, did all the rounding and playing
786 * around just make the area go away?
788 if (last_pfn
<= curr_pfn
)
791 size
= last_pfn
- curr_pfn
;
792 free_bootmem(PFN_PHYS(curr_pfn
), PFN_PHYS(size
));
795 /* reserve memory before memory_start, including bootmap */
796 reserve_bootmem(PAGE_OFFSET
,
797 memory_start
+ bootmap_size
+ PAGE_SIZE
- 1 - PAGE_OFFSET
,
801 #define EBSZ_TO_MEG(ebsz) \
804 switch (ebsz & 0xf) { \
805 case 0x1: meg = 16; break; \
806 case 0x3: meg = 32; break; \
807 case 0x5: meg = 64; break; \
808 case 0x7: meg = 128; break; \
809 case 0x9: meg = 256; break; \
810 case 0xb: meg = 512; break; \
814 static inline int __init
get_mem_size(void)
816 #if defined(EBIU_SDBCTL)
817 # if defined(BF561_FAMILY)
819 u32 sdbctl
= bfin_read_EBIU_SDBCTL();
820 ret
+= EBSZ_TO_MEG(sdbctl
>> 0);
821 ret
+= EBSZ_TO_MEG(sdbctl
>> 8);
822 ret
+= EBSZ_TO_MEG(sdbctl
>> 16);
823 ret
+= EBSZ_TO_MEG(sdbctl
>> 24);
826 return EBSZ_TO_MEG(bfin_read_EBIU_SDBCTL());
828 #elif defined(EBIU_DDRCTL1)
829 u32 ddrctl
= bfin_read_EBIU_DDRCTL1();
831 switch (ddrctl
& 0xc0000) {
832 case DEVSZ_64
: ret
= 64 / 8;
833 case DEVSZ_128
: ret
= 128 / 8;
834 case DEVSZ_256
: ret
= 256 / 8;
835 case DEVSZ_512
: ret
= 512 / 8;
837 switch (ddrctl
& 0x30000) {
838 case DEVWD_4
: ret
*= 2;
839 case DEVWD_8
: ret
*= 2;
840 case DEVWD_16
: break;
842 if ((ddrctl
& 0xc000) == 0x4000)
849 __attribute__((weak
))
850 void __init
native_machine_early_platform_add_devices(void)
854 void __init
setup_arch(char **cmdline_p
)
856 unsigned long sclk
, cclk
;
858 native_machine_early_platform_add_devices();
860 enable_shadow_console();
862 /* Check to make sure we are running on the right processor */
863 if (unlikely(CPUID
!= bfin_cpuid()))
864 printk(KERN_ERR
"ERROR: Not running on ADSP-%s: unknown CPUID 0x%04x Rev 0.%d\n",
865 CPU
, bfin_cpuid(), bfin_revid());
867 #ifdef CONFIG_DUMMY_CONSOLE
868 conswitchp
= &dummy_con
;
871 #if defined(CONFIG_CMDLINE_BOOL)
872 strncpy(&command_line
[0], CONFIG_CMDLINE
, sizeof(command_line
));
873 command_line
[sizeof(command_line
) - 1] = 0;
876 /* Keep a copy of command line */
877 *cmdline_p
= &command_line
[0];
878 memcpy(boot_command_line
, command_line
, COMMAND_LINE_SIZE
);
879 boot_command_line
[COMMAND_LINE_SIZE
- 1] = '\0';
881 memset(&bfin_memmap
, 0, sizeof(bfin_memmap
));
883 /* If the user does not specify things on the command line, use
884 * what the bootloader set things up as
886 physical_mem_end
= 0;
887 parse_cmdline_early(&command_line
[0]);
890 _ramend
= get_mem_size() * 1024 * 1024;
892 if (physical_mem_end
== 0)
893 physical_mem_end
= _ramend
;
897 /* Initialize Async memory banks */
898 bfin_write_EBIU_AMBCTL0(AMBCTL0VAL
);
899 bfin_write_EBIU_AMBCTL1(AMBCTL1VAL
);
900 bfin_write_EBIU_AMGCTL(AMGCTLVAL
);
901 #ifdef CONFIG_EBIU_MBSCTLVAL
902 bfin_write_EBIU_MBSCTL(CONFIG_EBIU_MBSCTLVAL
);
903 bfin_write_EBIU_MODE(CONFIG_EBIU_MODEVAL
);
904 bfin_write_EBIU_FCTL(CONFIG_EBIU_FCTLVAL
);
906 #ifdef CONFIG_BFIN_HYSTERESIS_CONTROL
907 bfin_write_PORTF_HYSTERISIS(HYST_PORTF_0_15
);
908 bfin_write_PORTG_HYSTERISIS(HYST_PORTG_0_15
);
909 bfin_write_PORTH_HYSTERISIS(HYST_PORTH_0_15
);
910 bfin_write_MISCPORT_HYSTERISIS((bfin_read_MISCPORT_HYSTERISIS() &
911 ~HYST_NONEGPIO_MASK
) | HYST_NONEGPIO
);
917 if ((ANOMALY_05000273
|| ANOMALY_05000274
) && (cclk
>> 1) < sclk
)
918 panic("ANOMALY 05000273 or 05000274: CCLK must be >= 2*SCLK");
921 if (ANOMALY_05000266
) {
922 bfin_read_IMDMA_D0_IRQ_STATUS();
923 bfin_read_IMDMA_D1_IRQ_STATUS();
926 printk(KERN_INFO
"Hardware Trace ");
927 if (bfin_read_TBUFCTL() & 0x1)
928 printk(KERN_CONT
"Active ");
930 printk(KERN_CONT
"Off ");
931 if (bfin_read_TBUFCTL() & 0x2)
932 printk(KERN_CONT
"and Enabled\n");
934 printk(KERN_CONT
"and Disabled\n");
936 printk(KERN_INFO
"Boot Mode: %i\n", bfin_read_SYSCR() & 0xF);
938 /* Newer parts mirror SWRST bits in SYSCR */
939 #if defined(CONFIG_BF53x) || defined(CONFIG_BF561) || \
940 defined(CONFIG_BF538) || defined(CONFIG_BF539)
941 _bfin_swrst
= bfin_read_SWRST();
943 /* Clear boot mode field */
944 _bfin_swrst
= bfin_read_SYSCR() & ~0xf;
947 #ifdef CONFIG_DEBUG_DOUBLEFAULT_PRINT
948 bfin_write_SWRST(_bfin_swrst
& ~DOUBLE_FAULT
);
950 #ifdef CONFIG_DEBUG_DOUBLEFAULT_RESET
951 bfin_write_SWRST(_bfin_swrst
| DOUBLE_FAULT
);
955 if (_bfin_swrst
& SWRST_DBL_FAULT_A
) {
957 if (_bfin_swrst
& RESET_DOUBLE
) {
959 printk(KERN_EMERG
"Recovering from DOUBLE FAULT event\n");
960 #ifdef CONFIG_DEBUG_DOUBLEFAULT
961 /* We assume the crashing kernel, and the current symbol table match */
962 printk(KERN_EMERG
" While handling exception (EXCAUSE = 0x%x) at %pF\n",
963 (int)init_saved_seqstat
& SEQSTAT_EXCAUSE
, init_saved_retx
);
964 printk(KERN_NOTICE
" DCPLB_FAULT_ADDR: %pF\n", init_saved_dcplb_fault_addr
);
965 printk(KERN_NOTICE
" ICPLB_FAULT_ADDR: %pF\n", init_saved_icplb_fault_addr
);
967 printk(KERN_NOTICE
" The instruction at %pF caused a double exception\n",
969 } else if (_bfin_swrst
& RESET_WDOG
)
970 printk(KERN_INFO
"Recovering from Watchdog event\n");
971 else if (_bfin_swrst
& RESET_SOFTWARE
)
972 printk(KERN_NOTICE
"Reset caused by Software reset\n");
974 printk(KERN_INFO
"Blackfin support (C) 2004-2010 Analog Devices, Inc.\n");
975 if (bfin_compiled_revid() == 0xffff)
976 printk(KERN_INFO
"Compiled for ADSP-%s Rev any, running on 0.%d\n", CPU
, bfin_revid());
977 else if (bfin_compiled_revid() == -1)
978 printk(KERN_INFO
"Compiled for ADSP-%s Rev none\n", CPU
);
980 printk(KERN_INFO
"Compiled for ADSP-%s Rev 0.%d\n", CPU
, bfin_compiled_revid());
982 if (likely(CPUID
== bfin_cpuid())) {
983 if (bfin_revid() != bfin_compiled_revid()) {
984 if (bfin_compiled_revid() == -1)
985 printk(KERN_ERR
"Warning: Compiled for Rev none, but running on Rev %d\n",
987 else if (bfin_compiled_revid() != 0xffff) {
988 printk(KERN_ERR
"Warning: Compiled for Rev %d, but running on Rev %d\n",
989 bfin_compiled_revid(), bfin_revid());
990 if (bfin_compiled_revid() > bfin_revid())
991 panic("Error: you are missing anomaly workarounds for this rev");
994 if (bfin_revid() < CONFIG_BF_REV_MIN
|| bfin_revid() > CONFIG_BF_REV_MAX
)
995 printk(KERN_ERR
"Warning: Unsupported Chip Revision ADSP-%s Rev 0.%d detected\n",
999 printk(KERN_INFO
"Blackfin Linux support by http://blackfin.uclinux.org/\n");
1001 printk(KERN_INFO
"Processor Speed: %lu MHz core clock and %lu MHz System Clock\n",
1002 cclk
/ 1000000, sclk
/ 1000000);
1004 setup_bootmem_allocator();
1008 /* Copy atomic sequences to their fixed location, and sanity check that
1009 these locations are the ones that we advertise to userspace. */
1010 memcpy((void *)FIXED_CODE_START
, &fixed_code_start
,
1011 FIXED_CODE_END
- FIXED_CODE_START
);
1012 BUG_ON((char *)&sigreturn_stub
- (char *)&fixed_code_start
1013 != SIGRETURN_STUB
- FIXED_CODE_START
);
1014 BUG_ON((char *)&atomic_xchg32
- (char *)&fixed_code_start
1015 != ATOMIC_XCHG32
- FIXED_CODE_START
);
1016 BUG_ON((char *)&atomic_cas32
- (char *)&fixed_code_start
1017 != ATOMIC_CAS32
- FIXED_CODE_START
);
1018 BUG_ON((char *)&atomic_add32
- (char *)&fixed_code_start
1019 != ATOMIC_ADD32
- FIXED_CODE_START
);
1020 BUG_ON((char *)&atomic_sub32
- (char *)&fixed_code_start
1021 != ATOMIC_SUB32
- FIXED_CODE_START
);
1022 BUG_ON((char *)&atomic_ior32
- (char *)&fixed_code_start
1023 != ATOMIC_IOR32
- FIXED_CODE_START
);
1024 BUG_ON((char *)&atomic_and32
- (char *)&fixed_code_start
1025 != ATOMIC_AND32
- FIXED_CODE_START
);
1026 BUG_ON((char *)&atomic_xor32
- (char *)&fixed_code_start
1027 != ATOMIC_XOR32
- FIXED_CODE_START
);
1028 BUG_ON((char *)&safe_user_instruction
- (char *)&fixed_code_start
1029 != SAFE_USER_INSTRUCTION
- FIXED_CODE_START
);
1032 platform_init_cpus();
1034 init_exception_vectors();
1035 bfin_cache_init(); /* Initialize caches for the boot CPU */
1038 static int __init
topology_init(void)
1042 for_each_possible_cpu(cpu
) {
1043 register_cpu(&per_cpu(cpu_data
, cpu
).cpu
, cpu
);
1049 subsys_initcall(topology_init
);
1051 /* Get the input clock frequency */
1052 static u_long cached_clkin_hz
= CONFIG_CLKIN_HZ
;
1053 static u_long
get_clkin_hz(void)
1055 return cached_clkin_hz
;
1057 static int __init
early_init_clkin_hz(char *buf
)
1059 cached_clkin_hz
= simple_strtoul(buf
, NULL
, 0);
1060 #ifdef BFIN_KERNEL_CLOCK
1061 if (cached_clkin_hz
!= CONFIG_CLKIN_HZ
)
1062 panic("cannot change clkin_hz when reprogramming clocks");
1066 early_param("clkin_hz=", early_init_clkin_hz
);
1068 /* Get the voltage input multiplier */
1069 static u_long
get_vco(void)
1071 static u_long cached_vco
;
1072 u_long msel
, pll_ctl
;
1074 /* The assumption here is that VCO never changes at runtime.
1075 * If, someday, we support that, then we'll have to change this.
1080 pll_ctl
= bfin_read_PLL_CTL();
1081 msel
= (pll_ctl
>> 9) & 0x3F;
1085 cached_vco
= get_clkin_hz();
1086 cached_vco
>>= (1 & pll_ctl
); /* DF bit */
1091 /* Get the Core clock */
1092 u_long
get_cclk(void)
1094 static u_long cached_cclk_pll_div
, cached_cclk
;
1097 if (bfin_read_PLL_STAT() & 0x1)
1098 return get_clkin_hz();
1100 ssel
= bfin_read_PLL_DIV();
1101 if (ssel
== cached_cclk_pll_div
)
1104 cached_cclk_pll_div
= ssel
;
1106 csel
= ((ssel
>> 4) & 0x03);
1108 if (ssel
&& ssel
< (1 << csel
)) /* SCLK > CCLK */
1109 cached_cclk
= get_vco() / ssel
;
1111 cached_cclk
= get_vco() >> csel
;
1114 EXPORT_SYMBOL(get_cclk
);
1116 /* Get the System clock */
1117 u_long
get_sclk(void)
1119 static u_long cached_sclk
;
1122 /* The assumption here is that SCLK never changes at runtime.
1123 * If, someday, we support that, then we'll have to change this.
1128 if (bfin_read_PLL_STAT() & 0x1)
1129 return get_clkin_hz();
1131 ssel
= bfin_read_PLL_DIV() & 0xf;
1133 printk(KERN_WARNING
"Invalid System Clock\n");
1137 cached_sclk
= get_vco() / ssel
;
1140 EXPORT_SYMBOL(get_sclk
);
1142 unsigned long sclk_to_usecs(unsigned long sclk
)
1144 u64 tmp
= USEC_PER_SEC
* (u64
)sclk
;
1145 do_div(tmp
, get_sclk());
1148 EXPORT_SYMBOL(sclk_to_usecs
);
1150 unsigned long usecs_to_sclk(unsigned long usecs
)
1152 u64 tmp
= get_sclk() * (u64
)usecs
;
1153 do_div(tmp
, USEC_PER_SEC
);
1156 EXPORT_SYMBOL(usecs_to_sclk
);
1159 * Get CPU information for use by the procfs.
1161 static int show_cpuinfo(struct seq_file
*m
, void *v
)
1163 char *cpu
, *mmu
, *fpu
, *vendor
, *cache
;
1165 int cpu_num
= *(unsigned int *)v
;
1167 u_int icache_size
= BFIN_ICACHESIZE
/ 1024, dcache_size
= 0, dsup_banks
= 0;
1168 struct blackfin_cpudata
*cpudata
= &per_cpu(cpu_data
, cpu_num
);
1173 revid
= bfin_revid();
1178 switch (bfin_read_CHIPID() & CHIPID_MANUFACTURE
) {
1180 vendor
= "Analog Devices";
1187 seq_printf(m
, "processor\t: %d\n" "vendor_id\t: %s\n", cpu_num
, vendor
);
1189 if (CPUID
== bfin_cpuid())
1190 seq_printf(m
, "cpu family\t: 0x%04x\n", CPUID
);
1192 seq_printf(m
, "cpu family\t: Compiled for:0x%04x, running on:0x%04x\n",
1193 CPUID
, bfin_cpuid());
1195 seq_printf(m
, "model name\t: ADSP-%s %lu(MHz CCLK) %lu(MHz SCLK) (%s)\n"
1197 cpu
, cclk
/1000000, sclk
/1000000,
1205 if (bfin_revid() != bfin_compiled_revid()) {
1206 if (bfin_compiled_revid() == -1)
1207 seq_printf(m
, "(Compiled for Rev none)");
1208 else if (bfin_compiled_revid() == 0xffff)
1209 seq_printf(m
, "(Compiled for Rev any)");
1211 seq_printf(m
, "(Compiled for Rev %d)", bfin_compiled_revid());
1214 seq_printf(m
, "\ncpu MHz\t\t: %lu.%03lu/%lu.%03lu\n",
1215 cclk
/1000000, cclk
%1000000,
1216 sclk
/1000000, sclk
%1000000);
1217 seq_printf(m
, "bogomips\t: %lu.%02lu\n"
1218 "Calibration\t: %lu loops\n",
1219 (loops_per_jiffy
* HZ
) / 500000,
1220 ((loops_per_jiffy
* HZ
) / 5000) % 100,
1221 (loops_per_jiffy
* HZ
));
1223 /* Check Cache configutation */
1224 switch (cpudata
->dmemctl
& (1 << DMC0_P
| 1 << DMC1_P
)) {
1226 cache
= "dbank-A/B\t: cache/sram";
1231 cache
= "dbank-A/B\t: cache/cache";
1236 cache
= "dbank-A/B\t: sram/sram";
1247 /* Is it turned on? */
1248 if ((cpudata
->dmemctl
& (ENDCPLB
| DMC_ENABLE
)) != (ENDCPLB
| DMC_ENABLE
))
1251 if ((cpudata
->imemctl
& (IMC
| ENICPLB
)) != (IMC
| ENICPLB
))
1254 seq_printf(m
, "cache size\t: %d KB(L1 icache) "
1255 "%d KB(L1 dcache) %d KB(L2 cache)\n",
1256 icache_size
, dcache_size
, 0);
1257 seq_printf(m
, "%s\n", cache
);
1258 seq_printf(m
, "external memory\t: "
1259 #if defined(CONFIG_BFIN_EXTMEM_ICACHEABLE)
1264 " in instruction cache\n");
1265 seq_printf(m
, "external memory\t: "
1266 #if defined(CONFIG_BFIN_EXTMEM_WRITEBACK)
1267 "cacheable (write-back)"
1268 #elif defined(CONFIG_BFIN_EXTMEM_WRITETHROUGH)
1269 "cacheable (write-through)"
1273 " in data cache\n");
1276 seq_printf(m
, "icache setup\t: %d Sub-banks/%d Ways, %d Lines/Way\n",
1277 BFIN_ISUBBANKS
, BFIN_IWAYS
, BFIN_ILINES
);
1279 seq_printf(m
, "icache setup\t: off\n");
1282 "dcache setup\t: %d Super-banks/%d Sub-banks/%d Ways, %d Lines/Way\n",
1283 dsup_banks
, BFIN_DSUBBANKS
, BFIN_DWAYS
,
1285 #ifdef __ARCH_SYNC_CORE_DCACHE
1286 seq_printf(m
, "dcache flushes\t: %lu\n", dcache_invld_count
[cpu_num
]);
1288 #ifdef __ARCH_SYNC_CORE_ICACHE
1289 seq_printf(m
, "icache flushes\t: %lu\n", icache_invld_count
[cpu_num
]);
1292 seq_printf(m
, "\n");
1294 if (cpu_num
!= num_possible_cpus() - 1)
1298 seq_printf(m
, "L2 SRAM\t\t: %dKB\n", L2_LENGTH
/0x400);
1299 seq_printf(m
, "L2 SRAM\t\t: "
1300 #if defined(CONFIG_BFIN_L2_ICACHEABLE)
1305 " in instruction cache\n");
1306 seq_printf(m
, "L2 SRAM\t\t: "
1307 #if defined(CONFIG_BFIN_L2_WRITEBACK)
1308 "cacheable (write-back)"
1309 #elif defined(CONFIG_BFIN_L2_WRITETHROUGH)
1310 "cacheable (write-through)"
1314 " in data cache\n");
1316 seq_printf(m
, "board name\t: %s\n", bfin_board_name
);
1317 seq_printf(m
, "board memory\t: %ld kB (0x%08lx -> 0x%08lx)\n",
1318 physical_mem_end
>> 10, 0ul, physical_mem_end
);
1319 seq_printf(m
, "kernel memory\t: %d kB (0x%08lx -> 0x%08lx)\n",
1320 ((int)memory_end
- (int)_rambase
) >> 10,
1321 _rambase
, memory_end
);
1326 static void *c_start(struct seq_file
*m
, loff_t
*pos
)
1329 *pos
= first_cpu(cpu_online_map
);
1330 if (*pos
>= num_online_cpus())
1336 static void *c_next(struct seq_file
*m
, void *v
, loff_t
*pos
)
1338 *pos
= next_cpu(*pos
, cpu_online_map
);
1340 return c_start(m
, pos
);
1343 static void c_stop(struct seq_file
*m
, void *v
)
1347 const struct seq_operations cpuinfo_op
= {
1351 .show
= show_cpuinfo
,
1354 void __init
cmdline_init(const char *r0
)
1356 early_shadow_stamp();
1358 strncpy(command_line
, r0
, COMMAND_LINE_SIZE
);