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ARM: 5621/1: at91/dmaengine: integration of at_hdmac driver in at91sam9g45 series
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / arch / arm / mach-at91 / at91sam9g45_devices.c
blob45720c84f0bfd1baed59e3d24c572b54e4b2d0e2
1 /*
2 * On-Chip devices setup code for the AT91SAM9G45 family
3 *
4 * Copyright (C) 2009 Atmel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 */
12 #include <asm/mach/arch.h>
13 #include <asm/mach/map.h>
14
15 #include <linux/dma-mapping.h>
16 #include <linux/platform_device.h>
17 #include <linux/i2c-gpio.h>
18
19 #include <linux/fb.h>
20 #include <video/atmel_lcdc.h>
21
22 #include <mach/board.h>
23 #include <mach/gpio.h>
24 #include <mach/at91sam9g45.h>
25 #include <mach/at91sam9g45_matrix.h>
26 #include <mach/at91sam9_smc.h>
27 #include <mach/at_hdmac.h>
28
29 #include "generic.h"
30
31
32 /* --------------------------------------------------------------------
33 * HDMAC - AHB DMA Controller
34 * -------------------------------------------------------------------- */
35
36 #if defined(CONFIG_AT_HDMAC) || defined(CONFIG_AT_HDMAC_MODULE)
37 static u64 hdmac_dmamask = DMA_BIT_MASK(32);
38
39 static struct at_dma_platform_data atdma_pdata = {
40 .nr_channels = 8,
41 };
42
43 static struct resource hdmac_resources[] = {
44 [0] = {
45 .start = AT91_BASE_SYS + AT91_DMA,
46 .end = AT91_BASE_SYS + AT91_DMA + SZ_512 - 1,
47 .flags = IORESOURCE_MEM,
48 },
49 [2] = {
50 .start = AT91SAM9G45_ID_DMA,
51 .end = AT91SAM9G45_ID_DMA,
52 .flags = IORESOURCE_IRQ,
53 },
54 };
55
56 static struct platform_device at_hdmac_device = {
57 .name = "at_hdmac",
58 .id = -1,
59 .dev = {
60 .dma_mask = &hdmac_dmamask,
61 .coherent_dma_mask = DMA_BIT_MASK(32),
62 .platform_data = &atdma_pdata,
63 },
64 .resource = hdmac_resources,
65 .num_resources = ARRAY_SIZE(hdmac_resources),
66 };
67
68 void __init at91_add_device_hdmac(void)
69 {
70 dma_cap_set(DMA_MEMCPY, atdma_pdata.cap_mask);
71 dma_cap_set(DMA_SLAVE, atdma_pdata.cap_mask);
72 platform_device_register(&at_hdmac_device);
73 }
74 #else
75 void __init at91_add_device_hdmac(void) {}
76 #endif
77
78
79 /* --------------------------------------------------------------------
80 * USB Host (OHCI)
81 * -------------------------------------------------------------------- */
82
83 #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
84 static u64 ohci_dmamask = DMA_BIT_MASK(32);
85 static struct at91_usbh_data usbh_ohci_data;
86
87 static struct resource usbh_ohci_resources[] = {
88 [0] = {
89 .start = AT91SAM9G45_OHCI_BASE,
90 .end = AT91SAM9G45_OHCI_BASE + SZ_1M - 1,
91 .flags = IORESOURCE_MEM,
92 },
93 [1] = {
94 .start = AT91SAM9G45_ID_UHPHS,
95 .end = AT91SAM9G45_ID_UHPHS,
96 .flags = IORESOURCE_IRQ,
97 },
98 };
99
100 static struct platform_device at91_usbh_ohci_device = {
101 .name = "at91_ohci",
102 .id = -1,
103 .dev = {
104 .dma_mask = &ohci_dmamask,
105 .coherent_dma_mask = DMA_BIT_MASK(32),
106 .platform_data = &usbh_ohci_data,
107 },
108 .resource = usbh_ohci_resources,
109 .num_resources = ARRAY_SIZE(usbh_ohci_resources),
110 };
111
112 void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data)
113 {
114 int i;
115
116 if (!data)
117 return;
118
119 /* Enable VBus control for UHP ports */
120 for (i = 0; i < data->ports; i++) {
121 if (data->vbus_pin[i])
122 at91_set_gpio_output(data->vbus_pin[i], 0);
123 }
124
125 usbh_ohci_data = *data;
126 platform_device_register(&at91_usbh_ohci_device);
127 }
128 #else
129 void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data) {}
130 #endif
131
132
133 /* --------------------------------------------------------------------
134 * USB HS Device (Gadget)
135 * -------------------------------------------------------------------- */
136
137 #if defined(CONFIG_USB_GADGET_ATMEL_USBA) || defined(CONFIG_USB_GADGET_ATMEL_USBA_MODULE)
138 static struct resource usba_udc_resources[] = {
139 [0] = {
140 .start = AT91SAM9G45_UDPHS_FIFO,
141 .end = AT91SAM9G45_UDPHS_FIFO + SZ_512K - 1,
142 .flags = IORESOURCE_MEM,
143 },
144 [1] = {
145 .start = AT91SAM9G45_BASE_UDPHS,
146 .end = AT91SAM9G45_BASE_UDPHS + SZ_1K - 1,
147 .flags = IORESOURCE_MEM,
148 },
149 [2] = {
150 .start = AT91SAM9G45_ID_UDPHS,
151 .end = AT91SAM9G45_ID_UDPHS,
152 .flags = IORESOURCE_IRQ,
153 },
154 };
155
156 #define EP(nam, idx, maxpkt, maxbk, dma, isoc) \
157 [idx] = { \
158 .name = nam, \
159 .index = idx, \
160 .fifo_size = maxpkt, \
161 .nr_banks = maxbk, \
162 .can_dma = dma, \
163 .can_isoc = isoc, \
164 }
165
166 static struct usba_ep_data usba_udc_ep[] __initdata = {
167 EP("ep0", 0, 64, 1, 0, 0),
168 EP("ep1", 1, 1024, 2, 1, 1),
169 EP("ep2", 2, 1024, 2, 1, 1),
170 EP("ep3", 3, 1024, 3, 1, 0),
171 EP("ep4", 4, 1024, 3, 1, 0),
172 EP("ep5", 5, 1024, 3, 1, 1),
173 EP("ep6", 6, 1024, 3, 1, 1),
174 };
175
176 #undef EP
177
178 /*
179 * pdata doesn't have room for any endpoints, so we need to
180 * append room for the ones we need right after it.
181 */
182 static struct {
183 struct usba_platform_data pdata;
184 struct usba_ep_data ep[7];
185 } usba_udc_data;
186
187 static struct platform_device at91_usba_udc_device = {
188 .name = "atmel_usba_udc",
189 .id = -1,
190 .dev = {
191 .platform_data = &usba_udc_data.pdata,
192 },
193 .resource = usba_udc_resources,
194 .num_resources = ARRAY_SIZE(usba_udc_resources),
195 };
196
197 void __init at91_add_device_usba(struct usba_platform_data *data)
198 {
199 usba_udc_data.pdata.vbus_pin = -EINVAL;
200 usba_udc_data.pdata.num_ep = ARRAY_SIZE(usba_udc_ep);
201 memcpy(usba_udc_data.ep, usba_udc_ep, sizeof(usba_udc_ep));;
202
203 if (data && data->vbus_pin > 0) {
204 at91_set_gpio_input(data->vbus_pin, 0);
205 at91_set_deglitch(data->vbus_pin, 1);
206 usba_udc_data.pdata.vbus_pin = data->vbus_pin;
207 }
208
209 /* Pullup pin is handled internally by USB device peripheral */
210
211 /* Clocks */
212 at91_clock_associate("utmi_clk", &at91_usba_udc_device.dev, "hclk");
213 at91_clock_associate("udphs_clk", &at91_usba_udc_device.dev, "pclk");
214
215 platform_device_register(&at91_usba_udc_device);
216 }
217 #else
218 void __init at91_add_device_usba(struct usba_platform_data *data) {}
219 #endif
220
221
222 /* --------------------------------------------------------------------
223 * Ethernet
224 * -------------------------------------------------------------------- */
225
226 #if defined(CONFIG_MACB) || defined(CONFIG_MACB_MODULE)
227 static u64 eth_dmamask = DMA_BIT_MASK(32);
228 static struct at91_eth_data eth_data;
229
230 static struct resource eth_resources[] = {
231 [0] = {
232 .start = AT91SAM9G45_BASE_EMAC,
233 .end = AT91SAM9G45_BASE_EMAC + SZ_16K - 1,
234 .flags = IORESOURCE_MEM,
235 },
236 [1] = {
237 .start = AT91SAM9G45_ID_EMAC,
238 .end = AT91SAM9G45_ID_EMAC,
239 .flags = IORESOURCE_IRQ,
240 },
241 };
242
243 static struct platform_device at91sam9g45_eth_device = {
244 .name = "macb",
245 .id = -1,
246 .dev = {
247 .dma_mask = &eth_dmamask,
248 .coherent_dma_mask = DMA_BIT_MASK(32),
249 .platform_data = &eth_data,
250 },
251 .resource = eth_resources,
252 .num_resources = ARRAY_SIZE(eth_resources),
253 };
254
255 void __init at91_add_device_eth(struct at91_eth_data *data)
256 {
257 if (!data)
258 return;
259
260 if (data->phy_irq_pin) {
261 at91_set_gpio_input(data->phy_irq_pin, 0);
262 at91_set_deglitch(data->phy_irq_pin, 1);
263 }
264
265 /* Pins used for MII and RMII */
266 at91_set_A_periph(AT91_PIN_PA17, 0); /* ETXCK_EREFCK */
267 at91_set_A_periph(AT91_PIN_PA15, 0); /* ERXDV */
268 at91_set_A_periph(AT91_PIN_PA12, 0); /* ERX0 */
269 at91_set_A_periph(AT91_PIN_PA13, 0); /* ERX1 */
270 at91_set_A_periph(AT91_PIN_PA16, 0); /* ERXER */
271 at91_set_A_periph(AT91_PIN_PA14, 0); /* ETXEN */
272 at91_set_A_periph(AT91_PIN_PA10, 0); /* ETX0 */
273 at91_set_A_periph(AT91_PIN_PA11, 0); /* ETX1 */
274 at91_set_A_periph(AT91_PIN_PA19, 0); /* EMDIO */
275 at91_set_A_periph(AT91_PIN_PA18, 0); /* EMDC */
276
277 if (!data->is_rmii) {
278 at91_set_B_periph(AT91_PIN_PA29, 0); /* ECRS */
279 at91_set_B_periph(AT91_PIN_PA30, 0); /* ECOL */
280 at91_set_B_periph(AT91_PIN_PA8, 0); /* ERX2 */
281 at91_set_B_periph(AT91_PIN_PA9, 0); /* ERX3 */
282 at91_set_B_periph(AT91_PIN_PA28, 0); /* ERXCK */
283 at91_set_B_periph(AT91_PIN_PA6, 0); /* ETX2 */
284 at91_set_B_periph(AT91_PIN_PA7, 0); /* ETX3 */
285 at91_set_B_periph(AT91_PIN_PA27, 0); /* ETXER */
286 }
287
288 eth_data = *data;
289 platform_device_register(&at91sam9g45_eth_device);
290 }
291 #else
292 void __init at91_add_device_eth(struct at91_eth_data *data) {}
293 #endif
294
295
296 /* --------------------------------------------------------------------
297 * NAND / SmartMedia
298 * -------------------------------------------------------------------- */
299
300 #if defined(CONFIG_MTD_NAND_ATMEL) || defined(CONFIG_MTD_NAND_ATMEL_MODULE)
301 static struct atmel_nand_data nand_data;
302
303 #define NAND_BASE AT91_CHIPSELECT_3
304
305 static struct resource nand_resources[] = {
306 [0] = {
307 .start = NAND_BASE,
308 .end = NAND_BASE + SZ_256M - 1,
309 .flags = IORESOURCE_MEM,
310 },
311 [1] = {
312 .start = AT91_BASE_SYS + AT91_ECC,
313 .end = AT91_BASE_SYS + AT91_ECC + SZ_512 - 1,
314 .flags = IORESOURCE_MEM,
315 }
316 };
317
318 static struct platform_device at91sam9g45_nand_device = {
319 .name = "atmel_nand",
320 .id = -1,
321 .dev = {
322 .platform_data = &nand_data,
323 },
324 .resource = nand_resources,
325 .num_resources = ARRAY_SIZE(nand_resources),
326 };
327
328 void __init at91_add_device_nand(struct atmel_nand_data *data)
329 {
330 unsigned long csa;
331
332 if (!data)
333 return;
334
335 csa = at91_sys_read(AT91_MATRIX_EBICSA);
336 at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA);
337
338 /* enable pin */
339 if (data->enable_pin)
340 at91_set_gpio_output(data->enable_pin, 1);
341
342 /* ready/busy pin */
343 if (data->rdy_pin)
344 at91_set_gpio_input(data->rdy_pin, 1);
345
346 /* card detect pin */
347 if (data->det_pin)
348 at91_set_gpio_input(data->det_pin, 1);
349
350 nand_data = *data;
351 platform_device_register(&at91sam9g45_nand_device);
352 }
353 #else
354 void __init at91_add_device_nand(struct atmel_nand_data *data) {}
355 #endif
356
357
358 /* --------------------------------------------------------------------
359 * TWI (i2c)
360 * -------------------------------------------------------------------- */
361
362 /*
363 * Prefer the GPIO code since the TWI controller isn't robust
364 * (gets overruns and underruns under load) and can only issue
365 * repeated STARTs in one scenario (the driver doesn't yet handle them).
366 */
367 #if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
368 static struct i2c_gpio_platform_data pdata_i2c0 = {
369 .sda_pin = AT91_PIN_PA20,
370 .sda_is_open_drain = 1,
371 .scl_pin = AT91_PIN_PA21,
372 .scl_is_open_drain = 1,
373 .udelay = 2, /* ~100 kHz */
374 };
375
376 static struct platform_device at91sam9g45_twi0_device = {
377 .name = "i2c-gpio",
378 .id = 0,
379 .dev.platform_data = &pdata_i2c0,
380 };
381
382 static struct i2c_gpio_platform_data pdata_i2c1 = {
383 .sda_pin = AT91_PIN_PB10,
384 .sda_is_open_drain = 1,
385 .scl_pin = AT91_PIN_PB11,
386 .scl_is_open_drain = 1,
387 .udelay = 2, /* ~100 kHz */
388 };
389
390 static struct platform_device at91sam9g45_twi1_device = {
391 .name = "i2c-gpio",
392 .id = 1,
393 .dev.platform_data = &pdata_i2c1,
394 };
395
396 void __init at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices)
397 {
398 i2c_register_board_info(i2c_id, devices, nr_devices);
399
400 if (i2c_id == 0) {
401 at91_set_GPIO_periph(AT91_PIN_PA20, 1); /* TWD (SDA) */
402 at91_set_multi_drive(AT91_PIN_PA20, 1);
403
404 at91_set_GPIO_periph(AT91_PIN_PA21, 1); /* TWCK (SCL) */
405 at91_set_multi_drive(AT91_PIN_PA21, 1);
406
407 platform_device_register(&at91sam9g45_twi0_device);
408 } else {
409 at91_set_GPIO_periph(AT91_PIN_PB10, 1); /* TWD (SDA) */
410 at91_set_multi_drive(AT91_PIN_PB10, 1);
411
412 at91_set_GPIO_periph(AT91_PIN_PB11, 1); /* TWCK (SCL) */
413 at91_set_multi_drive(AT91_PIN_PB11, 1);
414
415 platform_device_register(&at91sam9g45_twi1_device);
416 }
417 }
418
419 #elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
420 static struct resource twi0_resources[] = {
421 [0] = {
422 .start = AT91SAM9G45_BASE_TWI0,
423 .end = AT91SAM9G45_BASE_TWI0 + SZ_16K - 1,
424 .flags = IORESOURCE_MEM,
425 },
426 [1] = {
427 .start = AT91SAM9G45_ID_TWI0,
428 .end = AT91SAM9G45_ID_TWI0,
429 .flags = IORESOURCE_IRQ,
430 },
431 };
432
433 static struct platform_device at91sam9g45_twi0_device = {
434 .name = "at91_i2c",
435 .id = 0,
436 .resource = twi0_resources,
437 .num_resources = ARRAY_SIZE(twi0_resources),
438 };
439
440 static struct resource twi1_resources[] = {
441 [0] = {
442 .start = AT91SAM9G45_BASE_TWI1,
443 .end = AT91SAM9G45_BASE_TWI1 + SZ_16K - 1,
444 .flags = IORESOURCE_MEM,
445 },
446 [1] = {
447 .start = AT91SAM9G45_ID_TWI1,
448 .end = AT91SAM9G45_ID_TWI1,
449 .flags = IORESOURCE_IRQ,
450 },
451 };
452
453 static struct platform_device at91sam9g45_twi1_device = {
454 .name = "at91_i2c",
455 .id = 1,
456 .resource = twi1_resources,
457 .num_resources = ARRAY_SIZE(twi1_resources),
458 };
459
460 void __init at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices)
461 {
462 i2c_register_board_info(i2c_id, devices, nr_devices);
463
464 /* pins used for TWI interface */
465 if (i2c_id == 0) {
466 at91_set_A_periph(AT91_PIN_PA20, 0); /* TWD */
467 at91_set_multi_drive(AT91_PIN_PA20, 1);
468
469 at91_set_A_periph(AT91_PIN_PA21, 0); /* TWCK */
470 at91_set_multi_drive(AT91_PIN_PA21, 1);
471
472 platform_device_register(&at91sam9g45_twi0_device);
473 } else {
474 at91_set_A_periph(AT91_PIN_PB10, 0); /* TWD */
475 at91_set_multi_drive(AT91_PIN_PB10, 1);
476
477 at91_set_A_periph(AT91_PIN_PB11, 0); /* TWCK */
478 at91_set_multi_drive(AT91_PIN_PB11, 1);
479
480 platform_device_register(&at91sam9g45_twi1_device);
481 }
482 }
483 #else
484 void __init at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices) {}
485 #endif
486
487
488 /* --------------------------------------------------------------------
489 * SPI
490 * -------------------------------------------------------------------- */
491
492 #if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
493 static u64 spi_dmamask = DMA_BIT_MASK(32);
494
495 static struct resource spi0_resources[] = {
496 [0] = {
497 .start = AT91SAM9G45_BASE_SPI0,
498 .end = AT91SAM9G45_BASE_SPI0 + SZ_16K - 1,
499 .flags = IORESOURCE_MEM,
500 },
501 [1] = {
502 .start = AT91SAM9G45_ID_SPI0,
503 .end = AT91SAM9G45_ID_SPI0,
504 .flags = IORESOURCE_IRQ,
505 },
506 };
507
508 static struct platform_device at91sam9g45_spi0_device = {
509 .name = "atmel_spi",
510 .id = 0,
511 .dev = {
512 .dma_mask = &spi_dmamask,
513 .coherent_dma_mask = DMA_BIT_MASK(32),
514 },
515 .resource = spi0_resources,
516 .num_resources = ARRAY_SIZE(spi0_resources),
517 };
518
519 static const unsigned spi0_standard_cs[4] = { AT91_PIN_PB3, AT91_PIN_PB18, AT91_PIN_PB19, AT91_PIN_PD27 };
520
521 static struct resource spi1_resources[] = {
522 [0] = {
523 .start = AT91SAM9G45_BASE_SPI1,
524 .end = AT91SAM9G45_BASE_SPI1 + SZ_16K - 1,
525 .flags = IORESOURCE_MEM,
526 },
527 [1] = {
528 .start = AT91SAM9G45_ID_SPI1,
529 .end = AT91SAM9G45_ID_SPI1,
530 .flags = IORESOURCE_IRQ,
531 },
532 };
533
534 static struct platform_device at91sam9g45_spi1_device = {
535 .name = "atmel_spi",
536 .id = 1,
537 .dev = {
538 .dma_mask = &spi_dmamask,
539 .coherent_dma_mask = DMA_BIT_MASK(32),
540 },
541 .resource = spi1_resources,
542 .num_resources = ARRAY_SIZE(spi1_resources),
543 };
544
545 static const unsigned spi1_standard_cs[4] = { AT91_PIN_PB17, AT91_PIN_PD28, AT91_PIN_PD18, AT91_PIN_PD19 };
546
547 void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
548 {
549 int i;
550 unsigned long cs_pin;
551 short enable_spi0 = 0;
552 short enable_spi1 = 0;
553
554 /* Choose SPI chip-selects */
555 for (i = 0; i < nr_devices; i++) {
556 if (devices[i].controller_data)
557 cs_pin = (unsigned long) devices[i].controller_data;
558 else if (devices[i].bus_num == 0)
559 cs_pin = spi0_standard_cs[devices[i].chip_select];
560 else
561 cs_pin = spi1_standard_cs[devices[i].chip_select];
562
563 if (devices[i].bus_num == 0)
564 enable_spi0 = 1;
565 else
566 enable_spi1 = 1;
567
568 /* enable chip-select pin */
569 at91_set_gpio_output(cs_pin, 1);
570
571 /* pass chip-select pin to driver */
572 devices[i].controller_data = (void *) cs_pin;
573 }
574
575 spi_register_board_info(devices, nr_devices);
576
577 /* Configure SPI bus(es) */
578 if (enable_spi0) {
579 at91_set_A_periph(AT91_PIN_PB0, 0); /* SPI0_MISO */
580 at91_set_A_periph(AT91_PIN_PB1, 0); /* SPI0_MOSI */
581 at91_set_A_periph(AT91_PIN_PB2, 0); /* SPI0_SPCK */
582
583 at91_clock_associate("spi0_clk", &at91sam9g45_spi0_device.dev, "spi_clk");
584 platform_device_register(&at91sam9g45_spi0_device);
585 }
586 if (enable_spi1) {
587 at91_set_A_periph(AT91_PIN_PB14, 0); /* SPI1_MISO */
588 at91_set_A_periph(AT91_PIN_PB15, 0); /* SPI1_MOSI */
589 at91_set_A_periph(AT91_PIN_PB16, 0); /* SPI1_SPCK */
590
591 at91_clock_associate("spi1_clk", &at91sam9g45_spi1_device.dev, "spi_clk");
592 platform_device_register(&at91sam9g45_spi1_device);
593 }
594 }
595 #else
596 void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
597 #endif
598
599
600 /* --------------------------------------------------------------------
601 * LCD Controller
602 * -------------------------------------------------------------------- */
603
604 #if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
605 static u64 lcdc_dmamask = DMA_BIT_MASK(32);
606 static struct atmel_lcdfb_info lcdc_data;
607
608 static struct resource lcdc_resources[] = {
609 [0] = {
610 .start = AT91SAM9G45_LCDC_BASE,
611 .end = AT91SAM9G45_LCDC_BASE + SZ_4K - 1,
612 .flags = IORESOURCE_MEM,
613 },
614 [1] = {
615 .start = AT91SAM9G45_ID_LCDC,
616 .end = AT91SAM9G45_ID_LCDC,
617 .flags = IORESOURCE_IRQ,
618 },
619 };
620
621 static struct platform_device at91_lcdc_device = {
622 .name = "atmel_lcdfb",
623 .id = 0,
624 .dev = {
625 .dma_mask = &lcdc_dmamask,
626 .coherent_dma_mask = DMA_BIT_MASK(32),
627 .platform_data = &lcdc_data,
628 },
629 .resource = lcdc_resources,
630 .num_resources = ARRAY_SIZE(lcdc_resources),
631 };
632
633 void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
634 {
635 if (!data)
636 return;
637
638 at91_set_A_periph(AT91_PIN_PE0, 0); /* LCDDPWR */
639
640 at91_set_A_periph(AT91_PIN_PE2, 0); /* LCDCC */
641 at91_set_A_periph(AT91_PIN_PE3, 0); /* LCDVSYNC */
642 at91_set_A_periph(AT91_PIN_PE4, 0); /* LCDHSYNC */
643 at91_set_A_periph(AT91_PIN_PE5, 0); /* LCDDOTCK */
644 at91_set_A_periph(AT91_PIN_PE6, 0); /* LCDDEN */
645 at91_set_A_periph(AT91_PIN_PE7, 0); /* LCDD0 */
646 at91_set_A_periph(AT91_PIN_PE8, 0); /* LCDD1 */
647 at91_set_A_periph(AT91_PIN_PE9, 0); /* LCDD2 */
648 at91_set_A_periph(AT91_PIN_PE10, 0); /* LCDD3 */
649 at91_set_A_periph(AT91_PIN_PE11, 0); /* LCDD4 */
650 at91_set_A_periph(AT91_PIN_PE12, 0); /* LCDD5 */
651 at91_set_A_periph(AT91_PIN_PE13, 0); /* LCDD6 */
652 at91_set_A_periph(AT91_PIN_PE14, 0); /* LCDD7 */
653 at91_set_A_periph(AT91_PIN_PE15, 0); /* LCDD8 */
654 at91_set_A_periph(AT91_PIN_PE16, 0); /* LCDD9 */
655 at91_set_A_periph(AT91_PIN_PE17, 0); /* LCDD10 */
656 at91_set_A_periph(AT91_PIN_PE18, 0); /* LCDD11 */
657 at91_set_A_periph(AT91_PIN_PE19, 0); /* LCDD12 */
658 at91_set_A_periph(AT91_PIN_PE20, 0); /* LCDD13 */
659 at91_set_A_periph(AT91_PIN_PE21, 0); /* LCDD14 */
660 at91_set_A_periph(AT91_PIN_PE22, 0); /* LCDD15 */
661 at91_set_A_periph(AT91_PIN_PE23, 0); /* LCDD16 */
662 at91_set_A_periph(AT91_PIN_PE24, 0); /* LCDD17 */
663 at91_set_A_periph(AT91_PIN_PE25, 0); /* LCDD18 */
664 at91_set_A_periph(AT91_PIN_PE26, 0); /* LCDD19 */
665 at91_set_A_periph(AT91_PIN_PE27, 0); /* LCDD20 */
666 at91_set_A_periph(AT91_PIN_PE28, 0); /* LCDD21 */
667 at91_set_A_periph(AT91_PIN_PE29, 0); /* LCDD22 */
668 at91_set_A_periph(AT91_PIN_PE30, 0); /* LCDD23 */
669
670 lcdc_data = *data;
671 platform_device_register(&at91_lcdc_device);
672 }
673 #else
674 void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {}
675 #endif
676
677
678 /* --------------------------------------------------------------------
679 * Timer/Counter block
680 * -------------------------------------------------------------------- */
681
682 #ifdef CONFIG_ATMEL_TCLIB
683 static struct resource tcb0_resources[] = {
684 [0] = {
685 .start = AT91SAM9G45_BASE_TCB0,
686 .end = AT91SAM9G45_BASE_TCB0 + SZ_16K - 1,
687 .flags = IORESOURCE_MEM,
688 },
689 [1] = {
690 .start = AT91SAM9G45_ID_TCB,
691 .end = AT91SAM9G45_ID_TCB,
692 .flags = IORESOURCE_IRQ,
693 },
694 };
695
696 static struct platform_device at91sam9g45_tcb0_device = {
697 .name = "atmel_tcb",
698 .id = 0,
699 .resource = tcb0_resources,
700 .num_resources = ARRAY_SIZE(tcb0_resources),
701 };
702
703 /* TCB1 begins with TC3 */
704 static struct resource tcb1_resources[] = {
705 [0] = {
706 .start = AT91SAM9G45_BASE_TCB1,
707 .end = AT91SAM9G45_BASE_TCB1 + SZ_16K - 1,
708 .flags = IORESOURCE_MEM,
709 },
710 [1] = {
711 .start = AT91SAM9G45_ID_TCB,
712 .end = AT91SAM9G45_ID_TCB,
713 .flags = IORESOURCE_IRQ,
714 },
715 };
716
717 static struct platform_device at91sam9g45_tcb1_device = {
718 .name = "atmel_tcb",
719 .id = 1,
720 .resource = tcb1_resources,
721 .num_resources = ARRAY_SIZE(tcb1_resources),
722 };
723
724 static void __init at91_add_device_tc(void)
725 {
726 /* this chip has one clock and irq for all six TC channels */
727 at91_clock_associate("tcb_clk", &at91sam9g45_tcb0_device.dev, "t0_clk");
728 platform_device_register(&at91sam9g45_tcb0_device);
729 at91_clock_associate("tcb_clk", &at91sam9g45_tcb1_device.dev, "t0_clk");
730 platform_device_register(&at91sam9g45_tcb1_device);
731 }
732 #else
733 static void __init at91_add_device_tc(void) { }
734 #endif
735
736
737 /* --------------------------------------------------------------------
738 * RTC
739 * -------------------------------------------------------------------- */
740
741 #if defined(CONFIG_RTC_DRV_AT91RM9200) || defined(CONFIG_RTC_DRV_AT91RM9200_MODULE)
742 static struct platform_device at91sam9g45_rtc_device = {
743 .name = "at91_rtc",
744 .id = -1,
745 .num_resources = 0,
746 };
747
748 static void __init at91_add_device_rtc(void)
749 {
750 platform_device_register(&at91sam9g45_rtc_device);
751 }
752 #else
753 static void __init at91_add_device_rtc(void) {}
754 #endif
755
756
757 /* --------------------------------------------------------------------
758 * RTT
759 * -------------------------------------------------------------------- */
760
761 static struct resource rtt_resources[] = {
762 {
763 .start = AT91_BASE_SYS + AT91_RTT,
764 .end = AT91_BASE_SYS + AT91_RTT + SZ_16 - 1,
765 .flags = IORESOURCE_MEM,
766 }
767 };
768
769 static struct platform_device at91sam9g45_rtt_device = {
770 .name = "at91_rtt",
771 .id = 0,
772 .resource = rtt_resources,
773 .num_resources = ARRAY_SIZE(rtt_resources),
774 };
775
776 static void __init at91_add_device_rtt(void)
777 {
778 platform_device_register(&at91sam9g45_rtt_device);
779 }
780
781
782 /* --------------------------------------------------------------------
783 * Watchdog
784 * -------------------------------------------------------------------- */
785
786 #if defined(CONFIG_AT91SAM9_WATCHDOG) || defined(CONFIG_AT91SAM9_WATCHDOG_MODULE)
787 static struct platform_device at91sam9g45_wdt_device = {
788 .name = "at91_wdt",
789 .id = -1,
790 .num_resources = 0,
791 };
792
793 static void __init at91_add_device_watchdog(void)
794 {
795 platform_device_register(&at91sam9g45_wdt_device);
796 }
797 #else
798 static void __init at91_add_device_watchdog(void) {}
799 #endif
800
801
802 /* --------------------------------------------------------------------
803 * PWM
804 * --------------------------------------------------------------------*/
805
806 #if defined(CONFIG_ATMEL_PWM) || defined(CONFIG_ATMEL_PWM_MODULE)
807 static u32 pwm_mask;
808
809 static struct resource pwm_resources[] = {
810 [0] = {
811 .start = AT91SAM9G45_BASE_PWMC,
812 .end = AT91SAM9G45_BASE_PWMC + SZ_16K - 1,
813 .flags = IORESOURCE_MEM,
814 },
815 [1] = {
816 .start = AT91SAM9G45_ID_PWMC,
817 .end = AT91SAM9G45_ID_PWMC,
818 .flags = IORESOURCE_IRQ,
819 },
820 };
821
822 static struct platform_device at91sam9g45_pwm0_device = {
823 .name = "atmel_pwm",
824 .id = -1,
825 .dev = {
826 .platform_data = &pwm_mask,
827 },
828 .resource = pwm_resources,
829 .num_resources = ARRAY_SIZE(pwm_resources),
830 };
831
832 void __init at91_add_device_pwm(u32 mask)
833 {
834 if (mask & (1 << AT91_PWM0))
835 at91_set_B_periph(AT91_PIN_PD24, 1); /* enable PWM0 */
836
837 if (mask & (1 << AT91_PWM1))
838 at91_set_B_periph(AT91_PIN_PD31, 1); /* enable PWM1 */
839
840 if (mask & (1 << AT91_PWM2))
841 at91_set_B_periph(AT91_PIN_PD26, 1); /* enable PWM2 */
842
843 if (mask & (1 << AT91_PWM3))
844 at91_set_B_periph(AT91_PIN_PD0, 1); /* enable PWM3 */
845
846 pwm_mask = mask;
847
848 platform_device_register(&at91sam9g45_pwm0_device);
849 }
850 #else
851 void __init at91_add_device_pwm(u32 mask) {}
852 #endif
853
854
855 /* --------------------------------------------------------------------
856 * SSC -- Synchronous Serial Controller
857 * -------------------------------------------------------------------- */
858
859 #if defined(CONFIG_ATMEL_SSC) || defined(CONFIG_ATMEL_SSC_MODULE)
860 static u64 ssc0_dmamask = DMA_BIT_MASK(32);
861
862 static struct resource ssc0_resources[] = {
863 [0] = {
864 .start = AT91SAM9G45_BASE_SSC0,
865 .end = AT91SAM9G45_BASE_SSC0 + SZ_16K - 1,
866 .flags = IORESOURCE_MEM,
867 },
868 [1] = {
869 .start = AT91SAM9G45_ID_SSC0,
870 .end = AT91SAM9G45_ID_SSC0,
871 .flags = IORESOURCE_IRQ,
872 },
873 };
874
875 static struct platform_device at91sam9g45_ssc0_device = {
876 .name = "ssc",
877 .id = 0,
878 .dev = {
879 .dma_mask = &ssc0_dmamask,
880 .coherent_dma_mask = DMA_BIT_MASK(32),
881 },
882 .resource = ssc0_resources,
883 .num_resources = ARRAY_SIZE(ssc0_resources),
884 };
885
886 static inline void configure_ssc0_pins(unsigned pins)
887 {
888 if (pins & ATMEL_SSC_TF)
889 at91_set_A_periph(AT91_PIN_PD1, 1);
890 if (pins & ATMEL_SSC_TK)
891 at91_set_A_periph(AT91_PIN_PD0, 1);
892 if (pins & ATMEL_SSC_TD)
893 at91_set_A_periph(AT91_PIN_PD2, 1);
894 if (pins & ATMEL_SSC_RD)
895 at91_set_A_periph(AT91_PIN_PD3, 1);
896 if (pins & ATMEL_SSC_RK)
897 at91_set_A_periph(AT91_PIN_PD4, 1);
898 if (pins & ATMEL_SSC_RF)
899 at91_set_A_periph(AT91_PIN_PD5, 1);
900 }
901
902 static u64 ssc1_dmamask = DMA_BIT_MASK(32);
903
904 static struct resource ssc1_resources[] = {
905 [0] = {
906 .start = AT91SAM9G45_BASE_SSC1,
907 .end = AT91SAM9G45_BASE_SSC1 + SZ_16K - 1,
908 .flags = IORESOURCE_MEM,
909 },
910 [1] = {
911 .start = AT91SAM9G45_ID_SSC1,
912 .end = AT91SAM9G45_ID_SSC1,
913 .flags = IORESOURCE_IRQ,
914 },
915 };
916
917 static struct platform_device at91sam9g45_ssc1_device = {
918 .name = "ssc",
919 .id = 1,
920 .dev = {
921 .dma_mask = &ssc1_dmamask,
922 .coherent_dma_mask = DMA_BIT_MASK(32),
923 },
924 .resource = ssc1_resources,
925 .num_resources = ARRAY_SIZE(ssc1_resources),
926 };
927
928 static inline void configure_ssc1_pins(unsigned pins)
929 {
930 if (pins & ATMEL_SSC_TF)
931 at91_set_A_periph(AT91_PIN_PD14, 1);
932 if (pins & ATMEL_SSC_TK)
933 at91_set_A_periph(AT91_PIN_PD12, 1);
934 if (pins & ATMEL_SSC_TD)
935 at91_set_A_periph(AT91_PIN_PD10, 1);
936 if (pins & ATMEL_SSC_RD)
937 at91_set_A_periph(AT91_PIN_PD11, 1);
938 if (pins & ATMEL_SSC_RK)
939 at91_set_A_periph(AT91_PIN_PD13, 1);
940 if (pins & ATMEL_SSC_RF)
941 at91_set_A_periph(AT91_PIN_PD15, 1);
942 }
943
944 /*
945 * SSC controllers are accessed through library code, instead of any
946 * kind of all-singing/all-dancing driver. For example one could be
947 * used by a particular I2S audio codec's driver, while another one
948 * on the same system might be used by a custom data capture driver.
949 */
950 void __init at91_add_device_ssc(unsigned id, unsigned pins)
951 {
952 struct platform_device *pdev;
953
954 /*
955 * NOTE: caller is responsible for passing information matching
956 * "pins" to whatever will be using each particular controller.
957 */
958 switch (id) {
959 case AT91SAM9G45_ID_SSC0:
960 pdev = &at91sam9g45_ssc0_device;
961 configure_ssc0_pins(pins);
962 at91_clock_associate("ssc0_clk", &pdev->dev, "pclk");
963 break;
964 case AT91SAM9G45_ID_SSC1:
965 pdev = &at91sam9g45_ssc1_device;
966 configure_ssc1_pins(pins);
967 at91_clock_associate("ssc1_clk", &pdev->dev, "pclk");
968 break;
969 default:
970 return;
971 }
972
973 platform_device_register(pdev);
974 }
975
976 #else
977 void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
978 #endif
979
980
981 /* --------------------------------------------------------------------
982 * UART
983 * -------------------------------------------------------------------- */
984
985 #if defined(CONFIG_SERIAL_ATMEL)
986 static struct resource dbgu_resources[] = {
987 [0] = {
988 .start = AT91_VA_BASE_SYS + AT91_DBGU,
989 .end = AT91_VA_BASE_SYS + AT91_DBGU + SZ_512 - 1,
990 .flags = IORESOURCE_MEM,
991 },
992 [1] = {
993 .start = AT91_ID_SYS,
994 .end = AT91_ID_SYS,
995 .flags = IORESOURCE_IRQ,
996 },
997 };
998
999 static struct atmel_uart_data dbgu_data = {
1000 .use_dma_tx = 0,
1001 .use_dma_rx = 0,
1002 .regs = (void __iomem *)(AT91_VA_BASE_SYS + AT91_DBGU),
1003 };
1004
1005 static u64 dbgu_dmamask = DMA_BIT_MASK(32);
1006
1007 static struct platform_device at91sam9g45_dbgu_device = {
1008 .name = "atmel_usart",
1009 .id = 0,
1010 .dev = {
1011 .dma_mask = &dbgu_dmamask,
1012 .coherent_dma_mask = DMA_BIT_MASK(32),
1013 .platform_data = &dbgu_data,
1014 },
1015 .resource = dbgu_resources,
1016 .num_resources = ARRAY_SIZE(dbgu_resources),
1017 };
1018
1019 static inline void configure_dbgu_pins(void)
1020 {
1021 at91_set_A_periph(AT91_PIN_PB12, 0); /* DRXD */
1022 at91_set_A_periph(AT91_PIN_PB13, 1); /* DTXD */
1023 }
1024
1025 static struct resource uart0_resources[] = {
1026 [0] = {
1027 .start = AT91SAM9G45_BASE_US0,
1028 .end = AT91SAM9G45_BASE_US0 + SZ_16K - 1,
1029 .flags = IORESOURCE_MEM,
1030 },
1031 [1] = {
1032 .start = AT91SAM9G45_ID_US0,
1033 .end = AT91SAM9G45_ID_US0,
1034 .flags = IORESOURCE_IRQ,
1035 },
1036 };
1037
1038 static struct atmel_uart_data uart0_data = {
1039 .use_dma_tx = 1,
1040 .use_dma_rx = 1,
1041 };
1042
1043 static u64 uart0_dmamask = DMA_BIT_MASK(32);
1044
1045 static struct platform_device at91sam9g45_uart0_device = {
1046 .name = "atmel_usart",
1047 .id = 1,
1048 .dev = {
1049 .dma_mask = &uart0_dmamask,
1050 .coherent_dma_mask = DMA_BIT_MASK(32),
1051 .platform_data = &uart0_data,
1052 },
1053 .resource = uart0_resources,
1054 .num_resources = ARRAY_SIZE(uart0_resources),
1055 };
1056
1057 static inline void configure_usart0_pins(unsigned pins)
1058 {
1059 at91_set_A_periph(AT91_PIN_PB19, 1); /* TXD0 */
1060 at91_set_A_periph(AT91_PIN_PB18, 0); /* RXD0 */
1061
1062 if (pins & ATMEL_UART_RTS)
1063 at91_set_B_periph(AT91_PIN_PB17, 0); /* RTS0 */
1064 if (pins & ATMEL_UART_CTS)
1065 at91_set_B_periph(AT91_PIN_PB15, 0); /* CTS0 */
1066 }
1067
1068 static struct resource uart1_resources[] = {
1069 [0] = {
1070 .start = AT91SAM9G45_BASE_US1,
1071 .end = AT91SAM9G45_BASE_US1 + SZ_16K - 1,
1072 .flags = IORESOURCE_MEM,
1073 },
1074 [1] = {
1075 .start = AT91SAM9G45_ID_US1,
1076 .end = AT91SAM9G45_ID_US1,
1077 .flags = IORESOURCE_IRQ,
1078 },
1079 };
1080
1081 static struct atmel_uart_data uart1_data = {
1082 .use_dma_tx = 1,
1083 .use_dma_rx = 1,
1084 };
1085
1086 static u64 uart1_dmamask = DMA_BIT_MASK(32);
1087
1088 static struct platform_device at91sam9g45_uart1_device = {
1089 .name = "atmel_usart",
1090 .id = 2,
1091 .dev = {
1092 .dma_mask = &uart1_dmamask,
1093 .coherent_dma_mask = DMA_BIT_MASK(32),
1094 .platform_data = &uart1_data,
1095 },
1096 .resource = uart1_resources,
1097 .num_resources = ARRAY_SIZE(uart1_resources),
1098 };
1099
1100 static inline void configure_usart1_pins(unsigned pins)
1101 {
1102 at91_set_A_periph(AT91_PIN_PB4, 1); /* TXD1 */
1103 at91_set_A_periph(AT91_PIN_PB5, 0); /* RXD1 */
1104
1105 if (pins & ATMEL_UART_RTS)
1106 at91_set_A_periph(AT91_PIN_PD16, 0); /* RTS1 */
1107 if (pins & ATMEL_UART_CTS)
1108 at91_set_A_periph(AT91_PIN_PD17, 0); /* CTS1 */
1109 }
1110
1111 static struct resource uart2_resources[] = {
1112 [0] = {
1113 .start = AT91SAM9G45_BASE_US2,
1114 .end = AT91SAM9G45_BASE_US2 + SZ_16K - 1,
1115 .flags = IORESOURCE_MEM,
1116 },
1117 [1] = {
1118 .start = AT91SAM9G45_ID_US2,
1119 .end = AT91SAM9G45_ID_US2,
1120 .flags = IORESOURCE_IRQ,
1121 },
1122 };
1123
1124 static struct atmel_uart_data uart2_data = {
1125 .use_dma_tx = 1,
1126 .use_dma_rx = 1,
1127 };
1128
1129 static u64 uart2_dmamask = DMA_BIT_MASK(32);
1130
1131 static struct platform_device at91sam9g45_uart2_device = {
1132 .name = "atmel_usart",
1133 .id = 3,
1134 .dev = {
1135 .dma_mask = &uart2_dmamask,
1136 .coherent_dma_mask = DMA_BIT_MASK(32),
1137 .platform_data = &uart2_data,
1138 },
1139 .resource = uart2_resources,
1140 .num_resources = ARRAY_SIZE(uart2_resources),
1141 };
1142
1143 static inline void configure_usart2_pins(unsigned pins)
1144 {
1145 at91_set_A_periph(AT91_PIN_PB6, 1); /* TXD2 */
1146 at91_set_A_periph(AT91_PIN_PB7, 0); /* RXD2 */
1147
1148 if (pins & ATMEL_UART_RTS)
1149 at91_set_B_periph(AT91_PIN_PC9, 0); /* RTS2 */
1150 if (pins & ATMEL_UART_CTS)
1151 at91_set_B_periph(AT91_PIN_PC11, 0); /* CTS2 */
1152 }
1153
1154 static struct resource uart3_resources[] = {
1155 [0] = {
1156 .start = AT91SAM9G45_BASE_US3,
1157 .end = AT91SAM9G45_BASE_US3 + SZ_16K - 1,
1158 .flags = IORESOURCE_MEM,
1159 },
1160 [1] = {
1161 .start = AT91SAM9G45_ID_US3,
1162 .end = AT91SAM9G45_ID_US3,
1163 .flags = IORESOURCE_IRQ,
1164 },
1165 };
1166
1167 static struct atmel_uart_data uart3_data = {
1168 .use_dma_tx = 1,
1169 .use_dma_rx = 1,
1170 };
1171
1172 static u64 uart3_dmamask = DMA_BIT_MASK(32);
1173
1174 static struct platform_device at91sam9g45_uart3_device = {
1175 .name = "atmel_usart",
1176 .id = 4,
1177 .dev = {
1178 .dma_mask = &uart3_dmamask,
1179 .coherent_dma_mask = DMA_BIT_MASK(32),
1180 .platform_data = &uart3_data,
1181 },
1182 .resource = uart3_resources,
1183 .num_resources = ARRAY_SIZE(uart3_resources),
1184 };
1185
1186 static inline void configure_usart3_pins(unsigned pins)
1187 {
1188 at91_set_A_periph(AT91_PIN_PB8, 1); /* TXD3 */
1189 at91_set_A_periph(AT91_PIN_PB9, 0); /* RXD3 */
1190
1191 if (pins & ATMEL_UART_RTS)
1192 at91_set_B_periph(AT91_PIN_PA23, 0); /* RTS3 */
1193 if (pins & ATMEL_UART_CTS)
1194 at91_set_B_periph(AT91_PIN_PA24, 0); /* CTS3 */
1195 }
1196
1197 static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
1198 struct platform_device *atmel_default_console_device; /* the serial console device */
1199
1200 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
1201 {
1202 struct platform_device *pdev;
1203
1204 switch (id) {
1205 case 0: /* DBGU */
1206 pdev = &at91sam9g45_dbgu_device;
1207 configure_dbgu_pins();
1208 at91_clock_associate("mck", &pdev->dev, "usart");
1209 break;
1210 case AT91SAM9G45_ID_US0:
1211 pdev = &at91sam9g45_uart0_device;
1212 configure_usart0_pins(pins);
1213 at91_clock_associate("usart0_clk", &pdev->dev, "usart");
1214 break;
1215 case AT91SAM9G45_ID_US1:
1216 pdev = &at91sam9g45_uart1_device;
1217 configure_usart1_pins(pins);
1218 at91_clock_associate("usart1_clk", &pdev->dev, "usart");
1219 break;
1220 case AT91SAM9G45_ID_US2:
1221 pdev = &at91sam9g45_uart2_device;
1222 configure_usart2_pins(pins);
1223 at91_clock_associate("usart2_clk", &pdev->dev, "usart");
1224 break;
1225 case AT91SAM9G45_ID_US3:
1226 pdev = &at91sam9g45_uart3_device;
1227 configure_usart3_pins(pins);
1228 at91_clock_associate("usart3_clk", &pdev->dev, "usart");
1229 break;
1230 default:
1231 return;
1232 }
1233 pdev->id = portnr; /* update to mapped ID */
1234
1235 if (portnr < ATMEL_MAX_UART)
1236 at91_uarts[portnr] = pdev;
1237 }
1238
1239 void __init at91_set_serial_console(unsigned portnr)
1240 {
1241 if (portnr < ATMEL_MAX_UART)
1242 atmel_default_console_device = at91_uarts[portnr];
1243 }
1244
1245 void __init at91_add_device_serial(void)
1246 {
1247 int i;
1248
1249 for (i = 0; i < ATMEL_MAX_UART; i++) {
1250 if (at91_uarts[i])
1251 platform_device_register(at91_uarts[i]);
1252 }
1253
1254 if (!atmel_default_console_device)
1255 printk(KERN_INFO "AT91: No default serial console defined.\n");
1256 }
1257 #else
1258 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
1259 void __init at91_set_serial_console(unsigned portnr) {}
1260 void __init at91_add_device_serial(void) {}
1261 #endif
1262
1263
1264 /* -------------------------------------------------------------------- */
1265 /*
1266 * These devices are always present and don't need any board-specific
1267 * setup.
1268 */
1269 static int __init at91_add_standard_devices(void)
1270 {
1271 at91_add_device_hdmac();
1272 at91_add_device_rtc();
1273 at91_add_device_rtt();
1274 at91_add_device_watchdog();
1275 at91_add_device_tc();
1276 return 0;
1277 }
1278
1279 arch_initcall(at91_add_standard_devices);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree