x86, ioapic: Fix potential resume deadlock
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / arch / x86 / kernel / pci-dma.c
blob9ea999a4dcc178ce4e27dd069a957ff050d1dee7
1 #include <linux/dma-mapping.h>
2 #include <linux/dma-debug.h>
3 #include <linux/dmar.h>
4 #include <linux/bootmem.h>
5 #include <linux/gfp.h>
6 #include <linux/pci.h>
7 #include <linux/kmemleak.h>
9 #include <asm/proto.h>
10 #include <asm/dma.h>
11 #include <asm/iommu.h>
12 #include <asm/gart.h>
13 #include <asm/calgary.h>
14 #include <asm/x86_init.h>
15 #include <asm/iommu_table.h>
17 static int forbid_dac __read_mostly;
19 struct dma_map_ops *dma_ops = &nommu_dma_ops;
20 EXPORT_SYMBOL(dma_ops);
22 static int iommu_sac_force __read_mostly;
24 #ifdef CONFIG_IOMMU_DEBUG
25 int panic_on_overflow __read_mostly = 1;
26 int force_iommu __read_mostly = 1;
27 #else
28 int panic_on_overflow __read_mostly = 0;
29 int force_iommu __read_mostly = 0;
30 #endif
32 int iommu_merge __read_mostly = 0;
34 int no_iommu __read_mostly;
35 /* Set this to 1 if there is a HW IOMMU in the system */
36 int iommu_detected __read_mostly = 0;
39 * This variable becomes 1 if iommu=pt is passed on the kernel command line.
40 * If this variable is 1, IOMMU implementations do no DMA translation for
41 * devices and allow every device to access to whole physical memory. This is
42 * useful if a user wants to use an IOMMU only for KVM device assignment to
43 * guests and not for driver dma translation.
45 int iommu_pass_through __read_mostly;
47 extern struct iommu_table_entry __iommu_table[], __iommu_table_end[];
49 /* Dummy device used for NULL arguments (normally ISA). */
50 struct device x86_dma_fallback_dev = {
51 .init_name = "fallback device",
52 .coherent_dma_mask = ISA_DMA_BIT_MASK,
53 .dma_mask = &x86_dma_fallback_dev.coherent_dma_mask,
55 EXPORT_SYMBOL(x86_dma_fallback_dev);
57 /* Number of entries preallocated for DMA-API debugging */
58 #define PREALLOC_DMA_DEBUG_ENTRIES 32768
60 int dma_set_mask(struct device *dev, u64 mask)
62 if (!dev->dma_mask || !dma_supported(dev, mask))
63 return -EIO;
65 *dev->dma_mask = mask;
67 return 0;
69 EXPORT_SYMBOL(dma_set_mask);
71 #if defined(CONFIG_X86_64) && !defined(CONFIG_NUMA)
72 static __initdata void *dma32_bootmem_ptr;
73 static unsigned long dma32_bootmem_size __initdata = (128ULL<<20);
75 static int __init parse_dma32_size_opt(char *p)
77 if (!p)
78 return -EINVAL;
79 dma32_bootmem_size = memparse(p, &p);
80 return 0;
82 early_param("dma32_size", parse_dma32_size_opt);
84 void __init dma32_reserve_bootmem(void)
86 unsigned long size, align;
87 if (max_pfn <= MAX_DMA32_PFN)
88 return;
91 * check aperture_64.c allocate_aperture() for reason about
92 * using 512M as goal
94 align = 64ULL<<20;
95 size = roundup(dma32_bootmem_size, align);
96 dma32_bootmem_ptr = __alloc_bootmem_nopanic(size, align,
97 512ULL<<20);
99 * Kmemleak should not scan this block as it may not be mapped via the
100 * kernel direct mapping.
102 kmemleak_ignore(dma32_bootmem_ptr);
103 if (dma32_bootmem_ptr)
104 dma32_bootmem_size = size;
105 else
106 dma32_bootmem_size = 0;
108 static void __init dma32_free_bootmem(void)
111 if (max_pfn <= MAX_DMA32_PFN)
112 return;
114 if (!dma32_bootmem_ptr)
115 return;
117 free_bootmem(__pa(dma32_bootmem_ptr), dma32_bootmem_size);
119 dma32_bootmem_ptr = NULL;
120 dma32_bootmem_size = 0;
122 #else
123 void __init dma32_reserve_bootmem(void)
126 static void __init dma32_free_bootmem(void)
130 #endif
132 void __init pci_iommu_alloc(void)
134 struct iommu_table_entry *p;
136 /* free the range so iommu could get some range less than 4G */
137 dma32_free_bootmem();
139 sort_iommu_table(__iommu_table, __iommu_table_end);
140 check_iommu_entries(__iommu_table, __iommu_table_end);
142 for (p = __iommu_table; p < __iommu_table_end; p++) {
143 if (p && p->detect && p->detect() > 0) {
144 p->flags |= IOMMU_DETECTED;
145 if (p->early_init)
146 p->early_init();
147 if (p->flags & IOMMU_FINISH_IF_DETECTED)
148 break;
152 void *dma_generic_alloc_coherent(struct device *dev, size_t size,
153 dma_addr_t *dma_addr, gfp_t flag)
155 unsigned long dma_mask;
156 struct page *page;
157 dma_addr_t addr;
159 dma_mask = dma_alloc_coherent_mask(dev, flag);
161 flag |= __GFP_ZERO;
162 again:
163 page = alloc_pages_node(dev_to_node(dev), flag, get_order(size));
164 if (!page)
165 return NULL;
167 addr = page_to_phys(page);
168 if (addr + size > dma_mask) {
169 __free_pages(page, get_order(size));
171 if (dma_mask < DMA_BIT_MASK(32) && !(flag & GFP_DMA)) {
172 flag = (flag & ~GFP_DMA32) | GFP_DMA;
173 goto again;
176 return NULL;
179 *dma_addr = addr;
180 return page_address(page);
184 * See <Documentation/x86_64/boot-options.txt> for the iommu kernel parameter
185 * documentation.
187 static __init int iommu_setup(char *p)
189 iommu_merge = 1;
191 if (!p)
192 return -EINVAL;
194 while (*p) {
195 if (!strncmp(p, "off", 3))
196 no_iommu = 1;
197 /* gart_parse_options has more force support */
198 if (!strncmp(p, "force", 5))
199 force_iommu = 1;
200 if (!strncmp(p, "noforce", 7)) {
201 iommu_merge = 0;
202 force_iommu = 0;
205 if (!strncmp(p, "biomerge", 8)) {
206 iommu_merge = 1;
207 force_iommu = 1;
209 if (!strncmp(p, "panic", 5))
210 panic_on_overflow = 1;
211 if (!strncmp(p, "nopanic", 7))
212 panic_on_overflow = 0;
213 if (!strncmp(p, "merge", 5)) {
214 iommu_merge = 1;
215 force_iommu = 1;
217 if (!strncmp(p, "nomerge", 7))
218 iommu_merge = 0;
219 if (!strncmp(p, "forcesac", 8))
220 iommu_sac_force = 1;
221 if (!strncmp(p, "allowdac", 8))
222 forbid_dac = 0;
223 if (!strncmp(p, "nodac", 5))
224 forbid_dac = 1;
225 if (!strncmp(p, "usedac", 6)) {
226 forbid_dac = -1;
227 return 1;
229 #ifdef CONFIG_SWIOTLB
230 if (!strncmp(p, "soft", 4))
231 swiotlb = 1;
232 #endif
233 if (!strncmp(p, "pt", 2))
234 iommu_pass_through = 1;
236 gart_parse_options(p);
238 #ifdef CONFIG_CALGARY_IOMMU
239 if (!strncmp(p, "calgary", 7))
240 use_calgary = 1;
241 #endif /* CONFIG_CALGARY_IOMMU */
243 p += strcspn(p, ",");
244 if (*p == ',')
245 ++p;
247 return 0;
249 early_param("iommu", iommu_setup);
251 int dma_supported(struct device *dev, u64 mask)
253 struct dma_map_ops *ops = get_dma_ops(dev);
255 #ifdef CONFIG_PCI
256 if (mask > 0xffffffff && forbid_dac > 0) {
257 dev_info(dev, "PCI: Disallowing DAC for device\n");
258 return 0;
260 #endif
262 if (ops->dma_supported)
263 return ops->dma_supported(dev, mask);
265 /* Copied from i386. Doesn't make much sense, because it will
266 only work for pci_alloc_coherent.
267 The caller just has to use GFP_DMA in this case. */
268 if (mask < DMA_BIT_MASK(24))
269 return 0;
271 /* Tell the device to use SAC when IOMMU force is on. This
272 allows the driver to use cheaper accesses in some cases.
274 Problem with this is that if we overflow the IOMMU area and
275 return DAC as fallback address the device may not handle it
276 correctly.
278 As a special case some controllers have a 39bit address
279 mode that is as efficient as 32bit (aic79xx). Don't force
280 SAC for these. Assume all masks <= 40 bits are of this
281 type. Normally this doesn't make any difference, but gives
282 more gentle handling of IOMMU overflow. */
283 if (iommu_sac_force && (mask >= DMA_BIT_MASK(40))) {
284 dev_info(dev, "Force SAC with mask %Lx\n", mask);
285 return 0;
288 return 1;
290 EXPORT_SYMBOL(dma_supported);
292 static int __init pci_iommu_init(void)
294 struct iommu_table_entry *p;
295 dma_debug_init(PREALLOC_DMA_DEBUG_ENTRIES);
297 #ifdef CONFIG_PCI
298 dma_debug_add_bus(&pci_bus_type);
299 #endif
300 x86_init.iommu.iommu_init();
302 for (p = __iommu_table; p < __iommu_table_end; p++) {
303 if (p && (p->flags & IOMMU_DETECTED) && p->late_init)
304 p->late_init();
307 return 0;
309 /* Must execute after PCI subsystem */
310 rootfs_initcall(pci_iommu_init);
312 #ifdef CONFIG_PCI
313 /* Many VIA bridges seem to corrupt data for DAC. Disable it here */
315 static __devinit void via_no_dac(struct pci_dev *dev)
317 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI && forbid_dac == 0) {
318 dev_info(&dev->dev, "disabling DAC on VIA PCI bridge\n");
319 forbid_dac = 1;
322 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_ANY_ID, via_no_dac);
323 #endif