2 * xHCI host controller driver
4 * Copyright (C) 2008 Intel Corp.
7 * Some code borrowed from the Linux EHCI driver.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 * Ring initialization rules:
25 * 1. Each segment is initialized to zero, except for link TRBs.
26 * 2. Ring cycle state = 0. This represents Producer Cycle State (PCS) or
27 * Consumer Cycle State (CCS), depending on ring function.
28 * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
30 * Ring behavior rules:
31 * 1. A ring is empty if enqueue == dequeue. This means there will always be at
32 * least one free TRB in the ring. This is useful if you want to turn that
33 * into a link TRB and expand the ring.
34 * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
35 * link TRB, then load the pointer with the address in the link TRB. If the
36 * link TRB had its toggle bit set, you may need to update the ring cycle
37 * state (see cycle bit rules). You may have to do this multiple times
38 * until you reach a non-link TRB.
39 * 3. A ring is full if enqueue++ (for the definition of increment above)
40 * equals the dequeue pointer.
43 * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
44 * in a link TRB, it must toggle the ring cycle state.
45 * 2. When a producer increments an enqueue pointer and encounters a toggle bit
46 * in a link TRB, it must toggle the ring cycle state.
49 * 1. Check if ring is full before you enqueue.
50 * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
51 * Update enqueue pointer between each write (which may update the ring
53 * 3. Notify consumer. If SW is producer, it rings the doorbell for command
54 * and endpoint rings. If HC is the producer for the event ring,
55 * and it generates an interrupt according to interrupt modulation rules.
58 * 1. Check if TRB belongs to you. If the cycle bit == your ring cycle state,
59 * the TRB is owned by the consumer.
60 * 2. Update dequeue pointer (which may update the ring cycle state) and
61 * continue processing TRBs until you reach a TRB which is not owned by you.
62 * 3. Notify the producer. SW is the consumer for the event ring, and it
63 * updates event ring dequeue pointer. HC is the consumer for the command and
64 * endpoint rings; it generates events on the event ring for these.
67 #include <linux/scatterlist.h>
68 #include <linux/slab.h>
71 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd
*xhci
,
72 struct xhci_virt_device
*virt_dev
,
73 struct xhci_event_cmd
*event
);
76 * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
79 dma_addr_t
xhci_trb_virt_to_dma(struct xhci_segment
*seg
,
82 unsigned long segment_offset
;
84 if (!seg
|| !trb
|| trb
< seg
->trbs
)
87 segment_offset
= trb
- seg
->trbs
;
88 if (segment_offset
> TRBS_PER_SEGMENT
)
90 return seg
->dma
+ (segment_offset
* sizeof(*trb
));
93 /* Does this link TRB point to the first segment in a ring,
94 * or was the previous TRB the last TRB on the last segment in the ERST?
96 static bool last_trb_on_last_seg(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
97 struct xhci_segment
*seg
, union xhci_trb
*trb
)
99 if (ring
== xhci
->event_ring
)
100 return (trb
== &seg
->trbs
[TRBS_PER_SEGMENT
]) &&
101 (seg
->next
== xhci
->event_ring
->first_seg
);
103 return le32_to_cpu(trb
->link
.control
) & LINK_TOGGLE
;
106 /* Is this TRB a link TRB or was the last TRB the last TRB in this event ring
107 * segment? I.e. would the updated event TRB pointer step off the end of the
110 static int last_trb(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
111 struct xhci_segment
*seg
, union xhci_trb
*trb
)
113 if (ring
== xhci
->event_ring
)
114 return trb
== &seg
->trbs
[TRBS_PER_SEGMENT
];
116 return TRB_TYPE_LINK_LE32(trb
->link
.control
);
119 static int enqueue_is_link_trb(struct xhci_ring
*ring
)
121 struct xhci_link_trb
*link
= &ring
->enqueue
->link
;
122 return TRB_TYPE_LINK_LE32(link
->control
);
125 /* Updates trb to point to the next TRB in the ring, and updates seg if the next
126 * TRB is in a new segment. This does not skip over link TRBs, and it does not
127 * effect the ring dequeue or enqueue pointers.
129 static void next_trb(struct xhci_hcd
*xhci
,
130 struct xhci_ring
*ring
,
131 struct xhci_segment
**seg
,
132 union xhci_trb
**trb
)
134 if (last_trb(xhci
, ring
, *seg
, *trb
)) {
136 *trb
= ((*seg
)->trbs
);
143 * See Cycle bit rules. SW is the consumer for the event ring only.
144 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
146 static void inc_deq(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
, bool consumer
)
148 union xhci_trb
*next
= ++(ring
->dequeue
);
149 unsigned long long addr
;
152 /* Update the dequeue pointer further if that was a link TRB or we're at
153 * the end of an event ring segment (which doesn't have link TRBS)
155 while (last_trb(xhci
, ring
, ring
->deq_seg
, next
)) {
156 if (consumer
&& last_trb_on_last_seg(xhci
, ring
, ring
->deq_seg
, next
)) {
157 ring
->cycle_state
= (ring
->cycle_state
? 0 : 1);
159 xhci_dbg(xhci
, "Toggle cycle state for ring %p = %i\n",
161 (unsigned int) ring
->cycle_state
);
163 ring
->deq_seg
= ring
->deq_seg
->next
;
164 ring
->dequeue
= ring
->deq_seg
->trbs
;
165 next
= ring
->dequeue
;
167 addr
= (unsigned long long) xhci_trb_virt_to_dma(ring
->deq_seg
, ring
->dequeue
);
171 * See Cycle bit rules. SW is the consumer for the event ring only.
172 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
174 * If we've just enqueued a TRB that is in the middle of a TD (meaning the
175 * chain bit is set), then set the chain bit in all the following link TRBs.
176 * If we've enqueued the last TRB in a TD, make sure the following link TRBs
177 * have their chain bit cleared (so that each Link TRB is a separate TD).
179 * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
180 * set, but other sections talk about dealing with the chain bit set. This was
181 * fixed in the 0.96 specification errata, but we have to assume that all 0.95
182 * xHCI hardware can't handle the chain bit being cleared on a link TRB.
184 * @more_trbs_coming: Will you enqueue more TRBs before calling
185 * prepare_transfer()?
187 static void inc_enq(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
188 bool consumer
, bool more_trbs_coming
, bool isoc
)
191 union xhci_trb
*next
;
192 unsigned long long addr
;
194 chain
= le32_to_cpu(ring
->enqueue
->generic
.field
[3]) & TRB_CHAIN
;
195 next
= ++(ring
->enqueue
);
198 /* Update the dequeue pointer further if that was a link TRB or we're at
199 * the end of an event ring segment (which doesn't have link TRBS)
201 while (last_trb(xhci
, ring
, ring
->enq_seg
, next
)) {
203 if (ring
!= xhci
->event_ring
) {
205 * If the caller doesn't plan on enqueueing more
206 * TDs before ringing the doorbell, then we
207 * don't want to give the link TRB to the
208 * hardware just yet. We'll give the link TRB
209 * back in prepare_ring() just before we enqueue
210 * the TD at the top of the ring.
212 if (!chain
&& !more_trbs_coming
)
215 /* If we're not dealing with 0.95 hardware or
216 * isoc rings on AMD 0.96 host,
217 * carry over the chain bit of the previous TRB
218 * (which may mean the chain bit is cleared).
220 if (!(isoc
&& (xhci
->quirks
& XHCI_AMD_0x96_HOST
))
221 && !xhci_link_trb_quirk(xhci
)) {
222 next
->link
.control
&=
223 cpu_to_le32(~TRB_CHAIN
);
224 next
->link
.control
|=
227 /* Give this link TRB to the hardware */
229 next
->link
.control
^= cpu_to_le32(TRB_CYCLE
);
231 /* Toggle the cycle bit after the last ring segment. */
232 if (last_trb_on_last_seg(xhci
, ring
, ring
->enq_seg
, next
)) {
233 ring
->cycle_state
= (ring
->cycle_state
? 0 : 1);
235 xhci_dbg(xhci
, "Toggle cycle state for ring %p = %i\n",
237 (unsigned int) ring
->cycle_state
);
240 ring
->enq_seg
= ring
->enq_seg
->next
;
241 ring
->enqueue
= ring
->enq_seg
->trbs
;
242 next
= ring
->enqueue
;
244 addr
= (unsigned long long) xhci_trb_virt_to_dma(ring
->enq_seg
, ring
->enqueue
);
248 * Check to see if there's room to enqueue num_trbs on the ring. See rules
250 * FIXME: this would be simpler and faster if we just kept track of the number
251 * of free TRBs in a ring.
253 static int room_on_ring(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
254 unsigned int num_trbs
)
257 union xhci_trb
*enq
= ring
->enqueue
;
258 struct xhci_segment
*enq_seg
= ring
->enq_seg
;
259 struct xhci_segment
*cur_seg
;
260 unsigned int left_on_ring
;
262 /* If we are currently pointing to a link TRB, advance the
263 * enqueue pointer before checking for space */
264 while (last_trb(xhci
, ring
, enq_seg
, enq
)) {
265 enq_seg
= enq_seg
->next
;
269 /* Check if ring is empty */
270 if (enq
== ring
->dequeue
) {
271 /* Can't use link trbs */
272 left_on_ring
= TRBS_PER_SEGMENT
- 1;
273 for (cur_seg
= enq_seg
->next
; cur_seg
!= enq_seg
;
274 cur_seg
= cur_seg
->next
)
275 left_on_ring
+= TRBS_PER_SEGMENT
- 1;
277 /* Always need one TRB free in the ring. */
279 if (num_trbs
> left_on_ring
) {
280 xhci_warn(xhci
, "Not enough room on ring; "
281 "need %u TRBs, %u TRBs left\n",
282 num_trbs
, left_on_ring
);
287 /* Make sure there's an extra empty TRB available */
288 for (i
= 0; i
<= num_trbs
; ++i
) {
289 if (enq
== ring
->dequeue
)
292 while (last_trb(xhci
, ring
, enq_seg
, enq
)) {
293 enq_seg
= enq_seg
->next
;
300 /* Ring the host controller doorbell after placing a command on the ring */
301 void xhci_ring_cmd_db(struct xhci_hcd
*xhci
)
303 xhci_dbg(xhci
, "// Ding dong!\n");
304 xhci_writel(xhci
, DB_VALUE_HOST
, &xhci
->dba
->doorbell
[0]);
305 /* Flush PCI posted writes */
306 xhci_readl(xhci
, &xhci
->dba
->doorbell
[0]);
309 void xhci_ring_ep_doorbell(struct xhci_hcd
*xhci
,
310 unsigned int slot_id
,
311 unsigned int ep_index
,
312 unsigned int stream_id
)
314 __le32 __iomem
*db_addr
= &xhci
->dba
->doorbell
[slot_id
];
315 struct xhci_virt_ep
*ep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
316 unsigned int ep_state
= ep
->ep_state
;
318 /* Don't ring the doorbell for this endpoint if there are pending
319 * cancellations because we don't want to interrupt processing.
320 * We don't want to restart any stream rings if there's a set dequeue
321 * pointer command pending because the device can choose to start any
322 * stream once the endpoint is on the HW schedule.
323 * FIXME - check all the stream rings for pending cancellations.
325 if ((ep_state
& EP_HALT_PENDING
) || (ep_state
& SET_DEQ_PENDING
) ||
326 (ep_state
& EP_HALTED
))
328 xhci_writel(xhci
, DB_VALUE(ep_index
, stream_id
), db_addr
);
329 /* The CPU has better things to do at this point than wait for a
330 * write-posting flush. It'll get there soon enough.
334 /* Ring the doorbell for any rings with pending URBs */
335 static void ring_doorbell_for_active_rings(struct xhci_hcd
*xhci
,
336 unsigned int slot_id
,
337 unsigned int ep_index
)
339 unsigned int stream_id
;
340 struct xhci_virt_ep
*ep
;
342 ep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
344 /* A ring has pending URBs if its TD list is not empty */
345 if (!(ep
->ep_state
& EP_HAS_STREAMS
)) {
346 if (!(list_empty(&ep
->ring
->td_list
)))
347 xhci_ring_ep_doorbell(xhci
, slot_id
, ep_index
, 0);
351 for (stream_id
= 1; stream_id
< ep
->stream_info
->num_streams
;
353 struct xhci_stream_info
*stream_info
= ep
->stream_info
;
354 if (!list_empty(&stream_info
->stream_rings
[stream_id
]->td_list
))
355 xhci_ring_ep_doorbell(xhci
, slot_id
, ep_index
,
361 * Find the segment that trb is in. Start searching in start_seg.
362 * If we must move past a segment that has a link TRB with a toggle cycle state
363 * bit set, then we will toggle the value pointed at by cycle_state.
365 static struct xhci_segment
*find_trb_seg(
366 struct xhci_segment
*start_seg
,
367 union xhci_trb
*trb
, int *cycle_state
)
369 struct xhci_segment
*cur_seg
= start_seg
;
370 struct xhci_generic_trb
*generic_trb
;
372 while (cur_seg
->trbs
> trb
||
373 &cur_seg
->trbs
[TRBS_PER_SEGMENT
- 1] < trb
) {
374 generic_trb
= &cur_seg
->trbs
[TRBS_PER_SEGMENT
- 1].generic
;
375 if (generic_trb
->field
[3] & cpu_to_le32(LINK_TOGGLE
))
377 cur_seg
= cur_seg
->next
;
378 if (cur_seg
== start_seg
)
379 /* Looped over the entire list. Oops! */
386 static struct xhci_ring
*xhci_triad_to_transfer_ring(struct xhci_hcd
*xhci
,
387 unsigned int slot_id
, unsigned int ep_index
,
388 unsigned int stream_id
)
390 struct xhci_virt_ep
*ep
;
392 ep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
393 /* Common case: no streams */
394 if (!(ep
->ep_state
& EP_HAS_STREAMS
))
397 if (stream_id
== 0) {
399 "WARN: Slot ID %u, ep index %u has streams, "
400 "but URB has no stream ID.\n",
405 if (stream_id
< ep
->stream_info
->num_streams
)
406 return ep
->stream_info
->stream_rings
[stream_id
];
409 "WARN: Slot ID %u, ep index %u has "
410 "stream IDs 1 to %u allocated, "
411 "but stream ID %u is requested.\n",
413 ep
->stream_info
->num_streams
- 1,
418 /* Get the right ring for the given URB.
419 * If the endpoint supports streams, boundary check the URB's stream ID.
420 * If the endpoint doesn't support streams, return the singular endpoint ring.
422 static struct xhci_ring
*xhci_urb_to_transfer_ring(struct xhci_hcd
*xhci
,
425 return xhci_triad_to_transfer_ring(xhci
, urb
->dev
->slot_id
,
426 xhci_get_endpoint_index(&urb
->ep
->desc
), urb
->stream_id
);
430 * Move the xHC's endpoint ring dequeue pointer past cur_td.
431 * Record the new state of the xHC's endpoint ring dequeue segment,
432 * dequeue pointer, and new consumer cycle state in state.
433 * Update our internal representation of the ring's dequeue pointer.
435 * We do this in three jumps:
436 * - First we update our new ring state to be the same as when the xHC stopped.
437 * - Then we traverse the ring to find the segment that contains
438 * the last TRB in the TD. We toggle the xHC's new cycle state when we pass
439 * any link TRBs with the toggle cycle bit set.
440 * - Finally we move the dequeue state one TRB further, toggling the cycle bit
441 * if we've moved it past a link TRB with the toggle cycle bit set.
443 * Some of the uses of xhci_generic_trb are grotty, but if they're done
444 * with correct __le32 accesses they should work fine. Only users of this are
447 void xhci_find_new_dequeue_state(struct xhci_hcd
*xhci
,
448 unsigned int slot_id
, unsigned int ep_index
,
449 unsigned int stream_id
, struct xhci_td
*cur_td
,
450 struct xhci_dequeue_state
*state
)
452 struct xhci_virt_device
*dev
= xhci
->devs
[slot_id
];
453 struct xhci_ring
*ep_ring
;
454 struct xhci_generic_trb
*trb
;
455 struct xhci_ep_ctx
*ep_ctx
;
458 ep_ring
= xhci_triad_to_transfer_ring(xhci
, slot_id
,
459 ep_index
, stream_id
);
461 xhci_warn(xhci
, "WARN can't find new dequeue state "
462 "for invalid stream ID %u.\n",
466 state
->new_cycle_state
= 0;
467 xhci_dbg(xhci
, "Finding segment containing stopped TRB.\n");
468 state
->new_deq_seg
= find_trb_seg(cur_td
->start_seg
,
469 dev
->eps
[ep_index
].stopped_trb
,
470 &state
->new_cycle_state
);
471 if (!state
->new_deq_seg
) {
476 /* Dig out the cycle state saved by the xHC during the stop ep cmd */
477 xhci_dbg(xhci
, "Finding endpoint context\n");
478 ep_ctx
= xhci_get_ep_ctx(xhci
, dev
->out_ctx
, ep_index
);
479 state
->new_cycle_state
= 0x1 & le64_to_cpu(ep_ctx
->deq
);
481 state
->new_deq_ptr
= cur_td
->last_trb
;
482 xhci_dbg(xhci
, "Finding segment containing last TRB in TD.\n");
483 state
->new_deq_seg
= find_trb_seg(state
->new_deq_seg
,
485 &state
->new_cycle_state
);
486 if (!state
->new_deq_seg
) {
491 trb
= &state
->new_deq_ptr
->generic
;
492 if (TRB_TYPE_LINK_LE32(trb
->field
[3]) &&
493 (trb
->field
[3] & cpu_to_le32(LINK_TOGGLE
)))
494 state
->new_cycle_state
^= 0x1;
495 next_trb(xhci
, ep_ring
, &state
->new_deq_seg
, &state
->new_deq_ptr
);
498 * If there is only one segment in a ring, find_trb_seg()'s while loop
499 * will not run, and it will return before it has a chance to see if it
500 * needs to toggle the cycle bit. It can't tell if the stalled transfer
501 * ended just before the link TRB on a one-segment ring, or if the TD
502 * wrapped around the top of the ring, because it doesn't have the TD in
503 * question. Look for the one-segment case where stalled TRB's address
504 * is greater than the new dequeue pointer address.
506 if (ep_ring
->first_seg
== ep_ring
->first_seg
->next
&&
507 state
->new_deq_ptr
< dev
->eps
[ep_index
].stopped_trb
)
508 state
->new_cycle_state
^= 0x1;
509 xhci_dbg(xhci
, "Cycle state = 0x%x\n", state
->new_cycle_state
);
511 /* Don't update the ring cycle state for the producer (us). */
512 xhci_dbg(xhci
, "New dequeue segment = %p (virtual)\n",
514 addr
= xhci_trb_virt_to_dma(state
->new_deq_seg
, state
->new_deq_ptr
);
515 xhci_dbg(xhci
, "New dequeue pointer = 0x%llx (DMA)\n",
516 (unsigned long long) addr
);
519 /* flip_cycle means flip the cycle bit of all but the first and last TRB.
520 * (The last TRB actually points to the ring enqueue pointer, which is not part
521 * of this TD.) This is used to remove partially enqueued isoc TDs from a ring.
523 static void td_to_noop(struct xhci_hcd
*xhci
, struct xhci_ring
*ep_ring
,
524 struct xhci_td
*cur_td
, bool flip_cycle
)
526 struct xhci_segment
*cur_seg
;
527 union xhci_trb
*cur_trb
;
529 for (cur_seg
= cur_td
->start_seg
, cur_trb
= cur_td
->first_trb
;
531 next_trb(xhci
, ep_ring
, &cur_seg
, &cur_trb
)) {
532 if (TRB_TYPE_LINK_LE32(cur_trb
->generic
.field
[3])) {
533 /* Unchain any chained Link TRBs, but
534 * leave the pointers intact.
536 cur_trb
->generic
.field
[3] &= cpu_to_le32(~TRB_CHAIN
);
537 /* Flip the cycle bit (link TRBs can't be the first
541 cur_trb
->generic
.field
[3] ^=
542 cpu_to_le32(TRB_CYCLE
);
543 xhci_dbg(xhci
, "Cancel (unchain) link TRB\n");
544 xhci_dbg(xhci
, "Address = %p (0x%llx dma); "
545 "in seg %p (0x%llx dma)\n",
547 (unsigned long long)xhci_trb_virt_to_dma(cur_seg
, cur_trb
),
549 (unsigned long long)cur_seg
->dma
);
551 cur_trb
->generic
.field
[0] = 0;
552 cur_trb
->generic
.field
[1] = 0;
553 cur_trb
->generic
.field
[2] = 0;
554 /* Preserve only the cycle bit of this TRB */
555 cur_trb
->generic
.field
[3] &= cpu_to_le32(TRB_CYCLE
);
556 /* Flip the cycle bit except on the first or last TRB */
557 if (flip_cycle
&& cur_trb
!= cur_td
->first_trb
&&
558 cur_trb
!= cur_td
->last_trb
)
559 cur_trb
->generic
.field
[3] ^=
560 cpu_to_le32(TRB_CYCLE
);
561 cur_trb
->generic
.field
[3] |= cpu_to_le32(
562 TRB_TYPE(TRB_TR_NOOP
));
563 xhci_dbg(xhci
, "Cancel TRB %p (0x%llx dma) "
564 "in seg %p (0x%llx dma)\n",
566 (unsigned long long)xhci_trb_virt_to_dma(cur_seg
, cur_trb
),
568 (unsigned long long)cur_seg
->dma
);
570 if (cur_trb
== cur_td
->last_trb
)
575 static int queue_set_tr_deq(struct xhci_hcd
*xhci
, int slot_id
,
576 unsigned int ep_index
, unsigned int stream_id
,
577 struct xhci_segment
*deq_seg
,
578 union xhci_trb
*deq_ptr
, u32 cycle_state
);
580 void xhci_queue_new_dequeue_state(struct xhci_hcd
*xhci
,
581 unsigned int slot_id
, unsigned int ep_index
,
582 unsigned int stream_id
,
583 struct xhci_dequeue_state
*deq_state
)
585 struct xhci_virt_ep
*ep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
587 xhci_dbg(xhci
, "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), "
588 "new deq ptr = %p (0x%llx dma), new cycle = %u\n",
589 deq_state
->new_deq_seg
,
590 (unsigned long long)deq_state
->new_deq_seg
->dma
,
591 deq_state
->new_deq_ptr
,
592 (unsigned long long)xhci_trb_virt_to_dma(deq_state
->new_deq_seg
, deq_state
->new_deq_ptr
),
593 deq_state
->new_cycle_state
);
594 queue_set_tr_deq(xhci
, slot_id
, ep_index
, stream_id
,
595 deq_state
->new_deq_seg
,
596 deq_state
->new_deq_ptr
,
597 (u32
) deq_state
->new_cycle_state
);
598 /* Stop the TD queueing code from ringing the doorbell until
599 * this command completes. The HC won't set the dequeue pointer
600 * if the ring is running, and ringing the doorbell starts the
603 ep
->ep_state
|= SET_DEQ_PENDING
;
606 static void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd
*xhci
,
607 struct xhci_virt_ep
*ep
)
609 ep
->ep_state
&= ~EP_HALT_PENDING
;
610 /* Can't del_timer_sync in interrupt, so we attempt to cancel. If the
611 * timer is running on another CPU, we don't decrement stop_cmds_pending
612 * (since we didn't successfully stop the watchdog timer).
614 if (del_timer(&ep
->stop_cmd_timer
))
615 ep
->stop_cmds_pending
--;
618 /* Must be called with xhci->lock held in interrupt context */
619 static void xhci_giveback_urb_in_irq(struct xhci_hcd
*xhci
,
620 struct xhci_td
*cur_td
, int status
, char *adjective
)
624 struct urb_priv
*urb_priv
;
627 urb_priv
= urb
->hcpriv
;
629 hcd
= bus_to_hcd(urb
->dev
->bus
);
631 /* Only giveback urb when this is the last td in urb */
632 if (urb_priv
->td_cnt
== urb_priv
->length
) {
633 if (usb_pipetype(urb
->pipe
) == PIPE_ISOCHRONOUS
) {
634 xhci_to_hcd(xhci
)->self
.bandwidth_isoc_reqs
--;
635 if (xhci_to_hcd(xhci
)->self
.bandwidth_isoc_reqs
== 0) {
636 if (xhci
->quirks
& XHCI_AMD_PLL_FIX
)
637 usb_amd_quirk_pll_enable();
640 usb_hcd_unlink_urb_from_ep(hcd
, urb
);
642 spin_unlock(&xhci
->lock
);
643 usb_hcd_giveback_urb(hcd
, urb
, status
);
644 xhci_urb_free_priv(xhci
, urb_priv
);
645 spin_lock(&xhci
->lock
);
650 * When we get a command completion for a Stop Endpoint Command, we need to
651 * unlink any cancelled TDs from the ring. There are two ways to do that:
653 * 1. If the HW was in the middle of processing the TD that needs to be
654 * cancelled, then we must move the ring's dequeue pointer past the last TRB
655 * in the TD with a Set Dequeue Pointer Command.
656 * 2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
657 * bit cleared) so that the HW will skip over them.
659 static void handle_stopped_endpoint(struct xhci_hcd
*xhci
,
660 union xhci_trb
*trb
, struct xhci_event_cmd
*event
)
662 unsigned int slot_id
;
663 unsigned int ep_index
;
664 struct xhci_virt_device
*virt_dev
;
665 struct xhci_ring
*ep_ring
;
666 struct xhci_virt_ep
*ep
;
667 struct list_head
*entry
;
668 struct xhci_td
*cur_td
= NULL
;
669 struct xhci_td
*last_unlinked_td
;
671 struct xhci_dequeue_state deq_state
;
673 if (unlikely(TRB_TO_SUSPEND_PORT(
674 le32_to_cpu(xhci
->cmd_ring
->dequeue
->generic
.field
[3])))) {
675 slot_id
= TRB_TO_SLOT_ID(
676 le32_to_cpu(xhci
->cmd_ring
->dequeue
->generic
.field
[3]));
677 virt_dev
= xhci
->devs
[slot_id
];
679 handle_cmd_in_cmd_wait_list(xhci
, virt_dev
,
682 xhci_warn(xhci
, "Stop endpoint command "
683 "completion for disabled slot %u\n",
688 memset(&deq_state
, 0, sizeof(deq_state
));
689 slot_id
= TRB_TO_SLOT_ID(le32_to_cpu(trb
->generic
.field
[3]));
690 ep_index
= TRB_TO_EP_INDEX(le32_to_cpu(trb
->generic
.field
[3]));
691 ep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
693 if (list_empty(&ep
->cancelled_td_list
)) {
694 xhci_stop_watchdog_timer_in_irq(xhci
, ep
);
695 ep
->stopped_td
= NULL
;
696 ep
->stopped_trb
= NULL
;
697 ring_doorbell_for_active_rings(xhci
, slot_id
, ep_index
);
701 /* Fix up the ep ring first, so HW stops executing cancelled TDs.
702 * We have the xHCI lock, so nothing can modify this list until we drop
703 * it. We're also in the event handler, so we can't get re-interrupted
704 * if another Stop Endpoint command completes
706 list_for_each(entry
, &ep
->cancelled_td_list
) {
707 cur_td
= list_entry(entry
, struct xhci_td
, cancelled_td_list
);
708 xhci_dbg(xhci
, "Cancelling TD starting at %p, 0x%llx (dma).\n",
710 (unsigned long long)xhci_trb_virt_to_dma(cur_td
->start_seg
, cur_td
->first_trb
));
711 ep_ring
= xhci_urb_to_transfer_ring(xhci
, cur_td
->urb
);
713 /* This shouldn't happen unless a driver is mucking
714 * with the stream ID after submission. This will
715 * leave the TD on the hardware ring, and the hardware
716 * will try to execute it, and may access a buffer
717 * that has already been freed. In the best case, the
718 * hardware will execute it, and the event handler will
719 * ignore the completion event for that TD, since it was
720 * removed from the td_list for that endpoint. In
721 * short, don't muck with the stream ID after
724 xhci_warn(xhci
, "WARN Cancelled URB %p "
725 "has invalid stream ID %u.\n",
727 cur_td
->urb
->stream_id
);
728 goto remove_finished_td
;
731 * If we stopped on the TD we need to cancel, then we have to
732 * move the xHC endpoint ring dequeue pointer past this TD.
734 if (cur_td
== ep
->stopped_td
)
735 xhci_find_new_dequeue_state(xhci
, slot_id
, ep_index
,
736 cur_td
->urb
->stream_id
,
739 td_to_noop(xhci
, ep_ring
, cur_td
, false);
742 * The event handler won't see a completion for this TD anymore,
743 * so remove it from the endpoint ring's TD list. Keep it in
744 * the cancelled TD list for URB completion later.
746 list_del_init(&cur_td
->td_list
);
748 last_unlinked_td
= cur_td
;
749 xhci_stop_watchdog_timer_in_irq(xhci
, ep
);
751 /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */
752 if (deq_state
.new_deq_ptr
&& deq_state
.new_deq_seg
) {
753 xhci_queue_new_dequeue_state(xhci
,
755 ep
->stopped_td
->urb
->stream_id
,
757 xhci_ring_cmd_db(xhci
);
759 /* Otherwise ring the doorbell(s) to restart queued transfers */
760 ring_doorbell_for_active_rings(xhci
, slot_id
, ep_index
);
762 ep
->stopped_td
= NULL
;
763 ep
->stopped_trb
= NULL
;
766 * Drop the lock and complete the URBs in the cancelled TD list.
767 * New TDs to be cancelled might be added to the end of the list before
768 * we can complete all the URBs for the TDs we already unlinked.
769 * So stop when we've completed the URB for the last TD we unlinked.
772 cur_td
= list_entry(ep
->cancelled_td_list
.next
,
773 struct xhci_td
, cancelled_td_list
);
774 list_del_init(&cur_td
->cancelled_td_list
);
776 /* Clean up the cancelled URB */
777 /* Doesn't matter what we pass for status, since the core will
778 * just overwrite it (because the URB has been unlinked).
780 xhci_giveback_urb_in_irq(xhci
, cur_td
, 0, "cancelled");
782 /* Stop processing the cancelled list if the watchdog timer is
785 if (xhci
->xhc_state
& XHCI_STATE_DYING
)
787 } while (cur_td
!= last_unlinked_td
);
789 /* Return to the event handler with xhci->lock re-acquired */
792 /* Watchdog timer function for when a stop endpoint command fails to complete.
793 * In this case, we assume the host controller is broken or dying or dead. The
794 * host may still be completing some other events, so we have to be careful to
795 * let the event ring handler and the URB dequeueing/enqueueing functions know
796 * through xhci->state.
798 * The timer may also fire if the host takes a very long time to respond to the
799 * command, and the stop endpoint command completion handler cannot delete the
800 * timer before the timer function is called. Another endpoint cancellation may
801 * sneak in before the timer function can grab the lock, and that may queue
802 * another stop endpoint command and add the timer back. So we cannot use a
803 * simple flag to say whether there is a pending stop endpoint command for a
804 * particular endpoint.
806 * Instead we use a combination of that flag and a counter for the number of
807 * pending stop endpoint commands. If the timer is the tail end of the last
808 * stop endpoint command, and the endpoint's command is still pending, we assume
811 void xhci_stop_endpoint_command_watchdog(unsigned long arg
)
813 struct xhci_hcd
*xhci
;
814 struct xhci_virt_ep
*ep
;
815 struct xhci_virt_ep
*temp_ep
;
816 struct xhci_ring
*ring
;
817 struct xhci_td
*cur_td
;
821 ep
= (struct xhci_virt_ep
*) arg
;
824 spin_lock_irqsave(&xhci
->lock
, flags
);
826 ep
->stop_cmds_pending
--;
827 if (xhci
->xhc_state
& XHCI_STATE_DYING
) {
828 xhci_dbg(xhci
, "Stop EP timer ran, but another timer marked "
829 "xHCI as DYING, exiting.\n");
830 spin_unlock_irqrestore(&xhci
->lock
, flags
);
833 if (!(ep
->stop_cmds_pending
== 0 && (ep
->ep_state
& EP_HALT_PENDING
))) {
834 xhci_dbg(xhci
, "Stop EP timer ran, but no command pending, "
836 spin_unlock_irqrestore(&xhci
->lock
, flags
);
840 xhci_warn(xhci
, "xHCI host not responding to stop endpoint command.\n");
841 xhci_warn(xhci
, "Assuming host is dying, halting host.\n");
842 /* Oops, HC is dead or dying or at least not responding to the stop
845 xhci
->xhc_state
|= XHCI_STATE_DYING
;
846 /* Disable interrupts from the host controller and start halting it */
848 spin_unlock_irqrestore(&xhci
->lock
, flags
);
850 ret
= xhci_halt(xhci
);
852 spin_lock_irqsave(&xhci
->lock
, flags
);
854 /* This is bad; the host is not responding to commands and it's
855 * not allowing itself to be halted. At least interrupts are
856 * disabled. If we call usb_hc_died(), it will attempt to
857 * disconnect all device drivers under this host. Those
858 * disconnect() methods will wait for all URBs to be unlinked,
859 * so we must complete them.
861 xhci_warn(xhci
, "Non-responsive xHCI host is not halting.\n");
862 xhci_warn(xhci
, "Completing active URBs anyway.\n");
863 /* We could turn all TDs on the rings to no-ops. This won't
864 * help if the host has cached part of the ring, and is slow if
865 * we want to preserve the cycle bit. Skip it and hope the host
866 * doesn't touch the memory.
869 for (i
= 0; i
< MAX_HC_SLOTS
; i
++) {
872 for (j
= 0; j
< 31; j
++) {
873 temp_ep
= &xhci
->devs
[i
]->eps
[j
];
874 ring
= temp_ep
->ring
;
877 xhci_dbg(xhci
, "Killing URBs for slot ID %u, "
878 "ep index %u\n", i
, j
);
879 while (!list_empty(&ring
->td_list
)) {
880 cur_td
= list_first_entry(&ring
->td_list
,
883 list_del_init(&cur_td
->td_list
);
884 if (!list_empty(&cur_td
->cancelled_td_list
))
885 list_del_init(&cur_td
->cancelled_td_list
);
886 xhci_giveback_urb_in_irq(xhci
, cur_td
,
887 -ESHUTDOWN
, "killed");
889 while (!list_empty(&temp_ep
->cancelled_td_list
)) {
890 cur_td
= list_first_entry(
891 &temp_ep
->cancelled_td_list
,
894 list_del_init(&cur_td
->cancelled_td_list
);
895 xhci_giveback_urb_in_irq(xhci
, cur_td
,
896 -ESHUTDOWN
, "killed");
900 spin_unlock_irqrestore(&xhci
->lock
, flags
);
901 xhci_dbg(xhci
, "Calling usb_hc_died()\n");
902 usb_hc_died(xhci_to_hcd(xhci
)->primary_hcd
);
903 xhci_dbg(xhci
, "xHCI host controller is dead.\n");
907 * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
908 * we need to clear the set deq pending flag in the endpoint ring state, so that
909 * the TD queueing code can ring the doorbell again. We also need to ring the
910 * endpoint doorbell to restart the ring, but only if there aren't more
911 * cancellations pending.
913 static void handle_set_deq_completion(struct xhci_hcd
*xhci
,
914 struct xhci_event_cmd
*event
,
917 unsigned int slot_id
;
918 unsigned int ep_index
;
919 unsigned int stream_id
;
920 struct xhci_ring
*ep_ring
;
921 struct xhci_virt_device
*dev
;
922 struct xhci_ep_ctx
*ep_ctx
;
923 struct xhci_slot_ctx
*slot_ctx
;
925 slot_id
= TRB_TO_SLOT_ID(le32_to_cpu(trb
->generic
.field
[3]));
926 ep_index
= TRB_TO_EP_INDEX(le32_to_cpu(trb
->generic
.field
[3]));
927 stream_id
= TRB_TO_STREAM_ID(le32_to_cpu(trb
->generic
.field
[2]));
928 dev
= xhci
->devs
[slot_id
];
930 ep_ring
= xhci_stream_id_to_ring(dev
, ep_index
, stream_id
);
932 xhci_warn(xhci
, "WARN Set TR deq ptr command for "
933 "freed stream ID %u\n",
935 /* XXX: Harmless??? */
936 dev
->eps
[ep_index
].ep_state
&= ~SET_DEQ_PENDING
;
940 ep_ctx
= xhci_get_ep_ctx(xhci
, dev
->out_ctx
, ep_index
);
941 slot_ctx
= xhci_get_slot_ctx(xhci
, dev
->out_ctx
);
943 if (GET_COMP_CODE(le32_to_cpu(event
->status
)) != COMP_SUCCESS
) {
944 unsigned int ep_state
;
945 unsigned int slot_state
;
947 switch (GET_COMP_CODE(le32_to_cpu(event
->status
))) {
949 xhci_warn(xhci
, "WARN Set TR Deq Ptr cmd invalid because "
950 "of stream ID configuration\n");
953 xhci_warn(xhci
, "WARN Set TR Deq Ptr cmd failed due "
954 "to incorrect slot or ep state.\n");
955 ep_state
= le32_to_cpu(ep_ctx
->ep_info
);
956 ep_state
&= EP_STATE_MASK
;
957 slot_state
= le32_to_cpu(slot_ctx
->dev_state
);
958 slot_state
= GET_SLOT_STATE(slot_state
);
959 xhci_dbg(xhci
, "Slot state = %u, EP state = %u\n",
960 slot_state
, ep_state
);
963 xhci_warn(xhci
, "WARN Set TR Deq Ptr cmd failed because "
964 "slot %u was not enabled.\n", slot_id
);
967 xhci_warn(xhci
, "WARN Set TR Deq Ptr cmd with unknown "
968 "completion code of %u.\n",
969 GET_COMP_CODE(le32_to_cpu(event
->status
)));
972 /* OK what do we do now? The endpoint state is hosed, and we
973 * should never get to this point if the synchronization between
974 * queueing, and endpoint state are correct. This might happen
975 * if the device gets disconnected after we've finished
976 * cancelling URBs, which might not be an error...
979 xhci_dbg(xhci
, "Successful Set TR Deq Ptr cmd, deq = @%08llx\n",
980 le64_to_cpu(ep_ctx
->deq
));
981 if (xhci_trb_virt_to_dma(dev
->eps
[ep_index
].queued_deq_seg
,
982 dev
->eps
[ep_index
].queued_deq_ptr
) ==
983 (le64_to_cpu(ep_ctx
->deq
) & ~(EP_CTX_CYCLE_MASK
))) {
984 /* Update the ring's dequeue segment and dequeue pointer
985 * to reflect the new position.
987 ep_ring
->deq_seg
= dev
->eps
[ep_index
].queued_deq_seg
;
988 ep_ring
->dequeue
= dev
->eps
[ep_index
].queued_deq_ptr
;
990 xhci_warn(xhci
, "Mismatch between completed Set TR Deq "
991 "Ptr command & xHCI internal state.\n");
992 xhci_warn(xhci
, "ep deq seg = %p, deq ptr = %p\n",
993 dev
->eps
[ep_index
].queued_deq_seg
,
994 dev
->eps
[ep_index
].queued_deq_ptr
);
998 dev
->eps
[ep_index
].ep_state
&= ~SET_DEQ_PENDING
;
999 dev
->eps
[ep_index
].queued_deq_seg
= NULL
;
1000 dev
->eps
[ep_index
].queued_deq_ptr
= NULL
;
1001 /* Restart any rings with pending URBs */
1002 ring_doorbell_for_active_rings(xhci
, slot_id
, ep_index
);
1005 static void handle_reset_ep_completion(struct xhci_hcd
*xhci
,
1006 struct xhci_event_cmd
*event
,
1007 union xhci_trb
*trb
)
1010 unsigned int ep_index
;
1012 slot_id
= TRB_TO_SLOT_ID(le32_to_cpu(trb
->generic
.field
[3]));
1013 ep_index
= TRB_TO_EP_INDEX(le32_to_cpu(trb
->generic
.field
[3]));
1014 /* This command will only fail if the endpoint wasn't halted,
1015 * but we don't care.
1017 xhci_dbg(xhci
, "Ignoring reset ep completion code of %u\n",
1018 GET_COMP_CODE(le32_to_cpu(event
->status
)));
1020 /* HW with the reset endpoint quirk needs to have a configure endpoint
1021 * command complete before the endpoint can be used. Queue that here
1022 * because the HW can't handle two commands being queued in a row.
1024 if (xhci
->quirks
& XHCI_RESET_EP_QUIRK
) {
1025 xhci_dbg(xhci
, "Queueing configure endpoint command\n");
1026 xhci_queue_configure_endpoint(xhci
,
1027 xhci
->devs
[slot_id
]->in_ctx
->dma
, slot_id
,
1029 xhci_ring_cmd_db(xhci
);
1031 /* Clear our internal halted state and restart the ring(s) */
1032 xhci
->devs
[slot_id
]->eps
[ep_index
].ep_state
&= ~EP_HALTED
;
1033 ring_doorbell_for_active_rings(xhci
, slot_id
, ep_index
);
1037 /* Check to see if a command in the device's command queue matches this one.
1038 * Signal the completion or free the command, and return 1. Return 0 if the
1039 * completed command isn't at the head of the command list.
1041 static int handle_cmd_in_cmd_wait_list(struct xhci_hcd
*xhci
,
1042 struct xhci_virt_device
*virt_dev
,
1043 struct xhci_event_cmd
*event
)
1045 struct xhci_command
*command
;
1047 if (list_empty(&virt_dev
->cmd_list
))
1050 command
= list_entry(virt_dev
->cmd_list
.next
,
1051 struct xhci_command
, cmd_list
);
1052 if (xhci
->cmd_ring
->dequeue
!= command
->command_trb
)
1055 command
->status
= GET_COMP_CODE(le32_to_cpu(event
->status
));
1056 list_del(&command
->cmd_list
);
1057 if (command
->completion
)
1058 complete(command
->completion
);
1060 xhci_free_command(xhci
, command
);
1064 static void handle_cmd_completion(struct xhci_hcd
*xhci
,
1065 struct xhci_event_cmd
*event
)
1067 int slot_id
= TRB_TO_SLOT_ID(le32_to_cpu(event
->flags
));
1069 dma_addr_t cmd_dequeue_dma
;
1070 struct xhci_input_control_ctx
*ctrl_ctx
;
1071 struct xhci_virt_device
*virt_dev
;
1072 unsigned int ep_index
;
1073 struct xhci_ring
*ep_ring
;
1074 unsigned int ep_state
;
1076 cmd_dma
= le64_to_cpu(event
->cmd_trb
);
1077 cmd_dequeue_dma
= xhci_trb_virt_to_dma(xhci
->cmd_ring
->deq_seg
,
1078 xhci
->cmd_ring
->dequeue
);
1079 /* Is the command ring deq ptr out of sync with the deq seg ptr? */
1080 if (cmd_dequeue_dma
== 0) {
1081 xhci
->error_bitmask
|= 1 << 4;
1084 /* Does the DMA address match our internal dequeue pointer address? */
1085 if (cmd_dma
!= (u64
) cmd_dequeue_dma
) {
1086 xhci
->error_bitmask
|= 1 << 5;
1089 switch (le32_to_cpu(xhci
->cmd_ring
->dequeue
->generic
.field
[3])
1090 & TRB_TYPE_BITMASK
) {
1091 case TRB_TYPE(TRB_ENABLE_SLOT
):
1092 if (GET_COMP_CODE(le32_to_cpu(event
->status
)) == COMP_SUCCESS
)
1093 xhci
->slot_id
= slot_id
;
1096 complete(&xhci
->addr_dev
);
1098 case TRB_TYPE(TRB_DISABLE_SLOT
):
1099 if (xhci
->devs
[slot_id
]) {
1100 if (xhci
->quirks
& XHCI_EP_LIMIT_QUIRK
)
1101 /* Delete default control endpoint resources */
1102 xhci_free_device_endpoint_resources(xhci
,
1103 xhci
->devs
[slot_id
], true);
1104 xhci_free_virt_device(xhci
, slot_id
);
1107 case TRB_TYPE(TRB_CONFIG_EP
):
1108 virt_dev
= xhci
->devs
[slot_id
];
1109 if (handle_cmd_in_cmd_wait_list(xhci
, virt_dev
, event
))
1112 * Configure endpoint commands can come from the USB core
1113 * configuration or alt setting changes, or because the HW
1114 * needed an extra configure endpoint command after a reset
1115 * endpoint command or streams were being configured.
1116 * If the command was for a halted endpoint, the xHCI driver
1117 * is not waiting on the configure endpoint command.
1119 ctrl_ctx
= xhci_get_input_control_ctx(xhci
,
1121 /* Input ctx add_flags are the endpoint index plus one */
1122 ep_index
= xhci_last_valid_endpoint(le32_to_cpu(ctrl_ctx
->add_flags
)) - 1;
1123 /* A usb_set_interface() call directly after clearing a halted
1124 * condition may race on this quirky hardware. Not worth
1125 * worrying about, since this is prototype hardware. Not sure
1126 * if this will work for streams, but streams support was
1127 * untested on this prototype.
1129 if (xhci
->quirks
& XHCI_RESET_EP_QUIRK
&&
1130 ep_index
!= (unsigned int) -1 &&
1131 le32_to_cpu(ctrl_ctx
->add_flags
) - SLOT_FLAG
==
1132 le32_to_cpu(ctrl_ctx
->drop_flags
)) {
1133 ep_ring
= xhci
->devs
[slot_id
]->eps
[ep_index
].ring
;
1134 ep_state
= xhci
->devs
[slot_id
]->eps
[ep_index
].ep_state
;
1135 if (!(ep_state
& EP_HALTED
))
1136 goto bandwidth_change
;
1137 xhci_dbg(xhci
, "Completed config ep cmd - "
1138 "last ep index = %d, state = %d\n",
1139 ep_index
, ep_state
);
1140 /* Clear internal halted state and restart ring(s) */
1141 xhci
->devs
[slot_id
]->eps
[ep_index
].ep_state
&=
1143 ring_doorbell_for_active_rings(xhci
, slot_id
, ep_index
);
1147 xhci_dbg(xhci
, "Completed config ep cmd\n");
1148 xhci
->devs
[slot_id
]->cmd_status
=
1149 GET_COMP_CODE(le32_to_cpu(event
->status
));
1150 complete(&xhci
->devs
[slot_id
]->cmd_completion
);
1152 case TRB_TYPE(TRB_EVAL_CONTEXT
):
1153 virt_dev
= xhci
->devs
[slot_id
];
1154 if (handle_cmd_in_cmd_wait_list(xhci
, virt_dev
, event
))
1156 xhci
->devs
[slot_id
]->cmd_status
= GET_COMP_CODE(le32_to_cpu(event
->status
));
1157 complete(&xhci
->devs
[slot_id
]->cmd_completion
);
1159 case TRB_TYPE(TRB_ADDR_DEV
):
1160 xhci
->devs
[slot_id
]->cmd_status
= GET_COMP_CODE(le32_to_cpu(event
->status
));
1161 complete(&xhci
->addr_dev
);
1163 case TRB_TYPE(TRB_STOP_RING
):
1164 handle_stopped_endpoint(xhci
, xhci
->cmd_ring
->dequeue
, event
);
1166 case TRB_TYPE(TRB_SET_DEQ
):
1167 handle_set_deq_completion(xhci
, event
, xhci
->cmd_ring
->dequeue
);
1169 case TRB_TYPE(TRB_CMD_NOOP
):
1171 case TRB_TYPE(TRB_RESET_EP
):
1172 handle_reset_ep_completion(xhci
, event
, xhci
->cmd_ring
->dequeue
);
1174 case TRB_TYPE(TRB_RESET_DEV
):
1175 xhci_dbg(xhci
, "Completed reset device command.\n");
1176 slot_id
= TRB_TO_SLOT_ID(
1177 le32_to_cpu(xhci
->cmd_ring
->dequeue
->generic
.field
[3]));
1178 virt_dev
= xhci
->devs
[slot_id
];
1180 handle_cmd_in_cmd_wait_list(xhci
, virt_dev
, event
);
1182 xhci_warn(xhci
, "Reset device command completion "
1183 "for disabled slot %u\n", slot_id
);
1185 case TRB_TYPE(TRB_NEC_GET_FW
):
1186 if (!(xhci
->quirks
& XHCI_NEC_HOST
)) {
1187 xhci
->error_bitmask
|= 1 << 6;
1190 xhci_dbg(xhci
, "NEC firmware version %2x.%02x\n",
1191 NEC_FW_MAJOR(le32_to_cpu(event
->status
)),
1192 NEC_FW_MINOR(le32_to_cpu(event
->status
)));
1195 /* Skip over unknown commands on the event ring */
1196 xhci
->error_bitmask
|= 1 << 6;
1199 inc_deq(xhci
, xhci
->cmd_ring
, false);
1202 static void handle_vendor_event(struct xhci_hcd
*xhci
,
1203 union xhci_trb
*event
)
1207 trb_type
= TRB_FIELD_TO_TYPE(le32_to_cpu(event
->generic
.field
[3]));
1208 xhci_dbg(xhci
, "Vendor specific event TRB type = %u\n", trb_type
);
1209 if (trb_type
== TRB_NEC_CMD_COMP
&& (xhci
->quirks
& XHCI_NEC_HOST
))
1210 handle_cmd_completion(xhci
, &event
->event_cmd
);
1213 /* @port_id: the one-based port ID from the hardware (indexed from array of all
1214 * port registers -- USB 3.0 and USB 2.0).
1216 * Returns a zero-based port number, which is suitable for indexing into each of
1217 * the split roothubs' port arrays and bus state arrays.
1218 * Add one to it in order to call xhci_find_slot_id_by_port.
1220 static unsigned int find_faked_portnum_from_hw_portnum(struct usb_hcd
*hcd
,
1221 struct xhci_hcd
*xhci
, u32 port_id
)
1224 unsigned int num_similar_speed_ports
= 0;
1226 /* port_id from the hardware is 1-based, but port_array[], usb3_ports[],
1227 * and usb2_ports are 0-based indexes. Count the number of similar
1228 * speed ports, up to 1 port before this port.
1230 for (i
= 0; i
< (port_id
- 1); i
++) {
1231 u8 port_speed
= xhci
->port_array
[i
];
1234 * Skip ports that don't have known speeds, or have duplicate
1235 * Extended Capabilities port speed entries.
1237 if (port_speed
== 0 || port_speed
== DUPLICATE_ENTRY
)
1241 * USB 3.0 ports are always under a USB 3.0 hub. USB 2.0 and
1242 * 1.1 ports are under the USB 2.0 hub. If the port speed
1243 * matches the device speed, it's a similar speed port.
1245 if ((port_speed
== 0x03) == (hcd
->speed
== HCD_USB3
))
1246 num_similar_speed_ports
++;
1248 return num_similar_speed_ports
;
1251 static void handle_port_status(struct xhci_hcd
*xhci
,
1252 union xhci_trb
*event
)
1254 struct usb_hcd
*hcd
;
1259 unsigned int faked_port_index
;
1261 struct xhci_bus_state
*bus_state
;
1262 __le32 __iomem
**port_array
;
1263 bool bogus_port_status
= false;
1265 /* Port status change events always have a successful completion code */
1266 if (GET_COMP_CODE(le32_to_cpu(event
->generic
.field
[2])) != COMP_SUCCESS
) {
1267 xhci_warn(xhci
, "WARN: xHC returned failed port status event\n");
1268 xhci
->error_bitmask
|= 1 << 8;
1270 port_id
= GET_PORT_ID(le32_to_cpu(event
->generic
.field
[0]));
1271 xhci_dbg(xhci
, "Port Status Change Event for port %d\n", port_id
);
1273 max_ports
= HCS_MAX_PORTS(xhci
->hcs_params1
);
1274 if ((port_id
<= 0) || (port_id
> max_ports
)) {
1275 xhci_warn(xhci
, "Invalid port id %d\n", port_id
);
1276 bogus_port_status
= true;
1280 /* Figure out which usb_hcd this port is attached to:
1281 * is it a USB 3.0 port or a USB 2.0/1.1 port?
1283 major_revision
= xhci
->port_array
[port_id
- 1];
1284 if (major_revision
== 0) {
1285 xhci_warn(xhci
, "Event for port %u not in "
1286 "Extended Capabilities, ignoring.\n",
1288 bogus_port_status
= true;
1291 if (major_revision
== DUPLICATE_ENTRY
) {
1292 xhci_warn(xhci
, "Event for port %u duplicated in"
1293 "Extended Capabilities, ignoring.\n",
1295 bogus_port_status
= true;
1300 * Hardware port IDs reported by a Port Status Change Event include USB
1301 * 3.0 and USB 2.0 ports. We want to check if the port has reported a
1302 * resume event, but we first need to translate the hardware port ID
1303 * into the index into the ports on the correct split roothub, and the
1304 * correct bus_state structure.
1306 /* Find the right roothub. */
1307 hcd
= xhci_to_hcd(xhci
);
1308 if ((major_revision
== 0x03) != (hcd
->speed
== HCD_USB3
))
1309 hcd
= xhci
->shared_hcd
;
1310 bus_state
= &xhci
->bus_state
[hcd_index(hcd
)];
1311 if (hcd
->speed
== HCD_USB3
)
1312 port_array
= xhci
->usb3_ports
;
1314 port_array
= xhci
->usb2_ports
;
1315 /* Find the faked port hub number */
1316 faked_port_index
= find_faked_portnum_from_hw_portnum(hcd
, xhci
,
1319 temp
= xhci_readl(xhci
, port_array
[faked_port_index
]);
1320 if (hcd
->state
== HC_STATE_SUSPENDED
) {
1321 xhci_dbg(xhci
, "resume root hub\n");
1322 usb_hcd_resume_root_hub(hcd
);
1325 if ((temp
& PORT_PLC
) && (temp
& PORT_PLS_MASK
) == XDEV_RESUME
) {
1326 xhci_dbg(xhci
, "port resume event for port %d\n", port_id
);
1328 temp1
= xhci_readl(xhci
, &xhci
->op_regs
->command
);
1329 if (!(temp1
& CMD_RUN
)) {
1330 xhci_warn(xhci
, "xHC is not running.\n");
1334 if (DEV_SUPERSPEED(temp
)) {
1335 xhci_dbg(xhci
, "resume SS port %d\n", port_id
);
1336 xhci_set_link_state(xhci
, port_array
, faked_port_index
,
1338 slot_id
= xhci_find_slot_id_by_port(hcd
, xhci
,
1339 faked_port_index
+ 1);
1341 xhci_dbg(xhci
, "slot_id is zero\n");
1344 xhci_ring_device(xhci
, slot_id
);
1345 xhci_dbg(xhci
, "resume SS port %d finished\n", port_id
);
1346 /* Clear PORT_PLC */
1347 xhci_test_and_clear_bit(xhci
, port_array
,
1348 faked_port_index
, PORT_PLC
);
1350 xhci_dbg(xhci
, "resume HS port %d\n", port_id
);
1351 bus_state
->resume_done
[faked_port_index
] = jiffies
+
1352 msecs_to_jiffies(20);
1353 mod_timer(&hcd
->rh_timer
,
1354 bus_state
->resume_done
[faked_port_index
]);
1355 /* Do the rest in GetPortStatus */
1359 if (hcd
->speed
!= HCD_USB3
)
1360 xhci_test_and_clear_bit(xhci
, port_array
, faked_port_index
,
1364 /* Update event ring dequeue pointer before dropping the lock */
1365 inc_deq(xhci
, xhci
->event_ring
, true);
1367 /* Don't make the USB core poll the roothub if we got a bad port status
1368 * change event. Besides, at that point we can't tell which roothub
1369 * (USB 2.0 or USB 3.0) to kick.
1371 if (bogus_port_status
)
1374 spin_unlock(&xhci
->lock
);
1375 /* Pass this up to the core */
1376 usb_hcd_poll_rh_status(hcd
);
1377 spin_lock(&xhci
->lock
);
1381 * This TD is defined by the TRBs starting at start_trb in start_seg and ending
1382 * at end_trb, which may be in another segment. If the suspect DMA address is a
1383 * TRB in this TD, this function returns that TRB's segment. Otherwise it
1386 struct xhci_segment
*trb_in_td(struct xhci_segment
*start_seg
,
1387 union xhci_trb
*start_trb
,
1388 union xhci_trb
*end_trb
,
1389 dma_addr_t suspect_dma
)
1391 dma_addr_t start_dma
;
1392 dma_addr_t end_seg_dma
;
1393 dma_addr_t end_trb_dma
;
1394 struct xhci_segment
*cur_seg
;
1396 start_dma
= xhci_trb_virt_to_dma(start_seg
, start_trb
);
1397 cur_seg
= start_seg
;
1402 /* We may get an event for a Link TRB in the middle of a TD */
1403 end_seg_dma
= xhci_trb_virt_to_dma(cur_seg
,
1404 &cur_seg
->trbs
[TRBS_PER_SEGMENT
- 1]);
1405 /* If the end TRB isn't in this segment, this is set to 0 */
1406 end_trb_dma
= xhci_trb_virt_to_dma(cur_seg
, end_trb
);
1408 if (end_trb_dma
> 0) {
1409 /* The end TRB is in this segment, so suspect should be here */
1410 if (start_dma
<= end_trb_dma
) {
1411 if (suspect_dma
>= start_dma
&& suspect_dma
<= end_trb_dma
)
1414 /* Case for one segment with
1415 * a TD wrapped around to the top
1417 if ((suspect_dma
>= start_dma
&&
1418 suspect_dma
<= end_seg_dma
) ||
1419 (suspect_dma
>= cur_seg
->dma
&&
1420 suspect_dma
<= end_trb_dma
))
1425 /* Might still be somewhere in this segment */
1426 if (suspect_dma
>= start_dma
&& suspect_dma
<= end_seg_dma
)
1429 cur_seg
= cur_seg
->next
;
1430 start_dma
= xhci_trb_virt_to_dma(cur_seg
, &cur_seg
->trbs
[0]);
1431 } while (cur_seg
!= start_seg
);
1436 static void xhci_cleanup_halted_endpoint(struct xhci_hcd
*xhci
,
1437 unsigned int slot_id
, unsigned int ep_index
,
1438 unsigned int stream_id
,
1439 struct xhci_td
*td
, union xhci_trb
*event_trb
)
1441 struct xhci_virt_ep
*ep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
1442 ep
->ep_state
|= EP_HALTED
;
1443 ep
->stopped_td
= td
;
1444 ep
->stopped_trb
= event_trb
;
1445 ep
->stopped_stream
= stream_id
;
1447 xhci_queue_reset_ep(xhci
, slot_id
, ep_index
);
1448 xhci_cleanup_stalled_ring(xhci
, td
->urb
->dev
, ep_index
);
1450 ep
->stopped_td
= NULL
;
1451 ep
->stopped_trb
= NULL
;
1452 ep
->stopped_stream
= 0;
1454 xhci_ring_cmd_db(xhci
);
1457 /* Check if an error has halted the endpoint ring. The class driver will
1458 * cleanup the halt for a non-default control endpoint if we indicate a stall.
1459 * However, a babble and other errors also halt the endpoint ring, and the class
1460 * driver won't clear the halt in that case, so we need to issue a Set Transfer
1461 * Ring Dequeue Pointer command manually.
1463 static int xhci_requires_manual_halt_cleanup(struct xhci_hcd
*xhci
,
1464 struct xhci_ep_ctx
*ep_ctx
,
1465 unsigned int trb_comp_code
)
1467 /* TRB completion codes that may require a manual halt cleanup */
1468 if (trb_comp_code
== COMP_TX_ERR
||
1469 trb_comp_code
== COMP_BABBLE
||
1470 trb_comp_code
== COMP_SPLIT_ERR
)
1471 /* The 0.96 spec says a babbling control endpoint
1472 * is not halted. The 0.96 spec says it is. Some HW
1473 * claims to be 0.95 compliant, but it halts the control
1474 * endpoint anyway. Check if a babble halted the
1477 if ((ep_ctx
->ep_info
& cpu_to_le32(EP_STATE_MASK
)) ==
1478 cpu_to_le32(EP_STATE_HALTED
))
1484 int xhci_is_vendor_info_code(struct xhci_hcd
*xhci
, unsigned int trb_comp_code
)
1486 if (trb_comp_code
>= 224 && trb_comp_code
<= 255) {
1487 /* Vendor defined "informational" completion code,
1488 * treat as not-an-error.
1490 xhci_dbg(xhci
, "Vendor defined info completion code %u\n",
1492 xhci_dbg(xhci
, "Treating code as success.\n");
1499 * Finish the td processing, remove the td from td list;
1500 * Return 1 if the urb can be given back.
1502 static int finish_td(struct xhci_hcd
*xhci
, struct xhci_td
*td
,
1503 union xhci_trb
*event_trb
, struct xhci_transfer_event
*event
,
1504 struct xhci_virt_ep
*ep
, int *status
, bool skip
)
1506 struct xhci_virt_device
*xdev
;
1507 struct xhci_ring
*ep_ring
;
1508 unsigned int slot_id
;
1510 struct urb
*urb
= NULL
;
1511 struct xhci_ep_ctx
*ep_ctx
;
1513 struct urb_priv
*urb_priv
;
1516 slot_id
= TRB_TO_SLOT_ID(le32_to_cpu(event
->flags
));
1517 xdev
= xhci
->devs
[slot_id
];
1518 ep_index
= TRB_TO_EP_ID(le32_to_cpu(event
->flags
)) - 1;
1519 ep_ring
= xhci_dma_to_transfer_ring(ep
, le64_to_cpu(event
->buffer
));
1520 ep_ctx
= xhci_get_ep_ctx(xhci
, xdev
->out_ctx
, ep_index
);
1521 trb_comp_code
= GET_COMP_CODE(le32_to_cpu(event
->transfer_len
));
1526 if (trb_comp_code
== COMP_STOP_INVAL
||
1527 trb_comp_code
== COMP_STOP
) {
1528 /* The Endpoint Stop Command completion will take care of any
1529 * stopped TDs. A stopped TD may be restarted, so don't update
1530 * the ring dequeue pointer or take this TD off any lists yet.
1532 ep
->stopped_td
= td
;
1533 ep
->stopped_trb
= event_trb
;
1536 if (trb_comp_code
== COMP_STALL
) {
1537 /* The transfer is completed from the driver's
1538 * perspective, but we need to issue a set dequeue
1539 * command for this stalled endpoint to move the dequeue
1540 * pointer past the TD. We can't do that here because
1541 * the halt condition must be cleared first. Let the
1542 * USB class driver clear the stall later.
1544 ep
->stopped_td
= td
;
1545 ep
->stopped_trb
= event_trb
;
1546 ep
->stopped_stream
= ep_ring
->stream_id
;
1547 } else if (xhci_requires_manual_halt_cleanup(xhci
,
1548 ep_ctx
, trb_comp_code
)) {
1549 /* Other types of errors halt the endpoint, but the
1550 * class driver doesn't call usb_reset_endpoint() unless
1551 * the error is -EPIPE. Clear the halted status in the
1552 * xHCI hardware manually.
1554 xhci_cleanup_halted_endpoint(xhci
,
1555 slot_id
, ep_index
, ep_ring
->stream_id
,
1558 /* Update ring dequeue pointer */
1559 while (ep_ring
->dequeue
!= td
->last_trb
)
1560 inc_deq(xhci
, ep_ring
, false);
1561 inc_deq(xhci
, ep_ring
, false);
1565 /* Clean up the endpoint's TD list */
1567 urb_priv
= urb
->hcpriv
;
1569 /* Do one last check of the actual transfer length.
1570 * If the host controller said we transferred more data than
1571 * the buffer length, urb->actual_length will be a very big
1572 * number (since it's unsigned). Play it safe and say we didn't
1573 * transfer anything.
1575 if (urb
->actual_length
> urb
->transfer_buffer_length
) {
1576 xhci_warn(xhci
, "URB transfer length is wrong, "
1577 "xHC issue? req. len = %u, "
1579 urb
->transfer_buffer_length
,
1580 urb
->actual_length
);
1581 urb
->actual_length
= 0;
1582 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
1583 *status
= -EREMOTEIO
;
1587 list_del_init(&td
->td_list
);
1588 /* Was this TD slated to be cancelled but completed anyway? */
1589 if (!list_empty(&td
->cancelled_td_list
))
1590 list_del_init(&td
->cancelled_td_list
);
1593 /* Giveback the urb when all the tds are completed */
1594 if (urb_priv
->td_cnt
== urb_priv
->length
) {
1596 if (usb_pipetype(urb
->pipe
) == PIPE_ISOCHRONOUS
) {
1597 xhci_to_hcd(xhci
)->self
.bandwidth_isoc_reqs
--;
1598 if (xhci_to_hcd(xhci
)->self
.bandwidth_isoc_reqs
1600 if (xhci
->quirks
& XHCI_AMD_PLL_FIX
)
1601 usb_amd_quirk_pll_enable();
1611 * Process control tds, update urb status and actual_length.
1613 static int process_ctrl_td(struct xhci_hcd
*xhci
, struct xhci_td
*td
,
1614 union xhci_trb
*event_trb
, struct xhci_transfer_event
*event
,
1615 struct xhci_virt_ep
*ep
, int *status
)
1617 struct xhci_virt_device
*xdev
;
1618 struct xhci_ring
*ep_ring
;
1619 unsigned int slot_id
;
1621 struct xhci_ep_ctx
*ep_ctx
;
1624 slot_id
= TRB_TO_SLOT_ID(le32_to_cpu(event
->flags
));
1625 xdev
= xhci
->devs
[slot_id
];
1626 ep_index
= TRB_TO_EP_ID(le32_to_cpu(event
->flags
)) - 1;
1627 ep_ring
= xhci_dma_to_transfer_ring(ep
, le64_to_cpu(event
->buffer
));
1628 ep_ctx
= xhci_get_ep_ctx(xhci
, xdev
->out_ctx
, ep_index
);
1629 trb_comp_code
= GET_COMP_CODE(le32_to_cpu(event
->transfer_len
));
1631 xhci_debug_trb(xhci
, xhci
->event_ring
->dequeue
);
1632 switch (trb_comp_code
) {
1634 if (event_trb
== ep_ring
->dequeue
) {
1635 xhci_warn(xhci
, "WARN: Success on ctrl setup TRB "
1636 "without IOC set??\n");
1637 *status
= -ESHUTDOWN
;
1638 } else if (event_trb
!= td
->last_trb
) {
1639 xhci_warn(xhci
, "WARN: Success on ctrl data TRB "
1640 "without IOC set??\n");
1641 *status
= -ESHUTDOWN
;
1647 xhci_warn(xhci
, "WARN: short transfer on control ep\n");
1648 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
1649 *status
= -EREMOTEIO
;
1653 case COMP_STOP_INVAL
:
1655 return finish_td(xhci
, td
, event_trb
, event
, ep
, status
, false);
1657 if (!xhci_requires_manual_halt_cleanup(xhci
,
1658 ep_ctx
, trb_comp_code
))
1660 xhci_dbg(xhci
, "TRB error code %u, "
1661 "halted endpoint index = %u\n",
1662 trb_comp_code
, ep_index
);
1663 /* else fall through */
1665 /* Did we transfer part of the data (middle) phase? */
1666 if (event_trb
!= ep_ring
->dequeue
&&
1667 event_trb
!= td
->last_trb
)
1668 td
->urb
->actual_length
=
1669 td
->urb
->transfer_buffer_length
1670 - TRB_LEN(le32_to_cpu(event
->transfer_len
));
1672 td
->urb
->actual_length
= 0;
1674 xhci_cleanup_halted_endpoint(xhci
,
1675 slot_id
, ep_index
, 0, td
, event_trb
);
1676 return finish_td(xhci
, td
, event_trb
, event
, ep
, status
, true);
1679 * Did we transfer any data, despite the errors that might have
1680 * happened? I.e. did we get past the setup stage?
1682 if (event_trb
!= ep_ring
->dequeue
) {
1683 /* The event was for the status stage */
1684 if (event_trb
== td
->last_trb
) {
1685 if (td
->urb
->actual_length
!= 0) {
1686 /* Don't overwrite a previously set error code
1688 if ((*status
== -EINPROGRESS
|| *status
== 0) &&
1689 (td
->urb
->transfer_flags
1690 & URB_SHORT_NOT_OK
))
1691 /* Did we already see a short data
1693 *status
= -EREMOTEIO
;
1695 td
->urb
->actual_length
=
1696 td
->urb
->transfer_buffer_length
;
1699 /* Maybe the event was for the data stage? */
1700 td
->urb
->actual_length
=
1701 td
->urb
->transfer_buffer_length
-
1702 TRB_LEN(le32_to_cpu(event
->transfer_len
));
1703 xhci_dbg(xhci
, "Waiting for status "
1709 return finish_td(xhci
, td
, event_trb
, event
, ep
, status
, false);
1713 * Process isochronous tds, update urb packet status and actual_length.
1715 static int process_isoc_td(struct xhci_hcd
*xhci
, struct xhci_td
*td
,
1716 union xhci_trb
*event_trb
, struct xhci_transfer_event
*event
,
1717 struct xhci_virt_ep
*ep
, int *status
)
1719 struct xhci_ring
*ep_ring
;
1720 struct urb_priv
*urb_priv
;
1723 union xhci_trb
*cur_trb
;
1724 struct xhci_segment
*cur_seg
;
1725 struct usb_iso_packet_descriptor
*frame
;
1727 bool skip_td
= false;
1729 ep_ring
= xhci_dma_to_transfer_ring(ep
, le64_to_cpu(event
->buffer
));
1730 trb_comp_code
= GET_COMP_CODE(le32_to_cpu(event
->transfer_len
));
1731 urb_priv
= td
->urb
->hcpriv
;
1732 idx
= urb_priv
->td_cnt
;
1733 frame
= &td
->urb
->iso_frame_desc
[idx
];
1735 /* handle completion code */
1736 switch (trb_comp_code
) {
1741 frame
->status
= td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
?
1745 frame
->status
= -ECOMM
;
1748 case COMP_BUFF_OVER
:
1750 frame
->status
= -EOVERFLOW
;
1755 frame
->status
= -EPROTO
;
1759 case COMP_STOP_INVAL
:
1766 if (trb_comp_code
== COMP_SUCCESS
|| skip_td
) {
1767 frame
->actual_length
= frame
->length
;
1768 td
->urb
->actual_length
+= frame
->length
;
1770 for (cur_trb
= ep_ring
->dequeue
,
1771 cur_seg
= ep_ring
->deq_seg
; cur_trb
!= event_trb
;
1772 next_trb(xhci
, ep_ring
, &cur_seg
, &cur_trb
)) {
1773 if (!TRB_TYPE_NOOP_LE32(cur_trb
->generic
.field
[3]) &&
1774 !TRB_TYPE_LINK_LE32(cur_trb
->generic
.field
[3]))
1775 len
+= TRB_LEN(le32_to_cpu(cur_trb
->generic
.field
[2]));
1777 len
+= TRB_LEN(le32_to_cpu(cur_trb
->generic
.field
[2])) -
1778 TRB_LEN(le32_to_cpu(event
->transfer_len
));
1780 if (trb_comp_code
!= COMP_STOP_INVAL
) {
1781 frame
->actual_length
= len
;
1782 td
->urb
->actual_length
+= len
;
1786 return finish_td(xhci
, td
, event_trb
, event
, ep
, status
, false);
1789 static int skip_isoc_td(struct xhci_hcd
*xhci
, struct xhci_td
*td
,
1790 struct xhci_transfer_event
*event
,
1791 struct xhci_virt_ep
*ep
, int *status
)
1793 struct xhci_ring
*ep_ring
;
1794 struct urb_priv
*urb_priv
;
1795 struct usb_iso_packet_descriptor
*frame
;
1798 ep_ring
= xhci_dma_to_transfer_ring(ep
, le64_to_cpu(event
->buffer
));
1799 urb_priv
= td
->urb
->hcpriv
;
1800 idx
= urb_priv
->td_cnt
;
1801 frame
= &td
->urb
->iso_frame_desc
[idx
];
1803 /* The transfer is partly done. */
1804 frame
->status
= -EXDEV
;
1806 /* calc actual length */
1807 frame
->actual_length
= 0;
1809 /* Update ring dequeue pointer */
1810 while (ep_ring
->dequeue
!= td
->last_trb
)
1811 inc_deq(xhci
, ep_ring
, false);
1812 inc_deq(xhci
, ep_ring
, false);
1814 return finish_td(xhci
, td
, NULL
, event
, ep
, status
, true);
1818 * Process bulk and interrupt tds, update urb status and actual_length.
1820 static int process_bulk_intr_td(struct xhci_hcd
*xhci
, struct xhci_td
*td
,
1821 union xhci_trb
*event_trb
, struct xhci_transfer_event
*event
,
1822 struct xhci_virt_ep
*ep
, int *status
)
1824 struct xhci_ring
*ep_ring
;
1825 union xhci_trb
*cur_trb
;
1826 struct xhci_segment
*cur_seg
;
1829 ep_ring
= xhci_dma_to_transfer_ring(ep
, le64_to_cpu(event
->buffer
));
1830 trb_comp_code
= GET_COMP_CODE(le32_to_cpu(event
->transfer_len
));
1832 switch (trb_comp_code
) {
1834 /* Double check that the HW transferred everything. */
1835 if (event_trb
!= td
->last_trb
) {
1836 xhci_warn(xhci
, "WARN Successful completion "
1838 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
1839 *status
= -EREMOTEIO
;
1847 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
1848 *status
= -EREMOTEIO
;
1853 /* Others already handled above */
1856 if (trb_comp_code
== COMP_SHORT_TX
)
1857 xhci_dbg(xhci
, "ep %#x - asked for %d bytes, "
1858 "%d bytes untransferred\n",
1859 td
->urb
->ep
->desc
.bEndpointAddress
,
1860 td
->urb
->transfer_buffer_length
,
1861 TRB_LEN(le32_to_cpu(event
->transfer_len
)));
1862 /* Fast path - was this the last TRB in the TD for this URB? */
1863 if (event_trb
== td
->last_trb
) {
1864 if (TRB_LEN(le32_to_cpu(event
->transfer_len
)) != 0) {
1865 td
->urb
->actual_length
=
1866 td
->urb
->transfer_buffer_length
-
1867 TRB_LEN(le32_to_cpu(event
->transfer_len
));
1868 if (td
->urb
->transfer_buffer_length
<
1869 td
->urb
->actual_length
) {
1870 xhci_warn(xhci
, "HC gave bad length "
1871 "of %d bytes left\n",
1872 TRB_LEN(le32_to_cpu(event
->transfer_len
)));
1873 td
->urb
->actual_length
= 0;
1874 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
1875 *status
= -EREMOTEIO
;
1879 /* Don't overwrite a previously set error code */
1880 if (*status
== -EINPROGRESS
) {
1881 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
1882 *status
= -EREMOTEIO
;
1887 td
->urb
->actual_length
=
1888 td
->urb
->transfer_buffer_length
;
1889 /* Ignore a short packet completion if the
1890 * untransferred length was zero.
1892 if (*status
== -EREMOTEIO
)
1896 /* Slow path - walk the list, starting from the dequeue
1897 * pointer, to get the actual length transferred.
1899 td
->urb
->actual_length
= 0;
1900 for (cur_trb
= ep_ring
->dequeue
, cur_seg
= ep_ring
->deq_seg
;
1901 cur_trb
!= event_trb
;
1902 next_trb(xhci
, ep_ring
, &cur_seg
, &cur_trb
)) {
1903 if (!TRB_TYPE_NOOP_LE32(cur_trb
->generic
.field
[3]) &&
1904 !TRB_TYPE_LINK_LE32(cur_trb
->generic
.field
[3]))
1905 td
->urb
->actual_length
+=
1906 TRB_LEN(le32_to_cpu(cur_trb
->generic
.field
[2]));
1908 /* If the ring didn't stop on a Link or No-op TRB, add
1909 * in the actual bytes transferred from the Normal TRB
1911 if (trb_comp_code
!= COMP_STOP_INVAL
)
1912 td
->urb
->actual_length
+=
1913 TRB_LEN(le32_to_cpu(cur_trb
->generic
.field
[2])) -
1914 TRB_LEN(le32_to_cpu(event
->transfer_len
));
1917 return finish_td(xhci
, td
, event_trb
, event
, ep
, status
, false);
1921 * If this function returns an error condition, it means it got a Transfer
1922 * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
1923 * At this point, the host controller is probably hosed and should be reset.
1925 static int handle_tx_event(struct xhci_hcd
*xhci
,
1926 struct xhci_transfer_event
*event
)
1928 struct xhci_virt_device
*xdev
;
1929 struct xhci_virt_ep
*ep
;
1930 struct xhci_ring
*ep_ring
;
1931 unsigned int slot_id
;
1933 struct xhci_td
*td
= NULL
;
1934 dma_addr_t event_dma
;
1935 struct xhci_segment
*event_seg
;
1936 union xhci_trb
*event_trb
;
1937 struct urb
*urb
= NULL
;
1938 int status
= -EINPROGRESS
;
1939 struct urb_priv
*urb_priv
;
1940 struct xhci_ep_ctx
*ep_ctx
;
1941 struct list_head
*tmp
;
1946 slot_id
= TRB_TO_SLOT_ID(le32_to_cpu(event
->flags
));
1947 xdev
= xhci
->devs
[slot_id
];
1949 xhci_err(xhci
, "ERROR Transfer event pointed to bad slot\n");
1953 /* Endpoint ID is 1 based, our index is zero based */
1954 ep_index
= TRB_TO_EP_ID(le32_to_cpu(event
->flags
)) - 1;
1955 ep
= &xdev
->eps
[ep_index
];
1956 ep_ring
= xhci_dma_to_transfer_ring(ep
, le64_to_cpu(event
->buffer
));
1957 ep_ctx
= xhci_get_ep_ctx(xhci
, xdev
->out_ctx
, ep_index
);
1959 (le32_to_cpu(ep_ctx
->ep_info
) & EP_STATE_MASK
) ==
1960 EP_STATE_DISABLED
) {
1961 xhci_err(xhci
, "ERROR Transfer event for disabled endpoint "
1962 "or incorrect stream ring\n");
1966 /* Count current td numbers if ep->skip is set */
1968 list_for_each(tmp
, &ep_ring
->td_list
)
1972 event_dma
= le64_to_cpu(event
->buffer
);
1973 trb_comp_code
= GET_COMP_CODE(le32_to_cpu(event
->transfer_len
));
1974 /* Look for common error cases */
1975 switch (trb_comp_code
) {
1976 /* Skip codes that require special handling depending on
1983 xhci_dbg(xhci
, "Stopped on Transfer TRB\n");
1985 case COMP_STOP_INVAL
:
1986 xhci_dbg(xhci
, "Stopped on No-op or Link TRB\n");
1989 xhci_warn(xhci
, "WARN: Stalled endpoint\n");
1990 ep
->ep_state
|= EP_HALTED
;
1994 xhci_warn(xhci
, "WARN: TRB error on endpoint\n");
1997 case COMP_SPLIT_ERR
:
1999 xhci_warn(xhci
, "WARN: transfer error on endpoint\n");
2003 xhci_warn(xhci
, "WARN: babble error on endpoint\n");
2004 status
= -EOVERFLOW
;
2007 xhci_warn(xhci
, "WARN: HC couldn't access mem fast enough\n");
2011 xhci_warn(xhci
, "WARN: bandwidth overrun event on endpoint\n");
2013 case COMP_BUFF_OVER
:
2014 xhci_warn(xhci
, "WARN: buffer overrun event on endpoint\n");
2018 * When the Isoch ring is empty, the xHC will generate
2019 * a Ring Overrun Event for IN Isoch endpoint or Ring
2020 * Underrun Event for OUT Isoch endpoint.
2022 xhci_dbg(xhci
, "underrun event on endpoint\n");
2023 if (!list_empty(&ep_ring
->td_list
))
2024 xhci_dbg(xhci
, "Underrun Event for slot %d ep %d "
2025 "still with TDs queued?\n",
2026 TRB_TO_SLOT_ID(le32_to_cpu(event
->flags
)),
2030 xhci_dbg(xhci
, "overrun event on endpoint\n");
2031 if (!list_empty(&ep_ring
->td_list
))
2032 xhci_dbg(xhci
, "Overrun Event for slot %d ep %d "
2033 "still with TDs queued?\n",
2034 TRB_TO_SLOT_ID(le32_to_cpu(event
->flags
)),
2038 xhci_warn(xhci
, "WARN: detect an incompatible device");
2041 case COMP_MISSED_INT
:
2043 * When encounter missed service error, one or more isoc tds
2044 * may be missed by xHC.
2045 * Set skip flag of the ep_ring; Complete the missed tds as
2046 * short transfer when process the ep_ring next time.
2049 xhci_dbg(xhci
, "Miss service interval error, set skip flag\n");
2052 if (xhci_is_vendor_info_code(xhci
, trb_comp_code
)) {
2056 xhci_warn(xhci
, "ERROR Unknown event condition, HC probably "
2062 /* This TRB should be in the TD at the head of this ring's
2065 if (list_empty(&ep_ring
->td_list
)) {
2066 xhci_warn(xhci
, "WARN Event TRB for slot %d ep %d "
2067 "with no TDs queued?\n",
2068 TRB_TO_SLOT_ID(le32_to_cpu(event
->flags
)),
2070 xhci_dbg(xhci
, "Event TRB with TRB type ID %u\n",
2071 (le32_to_cpu(event
->flags
) &
2072 TRB_TYPE_BITMASK
)>>10);
2073 xhci_print_trb_offsets(xhci
, (union xhci_trb
*) event
);
2076 xhci_dbg(xhci
, "td_list is empty while skip "
2077 "flag set. Clear skip flag.\n");
2083 /* We've skipped all the TDs on the ep ring when ep->skip set */
2084 if (ep
->skip
&& td_num
== 0) {
2086 xhci_dbg(xhci
, "All tds on the ep_ring skipped. "
2087 "Clear skip flag.\n");
2092 td
= list_entry(ep_ring
->td_list
.next
, struct xhci_td
, td_list
);
2096 /* Is this a TRB in the currently executing TD? */
2097 event_seg
= trb_in_td(ep_ring
->deq_seg
, ep_ring
->dequeue
,
2098 td
->last_trb
, event_dma
);
2101 * Skip the Force Stopped Event. The event_trb(event_dma) of FSE
2102 * is not in the current TD pointed by ep_ring->dequeue because
2103 * that the hardware dequeue pointer still at the previous TRB
2104 * of the current TD. The previous TRB maybe a Link TD or the
2105 * last TRB of the previous TD. The command completion handle
2106 * will take care the rest.
2108 if (!event_seg
&& trb_comp_code
== COMP_STOP_INVAL
) {
2115 !usb_endpoint_xfer_isoc(&td
->urb
->ep
->desc
)) {
2116 /* Some host controllers give a spurious
2117 * successful event after a short transfer.
2120 if ((xhci
->quirks
& XHCI_SPURIOUS_SUCCESS
) &&
2121 ep_ring
->last_td_was_short
) {
2122 ep_ring
->last_td_was_short
= false;
2126 /* HC is busted, give up! */
2128 "ERROR Transfer event TRB DMA ptr not "
2129 "part of current TD\n");
2133 ret
= skip_isoc_td(xhci
, td
, event
, ep
, &status
);
2136 if (trb_comp_code
== COMP_SHORT_TX
)
2137 ep_ring
->last_td_was_short
= true;
2139 ep_ring
->last_td_was_short
= false;
2142 xhci_dbg(xhci
, "Found td. Clear skip flag.\n");
2146 event_trb
= &event_seg
->trbs
[(event_dma
- event_seg
->dma
) /
2147 sizeof(*event_trb
)];
2149 * No-op TRB should not trigger interrupts.
2150 * If event_trb is a no-op TRB, it means the
2151 * corresponding TD has been cancelled. Just ignore
2154 if (TRB_TYPE_NOOP_LE32(event_trb
->generic
.field
[3])) {
2156 "event_trb is a no-op TRB. Skip it\n");
2160 /* Now update the urb's actual_length and give back to
2163 if (usb_endpoint_xfer_control(&td
->urb
->ep
->desc
))
2164 ret
= process_ctrl_td(xhci
, td
, event_trb
, event
, ep
,
2166 else if (usb_endpoint_xfer_isoc(&td
->urb
->ep
->desc
))
2167 ret
= process_isoc_td(xhci
, td
, event_trb
, event
, ep
,
2170 ret
= process_bulk_intr_td(xhci
, td
, event_trb
, event
,
2175 * Do not update event ring dequeue pointer if ep->skip is set.
2176 * Will roll back to continue process missed tds.
2178 if (trb_comp_code
== COMP_MISSED_INT
|| !ep
->skip
) {
2179 inc_deq(xhci
, xhci
->event_ring
, true);
2184 urb_priv
= urb
->hcpriv
;
2185 /* Leave the TD around for the reset endpoint function
2186 * to use(but only if it's not a control endpoint,
2187 * since we already queued the Set TR dequeue pointer
2188 * command for stalled control endpoints).
2190 if (usb_endpoint_xfer_control(&urb
->ep
->desc
) ||
2191 (trb_comp_code
!= COMP_STALL
&&
2192 trb_comp_code
!= COMP_BABBLE
))
2193 xhci_urb_free_priv(xhci
, urb_priv
);
2195 usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb
->dev
->bus
), urb
);
2196 if ((urb
->actual_length
!= urb
->transfer_buffer_length
&&
2197 (urb
->transfer_flags
&
2198 URB_SHORT_NOT_OK
)) ||
2200 !usb_endpoint_xfer_isoc(&urb
->ep
->desc
)))
2201 xhci_dbg(xhci
, "Giveback URB %p, len = %d, "
2202 "expected = %x, status = %d\n",
2203 urb
, urb
->actual_length
,
2204 urb
->transfer_buffer_length
,
2206 spin_unlock(&xhci
->lock
);
2207 /* EHCI, UHCI, and OHCI always unconditionally set the
2208 * urb->status of an isochronous endpoint to 0.
2210 if (usb_pipetype(urb
->pipe
) == PIPE_ISOCHRONOUS
)
2212 usb_hcd_giveback_urb(bus_to_hcd(urb
->dev
->bus
), urb
, status
);
2213 spin_lock(&xhci
->lock
);
2217 * If ep->skip is set, it means there are missed tds on the
2218 * endpoint ring need to take care of.
2219 * Process them as short transfer until reach the td pointed by
2222 } while (ep
->skip
&& trb_comp_code
!= COMP_MISSED_INT
);
2228 * This function handles all OS-owned events on the event ring. It may drop
2229 * xhci->lock between event processing (e.g. to pass up port status changes).
2230 * Returns >0 for "possibly more events to process" (caller should call again),
2231 * otherwise 0 if done. In future, <0 returns should indicate error code.
2233 static int xhci_handle_event(struct xhci_hcd
*xhci
)
2235 union xhci_trb
*event
;
2236 int update_ptrs
= 1;
2239 if (!xhci
->event_ring
|| !xhci
->event_ring
->dequeue
) {
2240 xhci
->error_bitmask
|= 1 << 1;
2244 event
= xhci
->event_ring
->dequeue
;
2245 /* Does the HC or OS own the TRB? */
2246 if ((le32_to_cpu(event
->event_cmd
.flags
) & TRB_CYCLE
) !=
2247 xhci
->event_ring
->cycle_state
) {
2248 xhci
->error_bitmask
|= 1 << 2;
2253 * Barrier between reading the TRB_CYCLE (valid) flag above and any
2254 * speculative reads of the event's flags/data below.
2257 /* FIXME: Handle more event types. */
2258 switch ((le32_to_cpu(event
->event_cmd
.flags
) & TRB_TYPE_BITMASK
)) {
2259 case TRB_TYPE(TRB_COMPLETION
):
2260 handle_cmd_completion(xhci
, &event
->event_cmd
);
2262 case TRB_TYPE(TRB_PORT_STATUS
):
2263 handle_port_status(xhci
, event
);
2266 case TRB_TYPE(TRB_TRANSFER
):
2267 ret
= handle_tx_event(xhci
, &event
->trans_event
);
2269 xhci
->error_bitmask
|= 1 << 9;
2274 if ((le32_to_cpu(event
->event_cmd
.flags
) & TRB_TYPE_BITMASK
) >=
2276 handle_vendor_event(xhci
, event
);
2278 xhci
->error_bitmask
|= 1 << 3;
2280 /* Any of the above functions may drop and re-acquire the lock, so check
2281 * to make sure a watchdog timer didn't mark the host as non-responsive.
2283 if (xhci
->xhc_state
& XHCI_STATE_DYING
) {
2284 xhci_dbg(xhci
, "xHCI host dying, returning from "
2285 "event handler.\n");
2290 /* Update SW event ring dequeue pointer */
2291 inc_deq(xhci
, xhci
->event_ring
, true);
2293 /* Are there more items on the event ring? Caller will call us again to
2300 * xHCI spec says we can get an interrupt, and if the HC has an error condition,
2301 * we might get bad data out of the event ring. Section 4.10.2.7 has a list of
2302 * indicators of an event TRB error, but we check the status *first* to be safe.
2304 irqreturn_t
xhci_irq(struct usb_hcd
*hcd
)
2306 struct xhci_hcd
*xhci
= hcd_to_xhci(hcd
);
2308 union xhci_trb
*trb
;
2310 union xhci_trb
*event_ring_deq
;
2313 spin_lock(&xhci
->lock
);
2314 trb
= xhci
->event_ring
->dequeue
;
2315 /* Check if the xHC generated the interrupt, or the irq is shared */
2316 status
= xhci_readl(xhci
, &xhci
->op_regs
->status
);
2317 if (status
== 0xffffffff)
2320 if (!(status
& STS_EINT
)) {
2321 spin_unlock(&xhci
->lock
);
2324 if (status
& STS_FATAL
) {
2325 xhci_warn(xhci
, "WARNING: Host System Error\n");
2328 spin_unlock(&xhci
->lock
);
2333 * Clear the op reg interrupt status first,
2334 * so we can receive interrupts from other MSI-X interrupters.
2335 * Write 1 to clear the interrupt status.
2338 xhci_writel(xhci
, status
, &xhci
->op_regs
->status
);
2339 /* FIXME when MSI-X is supported and there are multiple vectors */
2340 /* Clear the MSI-X event interrupt status */
2342 if (hcd
->irq
!= -1) {
2344 /* Acknowledge the PCI interrupt */
2345 irq_pending
= xhci_readl(xhci
, &xhci
->ir_set
->irq_pending
);
2347 xhci_writel(xhci
, irq_pending
, &xhci
->ir_set
->irq_pending
);
2350 if (xhci
->xhc_state
& XHCI_STATE_DYING
) {
2351 xhci_dbg(xhci
, "xHCI dying, ignoring interrupt. "
2352 "Shouldn't IRQs be disabled?\n");
2353 /* Clear the event handler busy flag (RW1C);
2354 * the event ring should be empty.
2356 temp_64
= xhci_read_64(xhci
, &xhci
->ir_set
->erst_dequeue
);
2357 xhci_write_64(xhci
, temp_64
| ERST_EHB
,
2358 &xhci
->ir_set
->erst_dequeue
);
2359 spin_unlock(&xhci
->lock
);
2364 event_ring_deq
= xhci
->event_ring
->dequeue
;
2365 /* FIXME this should be a delayed service routine
2366 * that clears the EHB.
2368 while (xhci_handle_event(xhci
) > 0) {}
2370 temp_64
= xhci_read_64(xhci
, &xhci
->ir_set
->erst_dequeue
);
2371 /* If necessary, update the HW's version of the event ring deq ptr. */
2372 if (event_ring_deq
!= xhci
->event_ring
->dequeue
) {
2373 deq
= xhci_trb_virt_to_dma(xhci
->event_ring
->deq_seg
,
2374 xhci
->event_ring
->dequeue
);
2376 xhci_warn(xhci
, "WARN something wrong with SW event "
2377 "ring dequeue ptr.\n");
2378 /* Update HC event ring dequeue pointer */
2379 temp_64
&= ERST_PTR_MASK
;
2380 temp_64
|= ((u64
) deq
& (u64
) ~ERST_PTR_MASK
);
2383 /* Clear the event handler busy flag (RW1C); event ring is empty. */
2384 temp_64
|= ERST_EHB
;
2385 xhci_write_64(xhci
, temp_64
, &xhci
->ir_set
->erst_dequeue
);
2387 spin_unlock(&xhci
->lock
);
2392 irqreturn_t
xhci_msi_irq(int irq
, struct usb_hcd
*hcd
)
2395 struct xhci_hcd
*xhci
;
2397 xhci
= hcd_to_xhci(hcd
);
2398 set_bit(HCD_FLAG_SAW_IRQ
, &hcd
->flags
);
2399 if (xhci
->shared_hcd
)
2400 set_bit(HCD_FLAG_SAW_IRQ
, &xhci
->shared_hcd
->flags
);
2402 ret
= xhci_irq(hcd
);
2407 /**** Endpoint Ring Operations ****/
2410 * Generic function for queueing a TRB on a ring.
2411 * The caller must have checked to make sure there's room on the ring.
2413 * @more_trbs_coming: Will you enqueue more TRBs before calling
2414 * prepare_transfer()?
2416 static void queue_trb(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
2417 bool consumer
, bool more_trbs_coming
, bool isoc
,
2418 u32 field1
, u32 field2
, u32 field3
, u32 field4
)
2420 struct xhci_generic_trb
*trb
;
2422 trb
= &ring
->enqueue
->generic
;
2423 trb
->field
[0] = cpu_to_le32(field1
);
2424 trb
->field
[1] = cpu_to_le32(field2
);
2425 trb
->field
[2] = cpu_to_le32(field3
);
2426 trb
->field
[3] = cpu_to_le32(field4
);
2427 inc_enq(xhci
, ring
, consumer
, more_trbs_coming
, isoc
);
2431 * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
2432 * FIXME allocate segments if the ring is full.
2434 static int prepare_ring(struct xhci_hcd
*xhci
, struct xhci_ring
*ep_ring
,
2435 u32 ep_state
, unsigned int num_trbs
, bool isoc
, gfp_t mem_flags
)
2437 /* Make sure the endpoint has been added to xHC schedule */
2439 case EP_STATE_DISABLED
:
2441 * USB core changed config/interfaces without notifying us,
2442 * or hardware is reporting the wrong state.
2444 xhci_warn(xhci
, "WARN urb submitted to disabled ep\n");
2446 case EP_STATE_ERROR
:
2447 xhci_warn(xhci
, "WARN waiting for error on ep to be cleared\n");
2448 /* FIXME event handling code for error needs to clear it */
2449 /* XXX not sure if this should be -ENOENT or not */
2451 case EP_STATE_HALTED
:
2452 xhci_dbg(xhci
, "WARN halted endpoint, queueing URB anyway.\n");
2453 case EP_STATE_STOPPED
:
2454 case EP_STATE_RUNNING
:
2457 xhci_err(xhci
, "ERROR unknown endpoint state for ep\n");
2459 * FIXME issue Configure Endpoint command to try to get the HC
2460 * back into a known state.
2464 if (!room_on_ring(xhci
, ep_ring
, num_trbs
)) {
2465 /* FIXME allocate more room */
2466 xhci_err(xhci
, "ERROR no room on ep ring\n");
2470 if (enqueue_is_link_trb(ep_ring
)) {
2471 struct xhci_ring
*ring
= ep_ring
;
2472 union xhci_trb
*next
;
2474 next
= ring
->enqueue
;
2476 while (last_trb(xhci
, ring
, ring
->enq_seg
, next
)) {
2477 /* If we're not dealing with 0.95 hardware or isoc rings
2478 * on AMD 0.96 host, clear the chain bit.
2480 if (!xhci_link_trb_quirk(xhci
) && !(isoc
&&
2481 (xhci
->quirks
& XHCI_AMD_0x96_HOST
)))
2482 next
->link
.control
&= cpu_to_le32(~TRB_CHAIN
);
2484 next
->link
.control
|= cpu_to_le32(TRB_CHAIN
);
2487 next
->link
.control
^= cpu_to_le32(TRB_CYCLE
);
2489 /* Toggle the cycle bit after the last ring segment. */
2490 if (last_trb_on_last_seg(xhci
, ring
, ring
->enq_seg
, next
)) {
2491 ring
->cycle_state
= (ring
->cycle_state
? 0 : 1);
2492 if (!in_interrupt()) {
2493 xhci_dbg(xhci
, "queue_trb: Toggle cycle "
2494 "state for ring %p = %i\n",
2495 ring
, (unsigned int)ring
->cycle_state
);
2498 ring
->enq_seg
= ring
->enq_seg
->next
;
2499 ring
->enqueue
= ring
->enq_seg
->trbs
;
2500 next
= ring
->enqueue
;
2507 static int prepare_transfer(struct xhci_hcd
*xhci
,
2508 struct xhci_virt_device
*xdev
,
2509 unsigned int ep_index
,
2510 unsigned int stream_id
,
2511 unsigned int num_trbs
,
2513 unsigned int td_index
,
2518 struct urb_priv
*urb_priv
;
2520 struct xhci_ring
*ep_ring
;
2521 struct xhci_ep_ctx
*ep_ctx
= xhci_get_ep_ctx(xhci
, xdev
->out_ctx
, ep_index
);
2523 ep_ring
= xhci_stream_id_to_ring(xdev
, ep_index
, stream_id
);
2525 xhci_dbg(xhci
, "Can't prepare ring for bad stream ID %u\n",
2530 ret
= prepare_ring(xhci
, ep_ring
,
2531 le32_to_cpu(ep_ctx
->ep_info
) & EP_STATE_MASK
,
2532 num_trbs
, isoc
, mem_flags
);
2536 urb_priv
= urb
->hcpriv
;
2537 td
= urb_priv
->td
[td_index
];
2539 INIT_LIST_HEAD(&td
->td_list
);
2540 INIT_LIST_HEAD(&td
->cancelled_td_list
);
2542 if (td_index
== 0) {
2543 ret
= usb_hcd_link_urb_to_ep(bus_to_hcd(urb
->dev
->bus
), urb
);
2549 /* Add this TD to the tail of the endpoint ring's TD list */
2550 list_add_tail(&td
->td_list
, &ep_ring
->td_list
);
2551 td
->start_seg
= ep_ring
->enq_seg
;
2552 td
->first_trb
= ep_ring
->enqueue
;
2554 urb_priv
->td
[td_index
] = td
;
2559 static unsigned int count_sg_trbs_needed(struct xhci_hcd
*xhci
, struct urb
*urb
)
2561 int num_sgs
, num_trbs
, running_total
, temp
, i
;
2562 struct scatterlist
*sg
;
2565 num_sgs
= urb
->num_mapped_sgs
;
2566 temp
= urb
->transfer_buffer_length
;
2568 xhci_dbg(xhci
, "count sg list trbs: \n");
2570 for_each_sg(urb
->sg
, sg
, num_sgs
, i
) {
2571 unsigned int previous_total_trbs
= num_trbs
;
2572 unsigned int len
= sg_dma_len(sg
);
2574 /* Scatter gather list entries may cross 64KB boundaries */
2575 running_total
= TRB_MAX_BUFF_SIZE
-
2576 (sg_dma_address(sg
) & (TRB_MAX_BUFF_SIZE
- 1));
2577 running_total
&= TRB_MAX_BUFF_SIZE
- 1;
2578 if (running_total
!= 0)
2581 /* How many more 64KB chunks to transfer, how many more TRBs? */
2582 while (running_total
< sg_dma_len(sg
) && running_total
< temp
) {
2584 running_total
+= TRB_MAX_BUFF_SIZE
;
2586 xhci_dbg(xhci
, " sg #%d: dma = %#llx, len = %#x (%d), num_trbs = %d\n",
2587 i
, (unsigned long long)sg_dma_address(sg
),
2588 len
, len
, num_trbs
- previous_total_trbs
);
2590 len
= min_t(int, len
, temp
);
2595 xhci_dbg(xhci
, "\n");
2596 if (!in_interrupt())
2597 xhci_dbg(xhci
, "ep %#x - urb len = %d, sglist used, "
2599 urb
->ep
->desc
.bEndpointAddress
,
2600 urb
->transfer_buffer_length
,
2605 static void check_trb_math(struct urb
*urb
, int num_trbs
, int running_total
)
2608 dev_err(&urb
->dev
->dev
, "%s - ep %#x - Miscalculated number of "
2609 "TRBs, %d left\n", __func__
,
2610 urb
->ep
->desc
.bEndpointAddress
, num_trbs
);
2611 if (running_total
!= urb
->transfer_buffer_length
)
2612 dev_err(&urb
->dev
->dev
, "%s - ep %#x - Miscalculated tx length, "
2613 "queued %#x (%d), asked for %#x (%d)\n",
2615 urb
->ep
->desc
.bEndpointAddress
,
2616 running_total
, running_total
,
2617 urb
->transfer_buffer_length
,
2618 urb
->transfer_buffer_length
);
2621 static void giveback_first_trb(struct xhci_hcd
*xhci
, int slot_id
,
2622 unsigned int ep_index
, unsigned int stream_id
, int start_cycle
,
2623 struct xhci_generic_trb
*start_trb
)
2626 * Pass all the TRBs to the hardware at once and make sure this write
2631 start_trb
->field
[3] |= cpu_to_le32(start_cycle
);
2633 start_trb
->field
[3] &= cpu_to_le32(~TRB_CYCLE
);
2634 xhci_ring_ep_doorbell(xhci
, slot_id
, ep_index
, stream_id
);
2638 * xHCI uses normal TRBs for both bulk and interrupt. When the interrupt
2639 * endpoint is to be serviced, the xHC will consume (at most) one TD. A TD
2640 * (comprised of sg list entries) can take several service intervals to
2643 int xhci_queue_intr_tx(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
2644 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
2646 struct xhci_ep_ctx
*ep_ctx
= xhci_get_ep_ctx(xhci
,
2647 xhci
->devs
[slot_id
]->out_ctx
, ep_index
);
2651 xhci_interval
= EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx
->ep_info
));
2652 ep_interval
= urb
->interval
;
2653 /* Convert to microframes */
2654 if (urb
->dev
->speed
== USB_SPEED_LOW
||
2655 urb
->dev
->speed
== USB_SPEED_FULL
)
2657 /* FIXME change this to a warning and a suggestion to use the new API
2658 * to set the polling interval (once the API is added).
2660 if (xhci_interval
!= ep_interval
) {
2661 if (printk_ratelimit())
2662 dev_dbg(&urb
->dev
->dev
, "Driver uses different interval"
2663 " (%d microframe%s) than xHCI "
2664 "(%d microframe%s)\n",
2666 ep_interval
== 1 ? "" : "s",
2668 xhci_interval
== 1 ? "" : "s");
2669 urb
->interval
= xhci_interval
;
2670 /* Convert back to frames for LS/FS devices */
2671 if (urb
->dev
->speed
== USB_SPEED_LOW
||
2672 urb
->dev
->speed
== USB_SPEED_FULL
)
2675 return xhci_queue_bulk_tx(xhci
, GFP_ATOMIC
, urb
, slot_id
, ep_index
);
2679 * The TD size is the number of bytes remaining in the TD (including this TRB),
2680 * right shifted by 10.
2681 * It must fit in bits 21:17, so it can't be bigger than 31.
2683 static u32
xhci_td_remainder(unsigned int remainder
)
2685 u32 max
= (1 << (21 - 17 + 1)) - 1;
2687 if ((remainder
>> 10) >= max
)
2690 return (remainder
>> 10) << 17;
2694 * For xHCI 1.0 host controllers, TD size is the number of packets remaining in
2695 * the TD (*not* including this TRB).
2697 * Total TD packet count = total_packet_count =
2698 * roundup(TD size in bytes / wMaxPacketSize)
2700 * Packets transferred up to and including this TRB = packets_transferred =
2701 * rounddown(total bytes transferred including this TRB / wMaxPacketSize)
2703 * TD size = total_packet_count - packets_transferred
2705 * It must fit in bits 21:17, so it can't be bigger than 31.
2708 static u32
xhci_v1_0_td_remainder(int running_total
, int trb_buff_len
,
2709 unsigned int total_packet_count
, struct urb
*urb
)
2711 int packets_transferred
;
2713 /* One TRB with a zero-length data packet. */
2714 if (running_total
== 0 && trb_buff_len
== 0)
2717 /* All the TRB queueing functions don't count the current TRB in
2720 packets_transferred
= (running_total
+ trb_buff_len
) /
2721 usb_endpoint_maxp(&urb
->ep
->desc
);
2723 return xhci_td_remainder(total_packet_count
- packets_transferred
);
2726 static int queue_bulk_sg_tx(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
2727 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
2729 struct xhci_ring
*ep_ring
;
2730 unsigned int num_trbs
;
2731 struct urb_priv
*urb_priv
;
2733 struct scatterlist
*sg
;
2735 int trb_buff_len
, this_sg_len
, running_total
;
2736 unsigned int total_packet_count
;
2739 bool more_trbs_coming
;
2741 struct xhci_generic_trb
*start_trb
;
2744 ep_ring
= xhci_urb_to_transfer_ring(xhci
, urb
);
2748 num_trbs
= count_sg_trbs_needed(xhci
, urb
);
2749 num_sgs
= urb
->num_mapped_sgs
;
2750 total_packet_count
= roundup(urb
->transfer_buffer_length
,
2751 usb_endpoint_maxp(&urb
->ep
->desc
));
2753 trb_buff_len
= prepare_transfer(xhci
, xhci
->devs
[slot_id
],
2754 ep_index
, urb
->stream_id
,
2755 num_trbs
, urb
, 0, false, mem_flags
);
2756 if (trb_buff_len
< 0)
2757 return trb_buff_len
;
2759 urb_priv
= urb
->hcpriv
;
2760 td
= urb_priv
->td
[0];
2763 * Don't give the first TRB to the hardware (by toggling the cycle bit)
2764 * until we've finished creating all the other TRBs. The ring's cycle
2765 * state may change as we enqueue the other TRBs, so save it too.
2767 start_trb
= &ep_ring
->enqueue
->generic
;
2768 start_cycle
= ep_ring
->cycle_state
;
2772 * How much data is in the first TRB?
2774 * There are three forces at work for TRB buffer pointers and lengths:
2775 * 1. We don't want to walk off the end of this sg-list entry buffer.
2776 * 2. The transfer length that the driver requested may be smaller than
2777 * the amount of memory allocated for this scatter-gather list.
2778 * 3. TRBs buffers can't cross 64KB boundaries.
2781 addr
= (u64
) sg_dma_address(sg
);
2782 this_sg_len
= sg_dma_len(sg
);
2783 trb_buff_len
= TRB_MAX_BUFF_SIZE
- (addr
& (TRB_MAX_BUFF_SIZE
- 1));
2784 trb_buff_len
= min_t(int, trb_buff_len
, this_sg_len
);
2785 if (trb_buff_len
> urb
->transfer_buffer_length
)
2786 trb_buff_len
= urb
->transfer_buffer_length
;
2787 xhci_dbg(xhci
, "First length to xfer from 1st sglist entry = %u\n",
2791 /* Queue the first TRB, even if it's zero-length */
2794 u32 length_field
= 0;
2797 /* Don't change the cycle bit of the first TRB until later */
2800 if (start_cycle
== 0)
2803 field
|= ep_ring
->cycle_state
;
2805 /* Chain all the TRBs together; clear the chain bit in the last
2806 * TRB to indicate it's the last TRB in the chain.
2811 /* FIXME - add check for ZERO_PACKET flag before this */
2812 td
->last_trb
= ep_ring
->enqueue
;
2816 /* Only set interrupt on short packet for IN endpoints */
2817 if (usb_urb_dir_in(urb
))
2820 xhci_dbg(xhci
, " sg entry: dma = %#x, len = %#x (%d), "
2821 "64KB boundary at %#x, end dma = %#x\n",
2822 (unsigned int) addr
, trb_buff_len
, trb_buff_len
,
2823 (unsigned int) (addr
+ TRB_MAX_BUFF_SIZE
) & ~(TRB_MAX_BUFF_SIZE
- 1),
2824 (unsigned int) addr
+ trb_buff_len
);
2825 if (TRB_MAX_BUFF_SIZE
-
2826 (addr
& (TRB_MAX_BUFF_SIZE
- 1)) < trb_buff_len
) {
2827 xhci_warn(xhci
, "WARN: sg dma xfer crosses 64KB boundaries!\n");
2828 xhci_dbg(xhci
, "Next boundary at %#x, end dma = %#x\n",
2829 (unsigned int) (addr
+ TRB_MAX_BUFF_SIZE
) & ~(TRB_MAX_BUFF_SIZE
- 1),
2830 (unsigned int) addr
+ trb_buff_len
);
2833 /* Set the TRB length, TD size, and interrupter fields. */
2834 if (xhci
->hci_version
< 0x100) {
2835 remainder
= xhci_td_remainder(
2836 urb
->transfer_buffer_length
-
2839 remainder
= xhci_v1_0_td_remainder(running_total
,
2840 trb_buff_len
, total_packet_count
, urb
);
2842 length_field
= TRB_LEN(trb_buff_len
) |
2847 more_trbs_coming
= true;
2849 more_trbs_coming
= false;
2850 queue_trb(xhci
, ep_ring
, false, more_trbs_coming
, false,
2851 lower_32_bits(addr
),
2852 upper_32_bits(addr
),
2854 field
| TRB_TYPE(TRB_NORMAL
));
2856 running_total
+= trb_buff_len
;
2858 /* Calculate length for next transfer --
2859 * Are we done queueing all the TRBs for this sg entry?
2861 this_sg_len
-= trb_buff_len
;
2862 if (this_sg_len
== 0) {
2867 addr
= (u64
) sg_dma_address(sg
);
2868 this_sg_len
= sg_dma_len(sg
);
2870 addr
+= trb_buff_len
;
2873 trb_buff_len
= TRB_MAX_BUFF_SIZE
-
2874 (addr
& (TRB_MAX_BUFF_SIZE
- 1));
2875 trb_buff_len
= min_t(int, trb_buff_len
, this_sg_len
);
2876 if (running_total
+ trb_buff_len
> urb
->transfer_buffer_length
)
2878 urb
->transfer_buffer_length
- running_total
;
2879 } while (running_total
< urb
->transfer_buffer_length
);
2881 check_trb_math(urb
, num_trbs
, running_total
);
2882 giveback_first_trb(xhci
, slot_id
, ep_index
, urb
->stream_id
,
2883 start_cycle
, start_trb
);
2887 /* This is very similar to what ehci-q.c qtd_fill() does */
2888 int xhci_queue_bulk_tx(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
2889 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
2891 struct xhci_ring
*ep_ring
;
2892 struct urb_priv
*urb_priv
;
2895 struct xhci_generic_trb
*start_trb
;
2897 bool more_trbs_coming
;
2899 u32 field
, length_field
;
2901 int running_total
, trb_buff_len
, ret
;
2902 unsigned int total_packet_count
;
2906 return queue_bulk_sg_tx(xhci
, mem_flags
, urb
, slot_id
, ep_index
);
2908 ep_ring
= xhci_urb_to_transfer_ring(xhci
, urb
);
2913 /* How much data is (potentially) left before the 64KB boundary? */
2914 running_total
= TRB_MAX_BUFF_SIZE
-
2915 (urb
->transfer_dma
& (TRB_MAX_BUFF_SIZE
- 1));
2916 running_total
&= TRB_MAX_BUFF_SIZE
- 1;
2918 /* If there's some data on this 64KB chunk, or we have to send a
2919 * zero-length transfer, we need at least one TRB
2921 if (running_total
!= 0 || urb
->transfer_buffer_length
== 0)
2923 /* How many more 64KB chunks to transfer, how many more TRBs? */
2924 while (running_total
< urb
->transfer_buffer_length
) {
2926 running_total
+= TRB_MAX_BUFF_SIZE
;
2928 /* FIXME: this doesn't deal with URB_ZERO_PACKET - need one more */
2930 if (!in_interrupt())
2931 xhci_dbg(xhci
, "ep %#x - urb len = %#x (%d), "
2932 "addr = %#llx, num_trbs = %d\n",
2933 urb
->ep
->desc
.bEndpointAddress
,
2934 urb
->transfer_buffer_length
,
2935 urb
->transfer_buffer_length
,
2936 (unsigned long long)urb
->transfer_dma
,
2939 ret
= prepare_transfer(xhci
, xhci
->devs
[slot_id
],
2940 ep_index
, urb
->stream_id
,
2941 num_trbs
, urb
, 0, false, mem_flags
);
2945 urb_priv
= urb
->hcpriv
;
2946 td
= urb_priv
->td
[0];
2949 * Don't give the first TRB to the hardware (by toggling the cycle bit)
2950 * until we've finished creating all the other TRBs. The ring's cycle
2951 * state may change as we enqueue the other TRBs, so save it too.
2953 start_trb
= &ep_ring
->enqueue
->generic
;
2954 start_cycle
= ep_ring
->cycle_state
;
2957 total_packet_count
= roundup(urb
->transfer_buffer_length
,
2958 usb_endpoint_maxp(&urb
->ep
->desc
));
2959 /* How much data is in the first TRB? */
2960 addr
= (u64
) urb
->transfer_dma
;
2961 trb_buff_len
= TRB_MAX_BUFF_SIZE
-
2962 (urb
->transfer_dma
& (TRB_MAX_BUFF_SIZE
- 1));
2963 if (trb_buff_len
> urb
->transfer_buffer_length
)
2964 trb_buff_len
= urb
->transfer_buffer_length
;
2968 /* Queue the first TRB, even if it's zero-length */
2973 /* Don't change the cycle bit of the first TRB until later */
2976 if (start_cycle
== 0)
2979 field
|= ep_ring
->cycle_state
;
2981 /* Chain all the TRBs together; clear the chain bit in the last
2982 * TRB to indicate it's the last TRB in the chain.
2987 /* FIXME - add check for ZERO_PACKET flag before this */
2988 td
->last_trb
= ep_ring
->enqueue
;
2992 /* Only set interrupt on short packet for IN endpoints */
2993 if (usb_urb_dir_in(urb
))
2996 /* Set the TRB length, TD size, and interrupter fields. */
2997 if (xhci
->hci_version
< 0x100) {
2998 remainder
= xhci_td_remainder(
2999 urb
->transfer_buffer_length
-
3002 remainder
= xhci_v1_0_td_remainder(running_total
,
3003 trb_buff_len
, total_packet_count
, urb
);
3005 length_field
= TRB_LEN(trb_buff_len
) |
3010 more_trbs_coming
= true;
3012 more_trbs_coming
= false;
3013 queue_trb(xhci
, ep_ring
, false, more_trbs_coming
, false,
3014 lower_32_bits(addr
),
3015 upper_32_bits(addr
),
3017 field
| TRB_TYPE(TRB_NORMAL
));
3019 running_total
+= trb_buff_len
;
3021 /* Calculate length for next transfer */
3022 addr
+= trb_buff_len
;
3023 trb_buff_len
= urb
->transfer_buffer_length
- running_total
;
3024 if (trb_buff_len
> TRB_MAX_BUFF_SIZE
)
3025 trb_buff_len
= TRB_MAX_BUFF_SIZE
;
3026 } while (running_total
< urb
->transfer_buffer_length
);
3028 check_trb_math(urb
, num_trbs
, running_total
);
3029 giveback_first_trb(xhci
, slot_id
, ep_index
, urb
->stream_id
,
3030 start_cycle
, start_trb
);
3034 /* Caller must have locked xhci->lock */
3035 int xhci_queue_ctrl_tx(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
3036 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
3038 struct xhci_ring
*ep_ring
;
3041 struct usb_ctrlrequest
*setup
;
3042 struct xhci_generic_trb
*start_trb
;
3044 u32 field
, length_field
;
3045 struct urb_priv
*urb_priv
;
3048 ep_ring
= xhci_urb_to_transfer_ring(xhci
, urb
);
3053 * Need to copy setup packet into setup TRB, so we can't use the setup
3056 if (!urb
->setup_packet
)
3059 if (!in_interrupt())
3060 xhci_dbg(xhci
, "Queueing ctrl tx for slot id %d, ep %d\n",
3062 /* 1 TRB for setup, 1 for status */
3065 * Don't need to check if we need additional event data and normal TRBs,
3066 * since data in control transfers will never get bigger than 16MB
3067 * XXX: can we get a buffer that crosses 64KB boundaries?
3069 if (urb
->transfer_buffer_length
> 0)
3071 ret
= prepare_transfer(xhci
, xhci
->devs
[slot_id
],
3072 ep_index
, urb
->stream_id
,
3073 num_trbs
, urb
, 0, false, mem_flags
);
3077 urb_priv
= urb
->hcpriv
;
3078 td
= urb_priv
->td
[0];
3081 * Don't give the first TRB to the hardware (by toggling the cycle bit)
3082 * until we've finished creating all the other TRBs. The ring's cycle
3083 * state may change as we enqueue the other TRBs, so save it too.
3085 start_trb
= &ep_ring
->enqueue
->generic
;
3086 start_cycle
= ep_ring
->cycle_state
;
3088 /* Queue setup TRB - see section 6.4.1.2.1 */
3089 /* FIXME better way to translate setup_packet into two u32 fields? */
3090 setup
= (struct usb_ctrlrequest
*) urb
->setup_packet
;
3092 field
|= TRB_IDT
| TRB_TYPE(TRB_SETUP
);
3093 if (start_cycle
== 0)
3096 /* xHCI 1.0 6.4.1.2.1: Transfer Type field */
3097 if (xhci
->hci_version
== 0x100) {
3098 if (urb
->transfer_buffer_length
> 0) {
3099 if (setup
->bRequestType
& USB_DIR_IN
)
3100 field
|= TRB_TX_TYPE(TRB_DATA_IN
);
3102 field
|= TRB_TX_TYPE(TRB_DATA_OUT
);
3106 queue_trb(xhci
, ep_ring
, false, true, false,
3107 setup
->bRequestType
| setup
->bRequest
<< 8 | le16_to_cpu(setup
->wValue
) << 16,
3108 le16_to_cpu(setup
->wIndex
) | le16_to_cpu(setup
->wLength
) << 16,
3109 TRB_LEN(8) | TRB_INTR_TARGET(0),
3110 /* Immediate data in pointer */
3113 /* If there's data, queue data TRBs */
3114 /* Only set interrupt on short packet for IN endpoints */
3115 if (usb_urb_dir_in(urb
))
3116 field
= TRB_ISP
| TRB_TYPE(TRB_DATA
);
3118 field
= TRB_TYPE(TRB_DATA
);
3120 length_field
= TRB_LEN(urb
->transfer_buffer_length
) |
3121 xhci_td_remainder(urb
->transfer_buffer_length
) |
3123 if (urb
->transfer_buffer_length
> 0) {
3124 if (setup
->bRequestType
& USB_DIR_IN
)
3125 field
|= TRB_DIR_IN
;
3126 queue_trb(xhci
, ep_ring
, false, true, false,
3127 lower_32_bits(urb
->transfer_dma
),
3128 upper_32_bits(urb
->transfer_dma
),
3130 field
| ep_ring
->cycle_state
);
3133 /* Save the DMA address of the last TRB in the TD */
3134 td
->last_trb
= ep_ring
->enqueue
;
3136 /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
3137 /* If the device sent data, the status stage is an OUT transfer */
3138 if (urb
->transfer_buffer_length
> 0 && setup
->bRequestType
& USB_DIR_IN
)
3142 queue_trb(xhci
, ep_ring
, false, false, false,
3146 /* Event on completion */
3147 field
| TRB_IOC
| TRB_TYPE(TRB_STATUS
) | ep_ring
->cycle_state
);
3149 giveback_first_trb(xhci
, slot_id
, ep_index
, 0,
3150 start_cycle
, start_trb
);
3154 static int count_isoc_trbs_needed(struct xhci_hcd
*xhci
,
3155 struct urb
*urb
, int i
)
3160 addr
= (u64
) (urb
->transfer_dma
+ urb
->iso_frame_desc
[i
].offset
);
3161 td_len
= urb
->iso_frame_desc
[i
].length
;
3163 num_trbs
= DIV_ROUND_UP(td_len
+ (addr
& (TRB_MAX_BUFF_SIZE
- 1)),
3172 * The transfer burst count field of the isochronous TRB defines the number of
3173 * bursts that are required to move all packets in this TD. Only SuperSpeed
3174 * devices can burst up to bMaxBurst number of packets per service interval.
3175 * This field is zero based, meaning a value of zero in the field means one
3176 * burst. Basically, for everything but SuperSpeed devices, this field will be
3177 * zero. Only xHCI 1.0 host controllers support this field.
3179 static unsigned int xhci_get_burst_count(struct xhci_hcd
*xhci
,
3180 struct usb_device
*udev
,
3181 struct urb
*urb
, unsigned int total_packet_count
)
3183 unsigned int max_burst
;
3185 if (xhci
->hci_version
< 0x100 || udev
->speed
!= USB_SPEED_SUPER
)
3188 max_burst
= urb
->ep
->ss_ep_comp
.bMaxBurst
;
3189 return roundup(total_packet_count
, max_burst
+ 1) - 1;
3193 * Returns the number of packets in the last "burst" of packets. This field is
3194 * valid for all speeds of devices. USB 2.0 devices can only do one "burst", so
3195 * the last burst packet count is equal to the total number of packets in the
3196 * TD. SuperSpeed endpoints can have up to 3 bursts. All but the last burst
3197 * must contain (bMaxBurst + 1) number of packets, but the last burst can
3198 * contain 1 to (bMaxBurst + 1) packets.
3200 static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd
*xhci
,
3201 struct usb_device
*udev
,
3202 struct urb
*urb
, unsigned int total_packet_count
)
3204 unsigned int max_burst
;
3205 unsigned int residue
;
3207 if (xhci
->hci_version
< 0x100)
3210 switch (udev
->speed
) {
3211 case USB_SPEED_SUPER
:
3212 /* bMaxBurst is zero based: 0 means 1 packet per burst */
3213 max_burst
= urb
->ep
->ss_ep_comp
.bMaxBurst
;
3214 residue
= total_packet_count
% (max_burst
+ 1);
3215 /* If residue is zero, the last burst contains (max_burst + 1)
3216 * number of packets, but the TLBPC field is zero-based.
3222 if (total_packet_count
== 0)
3224 return total_packet_count
- 1;
3228 /* This is for isoc transfer */
3229 static int xhci_queue_isoc_tx(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
3230 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
3232 struct xhci_ring
*ep_ring
;
3233 struct urb_priv
*urb_priv
;
3235 int num_tds
, trbs_per_td
;
3236 struct xhci_generic_trb
*start_trb
;
3239 u32 field
, length_field
;
3240 int running_total
, trb_buff_len
, td_len
, td_remain_len
, ret
;
3241 u64 start_addr
, addr
;
3243 bool more_trbs_coming
;
3245 ep_ring
= xhci
->devs
[slot_id
]->eps
[ep_index
].ring
;
3247 num_tds
= urb
->number_of_packets
;
3249 xhci_dbg(xhci
, "Isoc URB with zero packets?\n");
3253 if (!in_interrupt())
3254 xhci_dbg(xhci
, "ep %#x - urb len = %#x (%d),"
3255 " addr = %#llx, num_tds = %d\n",
3256 urb
->ep
->desc
.bEndpointAddress
,
3257 urb
->transfer_buffer_length
,
3258 urb
->transfer_buffer_length
,
3259 (unsigned long long)urb
->transfer_dma
,
3262 start_addr
= (u64
) urb
->transfer_dma
;
3263 start_trb
= &ep_ring
->enqueue
->generic
;
3264 start_cycle
= ep_ring
->cycle_state
;
3266 urb_priv
= urb
->hcpriv
;
3267 /* Queue the first TRB, even if it's zero-length */
3268 for (i
= 0; i
< num_tds
; i
++) {
3269 unsigned int total_packet_count
;
3270 unsigned int burst_count
;
3271 unsigned int residue
;
3275 addr
= start_addr
+ urb
->iso_frame_desc
[i
].offset
;
3276 td_len
= urb
->iso_frame_desc
[i
].length
;
3277 td_remain_len
= td_len
;
3278 total_packet_count
= roundup(td_len
,
3279 usb_endpoint_maxp(&urb
->ep
->desc
));
3280 /* A zero-length transfer still involves at least one packet. */
3281 if (total_packet_count
== 0)
3282 total_packet_count
++;
3283 burst_count
= xhci_get_burst_count(xhci
, urb
->dev
, urb
,
3284 total_packet_count
);
3285 residue
= xhci_get_last_burst_packet_count(xhci
,
3286 urb
->dev
, urb
, total_packet_count
);
3288 trbs_per_td
= count_isoc_trbs_needed(xhci
, urb
, i
);
3290 ret
= prepare_transfer(xhci
, xhci
->devs
[slot_id
], ep_index
,
3291 urb
->stream_id
, trbs_per_td
, urb
, i
, true,
3299 td
= urb_priv
->td
[i
];
3300 for (j
= 0; j
< trbs_per_td
; j
++) {
3302 field
= TRB_TBC(burst_count
) | TRB_TLBPC(residue
);
3305 /* Queue the isoc TRB */
3306 field
|= TRB_TYPE(TRB_ISOC
);
3307 /* Assume URB_ISO_ASAP is set */
3310 if (start_cycle
== 0)
3313 field
|= ep_ring
->cycle_state
;
3316 /* Queue other normal TRBs */
3317 field
|= TRB_TYPE(TRB_NORMAL
);
3318 field
|= ep_ring
->cycle_state
;
3321 /* Only set interrupt on short packet for IN EPs */
3322 if (usb_urb_dir_in(urb
))
3325 /* Chain all the TRBs together; clear the chain bit in
3326 * the last TRB to indicate it's the last TRB in the
3329 if (j
< trbs_per_td
- 1) {
3331 more_trbs_coming
= true;
3333 td
->last_trb
= ep_ring
->enqueue
;
3335 if (xhci
->hci_version
== 0x100) {
3336 /* Set BEI bit except for the last td */
3337 if (i
< num_tds
- 1)
3340 more_trbs_coming
= false;
3343 /* Calculate TRB length */
3344 trb_buff_len
= TRB_MAX_BUFF_SIZE
-
3345 (addr
& ((1 << TRB_MAX_BUFF_SHIFT
) - 1));
3346 if (trb_buff_len
> td_remain_len
)
3347 trb_buff_len
= td_remain_len
;
3349 /* Set the TRB length, TD size, & interrupter fields. */
3350 if (xhci
->hci_version
< 0x100) {
3351 remainder
= xhci_td_remainder(
3352 td_len
- running_total
);
3354 remainder
= xhci_v1_0_td_remainder(
3355 running_total
, trb_buff_len
,
3356 total_packet_count
, urb
);
3358 length_field
= TRB_LEN(trb_buff_len
) |
3362 queue_trb(xhci
, ep_ring
, false, more_trbs_coming
, true,
3363 lower_32_bits(addr
),
3364 upper_32_bits(addr
),
3367 running_total
+= trb_buff_len
;
3369 addr
+= trb_buff_len
;
3370 td_remain_len
-= trb_buff_len
;
3373 /* Check TD length */
3374 if (running_total
!= td_len
) {
3375 xhci_err(xhci
, "ISOC TD length unmatch\n");
3380 if (xhci_to_hcd(xhci
)->self
.bandwidth_isoc_reqs
== 0) {
3381 if (xhci
->quirks
& XHCI_AMD_PLL_FIX
)
3382 usb_amd_quirk_pll_disable();
3384 xhci_to_hcd(xhci
)->self
.bandwidth_isoc_reqs
++;
3386 giveback_first_trb(xhci
, slot_id
, ep_index
, urb
->stream_id
,
3387 start_cycle
, start_trb
);
3390 /* Clean up a partially enqueued isoc transfer. */
3392 for (i
--; i
>= 0; i
--)
3393 list_del_init(&urb_priv
->td
[i
]->td_list
);
3395 /* Use the first TD as a temporary variable to turn the TDs we've queued
3396 * into No-ops with a software-owned cycle bit. That way the hardware
3397 * won't accidentally start executing bogus TDs when we partially
3398 * overwrite them. td->first_trb and td->start_seg are already set.
3400 urb_priv
->td
[0]->last_trb
= ep_ring
->enqueue
;
3401 /* Every TRB except the first & last will have its cycle bit flipped. */
3402 td_to_noop(xhci
, ep_ring
, urb_priv
->td
[0], true);
3404 /* Reset the ring enqueue back to the first TRB and its cycle bit. */
3405 ep_ring
->enqueue
= urb_priv
->td
[0]->first_trb
;
3406 ep_ring
->enq_seg
= urb_priv
->td
[0]->start_seg
;
3407 ep_ring
->cycle_state
= start_cycle
;
3408 usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb
->dev
->bus
), urb
);
3413 * Check transfer ring to guarantee there is enough room for the urb.
3414 * Update ISO URB start_frame and interval.
3415 * Update interval as xhci_queue_intr_tx does. Just use xhci frame_index to
3416 * update the urb->start_frame by now.
3417 * Always assume URB_ISO_ASAP set, and NEVER use urb->start_frame as input.
3419 int xhci_queue_isoc_tx_prepare(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
3420 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
3422 struct xhci_virt_device
*xdev
;
3423 struct xhci_ring
*ep_ring
;
3424 struct xhci_ep_ctx
*ep_ctx
;
3428 int num_tds
, num_trbs
, i
;
3431 xdev
= xhci
->devs
[slot_id
];
3432 ep_ring
= xdev
->eps
[ep_index
].ring
;
3433 ep_ctx
= xhci_get_ep_ctx(xhci
, xdev
->out_ctx
, ep_index
);
3436 num_tds
= urb
->number_of_packets
;
3437 for (i
= 0; i
< num_tds
; i
++)
3438 num_trbs
+= count_isoc_trbs_needed(xhci
, urb
, i
);
3440 /* Check the ring to guarantee there is enough room for the whole urb.
3441 * Do not insert any td of the urb to the ring if the check failed.
3443 ret
= prepare_ring(xhci
, ep_ring
, le32_to_cpu(ep_ctx
->ep_info
) & EP_STATE_MASK
,
3444 num_trbs
, true, mem_flags
);
3448 start_frame
= xhci_readl(xhci
, &xhci
->run_regs
->microframe_index
);
3449 start_frame
&= 0x3fff;
3451 urb
->start_frame
= start_frame
;
3452 if (urb
->dev
->speed
== USB_SPEED_LOW
||
3453 urb
->dev
->speed
== USB_SPEED_FULL
)
3454 urb
->start_frame
>>= 3;
3456 xhci_interval
= EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx
->ep_info
));
3457 ep_interval
= urb
->interval
;
3458 /* Convert to microframes */
3459 if (urb
->dev
->speed
== USB_SPEED_LOW
||
3460 urb
->dev
->speed
== USB_SPEED_FULL
)
3462 /* FIXME change this to a warning and a suggestion to use the new API
3463 * to set the polling interval (once the API is added).
3465 if (xhci_interval
!= ep_interval
) {
3466 if (printk_ratelimit())
3467 dev_dbg(&urb
->dev
->dev
, "Driver uses different interval"
3468 " (%d microframe%s) than xHCI "
3469 "(%d microframe%s)\n",
3471 ep_interval
== 1 ? "" : "s",
3473 xhci_interval
== 1 ? "" : "s");
3474 urb
->interval
= xhci_interval
;
3475 /* Convert back to frames for LS/FS devices */
3476 if (urb
->dev
->speed
== USB_SPEED_LOW
||
3477 urb
->dev
->speed
== USB_SPEED_FULL
)
3480 return xhci_queue_isoc_tx(xhci
, GFP_ATOMIC
, urb
, slot_id
, ep_index
);
3483 /**** Command Ring Operations ****/
3485 /* Generic function for queueing a command TRB on the command ring.
3486 * Check to make sure there's room on the command ring for one command TRB.
3487 * Also check that there's room reserved for commands that must not fail.
3488 * If this is a command that must not fail, meaning command_must_succeed = TRUE,
3489 * then only check for the number of reserved spots.
3490 * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
3491 * because the command event handler may want to resubmit a failed command.
3493 static int queue_command(struct xhci_hcd
*xhci
, u32 field1
, u32 field2
,
3494 u32 field3
, u32 field4
, bool command_must_succeed
)
3496 int reserved_trbs
= xhci
->cmd_ring_reserved_trbs
;
3499 if (!command_must_succeed
)
3502 ret
= prepare_ring(xhci
, xhci
->cmd_ring
, EP_STATE_RUNNING
,
3503 reserved_trbs
, false, GFP_ATOMIC
);
3505 xhci_err(xhci
, "ERR: No room for command on command ring\n");
3506 if (command_must_succeed
)
3507 xhci_err(xhci
, "ERR: Reserved TRB counting for "
3508 "unfailable commands failed.\n");
3511 queue_trb(xhci
, xhci
->cmd_ring
, false, false, false, field1
, field2
,
3512 field3
, field4
| xhci
->cmd_ring
->cycle_state
);
3516 /* Queue a slot enable or disable request on the command ring */
3517 int xhci_queue_slot_control(struct xhci_hcd
*xhci
, u32 trb_type
, u32 slot_id
)
3519 return queue_command(xhci
, 0, 0, 0,
3520 TRB_TYPE(trb_type
) | SLOT_ID_FOR_TRB(slot_id
), false);
3523 /* Queue an address device command TRB */
3524 int xhci_queue_address_device(struct xhci_hcd
*xhci
, dma_addr_t in_ctx_ptr
,
3527 return queue_command(xhci
, lower_32_bits(in_ctx_ptr
),
3528 upper_32_bits(in_ctx_ptr
), 0,
3529 TRB_TYPE(TRB_ADDR_DEV
) | SLOT_ID_FOR_TRB(slot_id
),
3533 int xhci_queue_vendor_command(struct xhci_hcd
*xhci
,
3534 u32 field1
, u32 field2
, u32 field3
, u32 field4
)
3536 return queue_command(xhci
, field1
, field2
, field3
, field4
, false);
3539 /* Queue a reset device command TRB */
3540 int xhci_queue_reset_device(struct xhci_hcd
*xhci
, u32 slot_id
)
3542 return queue_command(xhci
, 0, 0, 0,
3543 TRB_TYPE(TRB_RESET_DEV
) | SLOT_ID_FOR_TRB(slot_id
),
3547 /* Queue a configure endpoint command TRB */
3548 int xhci_queue_configure_endpoint(struct xhci_hcd
*xhci
, dma_addr_t in_ctx_ptr
,
3549 u32 slot_id
, bool command_must_succeed
)
3551 return queue_command(xhci
, lower_32_bits(in_ctx_ptr
),
3552 upper_32_bits(in_ctx_ptr
), 0,
3553 TRB_TYPE(TRB_CONFIG_EP
) | SLOT_ID_FOR_TRB(slot_id
),
3554 command_must_succeed
);
3557 /* Queue an evaluate context command TRB */
3558 int xhci_queue_evaluate_context(struct xhci_hcd
*xhci
, dma_addr_t in_ctx_ptr
,
3561 return queue_command(xhci
, lower_32_bits(in_ctx_ptr
),
3562 upper_32_bits(in_ctx_ptr
), 0,
3563 TRB_TYPE(TRB_EVAL_CONTEXT
) | SLOT_ID_FOR_TRB(slot_id
),
3568 * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop
3569 * activity on an endpoint that is about to be suspended.
3571 int xhci_queue_stop_endpoint(struct xhci_hcd
*xhci
, int slot_id
,
3572 unsigned int ep_index
, int suspend
)
3574 u32 trb_slot_id
= SLOT_ID_FOR_TRB(slot_id
);
3575 u32 trb_ep_index
= EP_ID_FOR_TRB(ep_index
);
3576 u32 type
= TRB_TYPE(TRB_STOP_RING
);
3577 u32 trb_suspend
= SUSPEND_PORT_FOR_TRB(suspend
);
3579 return queue_command(xhci
, 0, 0, 0,
3580 trb_slot_id
| trb_ep_index
| type
| trb_suspend
, false);
3583 /* Set Transfer Ring Dequeue Pointer command.
3584 * This should not be used for endpoints that have streams enabled.
3586 static int queue_set_tr_deq(struct xhci_hcd
*xhci
, int slot_id
,
3587 unsigned int ep_index
, unsigned int stream_id
,
3588 struct xhci_segment
*deq_seg
,
3589 union xhci_trb
*deq_ptr
, u32 cycle_state
)
3592 u32 trb_slot_id
= SLOT_ID_FOR_TRB(slot_id
);
3593 u32 trb_ep_index
= EP_ID_FOR_TRB(ep_index
);
3594 u32 trb_stream_id
= STREAM_ID_FOR_TRB(stream_id
);
3595 u32 type
= TRB_TYPE(TRB_SET_DEQ
);
3596 struct xhci_virt_ep
*ep
;
3598 addr
= xhci_trb_virt_to_dma(deq_seg
, deq_ptr
);
3600 xhci_warn(xhci
, "WARN Cannot submit Set TR Deq Ptr\n");
3601 xhci_warn(xhci
, "WARN deq seg = %p, deq pt = %p\n",
3605 ep
= &xhci
->devs
[slot_id
]->eps
[ep_index
];
3606 if ((ep
->ep_state
& SET_DEQ_PENDING
)) {
3607 xhci_warn(xhci
, "WARN Cannot submit Set TR Deq Ptr\n");
3608 xhci_warn(xhci
, "A Set TR Deq Ptr command is pending.\n");
3611 ep
->queued_deq_seg
= deq_seg
;
3612 ep
->queued_deq_ptr
= deq_ptr
;
3613 return queue_command(xhci
, lower_32_bits(addr
) | cycle_state
,
3614 upper_32_bits(addr
), trb_stream_id
,
3615 trb_slot_id
| trb_ep_index
| type
, false);
3618 int xhci_queue_reset_ep(struct xhci_hcd
*xhci
, int slot_id
,
3619 unsigned int ep_index
)
3621 u32 trb_slot_id
= SLOT_ID_FOR_TRB(slot_id
);
3622 u32 trb_ep_index
= EP_ID_FOR_TRB(ep_index
);
3623 u32 type
= TRB_TYPE(TRB_RESET_EP
);
3625 return queue_command(xhci
, 0, 0, 0, trb_slot_id
| trb_ep_index
| type
,