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drm/radeon/kms: add new pll algo for avivo asics
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / gpu / drm / radeon / radeon_display.c
blob1053d824b8a3299b32de13937ee25ff47a026a03
1 /*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26 #include "drmP.h"
27 #include "radeon_drm.h"
28 #include "radeon.h"
29
30 #include "atom.h"
31 #include <asm/div64.h>
32
33 #include "drm_crtc_helper.h"
34 #include "drm_edid.h"
35
36 static int radeon_ddc_dump(struct drm_connector *connector);
37
38 static void avivo_crtc_load_lut(struct drm_crtc *crtc)
39 {
40 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
41 struct drm_device *dev = crtc->dev;
42 struct radeon_device *rdev = dev->dev_private;
43 int i;
44
45 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
46 WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);
47
48 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
49 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
50 WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
51
52 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
53 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
54 WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
55
56 WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id);
57 WREG32(AVIVO_DC_LUT_RW_MODE, 0);
58 WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f);
59
60 WREG8(AVIVO_DC_LUT_RW_INDEX, 0);
61 for (i = 0; i < 256; i++) {
62 WREG32(AVIVO_DC_LUT_30_COLOR,
63 (radeon_crtc->lut_r[i] << 20) |
64 (radeon_crtc->lut_g[i] << 10) |
65 (radeon_crtc->lut_b[i] << 0));
66 }
67
68 WREG32(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id);
69 }
70
71 static void evergreen_crtc_load_lut(struct drm_crtc *crtc)
72 {
73 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
74 struct drm_device *dev = crtc->dev;
75 struct radeon_device *rdev = dev->dev_private;
76 int i;
77
78 DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
79 WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
80
81 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
82 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
83 WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
84
85 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
86 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
87 WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
88
89 WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
90 WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
91
92 WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
93 for (i = 0; i < 256; i++) {
94 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
95 (radeon_crtc->lut_r[i] << 20) |
96 (radeon_crtc->lut_g[i] << 10) |
97 (radeon_crtc->lut_b[i] << 0));
98 }
99 }
100
101 static void legacy_crtc_load_lut(struct drm_crtc *crtc)
102 {
103 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
104 struct drm_device *dev = crtc->dev;
105 struct radeon_device *rdev = dev->dev_private;
106 int i;
107 uint32_t dac2_cntl;
108
109 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
110 if (radeon_crtc->crtc_id == 0)
111 dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL;
112 else
113 dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL;
114 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
115
116 WREG8(RADEON_PALETTE_INDEX, 0);
117 for (i = 0; i < 256; i++) {
118 WREG32(RADEON_PALETTE_30_DATA,
119 (radeon_crtc->lut_r[i] << 20) |
120 (radeon_crtc->lut_g[i] << 10) |
121 (radeon_crtc->lut_b[i] << 0));
122 }
123 }
124
125 void radeon_crtc_load_lut(struct drm_crtc *crtc)
126 {
127 struct drm_device *dev = crtc->dev;
128 struct radeon_device *rdev = dev->dev_private;
129
130 if (!crtc->enabled)
131 return;
132
133 if (ASIC_IS_DCE4(rdev))
134 evergreen_crtc_load_lut(crtc);
135 else if (ASIC_IS_AVIVO(rdev))
136 avivo_crtc_load_lut(crtc);
137 else
138 legacy_crtc_load_lut(crtc);
139 }
140
141 /** Sets the color ramps on behalf of fbcon */
142 void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
143 u16 blue, int regno)
144 {
145 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
146
147 radeon_crtc->lut_r[regno] = red >> 6;
148 radeon_crtc->lut_g[regno] = green >> 6;
149 radeon_crtc->lut_b[regno] = blue >> 6;
150 }
151
152 /** Gets the color ramps on behalf of fbcon */
153 void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
154 u16 *blue, int regno)
155 {
156 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
157
158 *red = radeon_crtc->lut_r[regno] << 6;
159 *green = radeon_crtc->lut_g[regno] << 6;
160 *blue = radeon_crtc->lut_b[regno] << 6;
161 }
162
163 static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
164 u16 *blue, uint32_t start, uint32_t size)
165 {
166 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
167 int end = (start + size > 256) ? 256 : start + size, i;
168
169 /* userspace palettes are always correct as is */
170 for (i = start; i < end; i++) {
171 radeon_crtc->lut_r[i] = red[i] >> 6;
172 radeon_crtc->lut_g[i] = green[i] >> 6;
173 radeon_crtc->lut_b[i] = blue[i] >> 6;
174 }
175 radeon_crtc_load_lut(crtc);
176 }
177
178 static void radeon_crtc_destroy(struct drm_crtc *crtc)
179 {
180 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
181
182 drm_crtc_cleanup(crtc);
183 kfree(radeon_crtc);
184 }
185
186 static const struct drm_crtc_funcs radeon_crtc_funcs = {
187 .cursor_set = radeon_crtc_cursor_set,
188 .cursor_move = radeon_crtc_cursor_move,
189 .gamma_set = radeon_crtc_gamma_set,
190 .set_config = drm_crtc_helper_set_config,
191 .destroy = radeon_crtc_destroy,
192 };
193
194 static void radeon_crtc_init(struct drm_device *dev, int index)
195 {
196 struct radeon_device *rdev = dev->dev_private;
197 struct radeon_crtc *radeon_crtc;
198 int i;
199
200 radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
201 if (radeon_crtc == NULL)
202 return;
203
204 drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs);
205
206 drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256);
207 radeon_crtc->crtc_id = index;
208 rdev->mode_info.crtcs[index] = radeon_crtc;
209
210 #if 0
211 radeon_crtc->mode_set.crtc = &radeon_crtc->base;
212 radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1);
213 radeon_crtc->mode_set.num_connectors = 0;
214 #endif
215
216 for (i = 0; i < 256; i++) {
217 radeon_crtc->lut_r[i] = i << 2;
218 radeon_crtc->lut_g[i] = i << 2;
219 radeon_crtc->lut_b[i] = i << 2;
220 }
221
222 if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom))
223 radeon_atombios_init_crtc(dev, radeon_crtc);
224 else
225 radeon_legacy_init_crtc(dev, radeon_crtc);
226 }
227
228 static const char *encoder_names[34] = {
229 "NONE",
230 "INTERNAL_LVDS",
231 "INTERNAL_TMDS1",
232 "INTERNAL_TMDS2",
233 "INTERNAL_DAC1",
234 "INTERNAL_DAC2",
235 "INTERNAL_SDVOA",
236 "INTERNAL_SDVOB",
237 "SI170B",
238 "CH7303",
239 "CH7301",
240 "INTERNAL_DVO1",
241 "EXTERNAL_SDVOA",
242 "EXTERNAL_SDVOB",
243 "TITFP513",
244 "INTERNAL_LVTM1",
245 "VT1623",
246 "HDMI_SI1930",
247 "HDMI_INTERNAL",
248 "INTERNAL_KLDSCP_TMDS1",
249 "INTERNAL_KLDSCP_DVO1",
250 "INTERNAL_KLDSCP_DAC1",
251 "INTERNAL_KLDSCP_DAC2",
252 "SI178",
253 "MVPU_FPGA",
254 "INTERNAL_DDI",
255 "VT1625",
256 "HDMI_SI1932",
257 "DP_AN9801",
258 "DP_DP501",
259 "INTERNAL_UNIPHY",
260 "INTERNAL_KLDSCP_LVTMA",
261 "INTERNAL_UNIPHY1",
262 "INTERNAL_UNIPHY2",
263 };
264
265 static const char *connector_names[15] = {
266 "Unknown",
267 "VGA",
268 "DVI-I",
269 "DVI-D",
270 "DVI-A",
271 "Composite",
272 "S-video",
273 "LVDS",
274 "Component",
275 "DIN",
276 "DisplayPort",
277 "HDMI-A",
278 "HDMI-B",
279 "TV",
280 "eDP",
281 };
282
283 static const char *hpd_names[6] = {
284 "HPD1",
285 "HPD2",
286 "HPD3",
287 "HPD4",
288 "HPD5",
289 "HPD6",
290 };
291
292 static void radeon_print_display_setup(struct drm_device *dev)
293 {
294 struct drm_connector *connector;
295 struct radeon_connector *radeon_connector;
296 struct drm_encoder *encoder;
297 struct radeon_encoder *radeon_encoder;
298 uint32_t devices;
299 int i = 0;
300
301 DRM_INFO("Radeon Display Connectors\n");
302 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
303 radeon_connector = to_radeon_connector(connector);
304 DRM_INFO("Connector %d:\n", i);
305 DRM_INFO(" %s\n", connector_names[connector->connector_type]);
306 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
307 DRM_INFO(" %s\n", hpd_names[radeon_connector->hpd.hpd]);
308 if (radeon_connector->ddc_bus) {
309 DRM_INFO(" DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
310 radeon_connector->ddc_bus->rec.mask_clk_reg,
311 radeon_connector->ddc_bus->rec.mask_data_reg,
312 radeon_connector->ddc_bus->rec.a_clk_reg,
313 radeon_connector->ddc_bus->rec.a_data_reg,
314 radeon_connector->ddc_bus->rec.en_clk_reg,
315 radeon_connector->ddc_bus->rec.en_data_reg,
316 radeon_connector->ddc_bus->rec.y_clk_reg,
317 radeon_connector->ddc_bus->rec.y_data_reg);
318 if (radeon_connector->router.ddc_valid)
319 DRM_INFO(" DDC Router 0x%x/0x%x\n",
320 radeon_connector->router.ddc_mux_control_pin,
321 radeon_connector->router.ddc_mux_state);
322 if (radeon_connector->router.cd_valid)
323 DRM_INFO(" Clock/Data Router 0x%x/0x%x\n",
324 radeon_connector->router.cd_mux_control_pin,
325 radeon_connector->router.cd_mux_state);
326 } else {
327 if (connector->connector_type == DRM_MODE_CONNECTOR_VGA ||
328 connector->connector_type == DRM_MODE_CONNECTOR_DVII ||
329 connector->connector_type == DRM_MODE_CONNECTOR_DVID ||
330 connector->connector_type == DRM_MODE_CONNECTOR_DVIA ||
331 connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
332 connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
333 DRM_INFO(" DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");
334 }
335 DRM_INFO(" Encoders:\n");
336 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
337 radeon_encoder = to_radeon_encoder(encoder);
338 devices = radeon_encoder->devices & radeon_connector->devices;
339 if (devices) {
340 if (devices & ATOM_DEVICE_CRT1_SUPPORT)
341 DRM_INFO(" CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]);
342 if (devices & ATOM_DEVICE_CRT2_SUPPORT)
343 DRM_INFO(" CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]);
344 if (devices & ATOM_DEVICE_LCD1_SUPPORT)
345 DRM_INFO(" LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]);
346 if (devices & ATOM_DEVICE_DFP1_SUPPORT)
347 DRM_INFO(" DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]);
348 if (devices & ATOM_DEVICE_DFP2_SUPPORT)
349 DRM_INFO(" DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]);
350 if (devices & ATOM_DEVICE_DFP3_SUPPORT)
351 DRM_INFO(" DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]);
352 if (devices & ATOM_DEVICE_DFP4_SUPPORT)
353 DRM_INFO(" DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]);
354 if (devices & ATOM_DEVICE_DFP5_SUPPORT)
355 DRM_INFO(" DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]);
356 if (devices & ATOM_DEVICE_DFP6_SUPPORT)
357 DRM_INFO(" DFP6: %s\n", encoder_names[radeon_encoder->encoder_id]);
358 if (devices & ATOM_DEVICE_TV1_SUPPORT)
359 DRM_INFO(" TV1: %s\n", encoder_names[radeon_encoder->encoder_id]);
360 if (devices & ATOM_DEVICE_CV_SUPPORT)
361 DRM_INFO(" CV: %s\n", encoder_names[radeon_encoder->encoder_id]);
362 }
363 }
364 i++;
365 }
366 }
367
368 static bool radeon_setup_enc_conn(struct drm_device *dev)
369 {
370 struct radeon_device *rdev = dev->dev_private;
371 struct drm_connector *drm_connector;
372 bool ret = false;
373
374 if (rdev->bios) {
375 if (rdev->is_atom_bios) {
376 ret = radeon_get_atom_connector_info_from_supported_devices_table(dev);
377 if (ret == false)
378 ret = radeon_get_atom_connector_info_from_object_table(dev);
379 } else {
380 ret = radeon_get_legacy_connector_info_from_bios(dev);
381 if (ret == false)
382 ret = radeon_get_legacy_connector_info_from_table(dev);
383 }
384 } else {
385 if (!ASIC_IS_AVIVO(rdev))
386 ret = radeon_get_legacy_connector_info_from_table(dev);
387 }
388 if (ret) {
389 radeon_setup_encoder_clones(dev);
390 radeon_print_display_setup(dev);
391 list_for_each_entry(drm_connector, &dev->mode_config.connector_list, head)
392 radeon_ddc_dump(drm_connector);
393 }
394
395 return ret;
396 }
397
398 int radeon_ddc_get_modes(struct radeon_connector *radeon_connector)
399 {
400 struct drm_device *dev = radeon_connector->base.dev;
401 struct radeon_device *rdev = dev->dev_private;
402 int ret = 0;
403
404 /* on hw with routers, select right port */
405 if (radeon_connector->router.ddc_valid)
406 radeon_router_select_ddc_port(radeon_connector);
407
408 if ((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
409 (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)) {
410 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
411 if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT ||
412 dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) && dig->dp_i2c_bus)
413 radeon_connector->edid = drm_get_edid(&radeon_connector->base, &dig->dp_i2c_bus->adapter);
414 }
415 if (!radeon_connector->ddc_bus)
416 return -1;
417 if (!radeon_connector->edid) {
418 radeon_connector->edid = drm_get_edid(&radeon_connector->base, &radeon_connector->ddc_bus->adapter);
419 }
420 /* some servers provide a hardcoded edid in rom for KVMs */
421 if (!radeon_connector->edid)
422 radeon_connector->edid = radeon_combios_get_hardcoded_edid(rdev);
423 if (radeon_connector->edid) {
424 drm_mode_connector_update_edid_property(&radeon_connector->base, radeon_connector->edid);
425 ret = drm_add_edid_modes(&radeon_connector->base, radeon_connector->edid);
426 return ret;
427 }
428 drm_mode_connector_update_edid_property(&radeon_connector->base, NULL);
429 return 0;
430 }
431
432 static int radeon_ddc_dump(struct drm_connector *connector)
433 {
434 struct edid *edid;
435 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
436 int ret = 0;
437
438 /* on hw with routers, select right port */
439 if (radeon_connector->router.ddc_valid)
440 radeon_router_select_ddc_port(radeon_connector);
441
442 if (!radeon_connector->ddc_bus)
443 return -1;
444 edid = drm_get_edid(connector, &radeon_connector->ddc_bus->adapter);
445 if (edid) {
446 kfree(edid);
447 }
448 return ret;
449 }
450
451 /* avivo */
452 static void avivo_get_fb_div(struct radeon_pll *pll,
453 u32 target_clock,
454 u32 post_div,
455 u32 ref_div,
456 u32 *fb_div,
457 u32 *frac_fb_div)
458 {
459 u32 tmp = post_div * ref_div;
460
461 tmp *= target_clock;
462 *fb_div = tmp / pll->reference_freq;
463 *frac_fb_div = tmp % pll->reference_freq;
464 }
465
466 static u32 avivo_get_post_div(struct radeon_pll *pll,
467 u32 target_clock)
468 {
469 u32 vco, post_div, tmp;
470
471 if (pll->flags & RADEON_PLL_USE_POST_DIV)
472 return pll->post_div;
473
474 if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) {
475 if (pll->flags & RADEON_PLL_IS_LCD)
476 vco = pll->lcd_pll_out_min;
477 else
478 vco = pll->pll_out_min;
479 } else {
480 if (pll->flags & RADEON_PLL_IS_LCD)
481 vco = pll->lcd_pll_out_max;
482 else
483 vco = pll->pll_out_max;
484 }
485
486 post_div = vco / target_clock;
487 tmp = vco % target_clock;
488
489 if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) {
490 if (tmp)
491 post_div++;
492 } else {
493 if (!tmp)
494 post_div--;
495 }
496
497 return post_div;
498 }
499
500 #define MAX_TOLERANCE 10
501
502 void radeon_compute_pll_avivo(struct radeon_pll *pll,
503 u32 freq,
504 u32 *dot_clock_p,
505 u32 *fb_div_p,
506 u32 *frac_fb_div_p,
507 u32 *ref_div_p,
508 u32 *post_div_p)
509 {
510 u32 target_clock = freq / 10;
511 u32 post_div = avivo_get_post_div(pll, target_clock);
512 u32 ref_div = pll->min_ref_div;
513 u32 fb_div = 0, frac_fb_div = 0, tmp;
514
515 if (pll->flags & RADEON_PLL_USE_REF_DIV)
516 ref_div = pll->reference_div;
517
518 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
519 avivo_get_fb_div(pll, target_clock, post_div, ref_div, &fb_div, &frac_fb_div);
520 frac_fb_div = (100 * frac_fb_div) / pll->reference_freq;
521 if (frac_fb_div >= 5) {
522 frac_fb_div -= 5;
523 frac_fb_div = frac_fb_div / 10;
524 frac_fb_div++;
525 }
526 if (frac_fb_div >= 10) {
527 fb_div++;
528 frac_fb_div = 0;
529 }
530 } else {
531 while (ref_div <= pll->max_ref_div) {
532 avivo_get_fb_div(pll, target_clock, post_div, ref_div,
533 &fb_div, &frac_fb_div);
534 if (frac_fb_div >= (pll->reference_freq / 2))
535 fb_div++;
536 frac_fb_div = 0;
537 tmp = (pll->reference_freq * fb_div) / (post_div * ref_div);
538 tmp = (tmp * 10000) / target_clock;
539
540 if (tmp > (10000 + MAX_TOLERANCE))
541 ref_div++;
542 else if (tmp >= (10000 - MAX_TOLERANCE))
543 break;
544 else
545 ref_div++;
546 }
547 }
548
549 *dot_clock_p = ((pll->reference_freq * fb_div * 10) + (pll->reference_freq * frac_fb_div)) /
550 (ref_div * post_div * 10);
551 *fb_div_p = fb_div;
552 *frac_fb_div_p = frac_fb_div;
553 *ref_div_p = ref_div;
554 *post_div_p = post_div;
555 DRM_DEBUG_KMS("%d, pll dividers - fb: %d.%d ref: %d, post %d\n",
556 *dot_clock_p, fb_div, frac_fb_div, ref_div, post_div);
557 }
558
559 /* pre-avivo */
560 static inline uint32_t radeon_div(uint64_t n, uint32_t d)
561 {
562 uint64_t mod;
563
564 n += d / 2;
565
566 mod = do_div(n, d);
567 return n;
568 }
569
570 void radeon_compute_pll_legacy(struct radeon_pll *pll,
571 uint64_t freq,
572 uint32_t *dot_clock_p,
573 uint32_t *fb_div_p,
574 uint32_t *frac_fb_div_p,
575 uint32_t *ref_div_p,
576 uint32_t *post_div_p)
577 {
578 uint32_t min_ref_div = pll->min_ref_div;
579 uint32_t max_ref_div = pll->max_ref_div;
580 uint32_t min_post_div = pll->min_post_div;
581 uint32_t max_post_div = pll->max_post_div;
582 uint32_t min_fractional_feed_div = 0;
583 uint32_t max_fractional_feed_div = 0;
584 uint32_t best_vco = pll->best_vco;
585 uint32_t best_post_div = 1;
586 uint32_t best_ref_div = 1;
587 uint32_t best_feedback_div = 1;
588 uint32_t best_frac_feedback_div = 0;
589 uint32_t best_freq = -1;
590 uint32_t best_error = 0xffffffff;
591 uint32_t best_vco_diff = 1;
592 uint32_t post_div;
593 u32 pll_out_min, pll_out_max;
594
595 DRM_DEBUG_KMS("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div);
596 freq = freq * 1000;
597
598 if (pll->flags & RADEON_PLL_IS_LCD) {
599 pll_out_min = pll->lcd_pll_out_min;
600 pll_out_max = pll->lcd_pll_out_max;
601 } else {
602 pll_out_min = pll->pll_out_min;
603 pll_out_max = pll->pll_out_max;
604 }
605
606 if (pll->flags & RADEON_PLL_USE_REF_DIV)
607 min_ref_div = max_ref_div = pll->reference_div;
608 else {
609 while (min_ref_div < max_ref_div-1) {
610 uint32_t mid = (min_ref_div + max_ref_div) / 2;
611 uint32_t pll_in = pll->reference_freq / mid;
612 if (pll_in < pll->pll_in_min)
613 max_ref_div = mid;
614 else if (pll_in > pll->pll_in_max)
615 min_ref_div = mid;
616 else
617 break;
618 }
619 }
620
621 if (pll->flags & RADEON_PLL_USE_POST_DIV)
622 min_post_div = max_post_div = pll->post_div;
623
624 if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
625 min_fractional_feed_div = pll->min_frac_feedback_div;
626 max_fractional_feed_div = pll->max_frac_feedback_div;
627 }
628
629 for (post_div = min_post_div; post_div <= max_post_div; ++post_div) {
630 uint32_t ref_div;
631
632 if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
633 continue;
634
635 /* legacy radeons only have a few post_divs */
636 if (pll->flags & RADEON_PLL_LEGACY) {
637 if ((post_div == 5) ||
638 (post_div == 7) ||
639 (post_div == 9) ||
640 (post_div == 10) ||
641 (post_div == 11) ||
642 (post_div == 13) ||
643 (post_div == 14) ||
644 (post_div == 15))
645 continue;
646 }
647
648 for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) {
649 uint32_t feedback_div, current_freq = 0, error, vco_diff;
650 uint32_t pll_in = pll->reference_freq / ref_div;
651 uint32_t min_feed_div = pll->min_feedback_div;
652 uint32_t max_feed_div = pll->max_feedback_div + 1;
653
654 if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max)
655 continue;
656
657 while (min_feed_div < max_feed_div) {
658 uint32_t vco;
659 uint32_t min_frac_feed_div = min_fractional_feed_div;
660 uint32_t max_frac_feed_div = max_fractional_feed_div + 1;
661 uint32_t frac_feedback_div;
662 uint64_t tmp;
663
664 feedback_div = (min_feed_div + max_feed_div) / 2;
665
666 tmp = (uint64_t)pll->reference_freq * feedback_div;
667 vco = radeon_div(tmp, ref_div);
668
669 if (vco < pll_out_min) {
670 min_feed_div = feedback_div + 1;
671 continue;
672 } else if (vco > pll_out_max) {
673 max_feed_div = feedback_div;
674 continue;
675 }
676
677 while (min_frac_feed_div < max_frac_feed_div) {
678 frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2;
679 tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div;
680 tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div;
681 current_freq = radeon_div(tmp, ref_div * post_div);
682
683 if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) {
684 if (freq < current_freq)
685 error = 0xffffffff;
686 else
687 error = freq - current_freq;
688 } else
689 error = abs(current_freq - freq);
690 vco_diff = abs(vco - best_vco);
691
692 if ((best_vco == 0 && error < best_error) ||
693 (best_vco != 0 &&
694 ((best_error > 100 && error < best_error - 100) ||
695 (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) {
696 best_post_div = post_div;
697 best_ref_div = ref_div;
698 best_feedback_div = feedback_div;
699 best_frac_feedback_div = frac_feedback_div;
700 best_freq = current_freq;
701 best_error = error;
702 best_vco_diff = vco_diff;
703 } else if (current_freq == freq) {
704 if (best_freq == -1) {
705 best_post_div = post_div;
706 best_ref_div = ref_div;
707 best_feedback_div = feedback_div;
708 best_frac_feedback_div = frac_feedback_div;
709 best_freq = current_freq;
710 best_error = error;
711 best_vco_diff = vco_diff;
712 } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) ||
713 ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) ||
714 ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) ||
715 ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) ||
716 ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) ||
717 ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) {
718 best_post_div = post_div;
719 best_ref_div = ref_div;
720 best_feedback_div = feedback_div;
721 best_frac_feedback_div = frac_feedback_div;
722 best_freq = current_freq;
723 best_error = error;
724 best_vco_diff = vco_diff;
725 }
726 }
727 if (current_freq < freq)
728 min_frac_feed_div = frac_feedback_div + 1;
729 else
730 max_frac_feed_div = frac_feedback_div;
731 }
732 if (current_freq < freq)
733 min_feed_div = feedback_div + 1;
734 else
735 max_feed_div = feedback_div;
736 }
737 }
738 }
739
740 *dot_clock_p = best_freq / 10000;
741 *fb_div_p = best_feedback_div;
742 *frac_fb_div_p = best_frac_feedback_div;
743 *ref_div_p = best_ref_div;
744 *post_div_p = best_post_div;
745 DRM_DEBUG_KMS("%d %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
746 freq, best_freq / 1000, best_feedback_div, best_frac_feedback_div,
747 best_ref_div, best_post_div);
748
749 }
750
751 static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb)
752 {
753 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
754
755 if (radeon_fb->obj) {
756 drm_gem_object_unreference_unlocked(radeon_fb->obj);
757 }
758 drm_framebuffer_cleanup(fb);
759 kfree(radeon_fb);
760 }
761
762 static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb,
763 struct drm_file *file_priv,
764 unsigned int *handle)
765 {
766 struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
767
768 return drm_gem_handle_create(file_priv, radeon_fb->obj, handle);
769 }
770
771 static const struct drm_framebuffer_funcs radeon_fb_funcs = {
772 .destroy = radeon_user_framebuffer_destroy,
773 .create_handle = radeon_user_framebuffer_create_handle,
774 };
775
776 void
777 radeon_framebuffer_init(struct drm_device *dev,
778 struct radeon_framebuffer *rfb,
779 struct drm_mode_fb_cmd *mode_cmd,
780 struct drm_gem_object *obj)
781 {
782 rfb->obj = obj;
783 drm_framebuffer_init(dev, &rfb->base, &radeon_fb_funcs);
784 drm_helper_mode_fill_fb_struct(&rfb->base, mode_cmd);
785 }
786
787 static struct drm_framebuffer *
788 radeon_user_framebuffer_create(struct drm_device *dev,
789 struct drm_file *file_priv,
790 struct drm_mode_fb_cmd *mode_cmd)
791 {
792 struct drm_gem_object *obj;
793 struct radeon_framebuffer *radeon_fb;
794
795 obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handle);
796 if (obj == NULL) {
797 dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, "
798 "can't create framebuffer\n", mode_cmd->handle);
799 return ERR_PTR(-ENOENT);
800 }
801
802 radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL);
803 if (radeon_fb == NULL)
804 return ERR_PTR(-ENOMEM);
805
806 radeon_framebuffer_init(dev, radeon_fb, mode_cmd, obj);
807
808 return &radeon_fb->base;
809 }
810
811 static void radeon_output_poll_changed(struct drm_device *dev)
812 {
813 struct radeon_device *rdev = dev->dev_private;
814 radeon_fb_output_poll_changed(rdev);
815 }
816
817 static const struct drm_mode_config_funcs radeon_mode_funcs = {
818 .fb_create = radeon_user_framebuffer_create,
819 .output_poll_changed = radeon_output_poll_changed
820 };
821
822 struct drm_prop_enum_list {
823 int type;
824 char *name;
825 };
826
827 static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] =
828 { { 0, "driver" },
829 { 1, "bios" },
830 };
831
832 static struct drm_prop_enum_list radeon_tv_std_enum_list[] =
833 { { TV_STD_NTSC, "ntsc" },
834 { TV_STD_PAL, "pal" },
835 { TV_STD_PAL_M, "pal-m" },
836 { TV_STD_PAL_60, "pal-60" },
837 { TV_STD_NTSC_J, "ntsc-j" },
838 { TV_STD_SCART_PAL, "scart-pal" },
839 { TV_STD_PAL_CN, "pal-cn" },
840 { TV_STD_SECAM, "secam" },
841 };
842
843 static struct drm_prop_enum_list radeon_underscan_enum_list[] =
844 { { UNDERSCAN_OFF, "off" },
845 { UNDERSCAN_ON, "on" },
846 { UNDERSCAN_AUTO, "auto" },
847 };
848
849 static int radeon_modeset_create_props(struct radeon_device *rdev)
850 {
851 int i, sz;
852
853 if (rdev->is_atom_bios) {
854 rdev->mode_info.coherent_mode_property =
855 drm_property_create(rdev->ddev,
856 DRM_MODE_PROP_RANGE,
857 "coherent", 2);
858 if (!rdev->mode_info.coherent_mode_property)
859 return -ENOMEM;
860
861 rdev->mode_info.coherent_mode_property->values[0] = 0;
862 rdev->mode_info.coherent_mode_property->values[1] = 1;
863 }
864
865 if (!ASIC_IS_AVIVO(rdev)) {
866 sz = ARRAY_SIZE(radeon_tmds_pll_enum_list);
867 rdev->mode_info.tmds_pll_property =
868 drm_property_create(rdev->ddev,
869 DRM_MODE_PROP_ENUM,
870 "tmds_pll", sz);
871 for (i = 0; i < sz; i++) {
872 drm_property_add_enum(rdev->mode_info.tmds_pll_property,
873 i,
874 radeon_tmds_pll_enum_list[i].type,
875 radeon_tmds_pll_enum_list[i].name);
876 }
877 }
878
879 rdev->mode_info.load_detect_property =
880 drm_property_create(rdev->ddev,
881 DRM_MODE_PROP_RANGE,
882 "load detection", 2);
883 if (!rdev->mode_info.load_detect_property)
884 return -ENOMEM;
885 rdev->mode_info.load_detect_property->values[0] = 0;
886 rdev->mode_info.load_detect_property->values[1] = 1;
887
888 drm_mode_create_scaling_mode_property(rdev->ddev);
889
890 sz = ARRAY_SIZE(radeon_tv_std_enum_list);
891 rdev->mode_info.tv_std_property =
892 drm_property_create(rdev->ddev,
893 DRM_MODE_PROP_ENUM,
894 "tv standard", sz);
895 for (i = 0; i < sz; i++) {
896 drm_property_add_enum(rdev->mode_info.tv_std_property,
897 i,
898 radeon_tv_std_enum_list[i].type,
899 radeon_tv_std_enum_list[i].name);
900 }
901
902 sz = ARRAY_SIZE(radeon_underscan_enum_list);
903 rdev->mode_info.underscan_property =
904 drm_property_create(rdev->ddev,
905 DRM_MODE_PROP_ENUM,
906 "underscan", sz);
907 for (i = 0; i < sz; i++) {
908 drm_property_add_enum(rdev->mode_info.underscan_property,
909 i,
910 radeon_underscan_enum_list[i].type,
911 radeon_underscan_enum_list[i].name);
912 }
913
914 rdev->mode_info.underscan_hborder_property =
915 drm_property_create(rdev->ddev,
916 DRM_MODE_PROP_RANGE,
917 "underscan hborder", 2);
918 if (!rdev->mode_info.underscan_hborder_property)
919 return -ENOMEM;
920 rdev->mode_info.underscan_hborder_property->values[0] = 0;
921 rdev->mode_info.underscan_hborder_property->values[1] = 128;
922
923 rdev->mode_info.underscan_vborder_property =
924 drm_property_create(rdev->ddev,
925 DRM_MODE_PROP_RANGE,
926 "underscan vborder", 2);
927 if (!rdev->mode_info.underscan_vborder_property)
928 return -ENOMEM;
929 rdev->mode_info.underscan_vborder_property->values[0] = 0;
930 rdev->mode_info.underscan_vborder_property->values[1] = 128;
931
932 return 0;
933 }
934
935 void radeon_update_display_priority(struct radeon_device *rdev)
936 {
937 /* adjustment options for the display watermarks */
938 if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) {
939 /* set display priority to high for r3xx, rv515 chips
940 * this avoids flickering due to underflow to the
941 * display controllers during heavy acceleration.
942 * Don't force high on rs4xx igp chips as it seems to
943 * affect the sound card. See kernel bug 15982.
944 */
945 if ((ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) &&
946 !(rdev->flags & RADEON_IS_IGP))
947 rdev->disp_priority = 2;
948 else
949 rdev->disp_priority = 0;
950 } else
951 rdev->disp_priority = radeon_disp_priority;
952
953 }
954
955 int radeon_modeset_init(struct radeon_device *rdev)
956 {
957 int i;
958 int ret;
959
960 drm_mode_config_init(rdev->ddev);
961 rdev->mode_info.mode_config_initialized = true;
962
963 rdev->ddev->mode_config.funcs = (void *)&radeon_mode_funcs;
964
965 if (ASIC_IS_AVIVO(rdev)) {
966 rdev->ddev->mode_config.max_width = 8192;
967 rdev->ddev->mode_config.max_height = 8192;
968 } else {
969 rdev->ddev->mode_config.max_width = 4096;
970 rdev->ddev->mode_config.max_height = 4096;
971 }
972
973 rdev->ddev->mode_config.fb_base = rdev->mc.aper_base;
974
975 ret = radeon_modeset_create_props(rdev);
976 if (ret) {
977 return ret;
978 }
979
980 /* init i2c buses */
981 radeon_i2c_init(rdev);
982
983 /* check combios for a valid hardcoded EDID - Sun servers */
984 if (!rdev->is_atom_bios) {
985 /* check for hardcoded EDID in BIOS */
986 radeon_combios_check_hardcoded_edid(rdev);
987 }
988
989 /* allocate crtcs */
990 for (i = 0; i < rdev->num_crtc; i++) {
991 radeon_crtc_init(rdev->ddev, i);
992 }
993
994 /* okay we should have all the bios connectors */
995 ret = radeon_setup_enc_conn(rdev->ddev);
996 if (!ret) {
997 return ret;
998 }
999 /* initialize hpd */
1000 radeon_hpd_init(rdev);
1001
1002 /* Initialize power management */
1003 radeon_pm_init(rdev);
1004
1005 radeon_fbdev_init(rdev);
1006 drm_kms_helper_poll_init(rdev->ddev);
1007
1008 return 0;
1009 }
1010
1011 void radeon_modeset_fini(struct radeon_device *rdev)
1012 {
1013 radeon_fbdev_fini(rdev);
1014 kfree(rdev->mode_info.bios_hardcoded_edid);
1015 radeon_pm_fini(rdev);
1016
1017 if (rdev->mode_info.mode_config_initialized) {
1018 drm_kms_helper_poll_fini(rdev->ddev);
1019 radeon_hpd_fini(rdev);
1020 drm_mode_config_cleanup(rdev->ddev);
1021 rdev->mode_info.mode_config_initialized = false;
1022 }
1023 /* free i2c buses */
1024 radeon_i2c_fini(rdev);
1025 }
1026
1027 static bool is_hdtv_mode(struct drm_display_mode *mode)
1028 {
1029 /* try and guess if this is a tv or a monitor */
1030 if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */
1031 (mode->vdisplay == 576) || /* 576p */
1032 (mode->vdisplay == 720) || /* 720p */
1033 (mode->vdisplay == 1080)) /* 1080p */
1034 return true;
1035 else
1036 return false;
1037 }
1038
1039 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
1040 struct drm_display_mode *mode,
1041 struct drm_display_mode *adjusted_mode)
1042 {
1043 struct drm_device *dev = crtc->dev;
1044 struct radeon_device *rdev = dev->dev_private;
1045 struct drm_encoder *encoder;
1046 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1047 struct radeon_encoder *radeon_encoder;
1048 struct drm_connector *connector;
1049 struct radeon_connector *radeon_connector;
1050 bool first = true;
1051 u32 src_v = 1, dst_v = 1;
1052 u32 src_h = 1, dst_h = 1;
1053
1054 radeon_crtc->h_border = 0;
1055 radeon_crtc->v_border = 0;
1056
1057 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1058 if (encoder->crtc != crtc)
1059 continue;
1060 radeon_encoder = to_radeon_encoder(encoder);
1061 connector = radeon_get_connector_for_encoder(encoder);
1062 radeon_connector = to_radeon_connector(connector);
1063
1064 if (first) {
1065 /* set scaling */
1066 if (radeon_encoder->rmx_type == RMX_OFF)
1067 radeon_crtc->rmx_type = RMX_OFF;
1068 else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay ||
1069 mode->vdisplay < radeon_encoder->native_mode.vdisplay)
1070 radeon_crtc->rmx_type = radeon_encoder->rmx_type;
1071 else
1072 radeon_crtc->rmx_type = RMX_OFF;
1073 /* copy native mode */
1074 memcpy(&radeon_crtc->native_mode,
1075 &radeon_encoder->native_mode,
1076 sizeof(struct drm_display_mode));
1077 src_v = crtc->mode.vdisplay;
1078 dst_v = radeon_crtc->native_mode.vdisplay;
1079 src_h = crtc->mode.hdisplay;
1080 dst_h = radeon_crtc->native_mode.hdisplay;
1081
1082 /* fix up for overscan on hdmi */
1083 if (ASIC_IS_AVIVO(rdev) &&
1084 (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) &&
1085 ((radeon_encoder->underscan_type == UNDERSCAN_ON) ||
1086 ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) &&
1087 drm_detect_hdmi_monitor(radeon_connector->edid) &&
1088 is_hdtv_mode(mode)))) {
1089 if (radeon_encoder->underscan_hborder != 0)
1090 radeon_crtc->h_border = radeon_encoder->underscan_hborder;
1091 else
1092 radeon_crtc->h_border = (mode->hdisplay >> 5) + 16;
1093 if (radeon_encoder->underscan_vborder != 0)
1094 radeon_crtc->v_border = radeon_encoder->underscan_vborder;
1095 else
1096 radeon_crtc->v_border = (mode->vdisplay >> 5) + 16;
1097 radeon_crtc->rmx_type = RMX_FULL;
1098 src_v = crtc->mode.vdisplay;
1099 dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2);
1100 src_h = crtc->mode.hdisplay;
1101 dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2);
1102 }
1103 first = false;
1104 } else {
1105 if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) {
1106 /* WARNING: Right now this can't happen but
1107 * in the future we need to check that scaling
1108 * are consistent across different encoder
1109 * (ie all encoder can work with the same
1110 * scaling).
1111 */
1112 DRM_ERROR("Scaling not consistent across encoder.\n");
1113 return false;
1114 }
1115 }
1116 }
1117 if (radeon_crtc->rmx_type != RMX_OFF) {
1118 fixed20_12 a, b;
1119 a.full = dfixed_const(src_v);
1120 b.full = dfixed_const(dst_v);
1121 radeon_crtc->vsc.full = dfixed_div(a, b);
1122 a.full = dfixed_const(src_h);
1123 b.full = dfixed_const(dst_h);
1124 radeon_crtc->hsc.full = dfixed_div(a, b);
1125 } else {
1126 radeon_crtc->vsc.full = dfixed_const(1);
1127 radeon_crtc->hsc.full = dfixed_const(1);
1128 }
1129 return true;
1130 }
1131
1132 /*
1133 * Retrieve current video scanout position of crtc on a given gpu.
1134 *
1135 * \param rdev Device to query.
1136 * \param crtc Crtc to query.
1137 * \param *vpos Location where vertical scanout position should be stored.
1138 * \param *hpos Location where horizontal scanout position should go.
1139 *
1140 * Returns vpos as a positive number while in active scanout area.
1141 * Returns vpos as a negative number inside vblank, counting the number
1142 * of scanlines to go until end of vblank, e.g., -1 means "one scanline
1143 * until start of active scanout / end of vblank."
1144 *
1145 * \return Flags, or'ed together as follows:
1146 *
1147 * RADEON_SCANOUTPOS_VALID = Query successfull.
1148 * RADEON_SCANOUTPOS_INVBL = Inside vblank.
1149 * RADEON_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of
1150 * this flag means that returned position may be offset by a constant but
1151 * unknown small number of scanlines wrt. real scanout position.
1152 *
1153 */
1154 int radeon_get_crtc_scanoutpos(struct radeon_device *rdev, int crtc, int *vpos, int *hpos)
1155 {
1156 u32 stat_crtc = 0, vbl = 0, position = 0;
1157 int vbl_start, vbl_end, vtotal, ret = 0;
1158 bool in_vbl = true;
1159
1160 if (ASIC_IS_DCE4(rdev)) {
1161 if (crtc == 0) {
1162 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1163 EVERGREEN_CRTC0_REGISTER_OFFSET);
1164 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1165 EVERGREEN_CRTC0_REGISTER_OFFSET);
1166 ret |= RADEON_SCANOUTPOS_VALID;
1167 }
1168 if (crtc == 1) {
1169 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1170 EVERGREEN_CRTC1_REGISTER_OFFSET);
1171 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1172 EVERGREEN_CRTC1_REGISTER_OFFSET);
1173 ret |= RADEON_SCANOUTPOS_VALID;
1174 }
1175 if (crtc == 2) {
1176 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1177 EVERGREEN_CRTC2_REGISTER_OFFSET);
1178 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1179 EVERGREEN_CRTC2_REGISTER_OFFSET);
1180 ret |= RADEON_SCANOUTPOS_VALID;
1181 }
1182 if (crtc == 3) {
1183 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1184 EVERGREEN_CRTC3_REGISTER_OFFSET);
1185 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1186 EVERGREEN_CRTC3_REGISTER_OFFSET);
1187 ret |= RADEON_SCANOUTPOS_VALID;
1188 }
1189 if (crtc == 4) {
1190 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1191 EVERGREEN_CRTC4_REGISTER_OFFSET);
1192 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1193 EVERGREEN_CRTC4_REGISTER_OFFSET);
1194 ret |= RADEON_SCANOUTPOS_VALID;
1195 }
1196 if (crtc == 5) {
1197 vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1198 EVERGREEN_CRTC5_REGISTER_OFFSET);
1199 position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1200 EVERGREEN_CRTC5_REGISTER_OFFSET);
1201 ret |= RADEON_SCANOUTPOS_VALID;
1202 }
1203 } else if (ASIC_IS_AVIVO(rdev)) {
1204 if (crtc == 0) {
1205 vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END);
1206 position = RREG32(AVIVO_D1CRTC_STATUS_POSITION);
1207 ret |= RADEON_SCANOUTPOS_VALID;
1208 }
1209 if (crtc == 1) {
1210 vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END);
1211 position = RREG32(AVIVO_D2CRTC_STATUS_POSITION);
1212 ret |= RADEON_SCANOUTPOS_VALID;
1213 }
1214 } else {
1215 /* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */
1216 if (crtc == 0) {
1217 /* Assume vbl_end == 0, get vbl_start from
1218 * upper 16 bits.
1219 */
1220 vbl = (RREG32(RADEON_CRTC_V_TOTAL_DISP) &
1221 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1222 /* Only retrieve vpos from upper 16 bits, set hpos == 0. */
1223 position = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1224 stat_crtc = RREG32(RADEON_CRTC_STATUS);
1225 if (!(stat_crtc & 1))
1226 in_vbl = false;
1227
1228 ret |= RADEON_SCANOUTPOS_VALID;
1229 }
1230 if (crtc == 1) {
1231 vbl = (RREG32(RADEON_CRTC2_V_TOTAL_DISP) &
1232 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1233 position = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1234 stat_crtc = RREG32(RADEON_CRTC2_STATUS);
1235 if (!(stat_crtc & 1))
1236 in_vbl = false;
1237
1238 ret |= RADEON_SCANOUTPOS_VALID;
1239 }
1240 }
1241
1242 /* Decode into vertical and horizontal scanout position. */
1243 *vpos = position & 0x1fff;
1244 *hpos = (position >> 16) & 0x1fff;
1245
1246 /* Valid vblank area boundaries from gpu retrieved? */
1247 if (vbl > 0) {
1248 /* Yes: Decode. */
1249 ret |= RADEON_SCANOUTPOS_ACCURATE;
1250 vbl_start = vbl & 0x1fff;
1251 vbl_end = (vbl >> 16) & 0x1fff;
1252 }
1253 else {
1254 /* No: Fake something reasonable which gives at least ok results. */
1255 vbl_start = rdev->mode_info.crtcs[crtc]->base.mode.crtc_vdisplay;
1256 vbl_end = 0;
1257 }
1258
1259 /* Test scanout position against vblank region. */
1260 if ((*vpos < vbl_start) && (*vpos >= vbl_end))
1261 in_vbl = false;
1262
1263 /* Check if inside vblank area and apply corrective offsets:
1264 * vpos will then be >=0 in video scanout area, but negative
1265 * within vblank area, counting down the number of lines until
1266 * start of scanout.
1267 */
1268
1269 /* Inside "upper part" of vblank area? Apply corrective offset if so: */
1270 if (in_vbl && (*vpos >= vbl_start)) {
1271 vtotal = rdev->mode_info.crtcs[crtc]->base.mode.crtc_vtotal;
1272 *vpos = *vpos - vtotal;
1273 }
1274
1275 /* Correct for shifted end of vbl at vbl_end. */
1276 *vpos = *vpos - vbl_end;
1277
1278 /* In vblank? */
1279 if (in_vbl)
1280 ret |= RADEON_SCANOUTPOS_INVBL;
1281
1282 return ret;
1283 }
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree