iwlwifi: fix possible data overwrite in hcmd callback
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / wireless / iwlwifi / iwl-tx.c
blob52b1b66f32d0c026e6fe84d1d606d76e7ed8b995
1 /******************************************************************************
3 * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
28 *****************************************************************************/
30 #include <linux/etherdevice.h>
31 #include <linux/sched.h>
32 #include <linux/slab.h>
33 #include <net/mac80211.h>
34 #include "iwl-eeprom.h"
35 #include "iwl-dev.h"
36 #include "iwl-core.h"
37 #include "iwl-sta.h"
38 #include "iwl-io.h"
39 #include "iwl-helpers.h"
41 /**
42 * iwl_txq_update_write_ptr - Send new write index to hardware
44 void iwl_txq_update_write_ptr(struct iwl_priv *priv, struct iwl_tx_queue *txq)
46 u32 reg = 0;
47 int txq_id = txq->q.id;
49 if (txq->need_update == 0)
50 return;
52 if (priv->cfg->base_params->shadow_reg_enable) {
53 /* shadow register enabled */
54 iwl_write32(priv, HBUS_TARG_WRPTR,
55 txq->q.write_ptr | (txq_id << 8));
56 } else {
57 /* if we're trying to save power */
58 if (test_bit(STATUS_POWER_PMI, &priv->status)) {
59 /* wake up nic if it's powered down ...
60 * uCode will wake up, and interrupt us again, so next
61 * time we'll skip this part. */
62 reg = iwl_read32(priv, CSR_UCODE_DRV_GP1);
64 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
65 IWL_DEBUG_INFO(priv,
66 "Tx queue %d requesting wakeup,"
67 " GP1 = 0x%x\n", txq_id, reg);
68 iwl_set_bit(priv, CSR_GP_CNTRL,
69 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
70 return;
73 iwl_write_direct32(priv, HBUS_TARG_WRPTR,
74 txq->q.write_ptr | (txq_id << 8));
77 * else not in power-save mode,
78 * uCode will never sleep when we're
79 * trying to tx (during RFKILL, we're not trying to tx).
81 } else
82 iwl_write32(priv, HBUS_TARG_WRPTR,
83 txq->q.write_ptr | (txq_id << 8));
85 txq->need_update = 0;
88 /**
89 * iwl_tx_queue_unmap - Unmap any remaining DMA mappings and free skb's
91 void iwl_tx_queue_unmap(struct iwl_priv *priv, int txq_id)
93 struct iwl_tx_queue *txq = &priv->txq[txq_id];
94 struct iwl_queue *q = &txq->q;
96 if (q->n_bd == 0)
97 return;
99 while (q->write_ptr != q->read_ptr) {
100 priv->cfg->ops->lib->txq_free_tfd(priv, txq);
101 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd);
106 * iwl_tx_queue_free - Deallocate DMA queue.
107 * @txq: Transmit queue to deallocate.
109 * Empty queue by removing and destroying all BD's.
110 * Free all buffers.
111 * 0-fill, but do not free "txq" descriptor structure.
113 void iwl_tx_queue_free(struct iwl_priv *priv, int txq_id)
115 struct iwl_tx_queue *txq = &priv->txq[txq_id];
116 struct device *dev = &priv->pci_dev->dev;
117 int i;
119 iwl_tx_queue_unmap(priv, txq_id);
121 /* De-alloc array of command/tx buffers */
122 for (i = 0; i < TFD_TX_CMD_SLOTS; i++)
123 kfree(txq->cmd[i]);
125 /* De-alloc circular buffer of TFDs */
126 if (txq->q.n_bd)
127 dma_free_coherent(dev, priv->hw_params.tfd_size *
128 txq->q.n_bd, txq->tfds, txq->q.dma_addr);
130 /* De-alloc array of per-TFD driver data */
131 kfree(txq->txb);
132 txq->txb = NULL;
134 /* deallocate arrays */
135 kfree(txq->cmd);
136 kfree(txq->meta);
137 txq->cmd = NULL;
138 txq->meta = NULL;
140 /* 0-fill queue descriptor structure */
141 memset(txq, 0, sizeof(*txq));
145 * iwl_cmd_queue_unmap - Unmap any remaining DMA mappings from command queue
147 void iwl_cmd_queue_unmap(struct iwl_priv *priv)
149 struct iwl_tx_queue *txq = &priv->txq[priv->cmd_queue];
150 struct iwl_queue *q = &txq->q;
151 int i;
153 if (q->n_bd == 0)
154 return;
156 while (q->read_ptr != q->write_ptr) {
157 i = get_cmd_index(q, q->read_ptr, 0);
159 if (txq->meta[i].flags & CMD_MAPPED) {
160 pci_unmap_single(priv->pci_dev,
161 dma_unmap_addr(&txq->meta[i], mapping),
162 dma_unmap_len(&txq->meta[i], len),
163 PCI_DMA_BIDIRECTIONAL);
164 txq->meta[i].flags = 0;
167 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd);
170 i = q->n_window;
171 if (txq->meta[i].flags & CMD_MAPPED) {
172 pci_unmap_single(priv->pci_dev,
173 dma_unmap_addr(&txq->meta[i], mapping),
174 dma_unmap_len(&txq->meta[i], len),
175 PCI_DMA_BIDIRECTIONAL);
176 txq->meta[i].flags = 0;
181 * iwl_cmd_queue_free - Deallocate DMA queue.
182 * @txq: Transmit queue to deallocate.
184 * Empty queue by removing and destroying all BD's.
185 * Free all buffers.
186 * 0-fill, but do not free "txq" descriptor structure.
188 void iwl_cmd_queue_free(struct iwl_priv *priv)
190 struct iwl_tx_queue *txq = &priv->txq[priv->cmd_queue];
191 struct device *dev = &priv->pci_dev->dev;
192 int i;
194 iwl_cmd_queue_unmap(priv);
196 /* De-alloc array of command/tx buffers */
197 for (i = 0; i <= TFD_CMD_SLOTS; i++)
198 kfree(txq->cmd[i]);
200 /* De-alloc circular buffer of TFDs */
201 if (txq->q.n_bd)
202 dma_free_coherent(dev, priv->hw_params.tfd_size * txq->q.n_bd,
203 txq->tfds, txq->q.dma_addr);
205 /* deallocate arrays */
206 kfree(txq->cmd);
207 kfree(txq->meta);
208 txq->cmd = NULL;
209 txq->meta = NULL;
211 /* 0-fill queue descriptor structure */
212 memset(txq, 0, sizeof(*txq));
215 /*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
216 * DMA services
218 * Theory of operation
220 * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
221 * of buffer descriptors, each of which points to one or more data buffers for
222 * the device to read from or fill. Driver and device exchange status of each
223 * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
224 * entries in each circular buffer, to protect against confusing empty and full
225 * queue states.
227 * The device reads or writes the data in the queues via the device's several
228 * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
230 * For Tx queue, there are low mark and high mark limits. If, after queuing
231 * the packet for Tx, free space become < low mark, Tx queue stopped. When
232 * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
233 * Tx queue resumed.
235 ***************************************************/
237 int iwl_queue_space(const struct iwl_queue *q)
239 int s = q->read_ptr - q->write_ptr;
241 if (q->read_ptr > q->write_ptr)
242 s -= q->n_bd;
244 if (s <= 0)
245 s += q->n_window;
246 /* keep some reserve to not confuse empty and full situations */
247 s -= 2;
248 if (s < 0)
249 s = 0;
250 return s;
255 * iwl_queue_init - Initialize queue's high/low-water and read/write indexes
257 static int iwl_queue_init(struct iwl_priv *priv, struct iwl_queue *q,
258 int count, int slots_num, u32 id)
260 q->n_bd = count;
261 q->n_window = slots_num;
262 q->id = id;
264 /* count must be power-of-two size, otherwise iwl_queue_inc_wrap
265 * and iwl_queue_dec_wrap are broken. */
266 if (WARN_ON(!is_power_of_2(count)))
267 return -EINVAL;
269 /* slots_num must be power-of-two size, otherwise
270 * get_cmd_index is broken. */
271 if (WARN_ON(!is_power_of_2(slots_num)))
272 return -EINVAL;
274 q->low_mark = q->n_window / 4;
275 if (q->low_mark < 4)
276 q->low_mark = 4;
278 q->high_mark = q->n_window / 8;
279 if (q->high_mark < 2)
280 q->high_mark = 2;
282 q->write_ptr = q->read_ptr = 0;
284 return 0;
288 * iwl_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue
290 static int iwl_tx_queue_alloc(struct iwl_priv *priv,
291 struct iwl_tx_queue *txq, u32 id)
293 struct device *dev = &priv->pci_dev->dev;
294 size_t tfd_sz = priv->hw_params.tfd_size * TFD_QUEUE_SIZE_MAX;
296 /* Driver private data, only for Tx (not command) queues,
297 * not shared with device. */
298 if (id != priv->cmd_queue) {
299 txq->txb = kzalloc(sizeof(txq->txb[0]) *
300 TFD_QUEUE_SIZE_MAX, GFP_KERNEL);
301 if (!txq->txb) {
302 IWL_ERR(priv, "kmalloc for auxiliary BD "
303 "structures failed\n");
304 goto error;
306 } else {
307 txq->txb = NULL;
310 /* Circular buffer of transmit frame descriptors (TFDs),
311 * shared with device */
312 txq->tfds = dma_alloc_coherent(dev, tfd_sz, &txq->q.dma_addr,
313 GFP_KERNEL);
314 if (!txq->tfds) {
315 IWL_ERR(priv, "pci_alloc_consistent(%zd) failed\n", tfd_sz);
316 goto error;
318 txq->q.id = id;
320 return 0;
322 error:
323 kfree(txq->txb);
324 txq->txb = NULL;
326 return -ENOMEM;
330 * iwl_tx_queue_init - Allocate and initialize one tx/cmd queue
332 int iwl_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq,
333 int slots_num, u32 txq_id)
335 int i, len;
336 int ret;
337 int actual_slots = slots_num;
340 * Alloc buffer array for commands (Tx or other types of commands).
341 * For the command queue (#4/#9), allocate command space + one big
342 * command for scan, since scan command is very huge; the system will
343 * not have two scans at the same time, so only one is needed.
344 * For normal Tx queues (all other queues), no super-size command
345 * space is needed.
347 if (txq_id == priv->cmd_queue)
348 actual_slots++;
350 txq->meta = kzalloc(sizeof(struct iwl_cmd_meta) * actual_slots,
351 GFP_KERNEL);
352 txq->cmd = kzalloc(sizeof(struct iwl_device_cmd *) * actual_slots,
353 GFP_KERNEL);
355 if (!txq->meta || !txq->cmd)
356 goto out_free_arrays;
358 len = sizeof(struct iwl_device_cmd);
359 for (i = 0; i < actual_slots; i++) {
360 /* only happens for cmd queue */
361 if (i == slots_num)
362 len = IWL_MAX_CMD_SIZE;
364 txq->cmd[i] = kmalloc(len, GFP_KERNEL);
365 if (!txq->cmd[i])
366 goto err;
369 /* Alloc driver data array and TFD circular buffer */
370 ret = iwl_tx_queue_alloc(priv, txq, txq_id);
371 if (ret)
372 goto err;
374 txq->need_update = 0;
377 * For the default queues 0-3, set up the swq_id
378 * already -- all others need to get one later
379 * (if they need one at all).
381 if (txq_id < 4)
382 iwl_set_swq_id(txq, txq_id, txq_id);
384 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
385 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
386 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
388 /* Initialize queue's high/low-water marks, and head/tail indexes */
389 ret = iwl_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id);
390 if (ret)
391 return ret;
393 /* Tell device where to find queue */
394 priv->cfg->ops->lib->txq_init(priv, txq);
396 return 0;
397 err:
398 for (i = 0; i < actual_slots; i++)
399 kfree(txq->cmd[i]);
400 out_free_arrays:
401 kfree(txq->meta);
402 kfree(txq->cmd);
404 return -ENOMEM;
407 void iwl_tx_queue_reset(struct iwl_priv *priv, struct iwl_tx_queue *txq,
408 int slots_num, u32 txq_id)
410 int actual_slots = slots_num;
412 if (txq_id == priv->cmd_queue)
413 actual_slots++;
415 memset(txq->meta, 0, sizeof(struct iwl_cmd_meta) * actual_slots);
417 txq->need_update = 0;
419 /* Initialize queue's high/low-water marks, and head/tail indexes */
420 iwl_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id);
422 /* Tell device where to find queue */
423 priv->cfg->ops->lib->txq_init(priv, txq);
426 /*************** HOST COMMAND QUEUE FUNCTIONS *****/
429 * iwl_enqueue_hcmd - enqueue a uCode command
430 * @priv: device private data point
431 * @cmd: a point to the ucode command structure
433 * The function returns < 0 values to indicate the operation is
434 * failed. On success, it turns the index (> 0) of command in the
435 * command queue.
437 int iwl_enqueue_hcmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd)
439 struct iwl_tx_queue *txq = &priv->txq[priv->cmd_queue];
440 struct iwl_queue *q = &txq->q;
441 struct iwl_device_cmd *out_cmd;
442 struct iwl_cmd_meta *out_meta;
443 dma_addr_t phys_addr;
444 unsigned long flags;
445 int len;
446 u32 idx;
447 u16 fix_size;
448 bool is_ct_kill = false;
450 cmd->len = priv->cfg->ops->utils->get_hcmd_size(cmd->id, cmd->len);
451 fix_size = (u16)(cmd->len + sizeof(out_cmd->hdr));
454 * If any of the command structures end up being larger than
455 * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then
456 * we will need to increase the size of the TFD entries
457 * Also, check to see if command buffer should not exceed the size
458 * of device_cmd and max_cmd_size.
460 if (WARN_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) &&
461 !(cmd->flags & CMD_SIZE_HUGE)))
462 return -EINVAL;
464 if (WARN_ON(fix_size > IWL_MAX_CMD_SIZE))
465 return -EINVAL;
467 if (iwl_is_rfkill(priv) || iwl_is_ctkill(priv)) {
468 IWL_WARN(priv, "Not sending command - %s KILL\n",
469 iwl_is_rfkill(priv) ? "RF" : "CT");
470 return -EIO;
474 * As we only have a single huge buffer, check that the command
475 * is synchronous (otherwise buffers could end up being reused).
478 if (WARN_ON((cmd->flags & CMD_ASYNC) && (cmd->flags & CMD_SIZE_HUGE)))
479 return -EINVAL;
481 spin_lock_irqsave(&priv->hcmd_lock, flags);
483 if (iwl_queue_space(q) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) {
484 spin_unlock_irqrestore(&priv->hcmd_lock, flags);
486 IWL_ERR(priv, "No space in command queue\n");
487 is_ct_kill = iwl_check_for_ct_kill(priv);
488 if (!is_ct_kill) {
489 IWL_ERR(priv, "Restarting adapter due to queue full\n");
490 iwlagn_fw_error(priv, false);
492 return -ENOSPC;
495 idx = get_cmd_index(q, q->write_ptr, cmd->flags & CMD_SIZE_HUGE);
496 out_cmd = txq->cmd[idx];
497 out_meta = &txq->meta[idx];
499 if (WARN_ON(out_meta->flags & CMD_MAPPED)) {
500 spin_unlock_irqrestore(&priv->hcmd_lock, flags);
501 return -ENOSPC;
504 memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */
505 out_meta->flags = cmd->flags | CMD_MAPPED;
506 if (cmd->flags & CMD_WANT_SKB)
507 out_meta->source = cmd;
508 if (cmd->flags & CMD_ASYNC)
509 out_meta->callback = cmd->callback;
511 out_cmd->hdr.cmd = cmd->id;
512 memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len);
514 /* At this point, the out_cmd now has all of the incoming cmd
515 * information */
517 out_cmd->hdr.flags = 0;
518 out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(priv->cmd_queue) |
519 INDEX_TO_SEQ(q->write_ptr));
520 if (cmd->flags & CMD_SIZE_HUGE)
521 out_cmd->hdr.sequence |= SEQ_HUGE_FRAME;
522 len = sizeof(struct iwl_device_cmd);
523 if (idx == TFD_CMD_SLOTS)
524 len = IWL_MAX_CMD_SIZE;
526 #ifdef CONFIG_IWLWIFI_DEBUG
527 switch (out_cmd->hdr.cmd) {
528 case REPLY_TX_LINK_QUALITY_CMD:
529 case SENSITIVITY_CMD:
530 IWL_DEBUG_HC_DUMP(priv, "Sending command %s (#%x), seq: 0x%04X, "
531 "%d bytes at %d[%d]:%d\n",
532 get_cmd_string(out_cmd->hdr.cmd),
533 out_cmd->hdr.cmd,
534 le16_to_cpu(out_cmd->hdr.sequence), fix_size,
535 q->write_ptr, idx, priv->cmd_queue);
536 break;
537 default:
538 IWL_DEBUG_HC(priv, "Sending command %s (#%x), seq: 0x%04X, "
539 "%d bytes at %d[%d]:%d\n",
540 get_cmd_string(out_cmd->hdr.cmd),
541 out_cmd->hdr.cmd,
542 le16_to_cpu(out_cmd->hdr.sequence), fix_size,
543 q->write_ptr, idx, priv->cmd_queue);
545 #endif
546 txq->need_update = 1;
548 if (priv->cfg->ops->lib->txq_update_byte_cnt_tbl)
549 /* Set up entry in queue's byte count circular buffer */
550 priv->cfg->ops->lib->txq_update_byte_cnt_tbl(priv, txq, 0);
552 phys_addr = pci_map_single(priv->pci_dev, &out_cmd->hdr,
553 fix_size, PCI_DMA_BIDIRECTIONAL);
554 dma_unmap_addr_set(out_meta, mapping, phys_addr);
555 dma_unmap_len_set(out_meta, len, fix_size);
557 trace_iwlwifi_dev_hcmd(priv, &out_cmd->hdr, fix_size, cmd->flags);
559 priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq,
560 phys_addr, fix_size, 1,
561 U32_PAD(cmd->len));
563 /* Increment and update queue's write index */
564 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
565 iwl_txq_update_write_ptr(priv, txq);
567 spin_unlock_irqrestore(&priv->hcmd_lock, flags);
568 return idx;
572 * iwl_hcmd_queue_reclaim - Reclaim TX command queue entries already Tx'd
574 * When FW advances 'R' index, all entries between old and new 'R' index
575 * need to be reclaimed. As result, some free space forms. If there is
576 * enough free space (> low mark), wake the stack that feeds us.
578 static void iwl_hcmd_queue_reclaim(struct iwl_priv *priv, int txq_id,
579 int idx, int cmd_idx)
581 struct iwl_tx_queue *txq = &priv->txq[txq_id];
582 struct iwl_queue *q = &txq->q;
583 int nfreed = 0;
585 if ((idx >= q->n_bd) || (iwl_queue_used(q, idx) == 0)) {
586 IWL_ERR(priv, "Read index for DMA queue txq id (%d), index %d, "
587 "is out of range [0-%d] %d %d.\n", txq_id,
588 idx, q->n_bd, q->write_ptr, q->read_ptr);
589 return;
592 for (idx = iwl_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx;
593 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
595 if (nfreed++ > 0) {
596 IWL_ERR(priv, "HCMD skipped: index (%d) %d %d\n", idx,
597 q->write_ptr, q->read_ptr);
598 iwlagn_fw_error(priv, false);
605 * iwl_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
606 * @rxb: Rx buffer to reclaim
608 * If an Rx buffer has an async callback associated with it the callback
609 * will be executed. The attached skb (if present) will only be freed
610 * if the callback returns 1
612 void iwl_tx_cmd_complete(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb)
614 struct iwl_rx_packet *pkt = rxb_addr(rxb);
615 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
616 int txq_id = SEQ_TO_QUEUE(sequence);
617 int index = SEQ_TO_INDEX(sequence);
618 int cmd_index;
619 bool huge = !!(pkt->hdr.sequence & SEQ_HUGE_FRAME);
620 struct iwl_device_cmd *cmd;
621 struct iwl_cmd_meta *meta;
622 struct iwl_tx_queue *txq = &priv->txq[priv->cmd_queue];
623 unsigned long flags;
625 /* If a Tx command is being handled and it isn't in the actual
626 * command queue then there a command routing bug has been introduced
627 * in the queue management code. */
628 if (WARN(txq_id != priv->cmd_queue,
629 "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n",
630 txq_id, priv->cmd_queue, sequence,
631 priv->txq[priv->cmd_queue].q.read_ptr,
632 priv->txq[priv->cmd_queue].q.write_ptr)) {
633 iwl_print_hex_error(priv, pkt, 32);
634 return;
637 cmd_index = get_cmd_index(&txq->q, index, huge);
638 cmd = txq->cmd[cmd_index];
639 meta = &txq->meta[cmd_index];
641 pci_unmap_single(priv->pci_dev,
642 dma_unmap_addr(meta, mapping),
643 dma_unmap_len(meta, len),
644 PCI_DMA_BIDIRECTIONAL);
646 /* Input error checking is done when commands are added to queue. */
647 if (meta->flags & CMD_WANT_SKB) {
648 meta->source->reply_page = (unsigned long)rxb_addr(rxb);
649 rxb->page = NULL;
650 } else if (meta->callback)
651 meta->callback(priv, cmd, pkt);
653 spin_lock_irqsave(&priv->hcmd_lock, flags);
655 iwl_hcmd_queue_reclaim(priv, txq_id, index, cmd_index);
657 if (!(meta->flags & CMD_ASYNC)) {
658 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
659 IWL_DEBUG_INFO(priv, "Clearing HCMD_ACTIVE for command %s\n",
660 get_cmd_string(cmd->hdr.cmd));
661 wake_up_interruptible(&priv->wait_command_queue);
664 /* Mark as unmapped */
665 meta->flags = 0;
667 spin_unlock_irqrestore(&priv->hcmd_lock, flags);