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iio: adc: New driver for AD7280A Lithium Ion Battery Monitoring System
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / staging / iio / adc / ad7280a.c
blobab6cf9cb5a7fb9fdf849d38b79f31ebbcbea02c1
1 /*
2 * AD7280A Lithium Ion Battery Monitoring System
3 *
4 * Copyright 2011 Analog Devices Inc.
5 *
6 * Licensed under the GPL-2.
7 */
8
9 #include <linux/device.h>
10 #include <linux/kernel.h>
11 #include <linux/slab.h>
12 #include <linux/sysfs.h>
13 #include <linux/spi/spi.h>
14 #include <linux/err.h>
15 #include <linux/delay.h>
16 #include <linux/interrupt.h>
17
18 #include "../iio.h"
19 #include "../sysfs.h"
20
21 #include "ad7280a.h"
22
23 /* Registers */
24 #define AD7280A_CELL_VOLTAGE_1 0x0 /* D11 to D0, Read only */
25 #define AD7280A_CELL_VOLTAGE_2 0x1 /* D11 to D0, Read only */
26 #define AD7280A_CELL_VOLTAGE_3 0x2 /* D11 to D0, Read only */
27 #define AD7280A_CELL_VOLTAGE_4 0x3 /* D11 to D0, Read only */
28 #define AD7280A_CELL_VOLTAGE_5 0x4 /* D11 to D0, Read only */
29 #define AD7280A_CELL_VOLTAGE_6 0x5 /* D11 to D0, Read only */
30 #define AD7280A_AUX_ADC_1 0x6 /* D11 to D0, Read only */
31 #define AD7280A_AUX_ADC_2 0x7 /* D11 to D0, Read only */
32 #define AD7280A_AUX_ADC_3 0x8 /* D11 to D0, Read only */
33 #define AD7280A_AUX_ADC_4 0x9 /* D11 to D0, Read only */
34 #define AD7280A_AUX_ADC_5 0xA /* D11 to D0, Read only */
35 #define AD7280A_AUX_ADC_6 0xB /* D11 to D0, Read only */
36 #define AD7280A_SELF_TEST 0xC /* D11 to D0, Read only */
37 #define AD7280A_CONTROL_HB 0xD /* D15 to D8, Read/write */
38 #define AD7280A_CONTROL_LB 0xE /* D7 to D0, Read/write */
39 #define AD7280A_CELL_OVERVOLTAGE 0xF /* D7 to D0, Read/write */
40 #define AD7280A_CELL_UNDERVOLTAGE 0x10 /* D7 to D0, Read/write */
41 #define AD7280A_AUX_ADC_OVERVOLTAGE 0x11 /* D7 to D0, Read/write */
42 #define AD7280A_AUX_ADC_UNDERVOLTAGE 0x12 /* D7 to D0, Read/write */
43 #define AD7280A_ALERT 0x13 /* D7 to D0, Read/write */
44 #define AD7280A_CELL_BALANCE 0x14 /* D7 to D0, Read/write */
45 #define AD7280A_CB1_TIMER 0x15 /* D7 to D0, Read/write */
46 #define AD7280A_CB2_TIMER 0x16 /* D7 to D0, Read/write */
47 #define AD7280A_CB3_TIMER 0x17 /* D7 to D0, Read/write */
48 #define AD7280A_CB4_TIMER 0x18 /* D7 to D0, Read/write */
49 #define AD7280A_CB5_TIMER 0x19 /* D7 to D0, Read/write */
50 #define AD7280A_CB6_TIMER 0x1A /* D7 to D0, Read/write */
51 #define AD7280A_PD_TIMER 0x1B /* D7 to D0, Read/write */
52 #define AD7280A_READ 0x1C /* D7 to D0, Read/write */
53 #define AD7280A_CNVST_CONTROL 0x1D /* D7 to D0, Read/write */
54
55 /* Bits and Masks */
56 #define AD7280A_CTRL_HB_CONV_INPUT_ALL (0 << 6)
57 #define AD7280A_CTRL_HB_CONV_INPUT_6CELL_AUX1_3_4 (1 << 6)
58 #define AD7280A_CTRL_HB_CONV_INPUT_6CELL (2 << 6)
59 #define AD7280A_CTRL_HB_CONV_INPUT_SELF_TEST (3 << 6)
60 #define AD7280A_CTRL_HB_CONV_RES_READ_ALL (0 << 4)
61 #define AD7280A_CTRL_HB_CONV_RES_READ_6CELL_AUX1_3_4 (1 << 4)
62 #define AD7280A_CTRL_HB_CONV_RES_READ_6CELL (2 << 4)
63 #define AD7280A_CTRL_HB_CONV_RES_READ_NO (3 << 4)
64 #define AD7280A_CTRL_HB_CONV_START_CNVST (0 << 3)
65 #define AD7280A_CTRL_HB_CONV_START_CS (1 << 3)
66 #define AD7280A_CTRL_HB_CONV_AVG_DIS (0 << 1)
67 #define AD7280A_CTRL_HB_CONV_AVG_2 (1 << 1)
68 #define AD7280A_CTRL_HB_CONV_AVG_4 (2 << 1)
69 #define AD7280A_CTRL_HB_CONV_AVG_8 (3 << 1)
70 #define AD7280A_CTRL_HB_CONV_AVG(x) ((x) << 1)
71 #define AD7280A_CTRL_HB_PWRDN_SW (1 << 0)
72
73 #define AD7280A_CTRL_LB_SWRST (1 << 7)
74 #define AD7280A_CTRL_LB_ACQ_TIME_400ns (0 << 5)
75 #define AD7280A_CTRL_LB_ACQ_TIME_800ns (1 << 5)
76 #define AD7280A_CTRL_LB_ACQ_TIME_1200ns (2 << 5)
77 #define AD7280A_CTRL_LB_ACQ_TIME_1600ns (3 << 5)
78 #define AD7280A_CTRL_LB_ACQ_TIME(x) ((x) << 5)
79 #define AD7280A_CTRL_LB_MUST_SET (1 << 4)
80 #define AD7280A_CTRL_LB_THERMISTOR_EN (1 << 3)
81 #define AD7280A_CTRL_LB_LOCK_DEV_ADDR (1 << 2)
82 #define AD7280A_CTRL_LB_INC_DEV_ADDR (1 << 1)
83 #define AD7280A_CTRL_LB_DAISY_CHAIN_RB_EN (1 << 0)
84
85 #define AD7280A_ALERT_GEN_STATIC_HIGH (1 << 6)
86 #define AD7280A_ALERT_RELAY_SIG_CHAIN_DOWN (3 << 6)
87
88 #define AD7280A_ALL_CELLS (0xAD << 16)
89
90 #define AD7280A_MAX_SPI_CLK_Hz 700000 /* < 1MHz */
91 #define AD7280A_MAX_CHAIN 8
92 #define AD7280A_CELLS_PER_DEV 6
93 #define AD7280A_BITS 12
94 #define AD7280A_NUM_CH (AD7280A_AUX_ADC_6 - \
95 AD7280A_CELL_VOLTAGE_1 + 1)
96
97 #define AD7280A_DEVADDR_MASTER 0
98 #define AD7280A_DEVADDR_ALL 0x1F
99 /* 5-bit device address is sent LSB first */
100 #define AD7280A_DEVADDR(addr) (((addr & 0x1) << 4) | ((addr & 0x2) << 3) | \
101 (addr & 0x4) | ((addr & 0x8) >> 3) | \
102 ((addr & 0x10) >> 4))
103
104 /* During a read a valid write is mandatory.
105 * So writing to the highest available address (Address 0x1F)
106 * and setting the address all parts bit to 0 is recommended
107 * So the TXVAL is AD7280A_DEVADDR_ALL + CRC
108 */
109 #define AD7280A_READ_TXVAL 0xF800030A
110
111 /*
112 * AD7280 CRC
113 *
114 * P(x) = x^8 + x^5 + x^3 + x^2 + x^1 + x^0 = 0b100101111 => 0x2F
115 */
116 #define POLYNOM 0x2F
117 #define POLYNOM_ORDER 8
118 #define HIGHBIT 1 << (POLYNOM_ORDER - 1);
119
120 struct ad7280_state {
121 struct spi_device *spi;
122 struct iio_chan_spec *channels;
123 struct iio_dev_attr *iio_attr;
124 int slave_num;
125 int scan_cnt;
126 int readback_delay_us;
127 unsigned char crc_tab[256];
128 unsigned char ctrl_hb;
129 unsigned char ctrl_lb;
130 unsigned char cell_threshhigh;
131 unsigned char cell_threshlow;
132 unsigned char aux_threshhigh;
133 unsigned char aux_threshlow;
134 unsigned char cb_mask[AD7280A_MAX_CHAIN];
135 };
136
137 static void ad7280_crc8_build_table(unsigned char *crc_tab)
138 {
139 unsigned char bit, crc;
140 int cnt, i;
141
142 for (cnt = 0; cnt < 256; cnt++) {
143 crc = cnt;
144 for (i = 0; i < 8; i++) {
145 bit = crc & HIGHBIT;
146 crc <<= 1;
147 if (bit)
148 crc ^= POLYNOM;
149 }
150 crc_tab[cnt] = crc;
151 }
152 }
153
154 static unsigned char ad7280_calc_crc8(unsigned char *crc_tab, unsigned val)
155 {
156 unsigned char crc;
157
158 crc = crc_tab[val >> 16 & 0xFF];
159 crc = crc_tab[crc ^ (val >> 8 & 0xFF)];
160
161 return crc ^ (val & 0xFF);
162 }
163
164 static int ad7280_check_crc(struct ad7280_state *st, unsigned val)
165 {
166 unsigned char crc = ad7280_calc_crc8(st->crc_tab, val >> 10);
167
168 if (crc != ((val >> 2) & 0xFF))
169 return -EIO;
170
171 return 0;
172 }
173
174 /* After initiating a conversion sequence we need to wait until the
175 * conversion is done. The delay is typically in the range of 15..30 us
176 * however depending an the number of devices in the daisy chain and the
177 * number of averages taken, conversion delays and acquisition time options
178 * it may take up to 250us, in this case we better sleep instead of busy
179 * wait.
180 */
181
182 static void ad7280_delay(struct ad7280_state *st)
183 {
184 if (st->readback_delay_us < 50)
185 udelay(st->readback_delay_us);
186 else
187 msleep(1);
188 }
189
190 static int __ad7280_read32(struct spi_device *spi, unsigned *val)
191 {
192 unsigned rx_buf, tx_buf = cpu_to_be32(AD7280A_READ_TXVAL);
193 int ret;
194
195 struct spi_transfer t = {
196 .tx_buf = &tx_buf,
197 .rx_buf = &rx_buf,
198 .len = 4,
199 };
200 struct spi_message m;
201
202 spi_message_init(&m);
203 spi_message_add_tail(&t, &m);
204
205 ret = spi_sync(spi, &m);
206 if (ret)
207 return ret;
208
209 *val = be32_to_cpu(rx_buf);
210
211 return 0;
212 }
213
214 static int ad7280_write(struct ad7280_state *st, unsigned devaddr,
215 unsigned addr, bool all, unsigned val)
216 {
217 unsigned reg = (devaddr << 27 | addr << 21 |
218 (val & 0xFF) << 13 | all << 12);
219
220 reg |= ad7280_calc_crc8(st->crc_tab, reg >> 11) << 3 | 0x2;
221 reg = cpu_to_be32(reg);
222
223 return spi_write(st->spi, &reg, 4);
224 }
225
226 static int ad7280_read(struct ad7280_state *st, unsigned devaddr,
227 unsigned addr)
228 {
229 int ret;
230 unsigned tmp;
231
232 /* turns off the read operation on all parts */
233 ret = ad7280_write(st, AD7280A_DEVADDR_MASTER, AD7280A_CONTROL_HB, 1,
234 AD7280A_CTRL_HB_CONV_INPUT_ALL |
235 AD7280A_CTRL_HB_CONV_RES_READ_NO |
236 st->ctrl_hb);
237 if (ret)
238 return ret;
239
240 /* turns on the read operation on the addressed part */
241 ret = ad7280_write(st, devaddr, AD7280A_CONTROL_HB, 0,
242 AD7280A_CTRL_HB_CONV_INPUT_ALL |
243 AD7280A_CTRL_HB_CONV_RES_READ_ALL |
244 st->ctrl_hb);
245 if (ret)
246 return ret;
247
248 /* Set register address on the part to be read from */
249 ret = ad7280_write(st, devaddr, AD7280A_READ, 0, addr << 2);
250 if (ret)
251 return ret;
252
253 __ad7280_read32(st->spi, &tmp);
254
255 if (ad7280_check_crc(st, tmp))
256 return -EIO;
257
258 if (((tmp >> 27) != devaddr) || (((tmp >> 21) & 0x3F) != addr))
259 return -EFAULT;
260
261 return (tmp >> 13) & 0xFF;
262 }
263
264 static int ad7280_read_channel(struct ad7280_state *st, unsigned devaddr,
265 unsigned addr)
266 {
267 int ret;
268 unsigned tmp;
269
270 ret = ad7280_write(st, devaddr, AD7280A_READ, 0, addr << 2);
271 if (ret)
272 return ret;
273
274 ret = ad7280_write(st, AD7280A_DEVADDR_MASTER, AD7280A_CONTROL_HB, 1,
275 AD7280A_CTRL_HB_CONV_INPUT_ALL |
276 AD7280A_CTRL_HB_CONV_RES_READ_NO |
277 st->ctrl_hb);
278 if (ret)
279 return ret;
280
281 ret = ad7280_write(st, devaddr, AD7280A_CONTROL_HB, 0,
282 AD7280A_CTRL_HB_CONV_INPUT_ALL |
283 AD7280A_CTRL_HB_CONV_RES_READ_ALL |
284 AD7280A_CTRL_HB_CONV_START_CS |
285 st->ctrl_hb);
286 if (ret)
287 return ret;
288
289 ad7280_delay(st);
290
291 __ad7280_read32(st->spi, &tmp);
292
293 if (ad7280_check_crc(st, tmp))
294 return -EIO;
295
296 if (((tmp >> 27) != devaddr) || (((tmp >> 23) & 0xF) != addr))
297 return -EFAULT;
298
299 return (tmp >> 11) & 0xFFF;
300 }
301
302 static int ad7280_read_all_channels(struct ad7280_state *st, unsigned cnt,
303 unsigned *array)
304 {
305 int i, ret;
306 unsigned tmp, sum = 0;
307
308 ret = ad7280_write(st, AD7280A_DEVADDR_MASTER, AD7280A_READ, 1,
309 AD7280A_CELL_VOLTAGE_1 << 2);
310 if (ret)
311 return ret;
312
313 ret = ad7280_write(st, AD7280A_DEVADDR_MASTER, AD7280A_CONTROL_HB, 1,
314 AD7280A_CTRL_HB_CONV_INPUT_ALL |
315 AD7280A_CTRL_HB_CONV_RES_READ_ALL |
316 AD7280A_CTRL_HB_CONV_START_CS |
317 st->ctrl_hb);
318 if (ret)
319 return ret;
320
321 ad7280_delay(st);
322
323 for (i = 0; i < cnt; i++) {
324 __ad7280_read32(st->spi, &tmp);
325
326 if (ad7280_check_crc(st, tmp))
327 return -EIO;
328
329 if (array)
330 array[i] = tmp;
331 /* only sum cell voltages */
332 if (((tmp >> 23) & 0xF) <= AD7280A_CELL_VOLTAGE_6)
333 sum += ((tmp >> 11) & 0xFFF);
334 }
335
336 return sum;
337 }
338
339 static int ad7280_chain_setup(struct ad7280_state *st)
340 {
341 unsigned val, n;
342 int ret;
343
344 ret = ad7280_write(st, AD7280A_DEVADDR_MASTER, AD7280A_CONTROL_LB, 1,
345 AD7280A_CTRL_LB_DAISY_CHAIN_RB_EN |
346 AD7280A_CTRL_LB_LOCK_DEV_ADDR |
347 AD7280A_CTRL_LB_MUST_SET |
348 AD7280A_CTRL_LB_SWRST |
349 st->ctrl_lb);
350 if (ret)
351 return ret;
352
353 ret = ad7280_write(st, AD7280A_DEVADDR_MASTER, AD7280A_CONTROL_LB, 1,
354 AD7280A_CTRL_LB_DAISY_CHAIN_RB_EN |
355 AD7280A_CTRL_LB_LOCK_DEV_ADDR |
356 AD7280A_CTRL_LB_MUST_SET |
357 st->ctrl_lb);
358 if (ret)
359 return ret;
360
361 ret = ad7280_write(st, AD7280A_DEVADDR_MASTER, AD7280A_READ, 1,
362 AD7280A_CONTROL_LB << 2);
363 if (ret)
364 return ret;
365
366 for (n = 0; n <= AD7280A_MAX_CHAIN; n++) {
367 __ad7280_read32(st->spi, &val);
368 if (val == 0)
369 return n - 1;
370
371 if (ad7280_check_crc(st, val))
372 return -EIO;
373
374 if (n != AD7280A_DEVADDR(val >> 27))
375 return -EIO;
376 }
377
378 return -EFAULT;
379 }
380
381 static ssize_t ad7280_show_balance_sw(struct device *dev,
382 struct device_attribute *attr,
383 char *buf)
384 {
385 struct iio_dev *dev_info = dev_get_drvdata(dev);
386 struct ad7280_state *st = iio_priv(dev_info);
387 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
388
389 return sprintf(buf, "%d\n",
390 !!(st->cb_mask[this_attr->address >> 8] &
391 (1 << ((this_attr->address & 0xFF) + 2))));
392 }
393
394 static ssize_t ad7280_store_balance_sw(struct device *dev,
395 struct device_attribute *attr,
396 const char *buf,
397 size_t len)
398 {
399 struct iio_dev *dev_info = dev_get_drvdata(dev);
400 struct ad7280_state *st = iio_priv(dev_info);
401 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
402 bool readin;
403 int ret;
404 unsigned devaddr, ch;
405
406 ret = strtobool(buf, &readin);
407 if (ret)
408 return ret;
409
410 devaddr = this_attr->address >> 8;
411 ch = this_attr->address & 0xFF;
412
413 mutex_lock(&dev_info->mlock);
414 if (readin)
415 st->cb_mask[devaddr] |= 1 << (ch + 2);
416 else
417 st->cb_mask[devaddr] &= ~(1 << (ch + 2));
418
419 ret = ad7280_write(st, devaddr, AD7280A_CELL_BALANCE,
420 0, st->cb_mask[devaddr]);
421 mutex_unlock(&dev_info->mlock);
422
423 return ret ? ret : len;
424 }
425
426 static ssize_t ad7280_show_balance_timer(struct device *dev,
427 struct device_attribute *attr,
428 char *buf)
429 {
430 struct iio_dev *dev_info = dev_get_drvdata(dev);
431 struct ad7280_state *st = iio_priv(dev_info);
432 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
433 int ret;
434 unsigned msecs;
435
436 mutex_lock(&dev_info->mlock);
437 ret = ad7280_read(st, this_attr->address >> 8,
438 this_attr->address & 0xFF);
439 mutex_unlock(&dev_info->mlock);
440
441 if (ret < 0)
442 return ret;
443
444 msecs = (ret >> 3) * 71500;
445
446 return sprintf(buf, "%d\n", msecs);
447 }
448
449 static ssize_t ad7280_store_balance_timer(struct device *dev,
450 struct device_attribute *attr,
451 const char *buf,
452 size_t len)
453 {
454 struct iio_dev *dev_info = dev_get_drvdata(dev);
455 struct ad7280_state *st = iio_priv(dev_info);
456 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
457 long val;
458 int ret;
459
460 ret = strict_strtoul(buf, 10, &val);
461 if (ret)
462 return ret;
463
464 val /= 71500;
465
466 if (val > 31)
467 return -EINVAL;
468
469 mutex_lock(&dev_info->mlock);
470 ret = ad7280_write(st, this_attr->address >> 8,
471 this_attr->address & 0xFF,
472 0, (val & 0x1F) << 3);
473 mutex_unlock(&dev_info->mlock);
474
475 return ret ? ret : len;
476 }
477
478 static struct attribute *ad7280_attributes[AD7280A_MAX_CHAIN *
479 AD7280A_CELLS_PER_DEV * 2 + 1];
480
481 static struct attribute_group ad7280_attrs_group = {
482 .attrs = ad7280_attributes,
483 };
484
485 static int ad7280_channel_init(struct ad7280_state *st)
486 {
487 int dev, ch, cnt;
488
489 st->channels = kzalloc(sizeof(*st->channels) *
490 ((st->slave_num + 1) * 12 + 2), GFP_KERNEL);
491 if (st->channels == NULL)
492 return -ENOMEM;
493
494 for (dev = 0, cnt = 0; dev <= st->slave_num; dev++)
495 for (ch = AD7280A_CELL_VOLTAGE_1; ch <= AD7280A_AUX_ADC_6; ch++,
496 cnt++) {
497 if (ch < AD7280A_AUX_ADC_1) {
498 st->channels[cnt].type = IIO_IN_DIFF;
499 st->channels[cnt].channel = (dev * 6) + ch;
500 st->channels[cnt].channel2 =
501 st->channels[cnt].channel + 1;
502 } else {
503 st->channels[cnt].type = IIO_TEMP;
504 st->channels[cnt].channel = (dev * 6) + ch - 6;
505 }
506 st->channels[cnt].indexed = 1;
507 st->channels[cnt].info_mask =
508 (1 << IIO_CHAN_INFO_SCALE_SHARED);
509 st->channels[cnt].address =
510 AD7280A_DEVADDR(dev) << 8 | ch;
511 st->channels[cnt].scan_index = cnt;
512 st->channels[cnt].scan_type.sign = 'u';
513 st->channels[cnt].scan_type.realbits = 12;
514 st->channels[cnt].scan_type.storagebits = 32;
515 st->channels[cnt].scan_type.shift = 0;
516 }
517
518 st->channels[cnt].type = IIO_IN_DIFF;
519 st->channels[cnt].channel = 0;
520 st->channels[cnt].channel2 = dev * 6;
521 st->channels[cnt].address = AD7280A_ALL_CELLS;
522 st->channels[cnt].indexed = 1;
523 st->channels[cnt].info_mask = (1 << IIO_CHAN_INFO_SCALE_SHARED);
524 st->channels[cnt].scan_index = cnt;
525 st->channels[cnt].scan_type.sign = 'u';
526 st->channels[cnt].scan_type.realbits = 32;
527 st->channels[cnt].scan_type.storagebits = 32;
528 st->channels[cnt].scan_type.shift = 0;
529 cnt++;
530 st->channels[cnt].type = IIO_TIMESTAMP;
531 st->channels[cnt].channel = -1;
532 st->channels[cnt].scan_index = cnt;
533 st->channels[cnt].scan_type.sign = 's';
534 st->channels[cnt].scan_type.realbits = 64;
535 st->channels[cnt].scan_type.storagebits = 64;
536 st->channels[cnt].scan_type.shift = 0;
537
538 return cnt + 1;
539 }
540
541 static int ad7280_attr_init(struct ad7280_state *st)
542 {
543 int dev, ch, cnt;
544
545 st->iio_attr = kzalloc(sizeof(*st->iio_attr) * (st->slave_num + 1) *
546 AD7280A_CELLS_PER_DEV * 2, GFP_KERNEL);
547 if (st->iio_attr == NULL)
548 return -ENOMEM;
549
550 for (dev = 0, cnt = 0; dev <= st->slave_num; dev++)
551 for (ch = AD7280A_CELL_VOLTAGE_1; ch <= AD7280A_CELL_VOLTAGE_6;
552 ch++, cnt++) {
553 st->iio_attr[cnt].address =
554 AD7280A_DEVADDR(dev) << 8 | ch;
555 st->iio_attr[cnt].dev_attr.attr.mode =
556 S_IWUSR | S_IRUGO;
557 st->iio_attr[cnt].dev_attr.show =
558 ad7280_show_balance_sw;
559 st->iio_attr[cnt].dev_attr.store =
560 ad7280_store_balance_sw;
561 st->iio_attr[cnt].dev_attr.attr.name =
562 kasprintf(GFP_KERNEL,
563 "in%d-in%d_balance_switch_en",
564 (dev * AD7280A_CELLS_PER_DEV) + ch,
565 (dev * AD7280A_CELLS_PER_DEV) + ch + 1);
566 ad7280_attributes[cnt] =
567 &st->iio_attr[cnt].dev_attr.attr;
568 cnt++;
569 st->iio_attr[cnt].address =
570 AD7280A_DEVADDR(dev) << 8 |
571 (AD7280A_CB1_TIMER + ch);
572 st->iio_attr[cnt].dev_attr.attr.mode =
573 S_IWUSR | S_IRUGO;
574 st->iio_attr[cnt].dev_attr.show =
575 ad7280_show_balance_timer;
576 st->iio_attr[cnt].dev_attr.store =
577 ad7280_store_balance_timer;
578 st->iio_attr[cnt].dev_attr.attr.name =
579 kasprintf(GFP_KERNEL, "in%d-in%d_balance_timer",
580 (dev * AD7280A_CELLS_PER_DEV) + ch,
581 (dev * AD7280A_CELLS_PER_DEV) + ch + 1);
582 ad7280_attributes[cnt] =
583 &st->iio_attr[cnt].dev_attr.attr;
584 }
585
586 ad7280_attributes[cnt] = NULL;
587
588 return 0;
589 }
590
591 static ssize_t ad7280_read_channel_config(struct device *dev,
592 struct device_attribute *attr,
593 char *buf)
594 {
595 struct iio_dev *dev_info = dev_get_drvdata(dev);
596 struct ad7280_state *st = iio_priv(dev_info);
597 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
598 unsigned val;
599
600 switch (this_attr->address) {
601 case AD7280A_CELL_OVERVOLTAGE:
602 val = 1000 + (st->cell_threshhigh * 1568) / 100;
603 break;
604 case AD7280A_CELL_UNDERVOLTAGE:
605 val = 1000 + (st->cell_threshlow * 1568) / 100;
606 break;
607 case AD7280A_AUX_ADC_OVERVOLTAGE:
608 val = (st->aux_threshhigh * 196) / 10;
609 break;
610 case AD7280A_AUX_ADC_UNDERVOLTAGE:
611 val = (st->aux_threshlow * 196) / 10;
612 break;
613 default:
614 return -EINVAL;
615 }
616
617 return sprintf(buf, "%d\n", val);
618 }
619
620 static ssize_t ad7280_write_channel_config(struct device *dev,
621 struct device_attribute *attr,
622 const char *buf,
623 size_t len)
624 {
625 struct iio_dev *dev_info = dev_get_drvdata(dev);
626 struct ad7280_state *st = iio_priv(dev_info);
627 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
628
629 long val;
630 int ret;
631
632 ret = strict_strtol(buf, 10, &val);
633 if (ret)
634 return ret;
635
636 switch (this_attr->address) {
637 case AD7280A_CELL_OVERVOLTAGE:
638 case AD7280A_CELL_UNDERVOLTAGE:
639 val = ((val - 1000) * 100) / 1568; /* LSB 15.68mV */
640 break;
641 case AD7280A_AUX_ADC_OVERVOLTAGE:
642 case AD7280A_AUX_ADC_UNDERVOLTAGE:
643 val = (val * 10) / 196; /* LSB 19.6mV */
644 break;
645 default:
646 return -EFAULT;
647 }
648
649 val = clamp(val, 0L, 0xFFL);
650
651 mutex_lock(&dev_info->mlock);
652 switch (this_attr->address) {
653 case AD7280A_CELL_OVERVOLTAGE:
654 st->cell_threshhigh = val;
655 break;
656 case AD7280A_CELL_UNDERVOLTAGE:
657 st->cell_threshlow = val;
658 break;
659 case AD7280A_AUX_ADC_OVERVOLTAGE:
660 st->aux_threshhigh = val;
661 break;
662 case AD7280A_AUX_ADC_UNDERVOLTAGE:
663 st->aux_threshlow = val;
664 break;
665 }
666
667 ret = ad7280_write(st, AD7280A_DEVADDR_MASTER,
668 this_attr->address, 1, val);
669
670 mutex_unlock(&dev_info->mlock);
671
672 return ret ? ret : len;
673 }
674
675 static irqreturn_t ad7280_event_handler(int irq, void *private)
676 {
677 struct iio_dev *dev_info = private;
678 struct ad7280_state *st = iio_priv(dev_info);
679 unsigned *channels;
680 int i, ret;
681
682 channels = kzalloc(sizeof(*channels) * st->scan_cnt, GFP_KERNEL);
683 if (channels == NULL)
684 return IRQ_HANDLED;
685
686 ret = ad7280_read_all_channels(st, st->scan_cnt, channels);
687 if (ret < 0)
688 return IRQ_HANDLED;
689
690 for (i = 0; i < st->scan_cnt; i++) {
691 if (((channels[i] >> 23) & 0xF) <= AD7280A_CELL_VOLTAGE_6) {
692 if (((channels[i] >> 11) & 0xFFF) >=
693 st->cell_threshhigh)
694 iio_push_event(dev_info, 0,
695 IIO_UNMOD_EVENT_CODE(IIO_IN_DIFF,
696 0,
697 IIO_EV_TYPE_THRESH,
698 IIO_EV_DIR_RISING),
699 iio_get_time_ns());
700 else if (((channels[i] >> 11) & 0xFFF) <=
701 st->cell_threshlow)
702 iio_push_event(dev_info, 0,
703 IIO_UNMOD_EVENT_CODE(IIO_IN_DIFF,
704 0,
705 IIO_EV_TYPE_THRESH,
706 IIO_EV_DIR_FALLING),
707 iio_get_time_ns());
708 } else {
709 if (((channels[i] >> 11) & 0xFFF) >= st->aux_threshhigh)
710 iio_push_event(dev_info, 0,
711 IIO_UNMOD_EVENT_CODE(IIO_TEMP,
712 0,
713 IIO_EV_TYPE_THRESH,
714 IIO_EV_DIR_RISING),
715 iio_get_time_ns());
716 else if (((channels[i] >> 11) & 0xFFF) <=
717 st->aux_threshlow)
718 iio_push_event(dev_info, 0,
719 IIO_UNMOD_EVENT_CODE(IIO_TEMP,
720 0,
721 IIO_EV_TYPE_THRESH,
722 IIO_EV_DIR_FALLING),
723 iio_get_time_ns());
724 }
725 }
726
727 kfree(channels);
728
729 return IRQ_HANDLED;
730 }
731
732 static IIO_DEVICE_ATTR_NAMED(in_thresh_low_value,
733 in-in_thresh_low_value,
734 S_IRUGO | S_IWUSR,
735 ad7280_read_channel_config,
736 ad7280_write_channel_config,
737 AD7280A_CELL_UNDERVOLTAGE);
738
739 static IIO_DEVICE_ATTR_NAMED(in_thresh_high_value,
740 in-in_thresh_high_value,
741 S_IRUGO | S_IWUSR,
742 ad7280_read_channel_config,
743 ad7280_write_channel_config,
744 AD7280A_CELL_OVERVOLTAGE);
745
746 static IIO_DEVICE_ATTR(temp_thresh_low_value,
747 S_IRUGO | S_IWUSR,
748 ad7280_read_channel_config,
749 ad7280_write_channel_config,
750 AD7280A_AUX_ADC_UNDERVOLTAGE);
751
752 static IIO_DEVICE_ATTR(temp_thresh_high_value,
753 S_IRUGO | S_IWUSR,
754 ad7280_read_channel_config,
755 ad7280_write_channel_config,
756 AD7280A_AUX_ADC_OVERVOLTAGE);
757
758
759 static struct attribute *ad7280_event_attributes[] = {
760 &iio_dev_attr_in_thresh_low_value.dev_attr.attr,
761 &iio_dev_attr_in_thresh_high_value.dev_attr.attr,
762 &iio_dev_attr_temp_thresh_low_value.dev_attr.attr,
763 &iio_dev_attr_temp_thresh_high_value.dev_attr.attr,
764 NULL,
765 };
766
767 static struct attribute_group ad7280_event_attrs_group = {
768 .attrs = ad7280_event_attributes,
769 };
770
771 static int ad7280_read_raw(struct iio_dev *dev_info,
772 struct iio_chan_spec const *chan,
773 int *val,
774 int *val2,
775 long m)
776 {
777 struct ad7280_state *st = iio_priv(dev_info);
778 unsigned int scale_uv;
779 int ret;
780
781 switch (m) {
782 case 0:
783 mutex_lock(&dev_info->mlock);
784 if (chan->address == AD7280A_ALL_CELLS)
785 ret = ad7280_read_all_channels(st, st->scan_cnt, NULL);
786 else
787 ret = ad7280_read_channel(st, chan->address >> 8,
788 chan->address & 0xFF);
789 mutex_unlock(&dev_info->mlock);
790
791 if (ret < 0)
792 return ret;
793
794 *val = ret;
795
796 return IIO_VAL_INT;
797 case (1 << IIO_CHAN_INFO_SCALE_SHARED):
798 if ((chan->address & 0xFF) <= AD7280A_CELL_VOLTAGE_6)
799 scale_uv = (4000 * 1000) >> AD7280A_BITS;
800 else
801 scale_uv = (5000 * 1000) >> AD7280A_BITS;
802
803 *val = scale_uv / 1000;
804 *val2 = (scale_uv % 1000) * 1000;
805 return IIO_VAL_INT_PLUS_MICRO;
806 }
807 return -EINVAL;
808 }
809
810 static const struct iio_info ad7280_info = {
811 .read_raw = &ad7280_read_raw,
812 .num_interrupt_lines = 1,
813 .event_attrs = &ad7280_event_attrs_group,
814 .attrs = &ad7280_attrs_group,
815 .driver_module = THIS_MODULE,
816 };
817
818 static const struct ad7280_platform_data ad7793_default_pdata = {
819 .acquisition_time = AD7280A_ACQ_TIME_400ns,
820 .conversion_averaging = AD7280A_CONV_AVG_DIS,
821 .thermistor_term_en = true,
822 };
823
824 static int __devinit ad7280_probe(struct spi_device *spi)
825 {
826 const struct ad7280_platform_data *pdata = spi->dev.platform_data;
827 struct ad7280_state *st;
828 int ret, regdone = 0;
829 const unsigned short tACQ_ns[4] = {465, 1010, 1460, 1890};
830 const unsigned short nAVG[4] = {1, 2, 4, 8};
831 struct iio_dev *indio_dev = iio_allocate_device(sizeof(*st));
832
833 if (indio_dev == NULL)
834 return -ENOMEM;
835
836 st = iio_priv(indio_dev);
837 spi_set_drvdata(spi, indio_dev);
838 st->spi = spi;
839
840 if (!pdata)
841 pdata = &ad7793_default_pdata;
842
843 ad7280_crc8_build_table(st->crc_tab);
844
845 st->spi->max_speed_hz = AD7280A_MAX_SPI_CLK_Hz;
846 st->spi->mode = SPI_MODE_1;
847 spi_setup(st->spi);
848
849 st->ctrl_lb = AD7280A_CTRL_LB_ACQ_TIME(pdata->acquisition_time & 0x3);
850 st->ctrl_hb = AD7280A_CTRL_HB_CONV_AVG(pdata->conversion_averaging
851 & 0x3) | (pdata->thermistor_term_en ?
852 AD7280A_CTRL_LB_THERMISTOR_EN : 0);
853
854 ret = ad7280_chain_setup(st);
855 if (ret < 0)
856 goto error_free_device;
857
858 st->slave_num = ret;
859 st->scan_cnt = (st->slave_num + 1) * AD7280A_NUM_CH;
860 st->cell_threshhigh = 0xFF;
861 st->aux_threshhigh = 0xFF;
862
863 /*
864 * Total Conversion Time = ((tACQ + tCONV) *
865 * (Number of Conversions per Part)) −
866 * tACQ + ((N - 1) * tDELAY)
867 *
868 * Readback Delay = Total Conversion Time + tWAIT
869 */
870
871 st->readback_delay_us =
872 ((tACQ_ns[pdata->acquisition_time & 0x3] + 695) *
873 (AD7280A_NUM_CH * nAVG[pdata->conversion_averaging & 0x3]))
874 - tACQ_ns[pdata->acquisition_time & 0x3] +
875 st->slave_num * 250;
876
877 /* Convert to usecs */
878 st->readback_delay_us = DIV_ROUND_UP(st->readback_delay_us, 1000);
879 st->readback_delay_us += 5; /* Add tWAIT */
880
881 indio_dev->name = spi_get_device_id(spi)->name;
882 indio_dev->dev.parent = &spi->dev;
883 indio_dev->modes = INDIO_DIRECT_MODE;
884
885 ret = ad7280_channel_init(st);
886 if (ret < 0)
887 goto error_free_device;
888
889 indio_dev->num_channels = ret;
890 indio_dev->channels = st->channels;
891 indio_dev->info = &ad7280_info;
892
893 ret = ad7280_attr_init(st);
894 if (ret < 0)
895 goto error_free_channels;
896
897 ret = iio_device_register(indio_dev);
898 if (ret)
899 goto error_free_attr;
900 regdone = 1;
901
902 if (spi->irq > 0) {
903 ret = ad7280_write(st, AD7280A_DEVADDR_MASTER,
904 AD7280A_ALERT, 1,
905 AD7280A_ALERT_RELAY_SIG_CHAIN_DOWN);
906 if (ret)
907 goto error_free_attr;
908
909 ret = ad7280_write(st, AD7280A_DEVADDR(st->slave_num),
910 AD7280A_ALERT, 0,
911 AD7280A_ALERT_GEN_STATIC_HIGH |
912 (pdata->chain_last_alert_ignore & 0xF));
913 if (ret)
914 goto error_free_attr;
915
916 ret = request_threaded_irq(spi->irq,
917 NULL,
918 ad7280_event_handler,
919 IRQF_TRIGGER_FALLING |
920 IRQF_ONESHOT,
921 indio_dev->name,
922 indio_dev);
923 if (ret)
924 goto error_free_attr;
925 }
926
927 return 0;
928
929 error_free_attr:
930 kfree(st->iio_attr);
931
932 error_free_channels:
933 kfree(st->channels);
934
935 error_free_device:
936 if (regdone)
937 iio_device_unregister(indio_dev);
938 else
939 iio_free_device(indio_dev);
940
941 return ret;
942 }
943
944 static int __devexit ad7280_remove(struct spi_device *spi)
945 {
946 struct iio_dev *indio_dev = spi_get_drvdata(spi);
947 struct ad7280_state *st = iio_priv(indio_dev);
948
949 if (spi->irq > 0)
950 free_irq(spi->irq, indio_dev);
951
952 ad7280_write(st, AD7280A_DEVADDR_MASTER, AD7280A_CONTROL_HB, 1,
953 AD7280A_CTRL_HB_PWRDN_SW | st->ctrl_hb);
954
955 kfree(st->channels);
956 kfree(st->iio_attr);
957 iio_device_unregister(indio_dev);
958
959 return 0;
960 }
961
962 static const struct spi_device_id ad7280_id[] = {
963 {"ad7280a", 0},
964 {}
965 };
966
967 static struct spi_driver ad7280_driver = {
968 .driver = {
969 .name = "ad7280",
970 .bus = &spi_bus_type,
971 .owner = THIS_MODULE,
972 },
973 .probe = ad7280_probe,
974 .remove = __devexit_p(ad7280_remove),
975 .id_table = ad7280_id,
976 };
977
978 static int __init ad7280_init(void)
979 {
980 return spi_register_driver(&ad7280_driver);
981 }
982 module_init(ad7280_init);
983
984 static void __exit ad7280_exit(void)
985 {
986 spi_unregister_driver(&ad7280_driver);
987 }
988 module_exit(ad7280_exit);
989
990 MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>");
991 MODULE_DESCRIPTION("Analog Devices AD7280A");
992 MODULE_LICENSE("GPL v2");
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree