drivers/net/wireless/iwlwifi/iwl-agn-ucode.c

   1 /******************************************************************************
   2  *
   3  * GPL LICENSE SUMMARY
   4  *
   5  * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of version 2 of the GNU General Public License as
   9  * published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful, but
  12  * WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
  19  * USA
  20  *
  21  * The full GNU General Public License is included in this distribution
  22  * in the file called LICENSE.GPL.
  23  *
  24  * Contact Information:
  25  *  Intel Linux Wireless <ilw@linux.intel.com>
  26  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27  *
  28  *****************************************************************************/
  29
  30 #include <linux/kernel.h>
  31 #include <linux/module.h>
  32 #include <linux/init.h>
  33 #include <linux/sched.h>
  34
  35 #include "iwl-dev.h"
  36 #include "iwl-core.h"
  37 #include "iwl-io.h"
  38 #include "iwl-helpers.h"
  39 #include "iwl-agn-hw.h"
  40 #include "iwl-agn.h"
  41 #include "iwl-agn-calib.h"
  42
  43 #define IWL_AC_UNSET -1
  44
  45 struct queue_to_fifo_ac {
  46         s8 fifo, ac;
  47 };
  48
  49 static const struct queue_to_fifo_ac iwlagn_default_queue_to_tx_fifo[] = {
  50         { IWL_TX_FIFO_VO, IEEE80211_AC_VO, },
  51         { IWL_TX_FIFO_VI, IEEE80211_AC_VI, },
  52         { IWL_TX_FIFO_BE, IEEE80211_AC_BE, },
  53         { IWL_TX_FIFO_BK, IEEE80211_AC_BK, },
  54         { IWLAGN_CMD_FIFO_NUM, IWL_AC_UNSET, },
  55         { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
  56         { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
  57         { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
  58         { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
  59         { IWL_TX_FIFO_UNUSED, IWL_AC_UNSET, },
  60 };
  61
  62 static const struct queue_to_fifo_ac iwlagn_ipan_queue_to_tx_fifo[] = {
  63         { IWL_TX_FIFO_VO, IEEE80211_AC_VO, },
  64         { IWL_TX_FIFO_VI, IEEE80211_AC_VI, },
  65         { IWL_TX_FIFO_BE, IEEE80211_AC_BE, },
  66         { IWL_TX_FIFO_BK, IEEE80211_AC_BK, },
  67         { IWL_TX_FIFO_BK_IPAN, IEEE80211_AC_BK, },
  68         { IWL_TX_FIFO_BE_IPAN, IEEE80211_AC_BE, },
  69         { IWL_TX_FIFO_VI_IPAN, IEEE80211_AC_VI, },
  70         { IWL_TX_FIFO_VO_IPAN, IEEE80211_AC_VO, },
  71         { IWL_TX_FIFO_BE_IPAN, 2, },
  72         { IWLAGN_CMD_FIFO_NUM, IWL_AC_UNSET, },
  73 };
  74
  75 static struct iwl_wimax_coex_event_entry cu_priorities[COEX_NUM_OF_EVENTS] = {
  76         {COEX_CU_UNASSOC_IDLE_RP, COEX_CU_UNASSOC_IDLE_WP,
  77          0, COEX_UNASSOC_IDLE_FLAGS},
  78         {COEX_CU_UNASSOC_MANUAL_SCAN_RP, COEX_CU_UNASSOC_MANUAL_SCAN_WP,
  79          0, COEX_UNASSOC_MANUAL_SCAN_FLAGS},
  80         {COEX_CU_UNASSOC_AUTO_SCAN_RP, COEX_CU_UNASSOC_AUTO_SCAN_WP,
  81          0, COEX_UNASSOC_AUTO_SCAN_FLAGS},
  82         {COEX_CU_CALIBRATION_RP, COEX_CU_CALIBRATION_WP,
  83          0, COEX_CALIBRATION_FLAGS},
  84         {COEX_CU_PERIODIC_CALIBRATION_RP, COEX_CU_PERIODIC_CALIBRATION_WP,
  85          0, COEX_PERIODIC_CALIBRATION_FLAGS},
  86         {COEX_CU_CONNECTION_ESTAB_RP, COEX_CU_CONNECTION_ESTAB_WP,
  87          0, COEX_CONNECTION_ESTAB_FLAGS},
  88         {COEX_CU_ASSOCIATED_IDLE_RP, COEX_CU_ASSOCIATED_IDLE_WP,
  89          0, COEX_ASSOCIATED_IDLE_FLAGS},
  90         {COEX_CU_ASSOC_MANUAL_SCAN_RP, COEX_CU_ASSOC_MANUAL_SCAN_WP,
  91          0, COEX_ASSOC_MANUAL_SCAN_FLAGS},
  92         {COEX_CU_ASSOC_AUTO_SCAN_RP, COEX_CU_ASSOC_AUTO_SCAN_WP,
  93          0, COEX_ASSOC_AUTO_SCAN_FLAGS},
  94         {COEX_CU_ASSOC_ACTIVE_LEVEL_RP, COEX_CU_ASSOC_ACTIVE_LEVEL_WP,
  95          0, COEX_ASSOC_ACTIVE_LEVEL_FLAGS},
  96         {COEX_CU_RF_ON_RP, COEX_CU_RF_ON_WP, 0, COEX_CU_RF_ON_FLAGS},
  97         {COEX_CU_RF_OFF_RP, COEX_CU_RF_OFF_WP, 0, COEX_RF_OFF_FLAGS},
  98         {COEX_CU_STAND_ALONE_DEBUG_RP, COEX_CU_STAND_ALONE_DEBUG_WP,
  99          0, COEX_STAND_ALONE_DEBUG_FLAGS},
 100         {COEX_CU_IPAN_ASSOC_LEVEL_RP, COEX_CU_IPAN_ASSOC_LEVEL_WP,
 101          0, COEX_IPAN_ASSOC_LEVEL_FLAGS},
 102         {COEX_CU_RSRVD1_RP, COEX_CU_RSRVD1_WP, 0, COEX_RSRVD1_FLAGS},
 103         {COEX_CU_RSRVD2_RP, COEX_CU_RSRVD2_WP, 0, COEX_RSRVD2_FLAGS}
 104 };
 105
 106 /*
 107  * ucode
 108  */
 109 static int iwlagn_load_section(struct iwl_priv *priv, const char *name,
 110                                 struct fw_desc *image, u32 dst_addr)
 111 {
 112         dma_addr_t phy_addr = image->p_addr;
 113         u32 byte_cnt = image->len;
 114         int ret;
 115
 116         priv->ucode_write_complete = 0;
 117
 118         iwl_write_direct32(priv,
 119                 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 120                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
 121
 122         iwl_write_direct32(priv,
 123                 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), dst_addr);
 124
 125         iwl_write_direct32(priv,
 126                 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
 127                 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
 128
 129         iwl_write_direct32(priv,
 130                 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
 131                 (iwl_get_dma_hi_addr(phy_addr)
 132                         << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
 133
 134         iwl_write_direct32(priv,
 135                 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
 136                 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
 137                 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
 138                 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
 139
 140         iwl_write_direct32(priv,
 141                 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 142                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE       |
 143                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE    |
 144                 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
 145
 146         IWL_DEBUG_FW(priv, "%s uCode section being loaded...\n", name);
 147         ret = wait_event_interruptible_timeout(priv->wait_command_queue,
 148                                         priv->ucode_write_complete, 5 * HZ);
 149         if (ret == -ERESTARTSYS) {
 150                 IWL_ERR(priv, "Could not load the %s uCode section due "
 151                         "to interrupt\n", name);
 152                 return ret;
 153         }
 154         if (!ret) {
 155                 IWL_ERR(priv, "Could not load the %s uCode section\n",
 156                         name);
 157                 return -ETIMEDOUT;
 158         }
 159
 160         return 0;
 161 }
 162
 163 static int iwlagn_load_given_ucode(struct iwl_priv *priv,
 164                                    struct fw_img *image)
 165 {
 166         int ret = 0;
 167
 168         ret = iwlagn_load_section(priv, "INST", &image->code,
 169                                    IWLAGN_RTC_INST_LOWER_BOUND);
 170         if (ret)
 171                 return ret;
 172
 173         return iwlagn_load_section(priv, "DATA", &image->data,
 174                                     IWLAGN_RTC_DATA_LOWER_BOUND);
 175 }
 176
 177 /*
 178  *  Calibration
 179  */
 180 static int iwlagn_set_Xtal_calib(struct iwl_priv *priv)
 181 {
 182         struct iwl_calib_xtal_freq_cmd cmd;
 183         __le16 *xtal_calib =
 184                 (__le16 *)iwl_eeprom_query_addr(priv, EEPROM_XTAL);
 185
 186         iwl_set_calib_hdr(&cmd.hdr, IWL_PHY_CALIBRATE_CRYSTAL_FRQ_CMD);
 187         cmd.cap_pin1 = le16_to_cpu(xtal_calib[0]);
 188         cmd.cap_pin2 = le16_to_cpu(xtal_calib[1]);
 189         return iwl_calib_set(&priv->calib_results[IWL_CALIB_XTAL],
 190                              (u8 *)&cmd, sizeof(cmd));
 191 }
 192
 193 static int iwlagn_set_temperature_offset_calib(struct iwl_priv *priv)
 194 {
 195         struct iwl_calib_temperature_offset_cmd cmd;
 196         __le16 *offset_calib =
 197                 (__le16 *)iwl_eeprom_query_addr(priv, EEPROM_TEMPERATURE);
 198
 199         memset(&cmd, 0, sizeof(cmd));
 200         iwl_set_calib_hdr(&cmd.hdr, IWL_PHY_CALIBRATE_TEMP_OFFSET_CMD);
 201         cmd.radio_sensor_offset = le16_to_cpu(offset_calib[1]);
 202         if (!(cmd.radio_sensor_offset))
 203                 cmd.radio_sensor_offset = DEFAULT_RADIO_SENSOR_OFFSET;
 204
 205         IWL_DEBUG_CALIB(priv, "Radio sensor offset: %d\n",
 206                         cmd.radio_sensor_offset);
 207         return iwl_calib_set(&priv->calib_results[IWL_CALIB_TEMP_OFFSET],
 208                              (u8 *)&cmd, sizeof(cmd));
 209 }
 210
 211 static int iwlagn_send_calib_cfg(struct iwl_priv *priv)
 212 {
 213         struct iwl_calib_cfg_cmd calib_cfg_cmd;
 214         struct iwl_host_cmd cmd = {
 215                 .id = CALIBRATION_CFG_CMD,
 216                 .len = { sizeof(struct iwl_calib_cfg_cmd), },
 217                 .data = { &calib_cfg_cmd, },
 218         };
 219
 220         memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd));
 221         calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL;
 222         calib_cfg_cmd.ucd_calib_cfg.once.start = IWL_CALIB_INIT_CFG_ALL;
 223         calib_cfg_cmd.ucd_calib_cfg.once.send_res = IWL_CALIB_INIT_CFG_ALL;
 224         calib_cfg_cmd.ucd_calib_cfg.flags = IWL_CALIB_INIT_CFG_ALL;
 225
 226         return iwl_send_cmd(priv, &cmd);
 227 }
 228
 229 void iwlagn_rx_calib_result(struct iwl_priv *priv,
 230                              struct iwl_rx_mem_buffer *rxb)
 231 {
 232         struct iwl_rx_packet *pkt = rxb_addr(rxb);
 233         struct iwl_calib_hdr *hdr = (struct iwl_calib_hdr *)pkt->u.raw;
 234         int len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
 235         int index;
 236
 237         /* reduce the size of the length field itself */
 238         len -= 4;
 239
 240         /* Define the order in which the results will be sent to the runtime
 241          * uCode. iwl_send_calib_results sends them in a row according to
 242          * their index. We sort them here
 243          */
 244         switch (hdr->op_code) {
 245         case IWL_PHY_CALIBRATE_DC_CMD:
 246                 index = IWL_CALIB_DC;
 247                 break;
 248         case IWL_PHY_CALIBRATE_LO_CMD:
 249                 index = IWL_CALIB_LO;
 250                 break;
 251         case IWL_PHY_CALIBRATE_TX_IQ_CMD:
 252                 index = IWL_CALIB_TX_IQ;
 253                 break;
 254         case IWL_PHY_CALIBRATE_TX_IQ_PERD_CMD:
 255                 index = IWL_CALIB_TX_IQ_PERD;
 256                 break;
 257         case IWL_PHY_CALIBRATE_BASE_BAND_CMD:
 258                 index = IWL_CALIB_BASE_BAND;
 259                 break;
 260         default:
 261                 IWL_ERR(priv, "Unknown calibration notification %d\n",
 262                           hdr->op_code);
 263                 return;
 264         }
 265         iwl_calib_set(&priv->calib_results[index], pkt->u.raw, len);
 266 }
 267
 268 int iwlagn_init_alive_start(struct iwl_priv *priv)
 269 {
 270         int ret;
 271
 272         if (priv->cfg->bt_params &&
 273             priv->cfg->bt_params->advanced_bt_coexist) {
 274                 /*
 275                  * Tell uCode we are ready to perform calibration
 276                  * need to perform this before any calibration
 277                  * no need to close the envlope since we are going
 278                  * to load the runtime uCode later.
 279                  */
 280                 ret = iwlagn_send_bt_env(priv, IWL_BT_COEX_ENV_OPEN,
 281                         BT_COEX_PRIO_TBL_EVT_INIT_CALIB2);
 282                 if (ret)
 283                         return ret;
 284
 285         }
 286
 287         ret = iwlagn_send_calib_cfg(priv);
 288         if (ret)
 289                 return ret;
 290
 291         /**
 292          * temperature offset calibration is only needed for runtime ucode,
 293          * so prepare the value now.
 294          */
 295         if (priv->cfg->need_temp_offset_calib)
 296                 return iwlagn_set_temperature_offset_calib(priv);
 297
 298         return 0;
 299 }
 300
 301 static int iwlagn_send_wimax_coex(struct iwl_priv *priv)
 302 {
 303         struct iwl_wimax_coex_cmd coex_cmd;
 304
 305         if (priv->cfg->base_params->support_wimax_coexist) {
 306                 /* UnMask wake up src at associated sleep */
 307                 coex_cmd.flags = COEX_FLAGS_ASSOC_WA_UNMASK_MSK;
 308
 309                 /* UnMask wake up src at unassociated sleep */
 310                 coex_cmd.flags |= COEX_FLAGS_UNASSOC_WA_UNMASK_MSK;
 311                 memcpy(coex_cmd.sta_prio, cu_priorities,
 312                         sizeof(struct iwl_wimax_coex_event_entry) *
 313                          COEX_NUM_OF_EVENTS);
 314
 315                 /* enabling the coexistence feature */
 316                 coex_cmd.flags |= COEX_FLAGS_COEX_ENABLE_MSK;
 317
 318                 /* enabling the priorities tables */
 319                 coex_cmd.flags |= COEX_FLAGS_STA_TABLE_VALID_MSK;
 320         } else {
 321                 /* coexistence is disabled */
 322                 memset(&coex_cmd, 0, sizeof(coex_cmd));
 323         }
 324         return iwl_send_cmd_pdu(priv, COEX_PRIORITY_TABLE_CMD,
 325                                 sizeof(coex_cmd), &coex_cmd);
 326 }
 327
 328 static const u8 iwlagn_bt_prio_tbl[BT_COEX_PRIO_TBL_EVT_MAX] = {
 329         ((BT_COEX_PRIO_TBL_PRIO_BYPASS << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
 330                 (0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
 331         ((BT_COEX_PRIO_TBL_PRIO_BYPASS << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
 332                 (1 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
 333         ((BT_COEX_PRIO_TBL_PRIO_LOW << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
 334                 (0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
 335         ((BT_COEX_PRIO_TBL_PRIO_LOW << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
 336                 (1 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
 337         ((BT_COEX_PRIO_TBL_PRIO_HIGH << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
 338                 (0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
 339         ((BT_COEX_PRIO_TBL_PRIO_HIGH << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
 340                 (1 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
 341         ((BT_COEX_PRIO_TBL_PRIO_BYPASS << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
 342                 (0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
 343         ((BT_COEX_PRIO_TBL_PRIO_COEX_OFF << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
 344                 (0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
 345         ((BT_COEX_PRIO_TBL_PRIO_COEX_ON << IWL_BT_COEX_PRIO_TBL_PRIO_POS) |
 346                 (0 << IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS)),
 347         0, 0, 0, 0, 0, 0, 0
 348 };
 349
 350 void iwlagn_send_prio_tbl(struct iwl_priv *priv)
 351 {
 352         struct iwl_bt_coex_prio_table_cmd prio_tbl_cmd;
 353
 354         memcpy(prio_tbl_cmd.prio_tbl, iwlagn_bt_prio_tbl,
 355                 sizeof(iwlagn_bt_prio_tbl));
 356         if (iwl_send_cmd_pdu(priv, REPLY_BT_COEX_PRIO_TABLE,
 357                                 sizeof(prio_tbl_cmd), &prio_tbl_cmd))
 358                 IWL_ERR(priv, "failed to send BT prio tbl command\n");
 359 }
 360
 361 int iwlagn_send_bt_env(struct iwl_priv *priv, u8 action, u8 type)
 362 {
 363         struct iwl_bt_coex_prot_env_cmd env_cmd;
 364         int ret;
 365
 366         env_cmd.action = action;
 367         env_cmd.type = type;
 368         ret = iwl_send_cmd_pdu(priv, REPLY_BT_COEX_PROT_ENV,
 369                                sizeof(env_cmd), &env_cmd);
 370         if (ret)
 371                 IWL_ERR(priv, "failed to send BT env command\n");
 372         return ret;
 373 }
 374
 375
 376 static int iwlagn_alive_notify(struct iwl_priv *priv)
 377 {
 378         const struct queue_to_fifo_ac *queue_to_fifo;
 379         struct iwl_rxon_context *ctx;
 380         u32 a;
 381         unsigned long flags;
 382         int i, chan;
 383         u32 reg_val;
 384         int ret;
 385
 386         spin_lock_irqsave(&priv->lock, flags);
 387
 388         priv->scd_base_addr = iwl_read_prph(priv, IWLAGN_SCD_SRAM_BASE_ADDR);
 389         a = priv->scd_base_addr + IWLAGN_SCD_CONTEXT_DATA_OFFSET;
 390         for (; a < priv->scd_base_addr + IWLAGN_SCD_TX_STTS_BITMAP_OFFSET;
 391                 a += 4)
 392                 iwl_write_targ_mem(priv, a, 0);
 393         for (; a < priv->scd_base_addr + IWLAGN_SCD_TRANSLATE_TBL_OFFSET;
 394                 a += 4)
 395                 iwl_write_targ_mem(priv, a, 0);
 396         for (; a < priv->scd_base_addr +
 397                IWLAGN_SCD_TRANSLATE_TBL_OFFSET_QUEUE(priv->hw_params.max_txq_num); a += 4)
 398                 iwl_write_targ_mem(priv, a, 0);
 399
 400         iwl_write_prph(priv, IWLAGN_SCD_DRAM_BASE_ADDR,
 401                        priv->scd_bc_tbls.dma >> 10);
 402
 403         /* Enable DMA channel */
 404         for (chan = 0; chan < FH50_TCSR_CHNL_NUM ; chan++)
 405                 iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
 406                                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
 407                                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
 408
 409         /* Update FH chicken bits */
 410         reg_val = iwl_read_direct32(priv, FH_TX_CHICKEN_BITS_REG);
 411         iwl_write_direct32(priv, FH_TX_CHICKEN_BITS_REG,
 412                            reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
 413
 414         iwl_write_prph(priv, IWLAGN_SCD_QUEUECHAIN_SEL,
 415                 IWLAGN_SCD_QUEUECHAIN_SEL_ALL(priv));
 416         iwl_write_prph(priv, IWLAGN_SCD_AGGR_SEL, 0);
 417
 418         /* initiate the queues */
 419         for (i = 0; i < priv->hw_params.max_txq_num; i++) {
 420                 iwl_write_prph(priv, IWLAGN_SCD_QUEUE_RDPTR(i), 0);
 421                 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
 422                 iwl_write_targ_mem(priv, priv->scd_base_addr +
 423                                 IWLAGN_SCD_CONTEXT_QUEUE_OFFSET(i), 0);
 424                 iwl_write_targ_mem(priv, priv->scd_base_addr +
 425                                 IWLAGN_SCD_CONTEXT_QUEUE_OFFSET(i) +
 426                                 sizeof(u32),
 427                                 ((SCD_WIN_SIZE <<
 428                                 IWLAGN_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
 429                                 IWLAGN_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
 430                                 ((SCD_FRAME_LIMIT <<
 431                                 IWLAGN_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
 432                                 IWLAGN_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
 433         }
 434
 435         iwl_write_prph(priv, IWLAGN_SCD_INTERRUPT_MASK,
 436                         IWL_MASK(0, priv->hw_params.max_txq_num));
 437
 438         /* Activate all Tx DMA/FIFO channels */
 439         iwlagn_txq_set_sched(priv, IWL_MASK(0, 7));
 440
 441         /* map queues to FIFOs */
 442         if (priv->valid_contexts != BIT(IWL_RXON_CTX_BSS))
 443                 queue_to_fifo = iwlagn_ipan_queue_to_tx_fifo;
 444         else
 445                 queue_to_fifo = iwlagn_default_queue_to_tx_fifo;
 446
 447         iwlagn_set_wr_ptrs(priv, priv->cmd_queue, 0);
 448
 449         /* make sure all queue are not stopped */
 450         memset(&priv->queue_stopped[0], 0, sizeof(priv->queue_stopped));
 451         for (i = 0; i < 4; i++)
 452                 atomic_set(&priv->queue_stop_count[i], 0);
 453         for_each_context(priv, ctx)
 454                 ctx->last_tx_rejected = false;
 455
 456         /* reset to 0 to enable all the queue first */
 457         priv->txq_ctx_active_msk = 0;
 458
 459         BUILD_BUG_ON(ARRAY_SIZE(iwlagn_default_queue_to_tx_fifo) != 10);
 460         BUILD_BUG_ON(ARRAY_SIZE(iwlagn_ipan_queue_to_tx_fifo) != 10);
 461
 462         for (i = 0; i < 10; i++) {
 463                 int fifo = queue_to_fifo[i].fifo;
 464                 int ac = queue_to_fifo[i].ac;
 465
 466                 iwl_txq_ctx_activate(priv, i);
 467
 468                 if (fifo == IWL_TX_FIFO_UNUSED)
 469                         continue;
 470
 471                 if (ac != IWL_AC_UNSET)
 472                         iwl_set_swq_id(&priv->txq[i], ac, i);
 473                 iwlagn_tx_queue_set_status(priv, &priv->txq[i], fifo, 0);
 474         }
 475
 476         spin_unlock_irqrestore(&priv->lock, flags);
 477
 478         /* Enable L1-Active */
 479         iwl_clear_bits_prph(priv, APMG_PCIDEV_STT_REG,
 480                           APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
 481
 482         ret = iwlagn_send_wimax_coex(priv);
 483         if (ret)
 484                 return ret;
 485
 486         ret = iwlagn_set_Xtal_calib(priv);
 487         if (ret)
 488                 return ret;
 489
 490         return iwl_send_calib_results(priv);
 491 }
 492
 493
 494 /**
 495  * iwl_verify_inst_sparse - verify runtime uCode image in card vs. host,
 496  *   using sample data 100 bytes apart.  If these sample points are good,
 497  *   it's a pretty good bet that everything between them is good, too.
 498  */
 499 static int iwlcore_verify_inst_sparse(struct iwl_priv *priv,
 500                                       struct fw_desc *fw_desc)
 501 {
 502         __le32 *image = (__le32 *)fw_desc->v_addr;
 503         u32 len = fw_desc->len;
 504         u32 val;
 505         u32 i;
 506
 507         IWL_DEBUG_FW(priv, "ucode inst image size is %u\n", len);
 508
 509         for (i = 0; i < len; i += 100, image += 100/sizeof(u32)) {
 510                 /* read data comes through single port, auto-incr addr */
 511                 /* NOTE: Use the debugless read so we don't flood kernel log
 512                  * if IWL_DL_IO is set */
 513                 iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
 514                         i + IWLAGN_RTC_INST_LOWER_BOUND);
 515                 val = iwl_read32(priv, HBUS_TARG_MEM_RDAT);
 516                 if (val != le32_to_cpu(*image))
 517                         return -EIO;
 518         }
 519
 520         return 0;
 521 }
 522
 523 static void iwl_print_mismatch_inst(struct iwl_priv *priv,
 524                                     struct fw_desc *fw_desc)
 525 {
 526         __le32 *image = (__le32 *)fw_desc->v_addr;
 527         u32 len = fw_desc->len;
 528         u32 val;
 529         u32 offs;
 530         int errors = 0;
 531
 532         IWL_DEBUG_FW(priv, "ucode inst image size is %u\n", len);
 533
 534         iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR,
 535                            IWLAGN_RTC_INST_LOWER_BOUND);
 536
 537         for (offs = 0;
 538              offs < len && errors < 20;
 539              offs += sizeof(u32), image++) {
 540                 /* read data comes through single port, auto-incr addr */
 541                 val = iwl_read32(priv, HBUS_TARG_MEM_RDAT);
 542                 if (val != le32_to_cpu(*image)) {
 543                         IWL_ERR(priv, "uCode INST section at "
 544                                 "offset 0x%x, is 0x%x, s/b 0x%x\n",
 545                                 offs, val, le32_to_cpu(*image));
 546                         errors++;
 547                 }
 548         }
 549 }
 550
 551 /**
 552  * iwl_verify_ucode - determine which instruction image is in SRAM,
 553  *    and verify its contents
 554  */
 555 static int iwl_verify_ucode(struct iwl_priv *priv, struct fw_img *img)
 556 {
 557         if (!iwlcore_verify_inst_sparse(priv, &img->code)) {
 558                 IWL_DEBUG_FW(priv, "uCode is good in inst SRAM\n");
 559                 return 0;
 560         }
 561
 562         IWL_ERR(priv, "UCODE IMAGE IN INSTRUCTION SRAM NOT VALID!!\n");
 563
 564         iwl_print_mismatch_inst(priv, &img->code);
 565         return -EIO;
 566 }
 567
 568 struct iwlagn_alive_data {
 569         bool valid;
 570         u8 subtype;
 571 };
 572
 573 static void iwlagn_alive_fn(struct iwl_priv *priv,
 574                             struct iwl_rx_packet *pkt,
 575                             void *data)
 576 {
 577         struct iwlagn_alive_data *alive_data = data;
 578         struct iwl_alive_resp *palive;
 579
 580         palive = &pkt->u.alive_frame;
 581
 582         IWL_DEBUG_FW(priv, "Alive ucode status 0x%08X revision "
 583                        "0x%01X 0x%01X\n",
 584                        palive->is_valid, palive->ver_type,
 585                        palive->ver_subtype);
 586
 587         priv->device_pointers.error_event_table =
 588                 le32_to_cpu(palive->error_event_table_ptr);
 589         priv->device_pointers.log_event_table =
 590                 le32_to_cpu(palive->log_event_table_ptr);
 591
 592         alive_data->subtype = palive->ver_subtype;
 593         alive_data->valid = palive->is_valid == UCODE_VALID_OK;
 594 }
 595
 596 #define UCODE_ALIVE_TIMEOUT     HZ
 597 #define UCODE_CALIB_TIMEOUT     (2*HZ)
 598
 599 int iwlagn_load_ucode_wait_alive(struct iwl_priv *priv,
 600                                  struct fw_img *image,
 601                                  enum iwlagn_ucode_type ucode_type)
 602 {
 603         struct iwl_notification_wait alive_wait;
 604         struct iwlagn_alive_data alive_data;
 605         int ret;
 606         enum iwlagn_ucode_type old_type;
 607
 608         ret = iwlagn_start_device(priv);
 609         if (ret)
 610                 return ret;
 611
 612         iwlagn_init_notification_wait(priv, &alive_wait, REPLY_ALIVE,
 613                                       iwlagn_alive_fn, &alive_data);
 614
 615         old_type = priv->ucode_type;
 616         priv->ucode_type = ucode_type;
 617
 618         ret = iwlagn_load_given_ucode(priv, image);
 619         if (ret) {
 620                 priv->ucode_type = old_type;
 621                 iwlagn_remove_notification(priv, &alive_wait);
 622                 return ret;
 623         }
 624
 625         /* Remove all resets to allow NIC to operate */
 626         iwl_write32(priv, CSR_RESET, 0);
 627
 628         /*
 629          * Some things may run in the background now, but we
 630          * just wait for the ALIVE notification here.
 631          */
 632         ret = iwlagn_wait_notification(priv, &alive_wait, UCODE_ALIVE_TIMEOUT);
 633         if (ret) {
 634                 priv->ucode_type = old_type;
 635                 return ret;
 636         }
 637
 638         if (!alive_data.valid) {
 639                 IWL_ERR(priv, "Loaded ucode is not valid!\n");
 640                 priv->ucode_type = old_type;
 641                 return -EIO;
 642         }
 643
 644         ret = iwl_verify_ucode(priv, image);
 645         if (ret) {
 646                 priv->ucode_type = old_type;
 647                 return ret;
 648         }
 649
 650         /* delay a bit to give rfkill time to run */
 651         msleep(5);
 652
 653         ret = iwlagn_alive_notify(priv);
 654         if (ret) {
 655                 IWL_WARN(priv,
 656                         "Could not complete ALIVE transition: %d\n", ret);
 657                 priv->ucode_type = old_type;
 658                 return ret;
 659         }
 660
 661         return 0;
 662 }
 663
 664 int iwlagn_run_init_ucode(struct iwl_priv *priv)
 665 {
 666         struct iwl_notification_wait calib_wait;
 667         int ret;
 668
 669         lockdep_assert_held(&priv->mutex);
 670
 671         /* No init ucode required? Curious, but maybe ok */
 672         if (!priv->ucode_init.code.len)
 673                 return 0;
 674
 675         if (priv->ucode_type != IWL_UCODE_NONE)
 676                 return 0;
 677
 678         iwlagn_init_notification_wait(priv, &calib_wait,
 679                                       CALIBRATION_COMPLETE_NOTIFICATION,
 680                                       NULL, NULL);
 681
 682         /* Will also start the device */
 683         ret = iwlagn_load_ucode_wait_alive(priv, &priv->ucode_init,
 684                                            IWL_UCODE_INIT);
 685         if (ret)
 686                 goto error;
 687
 688         ret = iwlagn_init_alive_start(priv);
 689         if (ret)
 690                 goto error;
 691
 692         /*
 693          * Some things may run in the background now, but we
 694          * just wait for the calibration complete notification.
 695          */
 696         ret = iwlagn_wait_notification(priv, &calib_wait, UCODE_CALIB_TIMEOUT);
 697
 698         goto out;
 699
 700  error:
 701         iwlagn_remove_notification(priv, &calib_wait);
 702  out:
 703         /* Whatever happened, stop the device */
 704         iwlagn_stop_device(priv);
 705         return ret;
 706 }