sound/pci/au88x0/au8830.h

   1 /*
   2     Aureal Vortex Soundcard driver.
   3
   4     IO addr collected from asp4core.vxd:
   5     function    address
   6     0005D5A0    13004
   7     00080674    14004
   8     00080AFF    12818
   9
  10  */
  11
  12 #define CHIP_AU8830
  13
  14 #define CARD_NAME "Aureal Vortex 2 3D Sound Processor"
  15 #define CARD_NAME_SHORT "au8830"
  16
  17 #define NR_ADB 0x20
  18 #define NR_SRC 0x10
  19 #define NR_A3D 0x10
  20 #define NR_MIXIN 0x20
  21 #define NR_MIXOUT 0x10
  22 #define NR_WT 0x40
  23
  24 /* ADBDMA */
  25 #define VORTEX_ADBDMA_STAT 0x27e00      /* read only, subbuffer, DMA pos */
  26 #define         POS_MASK 0x00000fff
  27 #define     POS_SHIFT 0x0
  28 #define         ADB_SUBBUF_MASK 0x00003000      /* ADB only. */
  29 #define     ADB_SUBBUF_SHIFT 0xc        /* ADB only. */
  30 #define VORTEX_ADBDMA_CTRL 0x27a00      /* write only; format, flags, DMA pos */
  31 #define         OFFSET_MASK 0x00000fff
  32 #define     OFFSET_SHIFT 0x0
  33 #define         IE_MASK 0x00001000      /* interrupt enable. */
  34 #define     IE_SHIFT 0xc
  35 #define     DIR_MASK 0x00002000 /* Direction. */
  36 #define     DIR_SHIFT 0xd
  37 #define         FMT_MASK 0x0003c000
  38 #define         FMT_SHIFT 0xe
  39 #define         ADB_FIFO_EN_SHIFT       0x15
  40 #define         ADB_FIFO_EN                     (1 << 0x15)
  41 // The ADB masks and shift also are valid for the wtdma, except if specified otherwise.
  42 #define VORTEX_ADBDMA_BUFCFG0 0x27800
  43 #define VORTEX_ADBDMA_BUFCFG1 0x27804
  44 #define VORTEX_ADBDMA_BUFBASE 0x27400
  45 #define VORTEX_ADBDMA_START 0x27c00     /* Which subbuffer starts */
  46
  47 #define VORTEX_ADBDMA_STATUS 0x27A90    /* stored at AdbDma->this_10 / 2 DWORD in size. */
  48 /* Starting at the MSB, each pair of bits seem to be the current DMA page. */
  49 /* This current page bits are consistent (same value) with VORTEX_ADBDMA_STAT) */
  50
  51 /* DMA */
  52 #define VORTEX_ENGINE_CTRL 0x27ae8
  53 #define         ENGINE_INIT 0x1380000
  54
  55 /* WTDMA */
  56 #define VORTEX_WTDMA_CTRL 0x27900       /* format, DMA pos */
  57 #define VORTEX_WTDMA_STAT 0x27d00       /* DMA subbuf, DMA pos */
  58 #define     WT_SUBBUF_MASK 0x3
  59 #define     WT_SUBBUF_SHIFT 0xc
  60 #define VORTEX_WTDMA_BUFBASE 0x27000
  61 #define VORTEX_WTDMA_BUFCFG0 0x27600
  62 #define VORTEX_WTDMA_BUFCFG1 0x27604
  63 #define VORTEX_WTDMA_START 0x27b00      /* which subbuffer is first */
  64
  65 /* ADB */
  66 #define VORTEX_ADB_SR 0x28400   /* Samplerates enable/disable */
  67 #define VORTEX_ADB_RTBASE 0x28000
  68 #define VORTEX_ADB_RTBASE_COUNT 173
  69 #define VORTEX_ADB_CHNBASE 0x282b4
  70 #define VORTEX_ADB_CHNBASE_COUNT 24
  71 #define         ROUTE_MASK      0xffff
  72 #define         SOURCE_MASK     0xff00
  73 #define     ADB_MASK   0xff
  74 #define         ADB_SHIFT 0x8
  75 /* ADB address */
  76 #define         OFFSET_ADBDMA   0x00
  77 #define         OFFSET_ADBDMAB  0x20
  78 #define         OFFSET_SRCIN    0x40
  79 #define         OFFSET_SRCOUT   0x20    /* ch 0x11 */
  80 #define         OFFSET_MIXIN    0x50    /* ch 0x11 */
  81 #define         OFFSET_MIXOUT   0x30    /* ch 0x11 */
  82 #define         OFFSET_CODECIN  0x70 /* ch 0x11 */      /* adb source */
  83 #define         OFFSET_CODECOUT 0x88 /* ch 0x11 */      /* adb target */
  84 #define         OFFSET_SPORTIN  0x78    /* ch 0x13 ADB source. 2 routes. */
  85 #define         OFFSET_SPORTOUT 0x90    /* ch 0x13 ADB sink. 2 routes. */
  86 #define         OFFSET_SPDIFIN  0x7A    /* ch 0x14 ADB source. */
  87 #define         OFFSET_SPDIFOUT 0x92    /* ch 0x14 ADB sink. */
  88 #define         OFFSET_AC98IN   0x7c    /* ch 0x14 ADB source. */
  89 #define         OFFSET_AC98OUT  0x94    /* ch 0x14 ADB sink. */
  90 #define         OFFSET_EQIN             0xa0    /* ch 0x11 */
  91 #define         OFFSET_EQOUT    0x7e /* ch 0x11 */      /* 2 routes on ch 0x11 */
  92 #define         OFFSET_A3DIN    0x70    /* ADB sink. */
  93 #define         OFFSET_A3DOUT   0xA6    /* ADB source. 2 routes per slice = 8 */
  94 #define         OFFSET_WT0              0x40    /* WT bank 0 output. 0x40 - 0x65 */
  95 #define         OFFSET_WT1              0x80    /* WT bank 1 output. 0x80 - 0xA5 */
  96 /* WT sources offset : 0x00-0x1f Direct stream. */
  97 /* WT sources offset : 0x20-0x25 Mixed Output. */
  98 #define         OFFSET_XTALKOUT 0x66    /* crosstalk canceller (source) 2 routes */
  99 #define         OFFSET_XTALKIN  0x96    /* crosstalk canceller (sink). 10 routes */
 100 #define         OFFSET_EFXOUT   0x68    /* ADB source. 8 routes. */
 101 #define         OFFSET_EFXIN    0x80    /* ADB sink. 8 routes. */
 102
 103 /* ADB route translate helper */
 104 #define ADB_DMA(x) (x)
 105 #define ADB_SRCOUT(x) (x + OFFSET_SRCOUT)
 106 #define ADB_SRCIN(x) (x + OFFSET_SRCIN)
 107 #define ADB_MIXOUT(x) (x + OFFSET_MIXOUT)
 108 #define ADB_MIXIN(x) (x + OFFSET_MIXIN)
 109 #define ADB_CODECIN(x) (x + OFFSET_CODECIN)
 110 #define ADB_CODECOUT(x) (x + OFFSET_CODECOUT)
 111 #define ADB_SPORTIN(x) (x + OFFSET_SPORTIN)
 112 #define ADB_SPORTOUT(x) (x + OFFSET_SPORTOUT)
 113 #define ADB_SPDIFIN(x)  (x + OFFSET_SPDIFIN)
 114 #define ADB_SPDIFOUT(x) (x + OFFSET_SPDIFOUT)
 115 #define ADB_EQIN(x) (x + OFFSET_EQIN)
 116 #define ADB_EQOUT(x) (x + OFFSET_EQOUT)
 117 #define ADB_A3DOUT(x) (x + OFFSET_A3DOUT)       /* 0x10 A3D blocks */
 118 #define ADB_A3DIN(x) (x + OFFSET_A3DIN)
 119 //#define ADB_WTOUT(x) ((x<x20)?(x + OFFSET_WT0):(x + OFFSET_WT1))
 120 #define ADB_WTOUT(x,y) (((x)==0)?((y) + OFFSET_WT0):((y) + OFFSET_WT1))
 121 #define ADB_XTALKIN(x) ((x) + OFFSET_XTALKIN)
 122 #define ADB_XTALKOUT(x) ((x) + OFFSET_XTALKOUT)
 123
 124 #define MIX_DEFIGAIN 0x08
 125 #define MIX_DEFOGAIN 0x08       /* 0x8->6dB  (6dB = x4) 16 to 18 bit conversion? */
 126
 127 /* MIXER */
 128 #define VORTEX_MIXER_SR 0x21f00
 129 #define VORTEX_MIXER_CLIP 0x21f80
 130 #define VORTEX_MIXER_CHNBASE 0x21e40
 131 #define VORTEX_MIXER_RTBASE 0x21e00
 132 #define         MIXER_RTBASE_SIZE 0x38
 133 #define VORTEX_MIX_ENIN 0x21a00 /* Input enable bits. 4 bits wide. */
 134 #define VORTEX_MIX_SMP 0x21c00  /* wave data buffers. AU8820: 0x9c00 */
 135
 136 /* MIX */
 137 #define VORTEX_MIX_INVOL_B 0x20000      /* Input volume current */
 138 #define VORTEX_MIX_VOL_B 0x20800        /* Output Volume current */
 139 #define VORTEX_MIX_INVOL_A 0x21000      /* Input Volume target */
 140 #define VORTEX_MIX_VOL_A 0x21800        /* Output Volume target */
 141
 142 #define         VOL_MIN 0x80    /* Input volume when muted. */
 143 #define         VOL_MAX 0x7f    /* FIXME: Not confirmed! Just guessed. */
 144
 145 /* SRC */
 146 #define VORTEX_SRC_CHNBASE              0x26c40
 147 #define VORTEX_SRC_RTBASE               0x26c00
 148 #define VORTEX_SRCBLOCK_SR              0x26cc0
 149 #define VORTEX_SRC_SOURCE               0x26cc4
 150 #define VORTEX_SRC_SOURCESIZE   0x26cc8
 151 /* Params
 152         0x26e00 : 1 U0
 153         0x26e40 : 2 CR
 154         0x26e80 : 3 U3
 155         0x26ec0 : 4 DRIFT1
 156         0x26f00 : 5 U1
 157         0x26f40 : 6 DRIFT2
 158         0x26f80 : 7 U2 : Target rate, direction
 159 */
 160
 161 #define VORTEX_SRC_CONVRATIO    0x26e40
 162 #define VORTEX_SRC_DRIFT0               0x26e80
 163 #define VORTEX_SRC_DRIFT1               0x26ec0
 164 #define VORTEX_SRC_DRIFT2               0x26f40
 165 #define VORTEX_SRC_U0                   0x26e00
 166 #define         U0_SLOWLOCK             0x200
 167 #define VORTEX_SRC_U1                   0x26f00
 168 #define VORTEX_SRC_U2                   0x26f80
 169 #define VORTEX_SRC_DATA                 0x26800 /* 0xc800 */
 170 #define VORTEX_SRC_DATA0                0x26000
 171
 172 /* FIFO */
 173 #define VORTEX_FIFO_ADBCTRL 0x16100     /* Control bits. */
 174 #define VORTEX_FIFO_WTCTRL 0x16000
 175 #define         FIFO_RDONLY     0x00000001
 176 #define         FIFO_CTRL       0x00000002      /* Allow ctrl. ? */
 177 #define         FIFO_VALID      0x00000010
 178 #define         FIFO_EMPTY      0x00000020
 179 #define         FIFO_U0         0x00002000      /* Unknown. */
 180 #define         FIFO_U1         0x00040000
 181 #define         FIFO_SIZE_BITS 6
 182 #define         FIFO_SIZE       (1<<(FIFO_SIZE_BITS))   // 0x40
 183 #define         FIFO_MASK       (FIFO_SIZE-1)   //0x3f    /* at shift left 0xc */
 184 #define         FIFO_BITS       0x1c400000
 185 #define VORTEX_FIFO_ADBDATA 0x14000
 186 #define VORTEX_FIFO_WTDATA 0x10000
 187
 188 #define VORTEX_FIFO_GIRT        0x17000 /* wt0, wt1, adb */
 189 #define         GIRT_COUNT      3
 190
 191 /* CODEC */
 192
 193 #define VORTEX_CODEC_CHN 0x29080        /* The name "CHN" is wrong. */
 194
 195 #define VORTEX_CODEC_CTRL 0x29184
 196 #define VORTEX_CODEC_IO 0x29188
 197 #define         VORTEX_CODEC_WRITE 0x00800000
 198 #define         VORTEX_CODEC_ADDSHIFT 16
 199 #define         VORTEX_CODEC_ADDMASK 0x7f0000   /* 0x000f0000 */
 200 #define         VORTEX_CODEC_DATSHIFT 0
 201 #define         VORTEX_CODEC_DATMASK 0xffff
 202
 203 #define VORTEX_CODEC_SPORTCTRL 0x2918c
 204
 205 #define VORTEX_CODEC_EN 0x29190
 206 #define         EN_AUDIO0               0x00000300
 207 #define         EN_MODEM                0x00000c00
 208 #define         EN_AUDIO1               0x00003000
 209 #define         EN_SPORT                0x00030000
 210 #define         EN_SPDIF                0x000c0000
 211 #define         EN_CODEC                (EN_AUDIO1 | EN_AUDIO0)
 212
 213 #define VORTEX_SPDIF_SMPRATE    0x29194
 214
 215 #define VORTEX_SPDIF_FLAGS              0x2205c
 216 #define VORTEX_SPDIF_CFG0               0x291D0 /* status data */
 217 #define VORTEX_SPDIF_CFG1               0x291D4
 218
 219 #define VORTEX_SMP_TIME                 0x29198 /* Sample counter/timer */
 220 #define VORTEX_SMP_TIMER                0x2919c
 221 #define VORTEX_CODEC2_CTRL              0x291a0
 222
 223 #define VORTEX_MODEM_CTRL               0x291ac
 224
 225 /* IRQ */
 226 #define VORTEX_IRQ_SOURCE 0x2a000       /* Interrupt source flags. */
 227 #define VORTEX_IRQ_CTRL 0x2a004 /* Interrupt source mask. */
 228
 229 //#define VORTEX_IRQ_U0 0x2a008 /* ?? */
 230 #define VORTEX_STAT             0x2a008 /* Some sort of status */
 231 #define         STAT_IRQ        0x00000001      /* This bitis set if the IRQ is valid. */
 232
 233 #define VORTEX_CTRL             0x2a00c
 234 #define         CTRL_MIDI_EN    0x00000001
 235 #define         CTRL_MIDI_PORT  0x00000060
 236 #define         CTRL_GAME_EN    0x00000008
 237 #define         CTRL_GAME_PORT  0x00000e00
 238 #define         CTRL_IRQ_ENABLE 0x00004000
 239 #define         CTRL_SPDIF              0x00000000      /* unknown. Please find this value */
 240 #define         CTRL_SPORT              0x00200000
 241 #define         CTRL_RST                0x00800000
 242 #define         CTRL_UNKNOWN    0x01000000
 243
 244 /* write: Timer period config / read: TIMER IRQ ack. */
 245 #define VORTEX_IRQ_STAT 0x2919c
 246
 247                      /* MIDI *//* GAME. */
 248 #define VORTEX_MIDI_DATA 0x28800
 249 #define VORTEX_MIDI_CMD 0x28804 /* Write command / Read status */
 250
 251 #define VORTEX_GAME_LEGACY 0x28808
 252 #define VORTEX_CTRL2 0x2880c
 253 #define         CTRL2_GAME_ADCMODE 0x40
 254 #define VORTEX_GAME_AXIS 0x28810        /* Axis base register. 4 axis's */
 255 #define         AXIS_SIZE 4
 256 #define         AXIS_RANGE 0x1fff