?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Linux-2.6.12-rc2
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / sound / oss / sonicvibes.c
blobe1d69611a25736b82de23f0ab24605e491aa34ab
1 /*****************************************************************************/
2
3 /*
4 * sonicvibes.c -- S3 Sonic Vibes audio driver.
5 *
6 * Copyright (C) 1998-2001, 2003 Thomas Sailer (t.sailer@alumni.ethz.ch)
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 *
22 * Special thanks to David C. Niemi
23 *
24 *
25 * Module command line parameters:
26 * none so far
27 *
28 *
29 * Supported devices:
30 * /dev/dsp standard /dev/dsp device, (mostly) OSS compatible
31 * /dev/mixer standard /dev/mixer device, (mostly) OSS compatible
32 * /dev/midi simple MIDI UART interface, no ioctl
33 *
34 * The card has both an FM and a Wavetable synth, but I have to figure
35 * out first how to drive them...
36 *
37 * Revision history
38 * 06.05.1998 0.1 Initial release
39 * 10.05.1998 0.2 Fixed many bugs, esp. ADC rate calculation
40 * First stab at a simple midi interface (no bells&whistles)
41 * 13.05.1998 0.3 Fix stupid cut&paste error: set_adc_rate was called instead of
42 * set_dac_rate in the FMODE_WRITE case in sv_open
43 * Fix hwptr out of bounds (now mpg123 works)
44 * 14.05.1998 0.4 Don't allow excessive interrupt rates
45 * 08.06.1998 0.5 First release using Alan Cox' soundcore instead of miscdevice
46 * 03.08.1998 0.6 Do not include modversions.h
47 * Now mixer behaviour can basically be selected between
48 * "OSS documented" and "OSS actual" behaviour
49 * 31.08.1998 0.7 Fix realplayer problems - dac.count issues
50 * 10.12.1998 0.8 Fix drain_dac trying to wait on not yet initialized DMA
51 * 16.12.1998 0.9 Fix a few f_file & FMODE_ bugs
52 * 06.01.1999 0.10 remove the silly SA_INTERRUPT flag.
53 * hopefully killed the egcs section type conflict
54 * 12.03.1999 0.11 cinfo.blocks should be reset after GETxPTR ioctl.
55 * reported by Johan Maes <joma@telindus.be>
56 * 22.03.1999 0.12 return EAGAIN instead of EBUSY when O_NONBLOCK
57 * read/write cannot be executed
58 * 05.04.1999 0.13 added code to sv_read and sv_write which should detect
59 * lockups of the sound chip and revive it. This is basically
60 * an ugly hack, but at least applications using this driver
61 * won't hang forever. I don't know why these lockups happen,
62 * it might well be the motherboard chipset (an early 486 PCI
63 * board with ALI chipset), since every busmastering 100MB
64 * ethernet card I've tried (Realtek 8139 and Macronix tulip clone)
65 * exhibit similar behaviour (they work for a couple of packets
66 * and then lock up and can be revived by ifconfig down/up).
67 * 07.04.1999 0.14 implemented the following ioctl's: SOUND_PCM_READ_RATE,
68 * SOUND_PCM_READ_CHANNELS, SOUND_PCM_READ_BITS;
69 * Alpha fixes reported by Peter Jones <pjones@redhat.com>
70 * Note: dmaio hack might still be wrong on archs other than i386
71 * 15.06.1999 0.15 Fix bad allocation bug.
72 * Thanks to Deti Fliegl <fliegl@in.tum.de>
73 * 28.06.1999 0.16 Add pci_set_master
74 * 03.08.1999 0.17 adapt to Linus' new __setup/__initcall
75 * added kernel command line options "sonicvibes=reverb" and "sonicvibesdmaio=dmaioaddr"
76 * 12.08.1999 0.18 module_init/__setup fixes
77 * 24.08.1999 0.19 get rid of the dmaio kludge, replace with allocate_resource
78 * 31.08.1999 0.20 add spin_lock_init
79 * use new resource allocation to allocate DDMA IO space
80 * replaced current->state = x with set_current_state(x)
81 * 03.09.1999 0.21 change read semantics for MIDI to match
82 * OSS more closely; remove possible wakeup race
83 * 28.10.1999 0.22 More waitqueue races fixed
84 * 01.12.1999 0.23 New argument to allocate_resource
85 * 07.12.1999 0.24 More allocate_resource semantics change
86 * 08.01.2000 0.25 Prevent some ioctl's from returning bad count values on underrun/overrun;
87 * Tim Janik's BSE (Bedevilled Sound Engine) found this
88 * use Martin Mares' pci_assign_resource
89 * 07.02.2000 0.26 Use pci_alloc_consistent and pci_register_driver
90 * 21.11.2000 0.27 Initialize dma buffers in poll, otherwise poll may return a bogus mask
91 * 12.12.2000 0.28 More dma buffer initializations, patch from
92 * Tjeerd Mulder <tjeerd.mulder@fujitsu-siemens.com>
93 * 31.01.2001 0.29 Register/Unregister gameport
94 * Fix SETTRIGGER non OSS API conformity
95 * 18.05.2001 0.30 PCI probing and error values cleaned up by Marcus
96 * Meissner <mm@caldera.de>
97 * 03.01.2003 0.31 open_mode fixes from Georg Acher <acher@in.tum.de>
98 *
99 */
100
101 /*****************************************************************************/
102
103 #include <linux/module.h>
104 #include <linux/string.h>
105 #include <linux/ioport.h>
106 #include <linux/interrupt.h>
107 #include <linux/wait.h>
108 #include <linux/mm.h>
109 #include <linux/delay.h>
110 #include <linux/sound.h>
111 #include <linux/slab.h>
112 #include <linux/soundcard.h>
113 #include <linux/pci.h>
114 #include <linux/init.h>
115 #include <linux/poll.h>
116 #include <linux/spinlock.h>
117 #include <linux/smp_lock.h>
118 #include <linux/gameport.h>
119
120 #include <asm/io.h>
121 #include <asm/uaccess.h>
122
123 #include "dm.h"
124
125
126 /* --------------------------------------------------------------------- */
127
128 #undef OSS_DOCUMENTED_MIXER_SEMANTICS
129
130 /* --------------------------------------------------------------------- */
131
132 #ifndef PCI_VENDOR_ID_S3
133 #define PCI_VENDOR_ID_S3 0x5333
134 #endif
135 #ifndef PCI_DEVICE_ID_S3_SONICVIBES
136 #define PCI_DEVICE_ID_S3_SONICVIBES 0xca00
137 #endif
138
139 #define SV_MAGIC ((PCI_VENDOR_ID_S3<<16)|PCI_DEVICE_ID_S3_SONICVIBES)
140
141 #define SV_EXTENT_SB 0x10
142 #define SV_EXTENT_ENH 0x10
143 #define SV_EXTENT_SYNTH 0x4
144 #define SV_EXTENT_MIDI 0x4
145 #define SV_EXTENT_GAME 0x8
146 #define SV_EXTENT_DMA 0x10
147
148 /*
149 * we are not a bridge and thus use a resource for DDMA that is used for bridges but
150 * left empty for normal devices
151 */
152 #define RESOURCE_SB 0
153 #define RESOURCE_ENH 1
154 #define RESOURCE_SYNTH 2
155 #define RESOURCE_MIDI 3
156 #define RESOURCE_GAME 4
157 #define RESOURCE_DDMA 7
158
159 #define SV_MIDI_DATA 0
160 #define SV_MIDI_COMMAND 1
161 #define SV_MIDI_STATUS 1
162
163 #define SV_DMA_ADDR0 0
164 #define SV_DMA_ADDR1 1
165 #define SV_DMA_ADDR2 2
166 #define SV_DMA_ADDR3 3
167 #define SV_DMA_COUNT0 4
168 #define SV_DMA_COUNT1 5
169 #define SV_DMA_COUNT2 6
170 #define SV_DMA_MODE 0xb
171 #define SV_DMA_RESET 0xd
172 #define SV_DMA_MASK 0xf
173
174 /*
175 * DONT reset the DMA controllers unless you understand
176 * the reset semantics. Assuming reset semantics as in
177 * the 8237 does not work.
178 */
179
180 #define DMA_MODE_AUTOINIT 0x10
181 #define DMA_MODE_READ 0x44 /* I/O to memory, no autoinit, increment, single mode */
182 #define DMA_MODE_WRITE 0x48 /* memory to I/O, no autoinit, increment, single mode */
183
184 #define SV_CODEC_CONTROL 0
185 #define SV_CODEC_INTMASK 1
186 #define SV_CODEC_STATUS 2
187 #define SV_CODEC_IADDR 4
188 #define SV_CODEC_IDATA 5
189
190 #define SV_CCTRL_RESET 0x80
191 #define SV_CCTRL_INTADRIVE 0x20
192 #define SV_CCTRL_WAVETABLE 0x08
193 #define SV_CCTRL_REVERB 0x04
194 #define SV_CCTRL_ENHANCED 0x01
195
196 #define SV_CINTMASK_DMAA 0x01
197 #define SV_CINTMASK_DMAC 0x04
198 #define SV_CINTMASK_SPECIAL 0x08
199 #define SV_CINTMASK_UPDOWN 0x40
200 #define SV_CINTMASK_MIDI 0x80
201
202 #define SV_CSTAT_DMAA 0x01
203 #define SV_CSTAT_DMAC 0x04
204 #define SV_CSTAT_SPECIAL 0x08
205 #define SV_CSTAT_UPDOWN 0x40
206 #define SV_CSTAT_MIDI 0x80
207
208 #define SV_CIADDR_TRD 0x80
209 #define SV_CIADDR_MCE 0x40
210
211 /* codec indirect registers */
212 #define SV_CIMIX_ADCINL 0x00
213 #define SV_CIMIX_ADCINR 0x01
214 #define SV_CIMIX_AUX1INL 0x02
215 #define SV_CIMIX_AUX1INR 0x03
216 #define SV_CIMIX_CDINL 0x04
217 #define SV_CIMIX_CDINR 0x05
218 #define SV_CIMIX_LINEINL 0x06
219 #define SV_CIMIX_LINEINR 0x07
220 #define SV_CIMIX_MICIN 0x08
221 #define SV_CIMIX_SYNTHINL 0x0A
222 #define SV_CIMIX_SYNTHINR 0x0B
223 #define SV_CIMIX_AUX2INL 0x0C
224 #define SV_CIMIX_AUX2INR 0x0D
225 #define SV_CIMIX_ANALOGINL 0x0E
226 #define SV_CIMIX_ANALOGINR 0x0F
227 #define SV_CIMIX_PCMINL 0x10
228 #define SV_CIMIX_PCMINR 0x11
229
230 #define SV_CIGAMECONTROL 0x09
231 #define SV_CIDATAFMT 0x12
232 #define SV_CIENABLE 0x13
233 #define SV_CIUPDOWN 0x14
234 #define SV_CIREVISION 0x15
235 #define SV_CIADCOUTPUT 0x16
236 #define SV_CIDMAABASECOUNT1 0x18
237 #define SV_CIDMAABASECOUNT0 0x19
238 #define SV_CIDMACBASECOUNT1 0x1c
239 #define SV_CIDMACBASECOUNT0 0x1d
240 #define SV_CIPCMSR0 0x1e
241 #define SV_CIPCMSR1 0x1f
242 #define SV_CISYNTHSR0 0x20
243 #define SV_CISYNTHSR1 0x21
244 #define SV_CIADCCLKSOURCE 0x22
245 #define SV_CIADCALTSR 0x23
246 #define SV_CIADCPLLM 0x24
247 #define SV_CIADCPLLN 0x25
248 #define SV_CISYNTHPLLM 0x26
249 #define SV_CISYNTHPLLN 0x27
250 #define SV_CIUARTCONTROL 0x2a
251 #define SV_CIDRIVECONTROL 0x2b
252 #define SV_CISRSSPACE 0x2c
253 #define SV_CISRSCENTER 0x2d
254 #define SV_CIWAVETABLESRC 0x2e
255 #define SV_CIANALOGPWRDOWN 0x30
256 #define SV_CIDIGITALPWRDOWN 0x31
257
258
259 #define SV_CIMIX_ADCSRC_CD 0x20
260 #define SV_CIMIX_ADCSRC_DAC 0x40
261 #define SV_CIMIX_ADCSRC_AUX2 0x60
262 #define SV_CIMIX_ADCSRC_LINE 0x80
263 #define SV_CIMIX_ADCSRC_AUX1 0xa0
264 #define SV_CIMIX_ADCSRC_MIC 0xc0
265 #define SV_CIMIX_ADCSRC_MIXOUT 0xe0
266 #define SV_CIMIX_ADCSRC_MASK 0xe0
267
268 #define SV_CFMT_STEREO 0x01
269 #define SV_CFMT_16BIT 0x02
270 #define SV_CFMT_MASK 0x03
271 #define SV_CFMT_ASHIFT 0
272 #define SV_CFMT_CSHIFT 4
273
274 static const unsigned sample_size[] = { 1, 2, 2, 4 };
275 static const unsigned sample_shift[] = { 0, 1, 1, 2 };
276
277 #define SV_CENABLE_PPE 0x4
278 #define SV_CENABLE_RE 0x2
279 #define SV_CENABLE_PE 0x1
280
281
282 /* MIDI buffer sizes */
283
284 #define MIDIINBUF 256
285 #define MIDIOUTBUF 256
286
287 #define FMODE_MIDI_SHIFT 2
288 #define FMODE_MIDI_READ (FMODE_READ << FMODE_MIDI_SHIFT)
289 #define FMODE_MIDI_WRITE (FMODE_WRITE << FMODE_MIDI_SHIFT)
290
291 #define FMODE_DMFM 0x10
292
293 /* --------------------------------------------------------------------- */
294
295 struct sv_state {
296 /* magic */
297 unsigned int magic;
298
299 /* list of sonicvibes devices */
300 struct list_head devs;
301
302 /* the corresponding pci_dev structure */
303 struct pci_dev *dev;
304
305 /* soundcore stuff */
306 int dev_audio;
307 int dev_mixer;
308 int dev_midi;
309 int dev_dmfm;
310
311 /* hardware resources */
312 unsigned long iosb, ioenh, iosynth, iomidi; /* long for SPARC */
313 unsigned int iodmaa, iodmac, irq;
314
315 /* mixer stuff */
316 struct {
317 unsigned int modcnt;
318 #ifndef OSS_DOCUMENTED_MIXER_SEMANTICS
319 unsigned short vol[13];
320 #endif /* OSS_DOCUMENTED_MIXER_SEMANTICS */
321 } mix;
322
323 /* wave stuff */
324 unsigned int rateadc, ratedac;
325 unsigned char fmt, enable;
326
327 spinlock_t lock;
328 struct semaphore open_sem;
329 mode_t open_mode;
330 wait_queue_head_t open_wait;
331
332 struct dmabuf {
333 void *rawbuf;
334 dma_addr_t dmaaddr;
335 unsigned buforder;
336 unsigned numfrag;
337 unsigned fragshift;
338 unsigned hwptr, swptr;
339 unsigned total_bytes;
340 int count;
341 unsigned error; /* over/underrun */
342 wait_queue_head_t wait;
343 /* redundant, but makes calculations easier */
344 unsigned fragsize;
345 unsigned dmasize;
346 unsigned fragsamples;
347 /* OSS stuff */
348 unsigned mapped:1;
349 unsigned ready:1;
350 unsigned endcleared:1;
351 unsigned enabled:1;
352 unsigned ossfragshift;
353 int ossmaxfrags;
354 unsigned subdivision;
355 } dma_dac, dma_adc;
356
357 /* midi stuff */
358 struct {
359 unsigned ird, iwr, icnt;
360 unsigned ord, owr, ocnt;
361 wait_queue_head_t iwait;
362 wait_queue_head_t owait;
363 struct timer_list timer;
364 unsigned char ibuf[MIDIINBUF];
365 unsigned char obuf[MIDIOUTBUF];
366 } midi;
367
368 struct gameport *gameport;
369 };
370
371 /* --------------------------------------------------------------------- */
372
373 static LIST_HEAD(devs);
374 static unsigned long wavetable_mem;
375
376 /* --------------------------------------------------------------------- */
377
378 static inline unsigned ld2(unsigned int x)
379 {
380 unsigned r = 0;
381
382 if (x >= 0x10000) {
383 x >>= 16;
384 r += 16;
385 }
386 if (x >= 0x100) {
387 x >>= 8;
388 r += 8;
389 }
390 if (x >= 0x10) {
391 x >>= 4;
392 r += 4;
393 }
394 if (x >= 4) {
395 x >>= 2;
396 r += 2;
397 }
398 if (x >= 2)
399 r++;
400 return r;
401 }
402
403 /*
404 * hweightN: returns the hamming weight (i.e. the number
405 * of bits set) of a N-bit word
406 */
407
408 #ifdef hweight32
409 #undef hweight32
410 #endif
411
412 static inline unsigned int hweight32(unsigned int w)
413 {
414 unsigned int res = (w & 0x55555555) + ((w >> 1) & 0x55555555);
415 res = (res & 0x33333333) + ((res >> 2) & 0x33333333);
416 res = (res & 0x0F0F0F0F) + ((res >> 4) & 0x0F0F0F0F);
417 res = (res & 0x00FF00FF) + ((res >> 8) & 0x00FF00FF);
418 return (res & 0x0000FFFF) + ((res >> 16) & 0x0000FFFF);
419 }
420
421 /* --------------------------------------------------------------------- */
422
423 /*
424 * Why use byte IO? Nobody knows, but S3 does it also in their Windows driver.
425 */
426
427 #undef DMABYTEIO
428
429 static void set_dmaa(struct sv_state *s, unsigned int addr, unsigned int count)
430 {
431 #ifdef DMABYTEIO
432 unsigned io = s->iodmaa, u;
433
434 count--;
435 for (u = 4; u > 0; u--, addr >>= 8, io++)
436 outb(addr & 0xff, io);
437 for (u = 3; u > 0; u--, count >>= 8, io++)
438 outb(count & 0xff, io);
439 #else /* DMABYTEIO */
440 count--;
441 outl(addr, s->iodmaa + SV_DMA_ADDR0);
442 outl(count, s->iodmaa + SV_DMA_COUNT0);
443 #endif /* DMABYTEIO */
444 outb(0x18, s->iodmaa + SV_DMA_MODE);
445 }
446
447 static void set_dmac(struct sv_state *s, unsigned int addr, unsigned int count)
448 {
449 #ifdef DMABYTEIO
450 unsigned io = s->iodmac, u;
451
452 count >>= 1;
453 count--;
454 for (u = 4; u > 0; u--, addr >>= 8, io++)
455 outb(addr & 0xff, io);
456 for (u = 3; u > 0; u--, count >>= 8, io++)
457 outb(count & 0xff, io);
458 #else /* DMABYTEIO */
459 count >>= 1;
460 count--;
461 outl(addr, s->iodmac + SV_DMA_ADDR0);
462 outl(count, s->iodmac + SV_DMA_COUNT0);
463 #endif /* DMABYTEIO */
464 outb(0x14, s->iodmac + SV_DMA_MODE);
465 }
466
467 static inline unsigned get_dmaa(struct sv_state *s)
468 {
469 #ifdef DMABYTEIO
470 unsigned io = s->iodmaa+6, v = 0, u;
471
472 for (u = 3; u > 0; u--, io--) {
473 v <<= 8;
474 v |= inb(io);
475 }
476 return v + 1;
477 #else /* DMABYTEIO */
478 return (inl(s->iodmaa + SV_DMA_COUNT0) & 0xffffff) + 1;
479 #endif /* DMABYTEIO */
480 }
481
482 static inline unsigned get_dmac(struct sv_state *s)
483 {
484 #ifdef DMABYTEIO
485 unsigned io = s->iodmac+6, v = 0, u;
486
487 for (u = 3; u > 0; u--, io--) {
488 v <<= 8;
489 v |= inb(io);
490 }
491 return (v + 1) << 1;
492 #else /* DMABYTEIO */
493 return ((inl(s->iodmac + SV_DMA_COUNT0) & 0xffffff) + 1) << 1;
494 #endif /* DMABYTEIO */
495 }
496
497 static void wrindir(struct sv_state *s, unsigned char idx, unsigned char data)
498 {
499 outb(idx & 0x3f, s->ioenh + SV_CODEC_IADDR);
500 udelay(10);
501 outb(data, s->ioenh + SV_CODEC_IDATA);
502 udelay(10);
503 }
504
505 static unsigned char rdindir(struct sv_state *s, unsigned char idx)
506 {
507 unsigned char v;
508
509 outb(idx & 0x3f, s->ioenh + SV_CODEC_IADDR);
510 udelay(10);
511 v = inb(s->ioenh + SV_CODEC_IDATA);
512 udelay(10);
513 return v;
514 }
515
516 static void set_fmt(struct sv_state *s, unsigned char mask, unsigned char data)
517 {
518 unsigned long flags;
519
520 spin_lock_irqsave(&s->lock, flags);
521 outb(SV_CIDATAFMT | SV_CIADDR_MCE, s->ioenh + SV_CODEC_IADDR);
522 if (mask) {
523 s->fmt = inb(s->ioenh + SV_CODEC_IDATA);
524 udelay(10);
525 }
526 s->fmt = (s->fmt & mask) | data;
527 outb(s->fmt, s->ioenh + SV_CODEC_IDATA);
528 udelay(10);
529 outb(0, s->ioenh + SV_CODEC_IADDR);
530 spin_unlock_irqrestore(&s->lock, flags);
531 udelay(10);
532 }
533
534 static void frobindir(struct sv_state *s, unsigned char idx, unsigned char mask, unsigned char data)
535 {
536 outb(idx & 0x3f, s->ioenh + SV_CODEC_IADDR);
537 udelay(10);
538 outb((inb(s->ioenh + SV_CODEC_IDATA) & mask) ^ data, s->ioenh + SV_CODEC_IDATA);
539 udelay(10);
540 }
541
542 #define REFFREQUENCY 24576000
543 #define ADCMULT 512
544 #define FULLRATE 48000
545
546 static unsigned setpll(struct sv_state *s, unsigned char reg, unsigned rate)
547 {
548 unsigned long flags;
549 unsigned char r, m=0, n=0;
550 unsigned xm, xn, xr, xd, metric = ~0U;
551 /* the warnings about m and n used uninitialized are bogus and may safely be ignored */
552
553 if (rate < 625000/ADCMULT)
554 rate = 625000/ADCMULT;
555 if (rate > 150000000/ADCMULT)
556 rate = 150000000/ADCMULT;
557 /* slight violation of specs, needed for continuous sampling rates */
558 for (r = 0; rate < 75000000/ADCMULT; r += 0x20, rate <<= 1);
559 for (xn = 3; xn < 35; xn++)
560 for (xm = 3; xm < 130; xm++) {
561 xr = REFFREQUENCY/ADCMULT * xm / xn;
562 xd = abs((signed)(xr - rate));
563 if (xd < metric) {
564 metric = xd;
565 m = xm - 2;
566 n = xn - 2;
567 }
568 }
569 reg &= 0x3f;
570 spin_lock_irqsave(&s->lock, flags);
571 outb(reg, s->ioenh + SV_CODEC_IADDR);
572 udelay(10);
573 outb(m, s->ioenh + SV_CODEC_IDATA);
574 udelay(10);
575 outb(reg+1, s->ioenh + SV_CODEC_IADDR);
576 udelay(10);
577 outb(r | n, s->ioenh + SV_CODEC_IDATA);
578 spin_unlock_irqrestore(&s->lock, flags);
579 udelay(10);
580 return (REFFREQUENCY/ADCMULT * (m + 2) / (n + 2)) >> ((r >> 5) & 7);
581 }
582
583 #if 0
584
585 static unsigned getpll(struct sv_state *s, unsigned char reg)
586 {
587 unsigned long flags;
588 unsigned char m, n;
589
590 reg &= 0x3f;
591 spin_lock_irqsave(&s->lock, flags);
592 outb(reg, s->ioenh + SV_CODEC_IADDR);
593 udelay(10);
594 m = inb(s->ioenh + SV_CODEC_IDATA);
595 udelay(10);
596 outb(reg+1, s->ioenh + SV_CODEC_IADDR);
597 udelay(10);
598 n = inb(s->ioenh + SV_CODEC_IDATA);
599 spin_unlock_irqrestore(&s->lock, flags);
600 udelay(10);
601 return (REFFREQUENCY/ADCMULT * (m + 2) / ((n & 0x1f) + 2)) >> ((n >> 5) & 7);
602 }
603
604 #endif
605
606 static void set_dac_rate(struct sv_state *s, unsigned rate)
607 {
608 unsigned div;
609 unsigned long flags;
610
611 if (rate > 48000)
612 rate = 48000;
613 if (rate < 4000)
614 rate = 4000;
615 div = (rate * 65536 + FULLRATE/2) / FULLRATE;
616 if (div > 65535)
617 div = 65535;
618 spin_lock_irqsave(&s->lock, flags);
619 wrindir(s, SV_CIPCMSR1, div >> 8);
620 wrindir(s, SV_CIPCMSR0, div);
621 spin_unlock_irqrestore(&s->lock, flags);
622 s->ratedac = (div * FULLRATE + 32768) / 65536;
623 }
624
625 static void set_adc_rate(struct sv_state *s, unsigned rate)
626 {
627 unsigned long flags;
628 unsigned rate1, rate2, div;
629
630 if (rate > 48000)
631 rate = 48000;
632 if (rate < 4000)
633 rate = 4000;
634 rate1 = setpll(s, SV_CIADCPLLM, rate);
635 div = (48000 + rate/2) / rate;
636 if (div > 8)
637 div = 8;
638 rate2 = (48000 + div/2) / div;
639 spin_lock_irqsave(&s->lock, flags);
640 wrindir(s, SV_CIADCALTSR, (div-1) << 4);
641 if (abs((signed)(rate-rate2)) <= abs((signed)(rate-rate1))) {
642 wrindir(s, SV_CIADCCLKSOURCE, 0x10);
643 s->rateadc = rate2;
644 } else {
645 wrindir(s, SV_CIADCCLKSOURCE, 0x00);
646 s->rateadc = rate1;
647 }
648 spin_unlock_irqrestore(&s->lock, flags);
649 }
650
651 /* --------------------------------------------------------------------- */
652
653 static inline void stop_adc(struct sv_state *s)
654 {
655 unsigned long flags;
656
657 spin_lock_irqsave(&s->lock, flags);
658 s->enable &= ~SV_CENABLE_RE;
659 wrindir(s, SV_CIENABLE, s->enable);
660 spin_unlock_irqrestore(&s->lock, flags);
661 }
662
663 static inline void stop_dac(struct sv_state *s)
664 {
665 unsigned long flags;
666
667 spin_lock_irqsave(&s->lock, flags);
668 s->enable &= ~(SV_CENABLE_PPE | SV_CENABLE_PE);
669 wrindir(s, SV_CIENABLE, s->enable);
670 spin_unlock_irqrestore(&s->lock, flags);
671 }
672
673 static void start_dac(struct sv_state *s)
674 {
675 unsigned long flags;
676
677 spin_lock_irqsave(&s->lock, flags);
678 if ((s->dma_dac.mapped || s->dma_dac.count > 0) && s->dma_dac.ready) {
679 s->enable = (s->enable & ~SV_CENABLE_PPE) | SV_CENABLE_PE;
680 wrindir(s, SV_CIENABLE, s->enable);
681 }
682 spin_unlock_irqrestore(&s->lock, flags);
683 }
684
685 static void start_adc(struct sv_state *s)
686 {
687 unsigned long flags;
688
689 spin_lock_irqsave(&s->lock, flags);
690 if ((s->dma_adc.mapped || s->dma_adc.count < (signed)(s->dma_adc.dmasize - 2*s->dma_adc.fragsize))
691 && s->dma_adc.ready) {
692 s->enable |= SV_CENABLE_RE;
693 wrindir(s, SV_CIENABLE, s->enable);
694 }
695 spin_unlock_irqrestore(&s->lock, flags);
696 }
697
698 /* --------------------------------------------------------------------- */
699
700 #define DMABUF_DEFAULTORDER (17-PAGE_SHIFT)
701 #define DMABUF_MINORDER 1
702
703 static void dealloc_dmabuf(struct sv_state *s, struct dmabuf *db)
704 {
705 struct page *page, *pend;
706
707 if (db->rawbuf) {
708 /* undo marking the pages as reserved */
709 pend = virt_to_page(db->rawbuf + (PAGE_SIZE << db->buforder) - 1);
710 for (page = virt_to_page(db->rawbuf); page <= pend; page++)
711 ClearPageReserved(page);
712 pci_free_consistent(s->dev, PAGE_SIZE << db->buforder, db->rawbuf, db->dmaaddr);
713 }
714 db->rawbuf = NULL;
715 db->mapped = db->ready = 0;
716 }
717
718
719 /* DMAA is used for playback, DMAC is used for recording */
720
721 static int prog_dmabuf(struct sv_state *s, unsigned rec)
722 {
723 struct dmabuf *db = rec ? &s->dma_adc : &s->dma_dac;
724 unsigned rate = rec ? s->rateadc : s->ratedac;
725 int order;
726 unsigned bytepersec;
727 unsigned bufs;
728 struct page *page, *pend;
729 unsigned char fmt;
730 unsigned long flags;
731
732 spin_lock_irqsave(&s->lock, flags);
733 fmt = s->fmt;
734 if (rec) {
735 s->enable &= ~SV_CENABLE_RE;
736 fmt >>= SV_CFMT_CSHIFT;
737 } else {
738 s->enable &= ~SV_CENABLE_PE;
739 fmt >>= SV_CFMT_ASHIFT;
740 }
741 wrindir(s, SV_CIENABLE, s->enable);
742 spin_unlock_irqrestore(&s->lock, flags);
743 fmt &= SV_CFMT_MASK;
744 db->hwptr = db->swptr = db->total_bytes = db->count = db->error = db->endcleared = 0;
745 if (!db->rawbuf) {
746 db->ready = db->mapped = 0;
747 for (order = DMABUF_DEFAULTORDER; order >= DMABUF_MINORDER; order--)
748 if ((db->rawbuf = pci_alloc_consistent(s->dev, PAGE_SIZE << order, &db->dmaaddr)))
749 break;
750 if (!db->rawbuf)
751 return -ENOMEM;
752 db->buforder = order;
753 if ((virt_to_bus(db->rawbuf) ^ (virt_to_bus(db->rawbuf) + (PAGE_SIZE << db->buforder) - 1)) & ~0xffff)
754 printk(KERN_DEBUG "sv: DMA buffer crosses 64k boundary: busaddr 0x%lx size %ld\n",
755 virt_to_bus(db->rawbuf), PAGE_SIZE << db->buforder);
756 if ((virt_to_bus(db->rawbuf) + (PAGE_SIZE << db->buforder) - 1) & ~0xffffff)
757 printk(KERN_DEBUG "sv: DMA buffer beyond 16MB: busaddr 0x%lx size %ld\n",
758 virt_to_bus(db->rawbuf), PAGE_SIZE << db->buforder);
759 /* now mark the pages as reserved; otherwise remap_pfn_range doesn't do what we want */
760 pend = virt_to_page(db->rawbuf + (PAGE_SIZE << db->buforder) - 1);
761 for (page = virt_to_page(db->rawbuf); page <= pend; page++)
762 SetPageReserved(page);
763 }
764 bytepersec = rate << sample_shift[fmt];
765 bufs = PAGE_SIZE << db->buforder;
766 if (db->ossfragshift) {
767 if ((1000 << db->ossfragshift) < bytepersec)
768 db->fragshift = ld2(bytepersec/1000);
769 else
770 db->fragshift = db->ossfragshift;
771 } else {
772 db->fragshift = ld2(bytepersec/100/(db->subdivision ? db->subdivision : 1));
773 if (db->fragshift < 3)
774 db->fragshift = 3;
775 }
776 db->numfrag = bufs >> db->fragshift;
777 while (db->numfrag < 4 && db->fragshift > 3) {
778 db->fragshift--;
779 db->numfrag = bufs >> db->fragshift;
780 }
781 db->fragsize = 1 << db->fragshift;
782 if (db->ossmaxfrags >= 4 && db->ossmaxfrags < db->numfrag)
783 db->numfrag = db->ossmaxfrags;
784 db->fragsamples = db->fragsize >> sample_shift[fmt];
785 db->dmasize = db->numfrag << db->fragshift;
786 memset(db->rawbuf, (fmt & SV_CFMT_16BIT) ? 0 : 0x80, db->dmasize);
787 spin_lock_irqsave(&s->lock, flags);
788 if (rec) {
789 set_dmac(s, db->dmaaddr, db->numfrag << db->fragshift);
790 /* program enhanced mode registers */
791 wrindir(s, SV_CIDMACBASECOUNT1, (db->fragsamples-1) >> 8);
792 wrindir(s, SV_CIDMACBASECOUNT0, db->fragsamples-1);
793 } else {
794 set_dmaa(s, db->dmaaddr, db->numfrag << db->fragshift);
795 /* program enhanced mode registers */
796 wrindir(s, SV_CIDMAABASECOUNT1, (db->fragsamples-1) >> 8);
797 wrindir(s, SV_CIDMAABASECOUNT0, db->fragsamples-1);
798 }
799 spin_unlock_irqrestore(&s->lock, flags);
800 db->enabled = 1;
801 db->ready = 1;
802 return 0;
803 }
804
805 static inline void clear_advance(struct sv_state *s)
806 {
807 unsigned char c = (s->fmt & (SV_CFMT_16BIT << SV_CFMT_ASHIFT)) ? 0 : 0x80;
808 unsigned char *buf = s->dma_dac.rawbuf;
809 unsigned bsize = s->dma_dac.dmasize;
810 unsigned bptr = s->dma_dac.swptr;
811 unsigned len = s->dma_dac.fragsize;
812
813 if (bptr + len > bsize) {
814 unsigned x = bsize - bptr;
815 memset(buf + bptr, c, x);
816 bptr = 0;
817 len -= x;
818 }
819 memset(buf + bptr, c, len);
820 }
821
822 /* call with spinlock held! */
823 static void sv_update_ptr(struct sv_state *s)
824 {
825 unsigned hwptr;
826 int diff;
827
828 /* update ADC pointer */
829 if (s->dma_adc.ready) {
830 hwptr = (s->dma_adc.dmasize - get_dmac(s)) % s->dma_adc.dmasize;
831 diff = (s->dma_adc.dmasize + hwptr - s->dma_adc.hwptr) % s->dma_adc.dmasize;
832 s->dma_adc.hwptr = hwptr;
833 s->dma_adc.total_bytes += diff;
834 s->dma_adc.count += diff;
835 if (s->dma_adc.count >= (signed)s->dma_adc.fragsize)
836 wake_up(&s->dma_adc.wait);
837 if (!s->dma_adc.mapped) {
838 if (s->dma_adc.count > (signed)(s->dma_adc.dmasize - ((3 * s->dma_adc.fragsize) >> 1))) {
839 s->enable &= ~SV_CENABLE_RE;
840 wrindir(s, SV_CIENABLE, s->enable);
841 s->dma_adc.error++;
842 }
843 }
844 }
845 /* update DAC pointer */
846 if (s->dma_dac.ready) {
847 hwptr = (s->dma_dac.dmasize - get_dmaa(s)) % s->dma_dac.dmasize;
848 diff = (s->dma_dac.dmasize + hwptr - s->dma_dac.hwptr) % s->dma_dac.dmasize;
849 s->dma_dac.hwptr = hwptr;
850 s->dma_dac.total_bytes += diff;
851 if (s->dma_dac.mapped) {
852 s->dma_dac.count += diff;
853 if (s->dma_dac.count >= (signed)s->dma_dac.fragsize)
854 wake_up(&s->dma_dac.wait);
855 } else {
856 s->dma_dac.count -= diff;
857 if (s->dma_dac.count <= 0) {
858 s->enable &= ~SV_CENABLE_PE;
859 wrindir(s, SV_CIENABLE, s->enable);
860 s->dma_dac.error++;
861 } else if (s->dma_dac.count <= (signed)s->dma_dac.fragsize && !s->dma_dac.endcleared) {
862 clear_advance(s);
863 s->dma_dac.endcleared = 1;
864 }
865 if (s->dma_dac.count + (signed)s->dma_dac.fragsize <= (signed)s->dma_dac.dmasize)
866 wake_up(&s->dma_dac.wait);
867 }
868 }
869 }
870
871 /* hold spinlock for the following! */
872 static void sv_handle_midi(struct sv_state *s)
873 {
874 unsigned char ch;
875 int wake;
876
877 wake = 0;
878 while (!(inb(s->iomidi+1) & 0x80)) {
879 ch = inb(s->iomidi);
880 if (s->midi.icnt < MIDIINBUF) {
881 s->midi.ibuf[s->midi.iwr] = ch;
882 s->midi.iwr = (s->midi.iwr + 1) % MIDIINBUF;
883 s->midi.icnt++;
884 }
885 wake = 1;
886 }
887 if (wake)
888 wake_up(&s->midi.iwait);
889 wake = 0;
890 while (!(inb(s->iomidi+1) & 0x40) && s->midi.ocnt > 0) {
891 outb(s->midi.obuf[s->midi.ord], s->iomidi);
892 s->midi.ord = (s->midi.ord + 1) % MIDIOUTBUF;
893 s->midi.ocnt--;
894 if (s->midi.ocnt < MIDIOUTBUF-16)
895 wake = 1;
896 }
897 if (wake)
898 wake_up(&s->midi.owait);
899 }
900
901 static irqreturn_t sv_interrupt(int irq, void *dev_id, struct pt_regs *regs)
902 {
903 struct sv_state *s = (struct sv_state *)dev_id;
904 unsigned int intsrc;
905
906 /* fastpath out, to ease interrupt sharing */
907 intsrc = inb(s->ioenh + SV_CODEC_STATUS);
908 if (!(intsrc & (SV_CSTAT_DMAA | SV_CSTAT_DMAC | SV_CSTAT_MIDI)))
909 return IRQ_NONE;
910 spin_lock(&s->lock);
911 sv_update_ptr(s);
912 sv_handle_midi(s);
913 spin_unlock(&s->lock);
914 return IRQ_HANDLED;
915 }
916
917 static void sv_midi_timer(unsigned long data)
918 {
919 struct sv_state *s = (struct sv_state *)data;
920 unsigned long flags;
921
922 spin_lock_irqsave(&s->lock, flags);
923 sv_handle_midi(s);
924 spin_unlock_irqrestore(&s->lock, flags);
925 s->midi.timer.expires = jiffies+1;
926 add_timer(&s->midi.timer);
927 }
928
929 /* --------------------------------------------------------------------- */
930
931 static const char invalid_magic[] = KERN_CRIT "sv: invalid magic value\n";
932
933 #define VALIDATE_STATE(s) \
934 ({ \
935 if (!(s) || (s)->magic != SV_MAGIC) { \
936 printk(invalid_magic); \
937 return -ENXIO; \
938 } \
939 })
940
941 /* --------------------------------------------------------------------- */
942
943 #define MT_4 1
944 #define MT_5MUTE 2
945 #define MT_4MUTEMONO 3
946 #define MT_6MUTE 4
947
948 static const struct {
949 unsigned left:5;
950 unsigned right:5;
951 unsigned type:3;
952 unsigned rec:3;
953 } mixtable[SOUND_MIXER_NRDEVICES] = {
954 [SOUND_MIXER_RECLEV] = { SV_CIMIX_ADCINL, SV_CIMIX_ADCINR, MT_4, 0 },
955 [SOUND_MIXER_LINE1] = { SV_CIMIX_AUX1INL, SV_CIMIX_AUX1INR, MT_5MUTE, 5 },
956 [SOUND_MIXER_CD] = { SV_CIMIX_CDINL, SV_CIMIX_CDINR, MT_5MUTE, 1 },
957 [SOUND_MIXER_LINE] = { SV_CIMIX_LINEINL, SV_CIMIX_LINEINR, MT_5MUTE, 4 },
958 [SOUND_MIXER_MIC] = { SV_CIMIX_MICIN, SV_CIMIX_ADCINL, MT_4MUTEMONO, 6 },
959 [SOUND_MIXER_SYNTH] = { SV_CIMIX_SYNTHINL, SV_CIMIX_SYNTHINR, MT_5MUTE, 2 },
960 [SOUND_MIXER_LINE2] = { SV_CIMIX_AUX2INL, SV_CIMIX_AUX2INR, MT_5MUTE, 3 },
961 [SOUND_MIXER_VOLUME] = { SV_CIMIX_ANALOGINL, SV_CIMIX_ANALOGINR, MT_5MUTE, 7 },
962 [SOUND_MIXER_PCM] = { SV_CIMIX_PCMINL, SV_CIMIX_PCMINR, MT_6MUTE, 0 }
963 };
964
965 #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
966
967 static int return_mixval(struct sv_state *s, unsigned i, int *arg)
968 {
969 unsigned long flags;
970 unsigned char l, r, rl, rr;
971
972 spin_lock_irqsave(&s->lock, flags);
973 l = rdindir(s, mixtable[i].left);
974 r = rdindir(s, mixtable[i].right);
975 spin_unlock_irqrestore(&s->lock, flags);
976 switch (mixtable[i].type) {
977 case MT_4:
978 r &= 0xf;
979 l &= 0xf;
980 rl = 10 + 6 * (l & 15);
981 rr = 10 + 6 * (r & 15);
982 break;
983
984 case MT_4MUTEMONO:
985 rl = 55 - 3 * (l & 15);
986 if (r & 0x10)
987 rl += 45;
988 rr = rl;
989 r = l;
990 break;
991
992 case MT_5MUTE:
993 default:
994 rl = 100 - 3 * (l & 31);
995 rr = 100 - 3 * (r & 31);
996 break;
997
998 case MT_6MUTE:
999 rl = 100 - 3 * (l & 63) / 2;
1000 rr = 100 - 3 * (r & 63) / 2;
1001 break;
1002 }
1003 if (l & 0x80)
1004 rl = 0;
1005 if (r & 0x80)
1006 rr = 0;
1007 return put_user((rr << 8) | rl, arg);
1008 }
1009
1010 #else /* OSS_DOCUMENTED_MIXER_SEMANTICS */
1011
1012 static const unsigned char volidx[SOUND_MIXER_NRDEVICES] =
1013 {
1014 [SOUND_MIXER_RECLEV] = 1,
1015 [SOUND_MIXER_LINE1] = 2,
1016 [SOUND_MIXER_CD] = 3,
1017 [SOUND_MIXER_LINE] = 4,
1018 [SOUND_MIXER_MIC] = 5,
1019 [SOUND_MIXER_SYNTH] = 6,
1020 [SOUND_MIXER_LINE2] = 7,
1021 [SOUND_MIXER_VOLUME] = 8,
1022 [SOUND_MIXER_PCM] = 9
1023 };
1024
1025 #endif /* OSS_DOCUMENTED_MIXER_SEMANTICS */
1026
1027 static unsigned mixer_recmask(struct sv_state *s)
1028 {
1029 unsigned long flags;
1030 int i, j;
1031
1032 spin_lock_irqsave(&s->lock, flags);
1033 j = rdindir(s, SV_CIMIX_ADCINL) >> 5;
1034 spin_unlock_irqrestore(&s->lock, flags);
1035 j &= 7;
1036 for (i = 0; i < SOUND_MIXER_NRDEVICES && mixtable[i].rec != j; i++);
1037 return 1 << i;
1038 }
1039
1040 static int mixer_ioctl(struct sv_state *s, unsigned int cmd, unsigned long arg)
1041 {
1042 unsigned long flags;
1043 int i, val;
1044 unsigned char l, r, rl, rr;
1045 int __user *p = (int __user *)arg;
1046
1047 VALIDATE_STATE(s);
1048 if (cmd == SOUND_MIXER_INFO) {
1049 mixer_info info;
1050 memset(&info, 0, sizeof(info));
1051 strlcpy(info.id, "SonicVibes", sizeof(info.id));
1052 strlcpy(info.name, "S3 SonicVibes", sizeof(info.name));
1053 info.modify_counter = s->mix.modcnt;
1054 if (copy_to_user((void __user *)arg, &info, sizeof(info)))
1055 return -EFAULT;
1056 return 0;
1057 }
1058 if (cmd == SOUND_OLD_MIXER_INFO) {
1059 _old_mixer_info info;
1060 memset(&info, 0, sizeof(info));
1061 strlcpy(info.id, "SonicVibes", sizeof(info.id));
1062 strlcpy(info.name, "S3 SonicVibes", sizeof(info.name));
1063 if (copy_to_user((void __user *)arg, &info, sizeof(info)))
1064 return -EFAULT;
1065 return 0;
1066 }
1067 if (cmd == OSS_GETVERSION)
1068 return put_user(SOUND_VERSION, p);
1069 if (cmd == SOUND_MIXER_PRIVATE1) { /* SRS settings */
1070 if (get_user(val, p))
1071 return -EFAULT;
1072 spin_lock_irqsave(&s->lock, flags);
1073 if (val & 1) {
1074 if (val & 2) {
1075 l = 4 - ((val >> 2) & 7);
1076 if (l & ~3)
1077 l = 4;
1078 r = 4 - ((val >> 5) & 7);
1079 if (r & ~3)
1080 r = 4;
1081 wrindir(s, SV_CISRSSPACE, l);
1082 wrindir(s, SV_CISRSCENTER, r);
1083 } else
1084 wrindir(s, SV_CISRSSPACE, 0x80);
1085 }
1086 l = rdindir(s, SV_CISRSSPACE);
1087 r = rdindir(s, SV_CISRSCENTER);
1088 spin_unlock_irqrestore(&s->lock, flags);
1089 if (l & 0x80)
1090 return put_user(0, p);
1091 return put_user(((4 - (l & 7)) << 2) | ((4 - (r & 7)) << 5) | 2, p);
1092 }
1093 if (_IOC_TYPE(cmd) != 'M' || _SIOC_SIZE(cmd) != sizeof(int))
1094 return -EINVAL;
1095 if (_SIOC_DIR(cmd) == _SIOC_READ) {
1096 switch (_IOC_NR(cmd)) {
1097 case SOUND_MIXER_RECSRC: /* Arg contains a bit for each recording source */
1098 return put_user(mixer_recmask(s), p);
1099
1100 case SOUND_MIXER_DEVMASK: /* Arg contains a bit for each supported device */
1101 for (val = i = 0; i < SOUND_MIXER_NRDEVICES; i++)
1102 if (mixtable[i].type)
1103 val |= 1 << i;
1104 return put_user(val, p);
1105
1106 case SOUND_MIXER_RECMASK: /* Arg contains a bit for each supported recording source */
1107 for (val = i = 0; i < SOUND_MIXER_NRDEVICES; i++)
1108 if (mixtable[i].rec)
1109 val |= 1 << i;
1110 return put_user(val, p);
1111
1112 case SOUND_MIXER_STEREODEVS: /* Mixer channels supporting stereo */
1113 for (val = i = 0; i < SOUND_MIXER_NRDEVICES; i++)
1114 if (mixtable[i].type && mixtable[i].type != MT_4MUTEMONO)
1115 val |= 1 << i;
1116 return put_user(val, p);
1117
1118 case SOUND_MIXER_CAPS:
1119 return put_user(SOUND_CAP_EXCL_INPUT, p);
1120
1121 default:
1122 i = _IOC_NR(cmd);
1123 if (i >= SOUND_MIXER_NRDEVICES || !mixtable[i].type)
1124 return -EINVAL;
1125 #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
1126 return return_mixval(s, i, p);
1127 #else /* OSS_DOCUMENTED_MIXER_SEMANTICS */
1128 if (!volidx[i])
1129 return -EINVAL;
1130 return put_user(s->mix.vol[volidx[i]-1], p);
1131 #endif /* OSS_DOCUMENTED_MIXER_SEMANTICS */
1132 }
1133 }
1134 if (_SIOC_DIR(cmd) != (_SIOC_READ|_SIOC_WRITE))
1135 return -EINVAL;
1136 s->mix.modcnt++;
1137 switch (_IOC_NR(cmd)) {
1138 case SOUND_MIXER_RECSRC: /* Arg contains a bit for each recording source */
1139 if (get_user(val, p))
1140 return -EFAULT;
1141 i = hweight32(val);
1142 if (i == 0)
1143 return 0; /*val = mixer_recmask(s);*/
1144 else if (i > 1)
1145 val &= ~mixer_recmask(s);
1146 for (i = 0; i < SOUND_MIXER_NRDEVICES; i++) {
1147 if (!(val & (1 << i)))
1148 continue;
1149 if (mixtable[i].rec)
1150 break;
1151 }
1152 if (!mixtable[i].rec)
1153 return 0;
1154 spin_lock_irqsave(&s->lock, flags);
1155 frobindir(s, SV_CIMIX_ADCINL, 0x1f, mixtable[i].rec << 5);
1156 frobindir(s, SV_CIMIX_ADCINR, 0x1f, mixtable[i].rec << 5);
1157 spin_unlock_irqrestore(&s->lock, flags);
1158 return 0;
1159
1160 default:
1161 i = _IOC_NR(cmd);
1162 if (i >= SOUND_MIXER_NRDEVICES || !mixtable[i].type)
1163 return -EINVAL;
1164 if (get_user(val, p))
1165 return -EFAULT;
1166 l = val & 0xff;
1167 r = (val >> 8) & 0xff;
1168 if (mixtable[i].type == MT_4MUTEMONO)
1169 l = (r + l) / 2;
1170 if (l > 100)
1171 l = 100;
1172 if (r > 100)
1173 r = 100;
1174 spin_lock_irqsave(&s->lock, flags);
1175 switch (mixtable[i].type) {
1176 case MT_4:
1177 if (l >= 10)
1178 l -= 10;
1179 if (r >= 10)
1180 r -= 10;
1181 frobindir(s, mixtable[i].left, 0xf0, l / 6);
1182 frobindir(s, mixtable[i].right, 0xf0, l / 6);
1183 break;
1184
1185 case MT_4MUTEMONO:
1186 rr = 0;
1187 if (l < 10)
1188 rl = 0x80;
1189 else {
1190 if (l >= 55) {
1191 rr = 0x10;
1192 l -= 45;
1193 }
1194 rl = (55 - l) / 3;
1195 }
1196 wrindir(s, mixtable[i].left, rl);
1197 frobindir(s, mixtable[i].right, ~0x10, rr);
1198 break;
1199
1200 case MT_5MUTE:
1201 if (l < 7)
1202 rl = 0x80;
1203 else
1204 rl = (100 - l) / 3;
1205 if (r < 7)
1206 rr = 0x80;
1207 else
1208 rr = (100 - r) / 3;
1209 wrindir(s, mixtable[i].left, rl);
1210 wrindir(s, mixtable[i].right, rr);
1211 break;
1212
1213 case MT_6MUTE:
1214 if (l < 6)
1215 rl = 0x80;
1216 else
1217 rl = (100 - l) * 2 / 3;
1218 if (r < 6)
1219 rr = 0x80;
1220 else
1221 rr = (100 - r) * 2 / 3;
1222 wrindir(s, mixtable[i].left, rl);
1223 wrindir(s, mixtable[i].right, rr);
1224 break;
1225 }
1226 spin_unlock_irqrestore(&s->lock, flags);
1227 #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
1228 return return_mixval(s, i, p);
1229 #else /* OSS_DOCUMENTED_MIXER_SEMANTICS */
1230 if (!volidx[i])
1231 return -EINVAL;
1232 s->mix.vol[volidx[i]-1] = val;
1233 return put_user(s->mix.vol[volidx[i]-1], p);
1234 #endif /* OSS_DOCUMENTED_MIXER_SEMANTICS */
1235 }
1236 }
1237
1238 /* --------------------------------------------------------------------- */
1239
1240 static int sv_open_mixdev(struct inode *inode, struct file *file)
1241 {
1242 int minor = iminor(inode);
1243 struct list_head *list;
1244 struct sv_state *s;
1245
1246 for (list = devs.next; ; list = list->next) {
1247 if (list == &devs)
1248 return -ENODEV;
1249 s = list_entry(list, struct sv_state, devs);
1250 if (s->dev_mixer == minor)
1251 break;
1252 }
1253 VALIDATE_STATE(s);
1254 file->private_data = s;
1255 return nonseekable_open(inode, file);
1256 }
1257
1258 static int sv_release_mixdev(struct inode *inode, struct file *file)
1259 {
1260 struct sv_state *s = (struct sv_state *)file->private_data;
1261
1262 VALIDATE_STATE(s);
1263 return 0;
1264 }
1265
1266 static int sv_ioctl_mixdev(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
1267 {
1268 return mixer_ioctl((struct sv_state *)file->private_data, cmd, arg);
1269 }
1270
1271 static /*const*/ struct file_operations sv_mixer_fops = {
1272 .owner = THIS_MODULE,
1273 .llseek = no_llseek,
1274 .ioctl = sv_ioctl_mixdev,
1275 .open = sv_open_mixdev,
1276 .release = sv_release_mixdev,
1277 };
1278
1279 /* --------------------------------------------------------------------- */
1280
1281 static int drain_dac(struct sv_state *s, int nonblock)
1282 {
1283 DECLARE_WAITQUEUE(wait, current);
1284 unsigned long flags;
1285 int count, tmo;
1286
1287 if (s->dma_dac.mapped || !s->dma_dac.ready)
1288 return 0;
1289 add_wait_queue(&s->dma_dac.wait, &wait);
1290 for (;;) {
1291 __set_current_state(TASK_INTERRUPTIBLE);
1292 spin_lock_irqsave(&s->lock, flags);
1293 count = s->dma_dac.count;
1294 spin_unlock_irqrestore(&s->lock, flags);
1295 if (count <= 0)
1296 break;
1297 if (signal_pending(current))
1298 break;
1299 if (nonblock) {
1300 remove_wait_queue(&s->dma_dac.wait, &wait);
1301 set_current_state(TASK_RUNNING);
1302 return -EBUSY;
1303 }
1304 tmo = 3 * HZ * (count + s->dma_dac.fragsize) / 2 / s->ratedac;
1305 tmo >>= sample_shift[(s->fmt >> SV_CFMT_ASHIFT) & SV_CFMT_MASK];
1306 if (!schedule_timeout(tmo + 1))
1307 printk(KERN_DEBUG "sv: dma timed out??\n");
1308 }
1309 remove_wait_queue(&s->dma_dac.wait, &wait);
1310 set_current_state(TASK_RUNNING);
1311 if (signal_pending(current))
1312 return -ERESTARTSYS;
1313 return 0;
1314 }
1315
1316 /* --------------------------------------------------------------------- */
1317
1318 static ssize_t sv_read(struct file *file, char __user *buffer, size_t count, loff_t *ppos)
1319 {
1320 struct sv_state *s = (struct sv_state *)file->private_data;
1321 DECLARE_WAITQUEUE(wait, current);
1322 ssize_t ret;
1323 unsigned long flags;
1324 unsigned swptr;
1325 int cnt;
1326
1327 VALIDATE_STATE(s);
1328 if (s->dma_adc.mapped)
1329 return -ENXIO;
1330 if (!s->dma_adc.ready && (ret = prog_dmabuf(s, 1)))
1331 return ret;
1332 if (!access_ok(VERIFY_WRITE, buffer, count))
1333 return -EFAULT;
1334 ret = 0;
1335 #if 0
1336 spin_lock_irqsave(&s->lock, flags);
1337 sv_update_ptr(s);
1338 spin_unlock_irqrestore(&s->lock, flags);
1339 #endif
1340 add_wait_queue(&s->dma_adc.wait, &wait);
1341 while (count > 0) {
1342 spin_lock_irqsave(&s->lock, flags);
1343 swptr = s->dma_adc.swptr;
1344 cnt = s->dma_adc.dmasize-swptr;
1345 if (s->dma_adc.count < cnt)
1346 cnt = s->dma_adc.count;
1347 if (cnt <= 0)
1348 __set_current_state(TASK_INTERRUPTIBLE);
1349 spin_unlock_irqrestore(&s->lock, flags);
1350 if (cnt > count)
1351 cnt = count;
1352 if (cnt <= 0) {
1353 if (s->dma_adc.enabled)
1354 start_adc(s);
1355 if (file->f_flags & O_NONBLOCK) {
1356 if (!ret)
1357 ret = -EAGAIN;
1358 break;
1359 }
1360 if (!schedule_timeout(HZ)) {
1361 printk(KERN_DEBUG "sv: read: chip lockup? dmasz %u fragsz %u count %i hwptr %u swptr %u\n",
1362 s->dma_adc.dmasize, s->dma_adc.fragsize, s->dma_adc.count,
1363 s->dma_adc.hwptr, s->dma_adc.swptr);
1364 stop_adc(s);
1365 spin_lock_irqsave(&s->lock, flags);
1366 set_dmac(s, virt_to_bus(s->dma_adc.rawbuf), s->dma_adc.numfrag << s->dma_adc.fragshift);
1367 /* program enhanced mode registers */
1368 wrindir(s, SV_CIDMACBASECOUNT1, (s->dma_adc.fragsamples-1) >> 8);
1369 wrindir(s, SV_CIDMACBASECOUNT0, s->dma_adc.fragsamples-1);
1370 s->dma_adc.count = s->dma_adc.hwptr = s->dma_adc.swptr = 0;
1371 spin_unlock_irqrestore(&s->lock, flags);
1372 }
1373 if (signal_pending(current)) {
1374 if (!ret)
1375 ret = -ERESTARTSYS;
1376 break;
1377 }
1378 continue;
1379 }
1380 if (copy_to_user(buffer, s->dma_adc.rawbuf + swptr, cnt)) {
1381 if (!ret)
1382 ret = -EFAULT;
1383 break;
1384 }
1385 swptr = (swptr + cnt) % s->dma_adc.dmasize;
1386 spin_lock_irqsave(&s->lock, flags);
1387 s->dma_adc.swptr = swptr;
1388 s->dma_adc.count -= cnt;
1389 spin_unlock_irqrestore(&s->lock, flags);
1390 count -= cnt;
1391 buffer += cnt;
1392 ret += cnt;
1393 if (s->dma_adc.enabled)
1394 start_adc(s);
1395 }
1396 remove_wait_queue(&s->dma_adc.wait, &wait);
1397 set_current_state(TASK_RUNNING);
1398 return ret;
1399 }
1400
1401 static ssize_t sv_write(struct file *file, const char __user *buffer, size_t count, loff_t *ppos)
1402 {
1403 struct sv_state *s = (struct sv_state *)file->private_data;
1404 DECLARE_WAITQUEUE(wait, current);
1405 ssize_t ret;
1406 unsigned long flags;
1407 unsigned swptr;
1408 int cnt;
1409
1410 VALIDATE_STATE(s);
1411 if (s->dma_dac.mapped)
1412 return -ENXIO;
1413 if (!s->dma_dac.ready && (ret = prog_dmabuf(s, 0)))
1414 return ret;
1415 if (!access_ok(VERIFY_READ, buffer, count))
1416 return -EFAULT;
1417 ret = 0;
1418 #if 0
1419 spin_lock_irqsave(&s->lock, flags);
1420 sv_update_ptr(s);
1421 spin_unlock_irqrestore(&s->lock, flags);
1422 #endif
1423 add_wait_queue(&s->dma_dac.wait, &wait);
1424 while (count > 0) {
1425 spin_lock_irqsave(&s->lock, flags);
1426 if (s->dma_dac.count < 0) {
1427 s->dma_dac.count = 0;
1428 s->dma_dac.swptr = s->dma_dac.hwptr;
1429 }
1430 swptr = s->dma_dac.swptr;
1431 cnt = s->dma_dac.dmasize-swptr;
1432 if (s->dma_dac.count + cnt > s->dma_dac.dmasize)
1433 cnt = s->dma_dac.dmasize - s->dma_dac.count;
1434 if (cnt <= 0)
1435 __set_current_state(TASK_INTERRUPTIBLE);
1436 spin_unlock_irqrestore(&s->lock, flags);
1437 if (cnt > count)
1438 cnt = count;
1439 if (cnt <= 0) {
1440 if (s->dma_dac.enabled)
1441 start_dac(s);
1442 if (file->f_flags & O_NONBLOCK) {
1443 if (!ret)
1444 ret = -EAGAIN;
1445 break;
1446 }
1447 if (!schedule_timeout(HZ)) {
1448 printk(KERN_DEBUG "sv: write: chip lockup? dmasz %u fragsz %u count %i hwptr %u swptr %u\n",
1449 s->dma_dac.dmasize, s->dma_dac.fragsize, s->dma_dac.count,
1450 s->dma_dac.hwptr, s->dma_dac.swptr);
1451 stop_dac(s);
1452 spin_lock_irqsave(&s->lock, flags);
1453 set_dmaa(s, virt_to_bus(s->dma_dac.rawbuf), s->dma_dac.numfrag << s->dma_dac.fragshift);
1454 /* program enhanced mode registers */
1455 wrindir(s, SV_CIDMAABASECOUNT1, (s->dma_dac.fragsamples-1) >> 8);
1456 wrindir(s, SV_CIDMAABASECOUNT0, s->dma_dac.fragsamples-1);
1457 s->dma_dac.count = s->dma_dac.hwptr = s->dma_dac.swptr = 0;
1458 spin_unlock_irqrestore(&s->lock, flags);
1459 }
1460 if (signal_pending(current)) {
1461 if (!ret)
1462 ret = -ERESTARTSYS;
1463 break;
1464 }
1465 continue;
1466 }
1467 if (copy_from_user(s->dma_dac.rawbuf + swptr, buffer, cnt)) {
1468 if (!ret)
1469 ret = -EFAULT;
1470 break;
1471 }
1472 swptr = (swptr + cnt) % s->dma_dac.dmasize;
1473 spin_lock_irqsave(&s->lock, flags);
1474 s->dma_dac.swptr = swptr;
1475 s->dma_dac.count += cnt;
1476 s->dma_dac.endcleared = 0;
1477 spin_unlock_irqrestore(&s->lock, flags);
1478 count -= cnt;
1479 buffer += cnt;
1480 ret += cnt;
1481 if (s->dma_dac.enabled)
1482 start_dac(s);
1483 }
1484 remove_wait_queue(&s->dma_dac.wait, &wait);
1485 set_current_state(TASK_RUNNING);
1486 return ret;
1487 }
1488
1489 /* No kernel lock - we have our own spinlock */
1490 static unsigned int sv_poll(struct file *file, struct poll_table_struct *wait)
1491 {
1492 struct sv_state *s = (struct sv_state *)file->private_data;
1493 unsigned long flags;
1494 unsigned int mask = 0;
1495
1496 VALIDATE_STATE(s);
1497 if (file->f_mode & FMODE_WRITE) {
1498 if (!s->dma_dac.ready && prog_dmabuf(s, 1))
1499 return 0;
1500 poll_wait(file, &s->dma_dac.wait, wait);
1501 }
1502 if (file->f_mode & FMODE_READ) {
1503 if (!s->dma_adc.ready && prog_dmabuf(s, 0))
1504 return 0;
1505 poll_wait(file, &s->dma_adc.wait, wait);
1506 }
1507 spin_lock_irqsave(&s->lock, flags);
1508 sv_update_ptr(s);
1509 if (file->f_mode & FMODE_READ) {
1510 if (s->dma_adc.count >= (signed)s->dma_adc.fragsize)
1511 mask |= POLLIN | POLLRDNORM;
1512 }
1513 if (file->f_mode & FMODE_WRITE) {
1514 if (s->dma_dac.mapped) {
1515 if (s->dma_dac.count >= (signed)s->dma_dac.fragsize)
1516 mask |= POLLOUT | POLLWRNORM;
1517 } else {
1518 if ((signed)s->dma_dac.dmasize >= s->dma_dac.count + (signed)s->dma_dac.fragsize)
1519 mask |= POLLOUT | POLLWRNORM;
1520 }
1521 }
1522 spin_unlock_irqrestore(&s->lock, flags);
1523 return mask;
1524 }
1525
1526 static int sv_mmap(struct file *file, struct vm_area_struct *vma)
1527 {
1528 struct sv_state *s = (struct sv_state *)file->private_data;
1529 struct dmabuf *db;
1530 int ret = -EINVAL;
1531 unsigned long size;
1532
1533 VALIDATE_STATE(s);
1534 lock_kernel();
1535 if (vma->vm_flags & VM_WRITE) {
1536 if ((ret = prog_dmabuf(s, 1)) != 0)
1537 goto out;
1538 db = &s->dma_dac;
1539 } else if (vma->vm_flags & VM_READ) {
1540 if ((ret = prog_dmabuf(s, 0)) != 0)
1541 goto out;
1542 db = &s->dma_adc;
1543 } else
1544 goto out;
1545 ret = -EINVAL;
1546 if (vma->vm_pgoff != 0)
1547 goto out;
1548 size = vma->vm_end - vma->vm_start;
1549 if (size > (PAGE_SIZE << db->buforder))
1550 goto out;
1551 ret = -EAGAIN;
1552 if (remap_pfn_range(vma, vma->vm_start,
1553 virt_to_phys(db->rawbuf) >> PAGE_SHIFT,
1554 size, vma->vm_page_prot))
1555 goto out;
1556 db->mapped = 1;
1557 ret = 0;
1558 out:
1559 unlock_kernel();
1560 return ret;
1561 }
1562
1563 static int sv_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
1564 {
1565 struct sv_state *s = (struct sv_state *)file->private_data;
1566 unsigned long flags;
1567 audio_buf_info abinfo;
1568 count_info cinfo;
1569 int count;
1570 int val, mapped, ret;
1571 unsigned char fmtm, fmtd;
1572 void __user *argp = (void __user *)arg;
1573 int __user *p = argp;
1574
1575 VALIDATE_STATE(s);
1576 mapped = ((file->f_mode & FMODE_WRITE) && s->dma_dac.mapped) ||
1577 ((file->f_mode & FMODE_READ) && s->dma_adc.mapped);
1578 switch (cmd) {
1579 case OSS_GETVERSION:
1580 return put_user(SOUND_VERSION, p);
1581
1582 case SNDCTL_DSP_SYNC:
1583 if (file->f_mode & FMODE_WRITE)
1584 return drain_dac(s, 0/*file->f_flags & O_NONBLOCK*/);
1585 return 0;
1586
1587 case SNDCTL_DSP_SETDUPLEX:
1588 return 0;
1589
1590 case SNDCTL_DSP_GETCAPS:
1591 return put_user(DSP_CAP_DUPLEX | DSP_CAP_REALTIME | DSP_CAP_TRIGGER | DSP_CAP_MMAP, p);
1592
1593 case SNDCTL_DSP_RESET:
1594 if (file->f_mode & FMODE_WRITE) {
1595 stop_dac(s);
1596 synchronize_irq(s->irq);
1597 s->dma_dac.swptr = s->dma_dac.hwptr = s->dma_dac.count = s->dma_dac.total_bytes = 0;
1598 }
1599 if (file->f_mode & FMODE_READ) {
1600 stop_adc(s);
1601 synchronize_irq(s->irq);
1602 s->dma_adc.swptr = s->dma_adc.hwptr = s->dma_adc.count = s->dma_adc.total_bytes = 0;
1603 }
1604 return 0;
1605
1606 case SNDCTL_DSP_SPEED:
1607 if (get_user(val, p))
1608 return -EFAULT;
1609 if (val >= 0) {
1610 if (file->f_mode & FMODE_READ) {
1611 stop_adc(s);
1612 s->dma_adc.ready = 0;
1613 set_adc_rate(s, val);
1614 }
1615 if (file->f_mode & FMODE_WRITE) {
1616 stop_dac(s);
1617 s->dma_dac.ready = 0;
1618 set_dac_rate(s, val);
1619 }
1620 }
1621 return put_user((file->f_mode & FMODE_READ) ? s->rateadc : s->ratedac, p);
1622
1623 case SNDCTL_DSP_STEREO:
1624 if (get_user(val, p))
1625 return -EFAULT;
1626 fmtd = 0;
1627 fmtm = ~0;
1628 if (file->f_mode & FMODE_READ) {
1629 stop_adc(s);
1630 s->dma_adc.ready = 0;
1631 if (val)
1632 fmtd |= SV_CFMT_STEREO << SV_CFMT_CSHIFT;
1633 else
1634 fmtm &= ~(SV_CFMT_STEREO << SV_CFMT_CSHIFT);
1635 }
1636 if (file->f_mode & FMODE_WRITE) {
1637 stop_dac(s);
1638 s->dma_dac.ready = 0;
1639 if (val)
1640 fmtd |= SV_CFMT_STEREO << SV_CFMT_ASHIFT;
1641 else
1642 fmtm &= ~(SV_CFMT_STEREO << SV_CFMT_ASHIFT);
1643 }
1644 set_fmt(s, fmtm, fmtd);
1645 return 0;
1646
1647 case SNDCTL_DSP_CHANNELS:
1648 if (get_user(val, p))
1649 return -EFAULT;
1650 if (val != 0) {
1651 fmtd = 0;
1652 fmtm = ~0;
1653 if (file->f_mode & FMODE_READ) {
1654 stop_adc(s);
1655 s->dma_adc.ready = 0;
1656 if (val >= 2)
1657 fmtd |= SV_CFMT_STEREO << SV_CFMT_CSHIFT;
1658 else
1659 fmtm &= ~(SV_CFMT_STEREO << SV_CFMT_CSHIFT);
1660 }
1661 if (file->f_mode & FMODE_WRITE) {
1662 stop_dac(s);
1663 s->dma_dac.ready = 0;
1664 if (val >= 2)
1665 fmtd |= SV_CFMT_STEREO << SV_CFMT_ASHIFT;
1666 else
1667 fmtm &= ~(SV_CFMT_STEREO << SV_CFMT_ASHIFT);
1668 }
1669 set_fmt(s, fmtm, fmtd);
1670 }
1671 return put_user((s->fmt & ((file->f_mode & FMODE_READ) ? (SV_CFMT_STEREO << SV_CFMT_CSHIFT)
1672 : (SV_CFMT_STEREO << SV_CFMT_ASHIFT))) ? 2 : 1, p);
1673
1674 case SNDCTL_DSP_GETFMTS: /* Returns a mask */
1675 return put_user(AFMT_S16_LE|AFMT_U8, p);
1676
1677 case SNDCTL_DSP_SETFMT: /* Selects ONE fmt*/
1678 if (get_user(val, p))
1679 return -EFAULT;
1680 if (val != AFMT_QUERY) {
1681 fmtd = 0;
1682 fmtm = ~0;
1683 if (file->f_mode & FMODE_READ) {
1684 stop_adc(s);
1685 s->dma_adc.ready = 0;
1686 if (val == AFMT_S16_LE)
1687 fmtd |= SV_CFMT_16BIT << SV_CFMT_CSHIFT;
1688 else
1689 fmtm &= ~(SV_CFMT_16BIT << SV_CFMT_CSHIFT);
1690 }
1691 if (file->f_mode & FMODE_WRITE) {
1692 stop_dac(s);
1693 s->dma_dac.ready = 0;
1694 if (val == AFMT_S16_LE)
1695 fmtd |= SV_CFMT_16BIT << SV_CFMT_ASHIFT;
1696 else
1697 fmtm &= ~(SV_CFMT_16BIT << SV_CFMT_ASHIFT);
1698 }
1699 set_fmt(s, fmtm, fmtd);
1700 }
1701 return put_user((s->fmt & ((file->f_mode & FMODE_READ) ? (SV_CFMT_16BIT << SV_CFMT_CSHIFT)
1702 : (SV_CFMT_16BIT << SV_CFMT_ASHIFT))) ? AFMT_S16_LE : AFMT_U8, p);
1703
1704 case SNDCTL_DSP_POST:
1705 return 0;
1706
1707 case SNDCTL_DSP_GETTRIGGER:
1708 val = 0;
1709 if (file->f_mode & FMODE_READ && s->enable & SV_CENABLE_RE)
1710 val |= PCM_ENABLE_INPUT;
1711 if (file->f_mode & FMODE_WRITE && s->enable & SV_CENABLE_PE)
1712 val |= PCM_ENABLE_OUTPUT;
1713 return put_user(val, p);
1714
1715 case SNDCTL_DSP_SETTRIGGER:
1716 if (get_user(val, p))
1717 return -EFAULT;
1718 if (file->f_mode & FMODE_READ) {
1719 if (val & PCM_ENABLE_INPUT) {
1720 if (!s->dma_adc.ready && (ret = prog_dmabuf(s, 1)))
1721 return ret;
1722 s->dma_adc.enabled = 1;
1723 start_adc(s);
1724 } else {
1725 s->dma_adc.enabled = 0;
1726 stop_adc(s);
1727 }
1728 }
1729 if (file->f_mode & FMODE_WRITE) {
1730 if (val & PCM_ENABLE_OUTPUT) {
1731 if (!s->dma_dac.ready && (ret = prog_dmabuf(s, 0)))
1732 return ret;
1733 s->dma_dac.enabled = 1;
1734 start_dac(s);
1735 } else {
1736 s->dma_dac.enabled = 0;
1737 stop_dac(s);
1738 }
1739 }
1740 return 0;
1741
1742 case SNDCTL_DSP_GETOSPACE:
1743 if (!(file->f_mode & FMODE_WRITE))
1744 return -EINVAL;
1745 if (!s->dma_dac.ready && (val = prog_dmabuf(s, 0)) != 0)
1746 return val;
1747 spin_lock_irqsave(&s->lock, flags);
1748 sv_update_ptr(s);
1749 abinfo.fragsize = s->dma_dac.fragsize;
1750 count = s->dma_dac.count;
1751 if (count < 0)
1752 count = 0;
1753 abinfo.bytes = s->dma_dac.dmasize - count;
1754 abinfo.fragstotal = s->dma_dac.numfrag;
1755 abinfo.fragments = abinfo.bytes >> s->dma_dac.fragshift;
1756 spin_unlock_irqrestore(&s->lock, flags);
1757 return copy_to_user(argp, &abinfo, sizeof(abinfo)) ? -EFAULT : 0;
1758
1759 case SNDCTL_DSP_GETISPACE:
1760 if (!(file->f_mode & FMODE_READ))
1761 return -EINVAL;
1762 if (!s->dma_adc.ready && (val = prog_dmabuf(s, 1)) != 0)
1763 return val;
1764 spin_lock_irqsave(&s->lock, flags);
1765 sv_update_ptr(s);
1766 abinfo.fragsize = s->dma_adc.fragsize;
1767 count = s->dma_adc.count;
1768 if (count < 0)
1769 count = 0;
1770 abinfo.bytes = count;
1771 abinfo.fragstotal = s->dma_adc.numfrag;
1772 abinfo.fragments = abinfo.bytes >> s->dma_adc.fragshift;
1773 spin_unlock_irqrestore(&s->lock, flags);
1774 return copy_to_user(argp, &abinfo, sizeof(abinfo)) ? -EFAULT : 0;
1775
1776 case SNDCTL_DSP_NONBLOCK:
1777 file->f_flags |= O_NONBLOCK;
1778 return 0;
1779
1780 case SNDCTL_DSP_GETODELAY:
1781 if (!(file->f_mode & FMODE_WRITE))
1782 return -EINVAL;
1783 if (!s->dma_dac.ready && (val = prog_dmabuf(s, 0)) != 0)
1784 return val;
1785 spin_lock_irqsave(&s->lock, flags);
1786 sv_update_ptr(s);
1787 count = s->dma_dac.count;
1788 spin_unlock_irqrestore(&s->lock, flags);
1789 if (count < 0)
1790 count = 0;
1791 return put_user(count, p);
1792
1793 case SNDCTL_DSP_GETIPTR:
1794 if (!(file->f_mode & FMODE_READ))
1795 return -EINVAL;
1796 if (!s->dma_adc.ready && (val = prog_dmabuf(s, 1)) != 0)
1797 return val;
1798 spin_lock_irqsave(&s->lock, flags);
1799 sv_update_ptr(s);
1800 cinfo.bytes = s->dma_adc.total_bytes;
1801 count = s->dma_adc.count;
1802 if (count < 0)
1803 count = 0;
1804 cinfo.blocks = count >> s->dma_adc.fragshift;
1805 cinfo.ptr = s->dma_adc.hwptr;
1806 if (s->dma_adc.mapped)
1807 s->dma_adc.count &= s->dma_adc.fragsize-1;
1808 spin_unlock_irqrestore(&s->lock, flags);
1809 if (copy_to_user(argp, &cinfo, sizeof(cinfo)))
1810 return -EFAULT;
1811 return 0;
1812
1813 case SNDCTL_DSP_GETOPTR:
1814 if (!(file->f_mode & FMODE_WRITE))
1815 return -EINVAL;
1816 if (!s->dma_dac.ready && (val = prog_dmabuf(s, 0)) != 0)
1817 return val;
1818 spin_lock_irqsave(&s->lock, flags);
1819 sv_update_ptr(s);
1820 cinfo.bytes = s->dma_dac.total_bytes;
1821 count = s->dma_dac.count;
1822 if (count < 0)
1823 count = 0;
1824 cinfo.blocks = count >> s->dma_dac.fragshift;
1825 cinfo.ptr = s->dma_dac.hwptr;
1826 if (s->dma_dac.mapped)
1827 s->dma_dac.count &= s->dma_dac.fragsize-1;
1828 spin_unlock_irqrestore(&s->lock, flags);
1829 if (copy_to_user(argp, &cinfo, sizeof(cinfo)))
1830 return -EFAULT;
1831 return 0;
1832
1833 case SNDCTL_DSP_GETBLKSIZE:
1834 if (file->f_mode & FMODE_WRITE) {
1835 if ((val = prog_dmabuf(s, 0)))
1836 return val;
1837 return put_user(s->dma_dac.fragsize, p);
1838 }
1839 if ((val = prog_dmabuf(s, 1)))
1840 return val;
1841 return put_user(s->dma_adc.fragsize, p);
1842
1843 case SNDCTL_DSP_SETFRAGMENT:
1844 if (get_user(val, p))
1845 return -EFAULT;
1846 if (file->f_mode & FMODE_READ) {
1847 s->dma_adc.ossfragshift = val & 0xffff;
1848 s->dma_adc.ossmaxfrags = (val >> 16) & 0xffff;
1849 if (s->dma_adc.ossfragshift < 4)
1850 s->dma_adc.ossfragshift = 4;
1851 if (s->dma_adc.ossfragshift > 15)
1852 s->dma_adc.ossfragshift = 15;
1853 if (s->dma_adc.ossmaxfrags < 4)
1854 s->dma_adc.ossmaxfrags = 4;
1855 }
1856 if (file->f_mode & FMODE_WRITE) {
1857 s->dma_dac.ossfragshift = val & 0xffff;
1858 s->dma_dac.ossmaxfrags = (val >> 16) & 0xffff;
1859 if (s->dma_dac.ossfragshift < 4)
1860 s->dma_dac.ossfragshift = 4;
1861 if (s->dma_dac.ossfragshift > 15)
1862 s->dma_dac.ossfragshift = 15;
1863 if (s->dma_dac.ossmaxfrags < 4)
1864 s->dma_dac.ossmaxfrags = 4;
1865 }
1866 return 0;
1867
1868 case SNDCTL_DSP_SUBDIVIDE:
1869 if ((file->f_mode & FMODE_READ && s->dma_adc.subdivision) ||
1870 (file->f_mode & FMODE_WRITE && s->dma_dac.subdivision))
1871 return -EINVAL;
1872 if (get_user(val, p))
1873 return -EFAULT;
1874 if (val != 1 && val != 2 && val != 4)
1875 return -EINVAL;
1876 if (file->f_mode & FMODE_READ)
1877 s->dma_adc.subdivision = val;
1878 if (file->f_mode & FMODE_WRITE)
1879 s->dma_dac.subdivision = val;
1880 return 0;
1881
1882 case SOUND_PCM_READ_RATE:
1883 return put_user((file->f_mode & FMODE_READ) ? s->rateadc : s->ratedac, p);
1884
1885 case SOUND_PCM_READ_CHANNELS:
1886 return put_user((s->fmt & ((file->f_mode & FMODE_READ) ? (SV_CFMT_STEREO << SV_CFMT_CSHIFT)
1887 : (SV_CFMT_STEREO << SV_CFMT_ASHIFT))) ? 2 : 1, p);
1888
1889 case SOUND_PCM_READ_BITS:
1890 return put_user((s->fmt & ((file->f_mode & FMODE_READ) ? (SV_CFMT_16BIT << SV_CFMT_CSHIFT)
1891 : (SV_CFMT_16BIT << SV_CFMT_ASHIFT))) ? 16 : 8, p);
1892
1893 case SOUND_PCM_WRITE_FILTER:
1894 case SNDCTL_DSP_SETSYNCRO:
1895 case SOUND_PCM_READ_FILTER:
1896 return -EINVAL;
1897
1898 }
1899 return mixer_ioctl(s, cmd, arg);
1900 }
1901
1902 static int sv_open(struct inode *inode, struct file *file)
1903 {
1904 int minor = iminor(inode);
1905 DECLARE_WAITQUEUE(wait, current);
1906 unsigned char fmtm = ~0, fmts = 0;
1907 struct list_head *list;
1908 struct sv_state *s;
1909
1910 for (list = devs.next; ; list = list->next) {
1911 if (list == &devs)
1912 return -ENODEV;
1913 s = list_entry(list, struct sv_state, devs);
1914 if (!((s->dev_audio ^ minor) & ~0xf))
1915 break;
1916 }
1917 VALIDATE_STATE(s);
1918 file->private_data = s;
1919 /* wait for device to become free */
1920 down(&s->open_sem);
1921 while (s->open_mode & file->f_mode) {
1922 if (file->f_flags & O_NONBLOCK) {
1923 up(&s->open_sem);
1924 return -EBUSY;
1925 }
1926 add_wait_queue(&s->open_wait, &wait);
1927 __set_current_state(TASK_INTERRUPTIBLE);
1928 up(&s->open_sem);
1929 schedule();
1930 remove_wait_queue(&s->open_wait, &wait);
1931 set_current_state(TASK_RUNNING);
1932 if (signal_pending(current))
1933 return -ERESTARTSYS;
1934 down(&s->open_sem);
1935 }
1936 if (file->f_mode & FMODE_READ) {
1937 fmtm &= ~((SV_CFMT_STEREO | SV_CFMT_16BIT) << SV_CFMT_CSHIFT);
1938 if ((minor & 0xf) == SND_DEV_DSP16)
1939 fmts |= SV_CFMT_16BIT << SV_CFMT_CSHIFT;
1940 s->dma_adc.ossfragshift = s->dma_adc.ossmaxfrags = s->dma_adc.subdivision = 0;
1941 s->dma_adc.enabled = 1;
1942 set_adc_rate(s, 8000);
1943 }
1944 if (file->f_mode & FMODE_WRITE) {
1945 fmtm &= ~((SV_CFMT_STEREO | SV_CFMT_16BIT) << SV_CFMT_ASHIFT);
1946 if ((minor & 0xf) == SND_DEV_DSP16)
1947 fmts |= SV_CFMT_16BIT << SV_CFMT_ASHIFT;
1948 s->dma_dac.ossfragshift = s->dma_dac.ossmaxfrags = s->dma_dac.subdivision = 0;
1949 s->dma_dac.enabled = 1;
1950 set_dac_rate(s, 8000);
1951 }
1952 set_fmt(s, fmtm, fmts);
1953 s->open_mode |= file->f_mode & (FMODE_READ | FMODE_WRITE);
1954 up(&s->open_sem);
1955 return nonseekable_open(inode, file);
1956 }
1957
1958 static int sv_release(struct inode *inode, struct file *file)
1959 {
1960 struct sv_state *s = (struct sv_state *)file->private_data;
1961
1962 VALIDATE_STATE(s);
1963 lock_kernel();
1964 if (file->f_mode & FMODE_WRITE)
1965 drain_dac(s, file->f_flags & O_NONBLOCK);
1966 down(&s->open_sem);
1967 if (file->f_mode & FMODE_WRITE) {
1968 stop_dac(s);
1969 dealloc_dmabuf(s, &s->dma_dac);
1970 }
1971 if (file->f_mode & FMODE_READ) {
1972 stop_adc(s);
1973 dealloc_dmabuf(s, &s->dma_adc);
1974 }
1975 s->open_mode &= ~(file->f_mode & (FMODE_READ|FMODE_WRITE));
1976 wake_up(&s->open_wait);
1977 up(&s->open_sem);
1978 unlock_kernel();
1979 return 0;
1980 }
1981
1982 static /*const*/ struct file_operations sv_audio_fops = {
1983 .owner = THIS_MODULE,
1984 .llseek = no_llseek,
1985 .read = sv_read,
1986 .write = sv_write,
1987 .poll = sv_poll,
1988 .ioctl = sv_ioctl,
1989 .mmap = sv_mmap,
1990 .open = sv_open,
1991 .release = sv_release,
1992 };
1993
1994 /* --------------------------------------------------------------------- */
1995
1996 static ssize_t sv_midi_read(struct file *file, char __user *buffer, size_t count, loff_t *ppos)
1997 {
1998 struct sv_state *s = (struct sv_state *)file->private_data;
1999 DECLARE_WAITQUEUE(wait, current);
2000 ssize_t ret;
2001 unsigned long flags;
2002 unsigned ptr;
2003 int cnt;
2004
2005 VALIDATE_STATE(s);
2006 if (!access_ok(VERIFY_WRITE, buffer, count))
2007 return -EFAULT;
2008 if (count == 0)
2009 return 0;
2010 ret = 0;
2011 add_wait_queue(&s->midi.iwait, &wait);
2012 while (count > 0) {
2013 spin_lock_irqsave(&s->lock, flags);
2014 ptr = s->midi.ird;
2015 cnt = MIDIINBUF - ptr;
2016 if (s->midi.icnt < cnt)
2017 cnt = s->midi.icnt;
2018 if (cnt <= 0)
2019 __set_current_state(TASK_INTERRUPTIBLE);
2020 spin_unlock_irqrestore(&s->lock, flags);
2021 if (cnt > count)
2022 cnt = count;
2023 if (cnt <= 0) {
2024 if (file->f_flags & O_NONBLOCK) {
2025 if (!ret)
2026 ret = -EAGAIN;
2027 break;
2028 }
2029 schedule();
2030 if (signal_pending(current)) {
2031 if (!ret)
2032 ret = -ERESTARTSYS;
2033 break;
2034 }
2035 continue;
2036 }
2037 if (copy_to_user(buffer, s->midi.ibuf + ptr, cnt)) {
2038 if (!ret)
2039 ret = -EFAULT;
2040 break;
2041 }
2042 ptr = (ptr + cnt) % MIDIINBUF;
2043 spin_lock_irqsave(&s->lock, flags);
2044 s->midi.ird = ptr;
2045 s->midi.icnt -= cnt;
2046 spin_unlock_irqrestore(&s->lock, flags);
2047 count -= cnt;
2048 buffer += cnt;
2049 ret += cnt;
2050 break;
2051 }
2052 __set_current_state(TASK_RUNNING);
2053 remove_wait_queue(&s->midi.iwait, &wait);
2054 return ret;
2055 }
2056
2057 static ssize_t sv_midi_write(struct file *file, const char __user *buffer, size_t count, loff_t *ppos)
2058 {
2059 struct sv_state *s = (struct sv_state *)file->private_data;
2060 DECLARE_WAITQUEUE(wait, current);
2061 ssize_t ret;
2062 unsigned long flags;
2063 unsigned ptr;
2064 int cnt;
2065
2066 VALIDATE_STATE(s);
2067 if (!access_ok(VERIFY_READ, buffer, count))
2068 return -EFAULT;
2069 if (count == 0)
2070 return 0;
2071 ret = 0;
2072 add_wait_queue(&s->midi.owait, &wait);
2073 while (count > 0) {
2074 spin_lock_irqsave(&s->lock, flags);
2075 ptr = s->midi.owr;
2076 cnt = MIDIOUTBUF - ptr;
2077 if (s->midi.ocnt + cnt > MIDIOUTBUF)
2078 cnt = MIDIOUTBUF - s->midi.ocnt;
2079 if (cnt <= 0) {
2080 __set_current_state(TASK_INTERRUPTIBLE);
2081 sv_handle_midi(s);
2082 }
2083 spin_unlock_irqrestore(&s->lock, flags);
2084 if (cnt > count)
2085 cnt = count;
2086 if (cnt <= 0) {
2087 if (file->f_flags & O_NONBLOCK) {
2088 if (!ret)
2089 ret = -EAGAIN;
2090 break;
2091 }
2092 schedule();
2093 if (signal_pending(current)) {
2094 if (!ret)
2095 ret = -ERESTARTSYS;
2096 break;
2097 }
2098 continue;
2099 }
2100 if (copy_from_user(s->midi.obuf + ptr, buffer, cnt)) {
2101 if (!ret)
2102 ret = -EFAULT;
2103 break;
2104 }
2105 ptr = (ptr + cnt) % MIDIOUTBUF;
2106 spin_lock_irqsave(&s->lock, flags);
2107 s->midi.owr = ptr;
2108 s->midi.ocnt += cnt;
2109 spin_unlock_irqrestore(&s->lock, flags);
2110 count -= cnt;
2111 buffer += cnt;
2112 ret += cnt;
2113 spin_lock_irqsave(&s->lock, flags);
2114 sv_handle_midi(s);
2115 spin_unlock_irqrestore(&s->lock, flags);
2116 }
2117 __set_current_state(TASK_RUNNING);
2118 remove_wait_queue(&s->midi.owait, &wait);
2119 return ret;
2120 }
2121
2122 /* No kernel lock - we have our own spinlock */
2123 static unsigned int sv_midi_poll(struct file *file, struct poll_table_struct *wait)
2124 {
2125 struct sv_state *s = (struct sv_state *)file->private_data;
2126 unsigned long flags;
2127 unsigned int mask = 0;
2128
2129 VALIDATE_STATE(s);
2130 if (file->f_mode & FMODE_WRITE)
2131 poll_wait(file, &s->midi.owait, wait);
2132 if (file->f_mode & FMODE_READ)
2133 poll_wait(file, &s->midi.iwait, wait);
2134 spin_lock_irqsave(&s->lock, flags);
2135 if (file->f_mode & FMODE_READ) {
2136 if (s->midi.icnt > 0)
2137 mask |= POLLIN | POLLRDNORM;
2138 }
2139 if (file->f_mode & FMODE_WRITE) {
2140 if (s->midi.ocnt < MIDIOUTBUF)
2141 mask |= POLLOUT | POLLWRNORM;
2142 }
2143 spin_unlock_irqrestore(&s->lock, flags);
2144 return mask;
2145 }
2146
2147 static int sv_midi_open(struct inode *inode, struct file *file)
2148 {
2149 int minor = iminor(inode);
2150 DECLARE_WAITQUEUE(wait, current);
2151 unsigned long flags;
2152 struct list_head *list;
2153 struct sv_state *s;
2154
2155 for (list = devs.next; ; list = list->next) {
2156 if (list == &devs)
2157 return -ENODEV;
2158 s = list_entry(list, struct sv_state, devs);
2159 if (s->dev_midi == minor)
2160 break;
2161 }
2162 VALIDATE_STATE(s);
2163 file->private_data = s;
2164 /* wait for device to become free */
2165 down(&s->open_sem);
2166 while (s->open_mode & (file->f_mode << FMODE_MIDI_SHIFT)) {
2167 if (file->f_flags & O_NONBLOCK) {
2168 up(&s->open_sem);
2169 return -EBUSY;
2170 }
2171 add_wait_queue(&s->open_wait, &wait);
2172 __set_current_state(TASK_INTERRUPTIBLE);
2173 up(&s->open_sem);
2174 schedule();
2175 remove_wait_queue(&s->open_wait, &wait);
2176 set_current_state(TASK_RUNNING);
2177 if (signal_pending(current))
2178 return -ERESTARTSYS;
2179 down(&s->open_sem);
2180 }
2181 spin_lock_irqsave(&s->lock, flags);
2182 if (!(s->open_mode & (FMODE_MIDI_READ | FMODE_MIDI_WRITE))) {
2183 s->midi.ird = s->midi.iwr = s->midi.icnt = 0;
2184 s->midi.ord = s->midi.owr = s->midi.ocnt = 0;
2185 //outb(inb(s->ioenh + SV_CODEC_CONTROL) | SV_CCTRL_WAVETABLE, s->ioenh + SV_CODEC_CONTROL);
2186 outb(inb(s->ioenh + SV_CODEC_INTMASK) | SV_CINTMASK_MIDI, s->ioenh + SV_CODEC_INTMASK);
2187 wrindir(s, SV_CIUARTCONTROL, 5); /* output MIDI data to external and internal synth */
2188 wrindir(s, SV_CIWAVETABLESRC, 1); /* Wavetable in PC RAM */
2189 outb(0xff, s->iomidi+1); /* reset command */
2190 outb(0x3f, s->iomidi+1); /* uart command */
2191 if (!(inb(s->iomidi+1) & 0x80))
2192 inb(s->iomidi);
2193 s->midi.ird = s->midi.iwr = s->midi.icnt = 0;
2194 init_timer(&s->midi.timer);
2195 s->midi.timer.expires = jiffies+1;
2196 s->midi.timer.data = (unsigned long)s;
2197 s->midi.timer.function = sv_midi_timer;
2198 add_timer(&s->midi.timer);
2199 }
2200 if (file->f_mode & FMODE_READ) {
2201 s->midi.ird = s->midi.iwr = s->midi.icnt = 0;
2202 }
2203 if (file->f_mode & FMODE_WRITE) {
2204 s->midi.ord = s->midi.owr = s->midi.ocnt = 0;
2205 }
2206 spin_unlock_irqrestore(&s->lock, flags);
2207 s->open_mode |= (file->f_mode << FMODE_MIDI_SHIFT) & (FMODE_MIDI_READ | FMODE_MIDI_WRITE);
2208 up(&s->open_sem);
2209 return nonseekable_open(inode, file);
2210 }
2211
2212 static int sv_midi_release(struct inode *inode, struct file *file)
2213 {
2214 struct sv_state *s = (struct sv_state *)file->private_data;
2215 DECLARE_WAITQUEUE(wait, current);
2216 unsigned long flags;
2217 unsigned count, tmo;
2218
2219 VALIDATE_STATE(s);
2220
2221 lock_kernel();
2222 if (file->f_mode & FMODE_WRITE) {
2223 add_wait_queue(&s->midi.owait, &wait);
2224 for (;;) {
2225 __set_current_state(TASK_INTERRUPTIBLE);
2226 spin_lock_irqsave(&s->lock, flags);
2227 count = s->midi.ocnt;
2228 spin_unlock_irqrestore(&s->lock, flags);
2229 if (count <= 0)
2230 break;
2231 if (signal_pending(current))
2232 break;
2233 if (file->f_flags & O_NONBLOCK) {
2234 remove_wait_queue(&s->midi.owait, &wait);
2235 set_current_state(TASK_RUNNING);
2236 unlock_kernel();
2237 return -EBUSY;
2238 }
2239 tmo = (count * HZ) / 3100;
2240 if (!schedule_timeout(tmo ? : 1) && tmo)
2241 printk(KERN_DEBUG "sv: midi timed out??\n");
2242 }
2243 remove_wait_queue(&s->midi.owait, &wait);
2244 set_current_state(TASK_RUNNING);
2245 }
2246 down(&s->open_sem);
2247 s->open_mode &= ~((file->f_mode << FMODE_MIDI_SHIFT) & (FMODE_MIDI_READ|FMODE_MIDI_WRITE));
2248 spin_lock_irqsave(&s->lock, flags);
2249 if (!(s->open_mode & (FMODE_MIDI_READ | FMODE_MIDI_WRITE))) {
2250 outb(inb(s->ioenh + SV_CODEC_INTMASK) & ~SV_CINTMASK_MIDI, s->ioenh + SV_CODEC_INTMASK);
2251 del_timer(&s->midi.timer);
2252 }
2253 spin_unlock_irqrestore(&s->lock, flags);
2254 wake_up(&s->open_wait);
2255 up(&s->open_sem);
2256 unlock_kernel();
2257 return 0;
2258 }
2259
2260 static /*const*/ struct file_operations sv_midi_fops = {
2261 .owner = THIS_MODULE,
2262 .llseek = no_llseek,
2263 .read = sv_midi_read,
2264 .write = sv_midi_write,
2265 .poll = sv_midi_poll,
2266 .open = sv_midi_open,
2267 .release = sv_midi_release,
2268 };
2269
2270 /* --------------------------------------------------------------------- */
2271
2272 static int sv_dmfm_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
2273 {
2274 static const unsigned char op_offset[18] = {
2275 0x00, 0x01, 0x02, 0x03, 0x04, 0x05,
2276 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D,
2277 0x10, 0x11, 0x12, 0x13, 0x14, 0x15
2278 };
2279 struct sv_state *s = (struct sv_state *)file->private_data;
2280 struct dm_fm_voice v;
2281 struct dm_fm_note n;
2282 struct dm_fm_params p;
2283 unsigned int io;
2284 unsigned int regb;
2285
2286 switch (cmd) {
2287 case FM_IOCTL_RESET:
2288 for (regb = 0xb0; regb < 0xb9; regb++) {
2289 outb(regb, s->iosynth);
2290 outb(0, s->iosynth+1);
2291 outb(regb, s->iosynth+2);
2292 outb(0, s->iosynth+3);
2293 }
2294 return 0;
2295
2296 case FM_IOCTL_PLAY_NOTE:
2297 if (copy_from_user(&n, (void __user *)arg, sizeof(n)))
2298 return -EFAULT;
2299 if (n.voice >= 18)
2300 return -EINVAL;
2301 if (n.voice >= 9) {
2302 regb = n.voice - 9;
2303 io = s->iosynth+2;
2304 } else {
2305 regb = n.voice;
2306 io = s->iosynth;
2307 }
2308 outb(0xa0 + regb, io);
2309 outb(n.fnum & 0xff, io+1);
2310 outb(0xb0 + regb, io);
2311 outb(((n.fnum >> 8) & 3) | ((n.octave & 7) << 2) | ((n.key_on & 1) << 5), io+1);
2312 return 0;
2313
2314 case FM_IOCTL_SET_VOICE:
2315 if (copy_from_user(&v, (void __user *)arg, sizeof(v)))
2316 return -EFAULT;
2317 if (v.voice >= 18)
2318 return -EINVAL;
2319 regb = op_offset[v.voice];
2320 io = s->iosynth + ((v.op & 1) << 1);
2321 outb(0x20 + regb, io);
2322 outb(((v.am & 1) << 7) | ((v.vibrato & 1) << 6) | ((v.do_sustain & 1) << 5) |
2323 ((v.kbd_scale & 1) << 4) | (v.harmonic & 0xf), io+1);
2324 outb(0x40 + regb, io);
2325 outb(((v.scale_level & 0x3) << 6) | (v.volume & 0x3f), io+1);
2326 outb(0x60 + regb, io);
2327 outb(((v.attack & 0xf) << 4) | (v.decay & 0xf), io+1);
2328 outb(0x80 + regb, io);
2329 outb(((v.sustain & 0xf) << 4) | (v.release & 0xf), io+1);
2330 outb(0xe0 + regb, io);
2331 outb(v.waveform & 0x7, io+1);
2332 if (n.voice >= 9) {
2333 regb = n.voice - 9;
2334 io = s->iosynth+2;
2335 } else {
2336 regb = n.voice;
2337 io = s->iosynth;
2338 }
2339 outb(0xc0 + regb, io);
2340 outb(((v.right & 1) << 5) | ((v.left & 1) << 4) | ((v.feedback & 7) << 1) |
2341 (v.connection & 1), io+1);
2342 return 0;
2343
2344 case FM_IOCTL_SET_PARAMS:
2345 if (copy_from_user(&p, (void *__user )arg, sizeof(p)))
2346 return -EFAULT;
2347 outb(0x08, s->iosynth);
2348 outb((p.kbd_split & 1) << 6, s->iosynth+1);
2349 outb(0xbd, s->iosynth);
2350 outb(((p.am_depth & 1) << 7) | ((p.vib_depth & 1) << 6) | ((p.rhythm & 1) << 5) | ((p.bass & 1) << 4) |
2351 ((p.snare & 1) << 3) | ((p.tomtom & 1) << 2) | ((p.cymbal & 1) << 1) | (p.hihat & 1), s->iosynth+1);
2352 return 0;
2353
2354 case FM_IOCTL_SET_OPL:
2355 outb(4, s->iosynth+2);
2356 outb(arg, s->iosynth+3);
2357 return 0;
2358
2359 case FM_IOCTL_SET_MODE:
2360 outb(5, s->iosynth+2);
2361 outb(arg & 1, s->iosynth+3);
2362 return 0;
2363
2364 default:
2365 return -EINVAL;
2366 }
2367 }
2368
2369 static int sv_dmfm_open(struct inode *inode, struct file *file)
2370 {
2371 int minor = iminor(inode);
2372 DECLARE_WAITQUEUE(wait, current);
2373 struct list_head *list;
2374 struct sv_state *s;
2375
2376 for (list = devs.next; ; list = list->next) {
2377 if (list == &devs)
2378 return -ENODEV;
2379 s = list_entry(list, struct sv_state, devs);
2380 if (s->dev_dmfm == minor)
2381 break;
2382 }
2383 VALIDATE_STATE(s);
2384 file->private_data = s;
2385 /* wait for device to become free */
2386 down(&s->open_sem);
2387 while (s->open_mode & FMODE_DMFM) {
2388 if (file->f_flags & O_NONBLOCK) {
2389 up(&s->open_sem);
2390 return -EBUSY;
2391 }
2392 add_wait_queue(&s->open_wait, &wait);
2393 __set_current_state(TASK_INTERRUPTIBLE);
2394 up(&s->open_sem);
2395 schedule();
2396 remove_wait_queue(&s->open_wait, &wait);
2397 set_current_state(TASK_RUNNING);
2398 if (signal_pending(current))
2399 return -ERESTARTSYS;
2400 down(&s->open_sem);
2401 }
2402 /* init the stuff */
2403 outb(1, s->iosynth);
2404 outb(0x20, s->iosynth+1); /* enable waveforms */
2405 outb(4, s->iosynth+2);
2406 outb(0, s->iosynth+3); /* no 4op enabled */
2407 outb(5, s->iosynth+2);
2408 outb(1, s->iosynth+3); /* enable OPL3 */
2409 s->open_mode |= FMODE_DMFM;
2410 up(&s->open_sem);
2411 return nonseekable_open(inode, file);
2412 }
2413
2414 static int sv_dmfm_release(struct inode *inode, struct file *file)
2415 {
2416 struct sv_state *s = (struct sv_state *)file->private_data;
2417 unsigned int regb;
2418
2419 VALIDATE_STATE(s);
2420 lock_kernel();
2421 down(&s->open_sem);
2422 s->open_mode &= ~FMODE_DMFM;
2423 for (regb = 0xb0; regb < 0xb9; regb++) {
2424 outb(regb, s->iosynth);
2425 outb(0, s->iosynth+1);
2426 outb(regb, s->iosynth+2);
2427 outb(0, s->iosynth+3);
2428 }
2429 wake_up(&s->open_wait);
2430 up(&s->open_sem);
2431 unlock_kernel();
2432 return 0;
2433 }
2434
2435 static /*const*/ struct file_operations sv_dmfm_fops = {
2436 .owner = THIS_MODULE,
2437 .llseek = no_llseek,
2438 .ioctl = sv_dmfm_ioctl,
2439 .open = sv_dmfm_open,
2440 .release = sv_dmfm_release,
2441 };
2442
2443 /* --------------------------------------------------------------------- */
2444
2445 /* maximum number of devices; only used for command line params */
2446 #define NR_DEVICE 5
2447
2448 static int reverb[NR_DEVICE];
2449
2450 #if 0
2451 static int wavetable[NR_DEVICE];
2452 #endif
2453
2454 static unsigned int devindex;
2455
2456 module_param_array(reverb, bool, NULL, 0);
2457 MODULE_PARM_DESC(reverb, "if 1 enables the reverb circuitry. NOTE: your card must have the reverb RAM");
2458 #if 0
2459 MODULE_PARM(wavetable, "1-" __MODULE_STRING(NR_DEVICE) "i");
2460 MODULE_PARM_DESC(wavetable, "if 1 the wavetable synth is enabled");
2461 #endif
2462
2463 MODULE_AUTHOR("Thomas M. Sailer, sailer@ife.ee.ethz.ch, hb9jnx@hb9w.che.eu");
2464 MODULE_DESCRIPTION("S3 SonicVibes Driver");
2465 MODULE_LICENSE("GPL");
2466
2467
2468 /* --------------------------------------------------------------------- */
2469
2470 static struct initvol {
2471 int mixch;
2472 int vol;
2473 } initvol[] __devinitdata = {
2474 { SOUND_MIXER_WRITE_RECLEV, 0x4040 },
2475 { SOUND_MIXER_WRITE_LINE1, 0x4040 },
2476 { SOUND_MIXER_WRITE_CD, 0x4040 },
2477 { SOUND_MIXER_WRITE_LINE, 0x4040 },
2478 { SOUND_MIXER_WRITE_MIC, 0x4040 },
2479 { SOUND_MIXER_WRITE_SYNTH, 0x4040 },
2480 { SOUND_MIXER_WRITE_LINE2, 0x4040 },
2481 { SOUND_MIXER_WRITE_VOLUME, 0x4040 },
2482 { SOUND_MIXER_WRITE_PCM, 0x4040 }
2483 };
2484
2485 #define RSRCISIOREGION(dev,num) (pci_resource_start((dev), (num)) != 0 && \
2486 (pci_resource_flags((dev), (num)) & IORESOURCE_IO))
2487
2488 static int __devinit sv_register_gameport(struct sv_state *s, int io_port)
2489 {
2490 struct gameport *gp;
2491
2492 if (!request_region(io_port, SV_EXTENT_GAME, "S3 SonicVibes Gameport")) {
2493 printk(KERN_ERR "sv: gameport io ports are in use\n");
2494 return -EBUSY;
2495 }
2496
2497 s->gameport = gp = gameport_allocate_port();
2498 if (!gp) {
2499 printk(KERN_ERR "sv: can not allocate memory for gameport\n");
2500 release_region(io_port, SV_EXTENT_GAME);
2501 return -ENOMEM;
2502 }
2503
2504 gameport_set_name(gp, "S3 SonicVibes Gameport");
2505 gameport_set_phys(gp, "isa%04x/gameport0", io_port);
2506 gp->dev.parent = &s->dev->dev;
2507 gp->io = io_port;
2508
2509 gameport_register_port(gp);
2510
2511 return 0;
2512 }
2513
2514 static int __devinit sv_probe(struct pci_dev *pcidev, const struct pci_device_id *pciid)
2515 {
2516 static char __devinitdata sv_ddma_name[] = "S3 Inc. SonicVibes DDMA Controller";
2517 struct sv_state *s;
2518 mm_segment_t fs;
2519 int i, val, ret;
2520 int gpio;
2521 char *ddmaname;
2522 unsigned ddmanamelen;
2523
2524 if ((ret=pci_enable_device(pcidev)))
2525 return ret;
2526
2527 if (!RSRCISIOREGION(pcidev, RESOURCE_SB) ||
2528 !RSRCISIOREGION(pcidev, RESOURCE_ENH) ||
2529 !RSRCISIOREGION(pcidev, RESOURCE_SYNTH) ||
2530 !RSRCISIOREGION(pcidev, RESOURCE_MIDI) ||
2531 !RSRCISIOREGION(pcidev, RESOURCE_GAME))
2532 return -ENODEV;
2533 if (pcidev->irq == 0)
2534 return -ENODEV;
2535 if (pci_set_dma_mask(pcidev, 0x00ffffff)) {
2536 printk(KERN_WARNING "sonicvibes: architecture does not support 24bit PCI busmaster DMA\n");
2537 return -ENODEV;
2538 }
2539 /* try to allocate a DDMA resource if not already available */
2540 if (!RSRCISIOREGION(pcidev, RESOURCE_DDMA)) {
2541 pcidev->resource[RESOURCE_DDMA].start = 0;
2542 pcidev->resource[RESOURCE_DDMA].end = 2*SV_EXTENT_DMA-1;
2543 pcidev->resource[RESOURCE_DDMA].flags = PCI_BASE_ADDRESS_SPACE_IO | IORESOURCE_IO;
2544 ddmanamelen = strlen(sv_ddma_name)+1;
2545 if (!(ddmaname = kmalloc(ddmanamelen, GFP_KERNEL)))
2546 return -1;
2547 memcpy(ddmaname, sv_ddma_name, ddmanamelen);
2548 pcidev->resource[RESOURCE_DDMA].name = ddmaname;
2549 if (pci_assign_resource(pcidev, RESOURCE_DDMA)) {
2550 pcidev->resource[RESOURCE_DDMA].name = NULL;
2551 kfree(ddmaname);
2552 printk(KERN_ERR "sv: cannot allocate DDMA controller io ports\n");
2553 return -EBUSY;
2554 }
2555 }
2556 if (!(s = kmalloc(sizeof(struct sv_state), GFP_KERNEL))) {
2557 printk(KERN_WARNING "sv: out of memory\n");
2558 return -ENOMEM;
2559 }
2560 memset(s, 0, sizeof(struct sv_state));
2561 init_waitqueue_head(&s->dma_adc.wait);
2562 init_waitqueue_head(&s->dma_dac.wait);
2563 init_waitqueue_head(&s->open_wait);
2564 init_waitqueue_head(&s->midi.iwait);
2565 init_waitqueue_head(&s->midi.owait);
2566 init_MUTEX(&s->open_sem);
2567 spin_lock_init(&s->lock);
2568 s->magic = SV_MAGIC;
2569 s->dev = pcidev;
2570 s->iosb = pci_resource_start(pcidev, RESOURCE_SB);
2571 s->ioenh = pci_resource_start(pcidev, RESOURCE_ENH);
2572 s->iosynth = pci_resource_start(pcidev, RESOURCE_SYNTH);
2573 s->iomidi = pci_resource_start(pcidev, RESOURCE_MIDI);
2574 s->iodmaa = pci_resource_start(pcidev, RESOURCE_DDMA);
2575 s->iodmac = pci_resource_start(pcidev, RESOURCE_DDMA) + SV_EXTENT_DMA;
2576 gpio = pci_resource_start(pcidev, RESOURCE_GAME);
2577 pci_write_config_dword(pcidev, 0x40, s->iodmaa | 9); /* enable and use extended mode */
2578 pci_write_config_dword(pcidev, 0x48, s->iodmac | 9); /* enable */
2579 printk(KERN_DEBUG "sv: io ports: %#lx %#lx %#lx %#lx %#x %#x %#x\n",
2580 s->iosb, s->ioenh, s->iosynth, s->iomidi, gpio, s->iodmaa, s->iodmac);
2581 s->irq = pcidev->irq;
2582
2583 /* hack */
2584 pci_write_config_dword(pcidev, 0x60, wavetable_mem >> 12); /* wavetable base address */
2585
2586 ret = -EBUSY;
2587 if (!request_region(s->ioenh, SV_EXTENT_ENH, "S3 SonicVibes PCM")) {
2588 printk(KERN_ERR "sv: io ports %#lx-%#lx in use\n", s->ioenh, s->ioenh+SV_EXTENT_ENH-1);
2589 goto err_region5;
2590 }
2591 if (!request_region(s->iodmaa, SV_EXTENT_DMA, "S3 SonicVibes DMAA")) {
2592 printk(KERN_ERR "sv: io ports %#x-%#x in use\n", s->iodmaa, s->iodmaa+SV_EXTENT_DMA-1);
2593 goto err_region4;
2594 }
2595 if (!request_region(s->iodmac, SV_EXTENT_DMA, "S3 SonicVibes DMAC")) {
2596 printk(KERN_ERR "sv: io ports %#x-%#x in use\n", s->iodmac, s->iodmac+SV_EXTENT_DMA-1);
2597 goto err_region3;
2598 }
2599 if (!request_region(s->iomidi, SV_EXTENT_MIDI, "S3 SonicVibes Midi")) {
2600 printk(KERN_ERR "sv: io ports %#lx-%#lx in use\n", s->iomidi, s->iomidi+SV_EXTENT_MIDI-1);
2601 goto err_region2;
2602 }
2603 if (!request_region(s->iosynth, SV_EXTENT_SYNTH, "S3 SonicVibes Synth")) {
2604 printk(KERN_ERR "sv: io ports %#lx-%#lx in use\n", s->iosynth, s->iosynth+SV_EXTENT_SYNTH-1);
2605 goto err_region1;
2606 }
2607
2608 /* initialize codec registers */
2609 outb(0x80, s->ioenh + SV_CODEC_CONTROL); /* assert reset */
2610 udelay(50);
2611 outb(0x00, s->ioenh + SV_CODEC_CONTROL); /* deassert reset */
2612 udelay(50);
2613 outb(SV_CCTRL_INTADRIVE | SV_CCTRL_ENHANCED /*| SV_CCTRL_WAVETABLE */
2614 | (reverb[devindex] ? SV_CCTRL_REVERB : 0), s->ioenh + SV_CODEC_CONTROL);
2615 inb(s->ioenh + SV_CODEC_STATUS); /* clear ints */
2616 wrindir(s, SV_CIDRIVECONTROL, 0); /* drive current 16mA */
2617 wrindir(s, SV_CIENABLE, s->enable = 0); /* disable DMAA and DMAC */
2618 outb(~(SV_CINTMASK_DMAA | SV_CINTMASK_DMAC), s->ioenh + SV_CODEC_INTMASK);
2619 /* outb(0xff, s->iodmaa + SV_DMA_RESET); */
2620 /* outb(0xff, s->iodmac + SV_DMA_RESET); */
2621 inb(s->ioenh + SV_CODEC_STATUS); /* ack interrupts */
2622 wrindir(s, SV_CIADCCLKSOURCE, 0); /* use pll as ADC clock source */
2623 wrindir(s, SV_CIANALOGPWRDOWN, 0); /* power up the analog parts of the device */
2624 wrindir(s, SV_CIDIGITALPWRDOWN, 0); /* power up the digital parts of the device */
2625 setpll(s, SV_CIADCPLLM, 8000);
2626 wrindir(s, SV_CISRSSPACE, 0x80); /* SRS off */
2627 wrindir(s, SV_CIPCMSR0, (8000 * 65536 / FULLRATE) & 0xff);
2628 wrindir(s, SV_CIPCMSR1, ((8000 * 65536 / FULLRATE) >> 8) & 0xff);
2629 wrindir(s, SV_CIADCOUTPUT, 0);
2630 /* request irq */
2631 if ((ret=request_irq(s->irq,sv_interrupt,SA_SHIRQ,"S3 SonicVibes",s))) {
2632 printk(KERN_ERR "sv: irq %u in use\n", s->irq);
2633 goto err_irq;
2634 }
2635 printk(KERN_INFO "sv: found adapter at io %#lx irq %u dmaa %#06x dmac %#06x revision %u\n",
2636 s->ioenh, s->irq, s->iodmaa, s->iodmac, rdindir(s, SV_CIREVISION));
2637 /* register devices */
2638 if ((s->dev_audio = register_sound_dsp(&sv_audio_fops, -1)) < 0) {
2639 ret = s->dev_audio;
2640 goto err_dev1;
2641 }
2642 if ((s->dev_mixer = register_sound_mixer(&sv_mixer_fops, -1)) < 0) {
2643 ret = s->dev_mixer;
2644 goto err_dev2;
2645 }
2646 if ((s->dev_midi = register_sound_midi(&sv_midi_fops, -1)) < 0) {
2647 ret = s->dev_midi;
2648 goto err_dev3;
2649 }
2650 if ((s->dev_dmfm = register_sound_special(&sv_dmfm_fops, 15 /* ?? */)) < 0) {
2651 ret = s->dev_dmfm;
2652 goto err_dev4;
2653 }
2654 pci_set_master(pcidev); /* enable bus mastering */
2655 /* initialize the chips */
2656 fs = get_fs();
2657 set_fs(KERNEL_DS);
2658 val = SOUND_MASK_LINE|SOUND_MASK_SYNTH;
2659 mixer_ioctl(s, SOUND_MIXER_WRITE_RECSRC, (unsigned long)&val);
2660 for (i = 0; i < sizeof(initvol)/sizeof(initvol[0]); i++) {
2661 val = initvol[i].vol;
2662 mixer_ioctl(s, initvol[i].mixch, (unsigned long)&val);
2663 }
2664 set_fs(fs);
2665 /* register gameport */
2666 sv_register_gameport(s, gpio);
2667 /* store it in the driver field */
2668 pci_set_drvdata(pcidev, s);
2669 /* put it into driver list */
2670 list_add_tail(&s->devs, &devs);
2671 /* increment devindex */
2672 if (devindex < NR_DEVICE-1)
2673 devindex++;
2674 return 0;
2675
2676 err_dev4:
2677 unregister_sound_midi(s->dev_midi);
2678 err_dev3:
2679 unregister_sound_mixer(s->dev_mixer);
2680 err_dev2:
2681 unregister_sound_dsp(s->dev_audio);
2682 err_dev1:
2683 printk(KERN_ERR "sv: cannot register misc device\n");
2684 free_irq(s->irq, s);
2685 err_irq:
2686 release_region(s->iosynth, SV_EXTENT_SYNTH);
2687 err_region1:
2688 release_region(s->iomidi, SV_EXTENT_MIDI);
2689 err_region2:
2690 release_region(s->iodmac, SV_EXTENT_DMA);
2691 err_region3:
2692 release_region(s->iodmaa, SV_EXTENT_DMA);
2693 err_region4:
2694 release_region(s->ioenh, SV_EXTENT_ENH);
2695 err_region5:
2696 kfree(s);
2697 return ret;
2698 }
2699
2700 static void __devexit sv_remove(struct pci_dev *dev)
2701 {
2702 struct sv_state *s = pci_get_drvdata(dev);
2703
2704 if (!s)
2705 return;
2706 list_del(&s->devs);
2707 outb(~0, s->ioenh + SV_CODEC_INTMASK); /* disable ints */
2708 synchronize_irq(s->irq);
2709 inb(s->ioenh + SV_CODEC_STATUS); /* ack interrupts */
2710 wrindir(s, SV_CIENABLE, 0); /* disable DMAA and DMAC */
2711 /*outb(0, s->iodmaa + SV_DMA_RESET);*/
2712 /*outb(0, s->iodmac + SV_DMA_RESET);*/
2713 free_irq(s->irq, s);
2714 if (s->gameport) {
2715 int gpio = s->gameport->io;
2716 gameport_unregister_port(s->gameport);
2717 release_region(gpio, SV_EXTENT_GAME);
2718 }
2719 release_region(s->iodmac, SV_EXTENT_DMA);
2720 release_region(s->iodmaa, SV_EXTENT_DMA);
2721 release_region(s->ioenh, SV_EXTENT_ENH);
2722 release_region(s->iomidi, SV_EXTENT_MIDI);
2723 release_region(s->iosynth, SV_EXTENT_SYNTH);
2724 unregister_sound_dsp(s->dev_audio);
2725 unregister_sound_mixer(s->dev_mixer);
2726 unregister_sound_midi(s->dev_midi);
2727 unregister_sound_special(s->dev_dmfm);
2728 kfree(s);
2729 pci_set_drvdata(dev, NULL);
2730 }
2731
2732 static struct pci_device_id id_table[] = {
2733 { PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_SONICVIBES, PCI_ANY_ID, PCI_ANY_ID, 0, 0 },
2734 { 0, }
2735 };
2736
2737 MODULE_DEVICE_TABLE(pci, id_table);
2738
2739 static struct pci_driver sv_driver = {
2740 .name = "sonicvibes",
2741 .id_table = id_table,
2742 .probe = sv_probe,
2743 .remove = __devexit_p(sv_remove),
2744 };
2745
2746 static int __init init_sonicvibes(void)
2747 {
2748 printk(KERN_INFO "sv: version v0.31 time " __TIME__ " " __DATE__ "\n");
2749 #if 0
2750 if (!(wavetable_mem = __get_free_pages(GFP_KERNEL, 20-PAGE_SHIFT)))
2751 printk(KERN_INFO "sv: cannot allocate 1MB of contiguous nonpageable memory for wavetable data\n");
2752 #endif
2753 return pci_module_init(&sv_driver);
2754 }
2755
2756 static void __exit cleanup_sonicvibes(void)
2757 {
2758 printk(KERN_INFO "sv: unloading\n");
2759 pci_unregister_driver(&sv_driver);
2760 if (wavetable_mem)
2761 free_pages(wavetable_mem, 20-PAGE_SHIFT);
2762 }
2763
2764 module_init(init_sonicvibes);
2765 module_exit(cleanup_sonicvibes);
2766
2767 /* --------------------------------------------------------------------- */
2768
2769 #ifndef MODULE
2770
2771 /* format is: sonicvibes=[reverb] sonicvibesdmaio=dmaioaddr */
2772
2773 static int __init sonicvibes_setup(char *str)
2774 {
2775 static unsigned __initdata nr_dev = 0;
2776
2777 if (nr_dev >= NR_DEVICE)
2778 return 0;
2779 #if 0
2780 if (get_option(&str, &reverb[nr_dev]) == 2)
2781 (void)get_option(&str, &wavetable[nr_dev]);
2782 #else
2783 (void)get_option(&str, &reverb[nr_dev]);
2784 #endif
2785
2786 nr_dev++;
2787 return 1;
2788 }
2789
2790 __setup("sonicvibes=", sonicvibes_setup);
2791
2792 #endif /* MODULE */
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree