2 * Contains the definition of registers common to all PowerPC variants.
3 * If a register definition has been changed in a different PowerPC
4 * variant, we will case it in #ifndef XXX ... #endif, and have the
5 * number used in the Programming Environments Manual For 32-Bit
6 * Implementations of the PowerPC Architecture (a.k.a. Green Book) here.
10 #ifndef __ASM_PPC_REGS_H__
11 #define __ASM_PPC_REGS_H__
13 #include <linux/stringify.h>
15 /* Pickup Book E specific registers. */
16 #if defined(CONFIG_BOOKE) || defined(CONFIG_40x)
17 #include <asm/reg_booke.h>
20 /* Machine State Register (MSR) Fields */
21 #define MSR_SF (1<<63)
22 #define MSR_ISF (1<<61)
23 #define MSR_VEC (1<<25) /* Enable AltiVec */
24 #define MSR_POW (1<<18) /* Enable Power Management */
25 #define MSR_WE (1<<18) /* Wait State Enable */
26 #define MSR_TGPR (1<<17) /* TLB Update registers in use */
27 #define MSR_CE (1<<17) /* Critical Interrupt Enable */
28 #define MSR_ILE (1<<16) /* Interrupt Little Endian */
29 #define MSR_EE (1<<15) /* External Interrupt Enable */
30 #define MSR_PR (1<<14) /* Problem State / Privilege Level */
31 #define MSR_FP (1<<13) /* Floating Point enable */
32 #define MSR_ME (1<<12) /* Machine Check Enable */
33 #define MSR_FE0 (1<<11) /* Floating Exception mode 0 */
34 #define MSR_SE (1<<10) /* Single Step */
35 #define MSR_BE (1<<9) /* Branch Trace */
36 #define MSR_DE (1<<9) /* Debug Exception Enable */
37 #define MSR_FE1 (1<<8) /* Floating Exception mode 1 */
38 #define MSR_IP (1<<6) /* Exception prefix 0x000/0xFFF */
39 #define MSR_IR (1<<5) /* Instruction Relocate */
40 #define MSR_DR (1<<4) /* Data Relocate */
41 #define MSR_PE (1<<3) /* Protection Enable */
42 #define MSR_PX (1<<2) /* Protection Exclusive Mode */
43 #define MSR_RI (1<<1) /* Recoverable Exception */
44 #define MSR_LE (1<<0) /* Little Endian */
46 /* Default MSR for kernel mode. */
47 #ifdef CONFIG_APUS_FAST_EXCEPT
48 #define MSR_KERNEL (MSR_ME|MSR_IP|MSR_RI|MSR_IR|MSR_DR)
52 #define MSR_KERNEL (MSR_ME|MSR_RI|MSR_IR|MSR_DR)
55 #define MSR_USER (MSR_KERNEL|MSR_PR|MSR_EE)
57 /* Floating Point Status and Control Register (FPSCR) Fields */
58 #define FPSCR_FX 0x80000000 /* FPU exception summary */
59 #define FPSCR_FEX 0x40000000 /* FPU enabled exception summary */
60 #define FPSCR_VX 0x20000000 /* Invalid operation summary */
61 #define FPSCR_OX 0x10000000 /* Overflow exception summary */
62 #define FPSCR_UX 0x08000000 /* Underflow exception summary */
63 #define FPSCR_ZX 0x04000000 /* Zero-devide exception summary */
64 #define FPSCR_XX 0x02000000 /* Inexact exception summary */
65 #define FPSCR_VXSNAN 0x01000000 /* Invalid op for SNaN */
66 #define FPSCR_VXISI 0x00800000 /* Invalid op for Inv - Inv */
67 #define FPSCR_VXIDI 0x00400000 /* Invalid op for Inv / Inv */
68 #define FPSCR_VXZDZ 0x00200000 /* Invalid op for Zero / Zero */
69 #define FPSCR_VXIMZ 0x00100000 /* Invalid op for Inv * Zero */
70 #define FPSCR_VXVC 0x00080000 /* Invalid op for Compare */
71 #define FPSCR_FR 0x00040000 /* Fraction rounded */
72 #define FPSCR_FI 0x00020000 /* Fraction inexact */
73 #define FPSCR_FPRF 0x0001f000 /* FPU Result Flags */
74 #define FPSCR_FPCC 0x0000f000 /* FPU Condition Codes */
75 #define FPSCR_VXSOFT 0x00000400 /* Invalid op for software request */
76 #define FPSCR_VXSQRT 0x00000200 /* Invalid op for square root */
77 #define FPSCR_VXCVI 0x00000100 /* Invalid op for integer convert */
78 #define FPSCR_VE 0x00000080 /* Invalid op exception enable */
79 #define FPSCR_OE 0x00000040 /* IEEE overflow exception enable */
80 #define FPSCR_UE 0x00000020 /* IEEE underflow exception enable */
81 #define FPSCR_ZE 0x00000010 /* IEEE zero divide exception enable */
82 #define FPSCR_XE 0x00000008 /* FP inexact exception enable */
83 #define FPSCR_NI 0x00000004 /* FPU non IEEE-Mode */
84 #define FPSCR_RN 0x00000003 /* FPU rounding control */
86 /* Special Purpose Registers (SPRNs)*/
87 #define SPRN_CTR 0x009 /* Count Register */
88 #define SPRN_DABR 0x3F5 /* Data Address Breakpoint Register */
89 #define SPRN_DAR 0x013 /* Data Address Register */
90 #define SPRN_TBRL 0x10C /* Time Base Read Lower Register (user, R/O) */
91 #define SPRN_TBRU 0x10D /* Time Base Read Upper Register (user, R/O) */
92 #define SPRN_TBWL 0x11C /* Time Base Lower Register (super, R/W) */
93 #define SPRN_TBWU 0x11D /* Time Base Upper Register (super, R/W) */
94 #define SPRN_HIOR 0x137 /* 970 Hypervisor interrupt offset */
95 #define SPRN_DBAT0L 0x219 /* Data BAT 0 Lower Register */
96 #define SPRN_DBAT0U 0x218 /* Data BAT 0 Upper Register */
97 #define SPRN_DBAT1L 0x21B /* Data BAT 1 Lower Register */
98 #define SPRN_DBAT1U 0x21A /* Data BAT 1 Upper Register */
99 #define SPRN_DBAT2L 0x21D /* Data BAT 2 Lower Register */
100 #define SPRN_DBAT2U 0x21C /* Data BAT 2 Upper Register */
101 #define SPRN_DBAT3L 0x21F /* Data BAT 3 Lower Register */
102 #define SPRN_DBAT3U 0x21E /* Data BAT 3 Upper Register */
103 #define SPRN_DBAT4L 0x239 /* Data BAT 4 Lower Register */
104 #define SPRN_DBAT4U 0x238 /* Data BAT 4 Upper Register */
105 #define SPRN_DBAT5L 0x23B /* Data BAT 5 Lower Register */
106 #define SPRN_DBAT5U 0x23A /* Data BAT 5 Upper Register */
107 #define SPRN_DBAT6L 0x23D /* Data BAT 6 Lower Register */
108 #define SPRN_DBAT6U 0x23C /* Data BAT 6 Upper Register */
109 #define SPRN_DBAT7L 0x23F /* Data BAT 7 Lower Register */
110 #define SPRN_DBAT7U 0x23E /* Data BAT 7 Upper Register */
112 #define SPRN_DEC 0x016 /* Decrement Register */
113 #define SPRN_DER 0x095 /* Debug Enable Regsiter */
114 #define DER_RSTE 0x40000000 /* Reset Interrupt */
115 #define DER_CHSTPE 0x20000000 /* Check Stop */
116 #define DER_MCIE 0x10000000 /* Machine Check Interrupt */
117 #define DER_EXTIE 0x02000000 /* External Interrupt */
118 #define DER_ALIE 0x01000000 /* Alignment Interrupt */
119 #define DER_PRIE 0x00800000 /* Program Interrupt */
120 #define DER_FPUVIE 0x00400000 /* FP Unavailable Interrupt */
121 #define DER_DECIE 0x00200000 /* Decrementer Interrupt */
122 #define DER_SYSIE 0x00040000 /* System Call Interrupt */
123 #define DER_TRE 0x00020000 /* Trace Interrupt */
124 #define DER_SEIE 0x00004000 /* FP SW Emulation Interrupt */
125 #define DER_ITLBMSE 0x00002000 /* Imp. Spec. Instruction TLB Miss */
126 #define DER_ITLBERE 0x00001000 /* Imp. Spec. Instruction TLB Error */
127 #define DER_DTLBMSE 0x00000800 /* Imp. Spec. Data TLB Miss */
128 #define DER_DTLBERE 0x00000400 /* Imp. Spec. Data TLB Error */
129 #define DER_LBRKE 0x00000008 /* Load/Store Breakpoint Interrupt */
130 #define DER_IBRKE 0x00000004 /* Instruction Breakpoint Interrupt */
131 #define DER_EBRKE 0x00000002 /* External Breakpoint Interrupt */
132 #define DER_DPIE 0x00000001 /* Dev. Port Nonmaskable Request */
133 #define SPRN_DMISS 0x3D0 /* Data TLB Miss Register */
134 #define SPRN_DSISR 0x012 /* Data Storage Interrupt Status Register */
135 #define SPRN_EAR 0x11A /* External Address Register */
136 #define SPRN_HASH1 0x3D2 /* Primary Hash Address Register */
137 #define SPRN_HASH2 0x3D3 /* Secondary Hash Address Resgister */
138 #define SPRN_HID0 0x3F0 /* Hardware Implementation Register 0 */
139 #define HID0_EMCP (1<<31) /* Enable Machine Check pin */
140 #define HID0_EBA (1<<29) /* Enable Bus Address Parity */
141 #define HID0_EBD (1<<28) /* Enable Bus Data Parity */
142 #define HID0_SBCLK (1<<27)
143 #define HID0_EICE (1<<26)
144 #define HID0_TBEN (1<<26) /* Timebase enable - 745x */
145 #define HID0_ECLK (1<<25)
146 #define HID0_PAR (1<<24)
147 #define HID0_STEN (1<<24) /* Software table search enable - 745x */
148 #define HID0_HIGH_BAT (1<<23) /* Enable high BATs - 7455 */
149 #define HID0_DOZE (1<<23)
150 #define HID0_NAP (1<<22)
151 #define HID0_SLEEP (1<<21)
152 #define HID0_DPM (1<<20)
153 #define HID0_BHTCLR (1<<18) /* Clear branch history table - 7450 */
154 #define HID0_XAEN (1<<17) /* Extended addressing enable - 7450 */
155 #define HID0_NHR (1<<16) /* Not hard reset (software bit-7450)*/
156 #define HID0_ICE (1<<15) /* Instruction Cache Enable */
157 #define HID0_DCE (1<<14) /* Data Cache Enable */
158 #define HID0_ILOCK (1<<13) /* Instruction Cache Lock */
159 #define HID0_DLOCK (1<<12) /* Data Cache Lock */
160 #define HID0_ICFI (1<<11) /* Instr. Cache Flash Invalidate */
161 #define HID0_DCI (1<<10) /* Data Cache Invalidate */
162 #define HID0_SPD (1<<9) /* Speculative disable */
163 #define HID0_SGE (1<<7) /* Store Gathering Enable */
164 #define HID0_SIED (1<<7) /* Serial Instr. Execution [Disable] */
165 #define HID0_DFCA (1<<6) /* Data Cache Flush Assist */
166 #define HID0_LRSTK (1<<4) /* Link register stack - 745x */
167 #define HID0_BTIC (1<<5) /* Branch Target Instr Cache Enable */
168 #define HID0_ABE (1<<3) /* Address Broadcast Enable */
169 #define HID0_FOLD (1<<3) /* Branch Folding enable - 745x */
170 #define HID0_BHTE (1<<2) /* Branch History Table Enable */
171 #define HID0_BTCD (1<<1) /* Branch target cache disable */
172 #define HID0_NOPDST (1<<1) /* No-op dst, dstt, etc. instr. */
173 #define HID0_NOPTI (1<<0) /* No-op dcbt and dcbst instr. */
175 #define SPRN_HID1 0x3F1 /* Hardware Implementation Register 1 */
176 #define HID1_EMCP (1<<31) /* 7450 Machine Check Pin Enable */
177 #define HID1_DFS (1<<22) /* 7447A Dynamic Frequency Scaling */
178 #define HID1_PC0 (1<<16) /* 7450 PLL_CFG[0] */
179 #define HID1_PC1 (1<<15) /* 7450 PLL_CFG[1] */
180 #define HID1_PC2 (1<<14) /* 7450 PLL_CFG[2] */
181 #define HID1_PC3 (1<<13) /* 7450 PLL_CFG[3] */
182 #define HID1_SYNCBE (1<<11) /* 7450 ABE for sync, eieio */
183 #define HID1_ABE (1<<10) /* 7450 Address Broadcast Enable */
184 #define SPRN_HID2 0x3F8 /* Hardware Implementation Register 2 */
185 #define SPRN_IABR 0x3F2 /* Instruction Address Breakpoint Register */
186 #define SPRN_HID4 0x3F4 /* 970 HID4 */
187 #define SPRN_HID5 0x3F6 /* 970 HID5 */
188 #if !defined(SPRN_IAC1) && !defined(SPRN_IAC2)
189 #define SPRN_IAC1 0x3F4 /* Instruction Address Compare 1 */
190 #define SPRN_IAC2 0x3F5 /* Instruction Address Compare 2 */
192 #define SPRN_IBAT0L 0x211 /* Instruction BAT 0 Lower Register */
193 #define SPRN_IBAT0U 0x210 /* Instruction BAT 0 Upper Register */
194 #define SPRN_IBAT1L 0x213 /* Instruction BAT 1 Lower Register */
195 #define SPRN_IBAT1U 0x212 /* Instruction BAT 1 Upper Register */
196 #define SPRN_IBAT2L 0x215 /* Instruction BAT 2 Lower Register */
197 #define SPRN_IBAT2U 0x214 /* Instruction BAT 2 Upper Register */
198 #define SPRN_IBAT3L 0x217 /* Instruction BAT 3 Lower Register */
199 #define SPRN_IBAT3U 0x216 /* Instruction BAT 3 Upper Register */
200 #define SPRN_IBAT4L 0x231 /* Instruction BAT 4 Lower Register */
201 #define SPRN_IBAT4U 0x230 /* Instruction BAT 4 Upper Register */
202 #define SPRN_IBAT5L 0x233 /* Instruction BAT 5 Lower Register */
203 #define SPRN_IBAT5U 0x232 /* Instruction BAT 5 Upper Register */
204 #define SPRN_IBAT6L 0x235 /* Instruction BAT 6 Lower Register */
205 #define SPRN_IBAT6U 0x234 /* Instruction BAT 6 Upper Register */
206 #define SPRN_IBAT7L 0x237 /* Instruction BAT 7 Lower Register */
207 #define SPRN_IBAT7U 0x236 /* Instruction BAT 7 Upper Register */
208 #define SPRN_ICMP 0x3D5 /* Instruction TLB Compare Register */
209 #define SPRN_ICTC 0x3FB /* Instruction Cache Throttling Control Reg */
210 #define SPRN_ICTRL 0x3F3 /* 1011 7450 icache and interrupt ctrl */
211 #define ICTRL_EICE 0x08000000 /* enable icache parity errs */
212 #define ICTRL_EDC 0x04000000 /* enable dcache parity errs */
213 #define ICTRL_EICP 0x00000100 /* enable icache par. check */
214 #define SPRN_IMISS 0x3D4 /* Instruction TLB Miss Register */
215 #define SPRN_IMMR 0x27E /* Internal Memory Map Register */
216 #define SPRN_L2CR 0x3F9 /* Level 2 Cache Control Regsiter */
217 #define SPRN_L2CR2 0x3f8
218 #define L2CR_L2E 0x80000000 /* L2 enable */
219 #define L2CR_L2PE 0x40000000 /* L2 parity enable */
220 #define L2CR_L2SIZ_MASK 0x30000000 /* L2 size mask */
221 #define L2CR_L2SIZ_256KB 0x10000000 /* L2 size 256KB */
222 #define L2CR_L2SIZ_512KB 0x20000000 /* L2 size 512KB */
223 #define L2CR_L2SIZ_1MB 0x30000000 /* L2 size 1MB */
224 #define L2CR_L2CLK_MASK 0x0e000000 /* L2 clock mask */
225 #define L2CR_L2CLK_DISABLED 0x00000000 /* L2 clock disabled */
226 #define L2CR_L2CLK_DIV1 0x02000000 /* L2 clock / 1 */
227 #define L2CR_L2CLK_DIV1_5 0x04000000 /* L2 clock / 1.5 */
228 #define L2CR_L2CLK_DIV2 0x08000000 /* L2 clock / 2 */
229 #define L2CR_L2CLK_DIV2_5 0x0a000000 /* L2 clock / 2.5 */
230 #define L2CR_L2CLK_DIV3 0x0c000000 /* L2 clock / 3 */
231 #define L2CR_L2RAM_MASK 0x01800000 /* L2 RAM type mask */
232 #define L2CR_L2RAM_FLOW 0x00000000 /* L2 RAM flow through */
233 #define L2CR_L2RAM_PIPE 0x01000000 /* L2 RAM pipelined */
234 #define L2CR_L2RAM_PIPE_LW 0x01800000 /* L2 RAM pipelined latewr */
235 #define L2CR_L2DO 0x00400000 /* L2 data only */
236 #define L2CR_L2I 0x00200000 /* L2 global invalidate */
237 #define L2CR_L2CTL 0x00100000 /* L2 RAM control */
238 #define L2CR_L2WT 0x00080000 /* L2 write-through */
239 #define L2CR_L2TS 0x00040000 /* L2 test support */
240 #define L2CR_L2OH_MASK 0x00030000 /* L2 output hold mask */
241 #define L2CR_L2OH_0_5 0x00000000 /* L2 output hold 0.5 ns */
242 #define L2CR_L2OH_1_0 0x00010000 /* L2 output hold 1.0 ns */
243 #define L2CR_L2SL 0x00008000 /* L2 DLL slow */
244 #define L2CR_L2DF 0x00004000 /* L2 differential clock */
245 #define L2CR_L2BYP 0x00002000 /* L2 DLL bypass */
246 #define L2CR_L2IP 0x00000001 /* L2 GI in progress */
247 #define L2CR_L2IO_745x 0x00100000 /* L2 instr. only (745x) */
248 #define L2CR_L2DO_745x 0x00010000 /* L2 data only (745x) */
249 #define L2CR_L2REP_745x 0x00001000 /* L2 repl. algorithm (745x) */
250 #define L2CR_L2HWF_745x 0x00000800 /* L2 hardware flush (745x) */
251 #define SPRN_L3CR 0x3FA /* Level 3 Cache Control Regsiter */
252 #define L3CR_L3E 0x80000000 /* L3 enable */
253 #define L3CR_L3PE 0x40000000 /* L3 data parity enable */
254 #define L3CR_L3APE 0x20000000 /* L3 addr parity enable */
255 #define L3CR_L3SIZ 0x10000000 /* L3 size */
256 #define L3CR_L3CLKEN 0x08000000 /* L3 clock enable */
257 #define L3CR_L3RES 0x04000000 /* L3 special reserved bit */
258 #define L3CR_L3CLKDIV 0x03800000 /* L3 clock divisor */
259 #define L3CR_L3IO 0x00400000 /* L3 instruction only */
260 #define L3CR_L3SPO 0x00040000 /* L3 sample point override */
261 #define L3CR_L3CKSP 0x00030000 /* L3 clock sample point */
262 #define L3CR_L3PSP 0x0000e000 /* L3 P-clock sample point */
263 #define L3CR_L3REP 0x00001000 /* L3 replacement algorithm */
264 #define L3CR_L3HWF 0x00000800 /* L3 hardware flush */
265 #define L3CR_L3I 0x00000400 /* L3 global invalidate */
266 #define L3CR_L3RT 0x00000300 /* L3 SRAM type */
267 #define L3CR_L3NIRCA 0x00000080 /* L3 non-integer ratio clock adj. */
268 #define L3CR_L3DO 0x00000040 /* L3 data only mode */
269 #define L3CR_PMEN 0x00000004 /* L3 private memory enable */
270 #define L3CR_PMSIZ 0x00000001 /* L3 private memory size */
271 #define SPRN_MSSCR0 0x3f6 /* Memory Subsystem Control Register 0 */
272 #define SPRN_MSSSR0 0x3f7 /* Memory Subsystem Status Register 1 */
273 #define SPRN_LDSTCR 0x3f8 /* Load/Store control register */
274 #define SPRN_LDSTDB 0x3f4 /* */
275 #define SPRN_LR 0x008 /* Link Register */
276 #define SPRN_MMCR0 0x3B8 /* Monitor Mode Control Register 0 */
277 #define SPRN_MMCR1 0x3BC /* Monitor Mode Control Register 1 */
279 #define SPRN_PIR 0x3FF /* Processor Identification Register */
281 #define SPRN_PMC1 0x3B9 /* Performance Counter Register 1 */
282 #define SPRN_PMC2 0x3BA /* Performance Counter Register 2 */
283 #define SPRN_PMC3 0x3BD /* Performance Counter Register 3 */
284 #define SPRN_PMC4 0x3BE /* Performance Counter Register 4 */
285 #define SPRN_PTEHI 0x3D5 /* 981 7450 PTE HI word (S/W TLB load) */
286 #define SPRN_PTELO 0x3D6 /* 982 7450 PTE LO word (S/W TLB load) */
287 #define SPRN_PVR 0x11F /* Processor Version Register */
288 #define SPRN_RPA 0x3D6 /* Required Physical Address Register */
289 #define SPRN_SDA 0x3BF /* Sampled Data Address Register */
290 #define SPRN_SDR1 0x019 /* MMU Hash Base Register */
291 #define SPRN_SIA 0x3BB /* Sampled Instruction Address Register */
292 #define SPRN_SPRG0 0x110 /* Special Purpose Register General 0 */
293 #define SPRN_SPRG1 0x111 /* Special Purpose Register General 1 */
294 #define SPRN_SPRG2 0x112 /* Special Purpose Register General 2 */
295 #define SPRN_SPRG3 0x113 /* Special Purpose Register General 3 */
296 #define SPRN_SPRG4 0x114 /* Special Purpose Register General 4 */
297 #define SPRN_SPRG5 0x115 /* Special Purpose Register General 5 */
298 #define SPRN_SPRG6 0x116 /* Special Purpose Register General 6 */
299 #define SPRN_SPRG7 0x117 /* Special Purpose Register General 7 */
300 #define SPRN_SRR0 0x01A /* Save/Restore Register 0 */
301 #define SPRN_SRR1 0x01B /* Save/Restore Register 1 */
303 #define SPRN_SVR 0x11E /* System Version Register */
305 #define SPRN_THRM1 0x3FC /* Thermal Management Register 1 */
306 /* these bits were defined in inverted endian sense originally, ugh, confusing */
307 #define THRM1_TIN (1 << 31)
308 #define THRM1_TIV (1 << 30)
309 #define THRM1_THRES(x) ((x&0x7f)<<23)
310 #define THRM3_SITV(x) ((x&0x3fff)<<1)
311 #define THRM1_TID (1<<2)
312 #define THRM1_TIE (1<<1)
313 #define THRM1_V (1<<0)
314 #define SPRN_THRM2 0x3FD /* Thermal Management Register 2 */
315 #define SPRN_THRM3 0x3FE /* Thermal Management Register 3 */
316 #define THRM3_E (1<<0)
317 #define SPRN_TLBMISS 0x3D4 /* 980 7450 TLB Miss Register */
318 #define SPRN_UMMCR0 0x3A8 /* User Monitor Mode Control Register 0 */
319 #define SPRN_UMMCR1 0x3AC /* User Monitor Mode Control Register 0 */
320 #define SPRN_UPMC1 0x3A9 /* User Performance Counter Register 1 */
321 #define SPRN_UPMC2 0x3AA /* User Performance Counter Register 2 */
322 #define SPRN_UPMC3 0x3AD /* User Performance Counter Register 3 */
323 #define SPRN_UPMC4 0x3AE /* User Performance Counter Register 4 */
324 #define SPRN_USIA 0x3AB /* User Sampled Instruction Address Register */
325 #define SPRN_VRSAVE 0x100 /* Vector Register Save Register */
326 #define SPRN_XER 0x001 /* Fixed Point Exception Register */
328 /* Bit definitions for MMCR0 and PMC1 / PMC2. */
329 #define MMCR0_PMC1_CYCLES (1 << 7)
330 #define MMCR0_PMC1_ICACHEMISS (5 << 7)
331 #define MMCR0_PMC1_DTLB (6 << 7)
332 #define MMCR0_PMC2_DCACHEMISS 0x6
333 #define MMCR0_PMC2_CYCLES 0x1
334 #define MMCR0_PMC2_ITLB 0x7
335 #define MMCR0_PMC2_LOADMISSTIME 0x5
336 #define MMCR0_PMXE (1 << 26)
338 /* Processor Version Register */
340 /* Processor Version Register (PVR) field extraction */
342 #define PVR_VER(pvr) (((pvr) >> 16) & 0xFFFF) /* Version field */
343 #define PVR_REV(pvr) (((pvr) >> 0) & 0xFFFF) /* Revison field */
346 * IBM has further subdivided the standard PowerPC 16-bit version and
347 * revision subfields of the PVR for the PowerPC 403s into the following:
350 #define PVR_FAM(pvr) (((pvr) >> 20) & 0xFFF) /* Family field */
351 #define PVR_MEM(pvr) (((pvr) >> 16) & 0xF) /* Member field */
352 #define PVR_CORE(pvr) (((pvr) >> 12) & 0xF) /* Core field */
353 #define PVR_CFG(pvr) (((pvr) >> 8) & 0xF) /* Configuration field */
354 #define PVR_MAJ(pvr) (((pvr) >> 4) & 0xF) /* Major revision field */
355 #define PVR_MIN(pvr) (((pvr) >> 0) & 0xF) /* Minor revision field */
357 /* Processor Version Numbers */
359 #define PVR_403GA 0x00200000
360 #define PVR_403GB 0x00200100
361 #define PVR_403GC 0x00200200
362 #define PVR_403GCX 0x00201400
363 #define PVR_405GP 0x40110000
364 #define PVR_STB03XXX 0x40310000
365 #define PVR_NP405H 0x41410000
366 #define PVR_NP405L 0x41610000
367 #define PVR_440GP_RB 0x40120440
368 #define PVR_440GP_RC1 0x40120481
369 #define PVR_440GP_RC2 0x40200481
370 #define PVR_440GX_RA 0x51b21850
371 #define PVR_440GX_RB 0x51b21851
372 #define PVR_440GX_RC 0x51b21892
373 #define PVR_601 0x00010000
374 #define PVR_602 0x00050000
375 #define PVR_603 0x00030000
376 #define PVR_603e 0x00060000
377 #define PVR_603ev 0x00070000
378 #define PVR_603r 0x00071000
379 #define PVR_604 0x00040000
380 #define PVR_604e 0x00090000
381 #define PVR_604r 0x000A0000
382 #define PVR_620 0x00140000
383 #define PVR_740 0x00080000
384 #define PVR_750 PVR_740
385 #define PVR_740P 0x10080000
386 #define PVR_750P PVR_740P
387 #define PVR_7400 0x000C0000
388 #define PVR_7410 0x800C0000
389 #define PVR_7450 0x80000000
390 #define PVR_8540 0x80200000
391 #define PVR_8560 0x80200000
393 * For the 8xx processors, all of them report the same PVR family for
394 * the PowerPC core. The various versions of these processors must be
395 * differentiated by the version number in the Communication Processor
398 #define PVR_821 0x00500000
399 #define PVR_823 PVR_821
400 #define PVR_850 PVR_821
401 #define PVR_860 PVR_821
402 #define PVR_8240 0x00810100
403 #define PVR_8245 0x80811014
404 #define PVR_8260 PVR_8240
407 /* Segment Registers */
426 /* Macros for setting and retrieving special purpose registers */
428 #define mfmsr() ({unsigned int rval; \
429 asm volatile("mfmsr %0" : "=r" (rval)); rval;})
430 #define mtmsr(v) asm volatile("mtmsr %0" : : "r" (v))
432 #define mfspr(rn) ({unsigned int rval; \
433 asm volatile("mfspr %0," __stringify(rn) \
434 : "=r" (rval)); rval;})
435 #define mtspr(rn, v) asm volatile("mtspr " __stringify(rn) ",%0" : : "r" (v))
437 #define mfsrin(v) ({unsigned int rval; \
438 asm volatile("mfsrin %0,%1" : "=r" (rval) : "r" (v)); \
441 #define proc_trap() asm volatile("trap")
442 #endif /* __ASSEMBLY__ */
443 #endif /* __ASM_PPC_REGS_H__ */
444 #endif /* __KERNEL__ */
