include/asm-mips/cobalt/cobalt.h

   1 /*
   2  * Lowlevel hardware stuff for the MIPS based Cobalt microservers.
   3  *
   4  * This file is subject to the terms and conditions of the GNU General Public
   5  * License.  See the file "COPYING" in the main directory of this archive
   6  * for more details.
   7  *
   8  * Copyright (C) 1997 Cobalt Microserver
   9  * Copyright (C) 1997, 2003 Ralf Baechle
  10  * Copyright (C) 2001, 2002, 2003 Liam Davies (ldavies@agile.tv)
  11  */
  12 #ifndef __ASM_COBALT_H
  13 #define __ASM_COBALT_H
  14
  15 /*
  16  * i8259 legacy interrupts used on Cobalt:
  17  *
  18  *     8  - RTC
  19  *     9  - PCI
  20  *    14  - IDE0
  21  *    15  - IDE1
  22  *
  23  * CPU IRQs  are 16 ... 23
  24  */
  25 #define COBALT_TIMER_IRQ        18
  26 #define COBALT_SCC_IRQ          19              /* pre-production has 85C30 */
  27 #define COBALT_RAQ_SCSI_IRQ     19
  28 #define COBALT_ETH0_IRQ         19
  29 #define COBALT_ETH1_IRQ         20
  30 #define COBALT_SERIAL_IRQ       21
  31 #define COBALT_SCSI_IRQ         21
  32 #define COBALT_VIA_IRQ          22              /* Chained to VIA ISA bridge */
  33 #define COBALT_QUBE_SLOT_IRQ    23
  34
  35 /*
  36  * PCI configuration space manifest constants.  These are wired into
  37  * the board layout according to the PCI spec to enable the software
  38  * to probe the hardware configuration space in a well defined manner.
  39  *
  40  * The PCI_DEVSHFT() macro transforms these values into numbers
  41  * suitable for passing as the dev parameter to the various
  42  * pcibios_read/write_config routines.
  43  */
  44 #define COBALT_PCICONF_CPU      0x06
  45 #define COBALT_PCICONF_ETH0     0x07
  46 #define COBALT_PCICONF_RAQSCSI  0x08
  47 #define COBALT_PCICONF_VIA      0x09
  48 #define COBALT_PCICONF_PCISLOT  0x0A
  49 #define COBALT_PCICONF_ETH1     0x0C
  50
  51
  52 /*
  53  * The Cobalt board id information.  The boards have an ID number wired
  54  * into the VIA that is available in the high nibble of register 94.
  55  * This register is available in the VIA configuration space through the
  56  * interface routines qube_pcibios_read/write_config. See cobalt/pci.c
  57  */
  58 #define VIA_COBALT_BRD_ID_REG  0x94
  59 #define VIA_COBALT_BRD_REG_to_ID(reg)  ((unsigned char) (reg) >> 4)
  60 #define COBALT_BRD_ID_QUBE1    0x3
  61 #define COBALT_BRD_ID_RAQ1     0x4
  62 #define COBALT_BRD_ID_QUBE2    0x5
  63 #define COBALT_BRD_ID_RAQ2     0x6
  64
  65 /*
  66  * Galileo chipset access macros for the Cobalt. The base address for
  67  * the GT64111 chip is 0x14000000
  68  *
  69  * Most of this really should go into a separate GT64111 header file.
  70  */
  71 #define GT64111_IO_BASE         0x10000000UL
  72 #define GT64111_BASE            0x14000000UL
  73 #define GALILEO_REG(ofs)        (KSEG0 + GT64111_BASE + (unsigned long)(ofs))
  74
  75 #define GALILEO_INL(port)       (*(volatile unsigned int *) GALILEO_REG(port))
  76 #define GALILEO_OUTL(val, port)                                         \
  77 do {                                                                    \
  78         *(volatile unsigned int *) GALILEO_REG(port) = (port);          \
  79 } while (0)
  80
  81 #define GALILEO_T0EXP           0x0100
  82 #define GALILEO_ENTC0           0x01
  83 #define GALILEO_SELTC0          0x02
  84
  85 #define PCI_CFG_SET(devfn,where)                                        \
  86         GALILEO_OUTL((0x80000000 | (PCI_SLOT (devfn) << 11) |           \
  87                 (PCI_FUNC (devfn) << 8) | (where)), GT_PCI0_CFGADDR_OFS)
  88
  89
  90 #endif /* __ASM_COBALT_H */