include/asm-i386/mach-summit/mach_apic.h

   1 #ifndef __ASM_MACH_APIC_H
   2 #define __ASM_MACH_APIC_H
   3
   4 #include <linux/config.h>
   5 #include <asm/smp.h>
   6
   7 #define esr_disable (1)
   8 #define NO_BALANCE_IRQ (0)
   9
  10 #define NO_IOAPIC_CHECK (1)     /* Don't check I/O APIC ID for xAPIC */
  11
  12 /* In clustered mode, the high nibble of APIC ID is a cluster number.
  13  * The low nibble is a 4-bit bitmap. */
  14 #define XAPIC_DEST_CPUS_SHIFT   4
  15 #define XAPIC_DEST_CPUS_MASK    ((1u << XAPIC_DEST_CPUS_SHIFT) - 1)
  16 #define XAPIC_DEST_CLUSTER_MASK (XAPIC_DEST_CPUS_MASK << XAPIC_DEST_CPUS_SHIFT)
  17
  18 #define APIC_DFR_VALUE  (APIC_DFR_CLUSTER)
  19
  20 static inline cpumask_t target_cpus(void)
  21 {
  22         /* CPU_MASK_ALL (0xff) has undefined behaviour with
  23          * dest_LowestPrio mode logical clustered apic interrupt routing
  24          * Just start on cpu 0.  IRQ balancing will spread load
  25          */
  26         return cpumask_of_cpu(0);
  27 }
  28 #define TARGET_CPUS     (target_cpus())
  29
  30 #define INT_DELIVERY_MODE (dest_LowestPrio)
  31 #define INT_DEST_MODE 1     /* logical delivery broadcast to all procs */
  32
  33 static inline unsigned long check_apicid_used(physid_mask_t bitmap, int apicid)
  34 {
  35         return 0;
  36 }
  37
  38 /* we don't use the phys_cpu_present_map to indicate apicid presence */
  39 static inline unsigned long check_apicid_present(int bit)
  40 {
  41         return 1;
  42 }
  43
  44 #define apicid_cluster(apicid) ((apicid) & XAPIC_DEST_CLUSTER_MASK)
  45
  46 extern u8 bios_cpu_apicid[];
  47 extern u8 cpu_2_logical_apicid[];
  48
  49 static inline void init_apic_ldr(void)
  50 {
  51         unsigned long val, id;
  52         int i, count;
  53         u8 lid;
  54         u8 my_id = (u8)hard_smp_processor_id();
  55         u8 my_cluster = (u8)apicid_cluster(my_id);
  56
  57         /* Create logical APIC IDs by counting CPUs already in cluster. */
  58         for (count = 0, i = NR_CPUS; --i >= 0; ) {
  59                 lid = cpu_2_logical_apicid[i];
  60                 if (lid != BAD_APICID && apicid_cluster(lid) == my_cluster)
  61                         ++count;
  62         }
  63         /* We only have a 4 wide bitmap in cluster mode.  If a deranged
  64          * BIOS puts 5 CPUs in one APIC cluster, we're hosed. */
  65         BUG_ON(count >= XAPIC_DEST_CPUS_SHIFT);
  66         id = my_cluster | (1UL << count);
  67         apic_write_around(APIC_DFR, APIC_DFR_VALUE);
  68         val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
  69         val |= SET_APIC_LOGICAL_ID(id);
  70         apic_write_around(APIC_LDR, val);
  71 }
  72
  73 static inline int multi_timer_check(int apic, int irq)
  74 {
  75         return 0;
  76 }
  77
  78 static inline int apic_id_registered(void)
  79 {
  80         return 1;
  81 }
  82
  83 static inline void clustered_apic_check(void)
  84 {
  85         printk("Enabling APIC mode:  Summit.  Using %d I/O APICs\n",
  86                                                 nr_ioapics);
  87 }
  88
  89 static inline int apicid_to_node(int logical_apicid)
  90 {
  91         return logical_apicid >> 5;          /* 2 clusterids per CEC */
  92 }
  93
  94 /* Mapping from cpu number to logical apicid */
  95 static inline int cpu_to_logical_apicid(int cpu)
  96 {
  97        if (cpu >= NR_CPUS)
  98                return BAD_APICID;
  99         return (int)cpu_2_logical_apicid[cpu];
 100 }
 101
 102 static inline int cpu_present_to_apicid(int mps_cpu)
 103 {
 104         if (mps_cpu < NR_CPUS)
 105                 return (int)bios_cpu_apicid[mps_cpu];
 106         else
 107                 return BAD_APICID;
 108 }
 109
 110 static inline physid_mask_t ioapic_phys_id_map(physid_mask_t phys_id_map)
 111 {
 112         /* For clustered we don't have a good way to do this yet - hack */
 113         return physids_promote(0x0F);
 114 }
 115
 116 static inline physid_mask_t apicid_to_cpu_present(int apicid)
 117 {
 118         return physid_mask_of_physid(0);
 119 }
 120
 121 static inline int mpc_apic_id(struct mpc_config_processor *m,
 122                         struct mpc_config_translation *translation_record)
 123 {
 124         printk("Processor #%d %ld:%ld APIC version %d\n",
 125                         m->mpc_apicid,
 126                         (m->mpc_cpufeature & CPU_FAMILY_MASK) >> 8,
 127                         (m->mpc_cpufeature & CPU_MODEL_MASK) >> 4,
 128                         m->mpc_apicver);
 129         return (m->mpc_apicid);
 130 }
 131
 132 static inline void setup_portio_remap(void)
 133 {
 134 }
 135
 136 static inline int check_phys_apicid_present(int boot_cpu_physical_apicid)
 137 {
 138         return 1;
 139 }
 140
 141 static inline void enable_apic_mode(void)
 142 {
 143 }
 144
 145 static inline unsigned int cpu_mask_to_apicid(cpumask_t cpumask)
 146 {
 147         int num_bits_set;
 148         int cpus_found = 0;
 149         int cpu;
 150         int apicid;
 151
 152         num_bits_set = cpus_weight(cpumask);
 153         /* Return id to all */
 154         if (num_bits_set == NR_CPUS)
 155                 return (int) 0xFF;
 156         /*
 157          * The cpus in the mask must all be on the apic cluster.  If are not
 158          * on the same apicid cluster return default value of TARGET_CPUS.
 159          */
 160         cpu = first_cpu(cpumask);
 161         apicid = cpu_to_logical_apicid(cpu);
 162         while (cpus_found < num_bits_set) {
 163                 if (cpu_isset(cpu, cpumask)) {
 164                         int new_apicid = cpu_to_logical_apicid(cpu);
 165                         if (apicid_cluster(apicid) !=
 166                                         apicid_cluster(new_apicid)){
 167                                 printk ("%s: Not a valid mask!\n",__FUNCTION__);
 168                                 return 0xFF;
 169                         }
 170                         apicid = apicid | new_apicid;
 171                         cpus_found++;
 172                 }
 173                 cpu++;
 174         }
 175         return apicid;
 176 }
 177
 178 /* cpuid returns the value latched in the HW at reset, not the APIC ID
 179  * register's value.  For any box whose BIOS changes APIC IDs, like
 180  * clustered APIC systems, we must use hard_smp_processor_id.
 181  *
 182  * See Intel's IA-32 SW Dev's Manual Vol2 under CPUID.
 183  */
 184 static inline u32 phys_pkg_id(u32 cpuid_apic, int index_msb)
 185 {
 186         return hard_smp_processor_id() >> index_msb;
 187 }
 188
 189 #endif /* __ASM_MACH_APIC_H */