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Linux-2.6.12-rc2
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / video / tgafb.c
blob3099630d0c3d0b0e4cd17513085c1c1500784dc3
1 /*
2 * linux/drivers/video/tgafb.c -- DEC 21030 TGA frame buffer device
3 *
4 * Copyright (C) 1995 Jay Estabrook
5 * Copyright (C) 1997 Geert Uytterhoeven
6 * Copyright (C) 1999,2000 Martin Lucina, Tom Zerucha
7 * Copyright (C) 2002 Richard Henderson
8 *
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file COPYING in the main directory of this archive for
11 * more details.
12 */
13
14 #include <linux/module.h>
15 #include <linux/kernel.h>
16 #include <linux/sched.h>
17 #include <linux/errno.h>
18 #include <linux/string.h>
19 #include <linux/mm.h>
20 #include <linux/tty.h>
21 #include <linux/slab.h>
22 #include <linux/delay.h>
23 #include <linux/init.h>
24 #include <linux/fb.h>
25 #include <linux/pci.h>
26 #include <linux/selection.h>
27 #include <asm/io.h>
28 #include <video/tgafb.h>
29 #include <linux/selection.h>
30
31 /*
32 * Local functions.
33 */
34
35 static int tgafb_check_var(struct fb_var_screeninfo *, struct fb_info *);
36 static int tgafb_set_par(struct fb_info *);
37 static void tgafb_set_pll(struct tga_par *, int);
38 static int tgafb_setcolreg(unsigned, unsigned, unsigned, unsigned,
39 unsigned, struct fb_info *);
40 static int tgafb_blank(int, struct fb_info *);
41 static void tgafb_init_fix(struct fb_info *);
42
43 static void tgafb_imageblit(struct fb_info *, const struct fb_image *);
44 static void tgafb_fillrect(struct fb_info *, const struct fb_fillrect *);
45 static void tgafb_copyarea(struct fb_info *, const struct fb_copyarea *);
46
47 static int tgafb_pci_register(struct pci_dev *, const struct pci_device_id *);
48 #ifdef MODULE
49 static void tgafb_pci_unregister(struct pci_dev *);
50 #endif
51
52 static const char *mode_option = "640x480@60";
53
54
55 /*
56 * Frame buffer operations
57 */
58
59 static struct fb_ops tgafb_ops = {
60 .owner = THIS_MODULE,
61 .fb_check_var = tgafb_check_var,
62 .fb_set_par = tgafb_set_par,
63 .fb_setcolreg = tgafb_setcolreg,
64 .fb_blank = tgafb_blank,
65 .fb_fillrect = tgafb_fillrect,
66 .fb_copyarea = tgafb_copyarea,
67 .fb_imageblit = tgafb_imageblit,
68 .fb_cursor = soft_cursor,
69 };
70
71
72 /*
73 * PCI registration operations
74 */
75
76 static struct pci_device_id const tgafb_pci_table[] = {
77 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TGA, PCI_ANY_ID, PCI_ANY_ID,
78 0, 0, 0 }
79 };
80
81 static struct pci_driver tgafb_driver = {
82 .name = "tgafb",
83 .id_table = tgafb_pci_table,
84 .probe = tgafb_pci_register,
85 .remove = __devexit_p(tgafb_pci_unregister),
86 };
87
88
89 /**
90 * tgafb_check_var - Optional function. Validates a var passed in.
91 * @var: frame buffer variable screen structure
92 * @info: frame buffer structure that represents a single frame buffer
93 */
94 static int
95 tgafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
96 {
97 struct tga_par *par = (struct tga_par *)info->par;
98
99 if (par->tga_type == TGA_TYPE_8PLANE) {
100 if (var->bits_per_pixel != 8)
101 return -EINVAL;
102 } else {
103 if (var->bits_per_pixel != 32)
104 return -EINVAL;
105 }
106
107 if (var->xres_virtual != var->xres || var->yres_virtual != var->yres)
108 return -EINVAL;
109 if (var->nonstd)
110 return -EINVAL;
111 if (1000000000 / var->pixclock > TGA_PLL_MAX_FREQ)
112 return -EINVAL;
113 if ((var->vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED)
114 return -EINVAL;
115
116 /* Some of the acceleration routines assume the line width is
117 a multiple of 64 bytes. */
118 if (var->xres * (par->tga_type == TGA_TYPE_8PLANE ? 1 : 4) % 64)
119 return -EINVAL;
120
121 return 0;
122 }
123
124 /**
125 * tgafb_set_par - Optional function. Alters the hardware state.
126 * @info: frame buffer structure that represents a single frame buffer
127 */
128 static int
129 tgafb_set_par(struct fb_info *info)
130 {
131 static unsigned int const deep_presets[4] = {
132 0x00014000,
133 0x0001440d,
134 0xffffffff,
135 0x0001441d
136 };
137 static unsigned int const rasterop_presets[4] = {
138 0x00000003,
139 0x00000303,
140 0xffffffff,
141 0x00000303
142 };
143 static unsigned int const mode_presets[4] = {
144 0x00002000,
145 0x00002300,
146 0xffffffff,
147 0x00002300
148 };
149 static unsigned int const base_addr_presets[4] = {
150 0x00000000,
151 0x00000001,
152 0xffffffff,
153 0x00000001
154 };
155
156 struct tga_par *par = (struct tga_par *) info->par;
157 u32 htimings, vtimings, pll_freq;
158 u8 tga_type;
159 int i, j;
160
161 /* Encode video timings. */
162 htimings = (((info->var.xres/4) & TGA_HORIZ_ACT_LSB)
163 | (((info->var.xres/4) & 0x600 << 19) & TGA_HORIZ_ACT_MSB));
164 vtimings = (info->var.yres & TGA_VERT_ACTIVE);
165 htimings |= ((info->var.right_margin/4) << 9) & TGA_HORIZ_FP;
166 vtimings |= (info->var.lower_margin << 11) & TGA_VERT_FP;
167 htimings |= ((info->var.hsync_len/4) << 14) & TGA_HORIZ_SYNC;
168 vtimings |= (info->var.vsync_len << 16) & TGA_VERT_SYNC;
169 htimings |= ((info->var.left_margin/4) << 21) & TGA_HORIZ_BP;
170 vtimings |= (info->var.upper_margin << 22) & TGA_VERT_BP;
171
172 if (info->var.sync & FB_SYNC_HOR_HIGH_ACT)
173 htimings |= TGA_HORIZ_POLARITY;
174 if (info->var.sync & FB_SYNC_VERT_HIGH_ACT)
175 vtimings |= TGA_VERT_POLARITY;
176
177 par->htimings = htimings;
178 par->vtimings = vtimings;
179
180 par->sync_on_green = !!(info->var.sync & FB_SYNC_ON_GREEN);
181
182 /* Store other useful values in par. */
183 par->xres = info->var.xres;
184 par->yres = info->var.yres;
185 par->pll_freq = pll_freq = 1000000000 / info->var.pixclock;
186 par->bits_per_pixel = info->var.bits_per_pixel;
187
188 tga_type = par->tga_type;
189
190 /* First, disable video. */
191 TGA_WRITE_REG(par, TGA_VALID_VIDEO | TGA_VALID_BLANK, TGA_VALID_REG);
192
193 /* Write the DEEP register. */
194 while (TGA_READ_REG(par, TGA_CMD_STAT_REG) & 1) /* wait for not busy */
195 continue;
196 mb();
197 TGA_WRITE_REG(par, deep_presets[tga_type], TGA_DEEP_REG);
198 while (TGA_READ_REG(par, TGA_CMD_STAT_REG) & 1) /* wait for not busy */
199 continue;
200 mb();
201
202 /* Write some more registers. */
203 TGA_WRITE_REG(par, rasterop_presets[tga_type], TGA_RASTEROP_REG);
204 TGA_WRITE_REG(par, mode_presets[tga_type], TGA_MODE_REG);
205 TGA_WRITE_REG(par, base_addr_presets[tga_type], TGA_BASE_ADDR_REG);
206
207 /* Calculate & write the PLL. */
208 tgafb_set_pll(par, pll_freq);
209
210 /* Write some more registers. */
211 TGA_WRITE_REG(par, 0xffffffff, TGA_PLANEMASK_REG);
212 TGA_WRITE_REG(par, 0xffffffff, TGA_PIXELMASK_REG);
213
214 /* Init video timing regs. */
215 TGA_WRITE_REG(par, htimings, TGA_HORIZ_REG);
216 TGA_WRITE_REG(par, vtimings, TGA_VERT_REG);
217
218 /* Initalise RAMDAC. */
219 if (tga_type == TGA_TYPE_8PLANE) {
220
221 /* Init BT485 RAMDAC registers. */
222 BT485_WRITE(par, 0xa2 | (par->sync_on_green ? 0x8 : 0x0),
223 BT485_CMD_0);
224 BT485_WRITE(par, 0x01, BT485_ADDR_PAL_WRITE);
225 BT485_WRITE(par, 0x14, BT485_CMD_3); /* cursor 64x64 */
226 BT485_WRITE(par, 0x40, BT485_CMD_1);
227 BT485_WRITE(par, 0x20, BT485_CMD_2); /* cursor off, for now */
228 BT485_WRITE(par, 0xff, BT485_PIXEL_MASK);
229
230 /* Fill palette registers. */
231 BT485_WRITE(par, 0x00, BT485_ADDR_PAL_WRITE);
232 TGA_WRITE_REG(par, BT485_DATA_PAL, TGA_RAMDAC_SETUP_REG);
233
234 for (i = 0; i < 16; i++) {
235 j = color_table[i];
236 TGA_WRITE_REG(par, default_red[j]|(BT485_DATA_PAL<<8),
237 TGA_RAMDAC_REG);
238 TGA_WRITE_REG(par, default_grn[j]|(BT485_DATA_PAL<<8),
239 TGA_RAMDAC_REG);
240 TGA_WRITE_REG(par, default_blu[j]|(BT485_DATA_PAL<<8),
241 TGA_RAMDAC_REG);
242 }
243 for (i = 0; i < 240*3; i += 4) {
244 TGA_WRITE_REG(par, 0x55|(BT485_DATA_PAL<<8),
245 TGA_RAMDAC_REG);
246 TGA_WRITE_REG(par, 0x00|(BT485_DATA_PAL<<8),
247 TGA_RAMDAC_REG);
248 TGA_WRITE_REG(par, 0x00|(BT485_DATA_PAL<<8),
249 TGA_RAMDAC_REG);
250 TGA_WRITE_REG(par, 0x00|(BT485_DATA_PAL<<8),
251 TGA_RAMDAC_REG);
252 }
253
254 } else { /* 24-plane or 24plusZ */
255
256 /* Init BT463 registers. */
257 BT463_WRITE(par, BT463_REG_ACC, BT463_CMD_REG_0, 0x40);
258 BT463_WRITE(par, BT463_REG_ACC, BT463_CMD_REG_1, 0x08);
259 BT463_WRITE(par, BT463_REG_ACC, BT463_CMD_REG_2,
260 (par->sync_on_green ? 0x80 : 0x40));
261
262 BT463_WRITE(par, BT463_REG_ACC, BT463_READ_MASK_0, 0xff);
263 BT463_WRITE(par, BT463_REG_ACC, BT463_READ_MASK_1, 0xff);
264 BT463_WRITE(par, BT463_REG_ACC, BT463_READ_MASK_2, 0xff);
265 BT463_WRITE(par, BT463_REG_ACC, BT463_READ_MASK_3, 0x0f);
266
267 BT463_WRITE(par, BT463_REG_ACC, BT463_BLINK_MASK_0, 0x00);
268 BT463_WRITE(par, BT463_REG_ACC, BT463_BLINK_MASK_1, 0x00);
269 BT463_WRITE(par, BT463_REG_ACC, BT463_BLINK_MASK_2, 0x00);
270 BT463_WRITE(par, BT463_REG_ACC, BT463_BLINK_MASK_3, 0x00);
271
272 /* Fill the palette. */
273 BT463_LOAD_ADDR(par, 0x0000);
274 TGA_WRITE_REG(par, BT463_PALETTE<<2, TGA_RAMDAC_REG);
275
276 for (i = 0; i < 16; i++) {
277 j = color_table[i];
278 TGA_WRITE_REG(par, default_red[j]|(BT463_PALETTE<<10),
279 TGA_RAMDAC_REG);
280 TGA_WRITE_REG(par, default_grn[j]|(BT463_PALETTE<<10),
281 TGA_RAMDAC_REG);
282 TGA_WRITE_REG(par, default_blu[j]|(BT463_PALETTE<<10),
283 TGA_RAMDAC_REG);
284 }
285 for (i = 0; i < 512*3; i += 4) {
286 TGA_WRITE_REG(par, 0x55|(BT463_PALETTE<<10),
287 TGA_RAMDAC_REG);
288 TGA_WRITE_REG(par, 0x00|(BT463_PALETTE<<10),
289 TGA_RAMDAC_REG);
290 TGA_WRITE_REG(par, 0x00|(BT463_PALETTE<<10),
291 TGA_RAMDAC_REG);
292 TGA_WRITE_REG(par, 0x00|(BT463_PALETTE<<10),
293 TGA_RAMDAC_REG);
294 }
295
296 /* Fill window type table after start of vertical retrace. */
297 while (!(TGA_READ_REG(par, TGA_INTR_STAT_REG) & 0x01))
298 continue;
299 TGA_WRITE_REG(par, 0x01, TGA_INTR_STAT_REG);
300 mb();
301 while (!(TGA_READ_REG(par, TGA_INTR_STAT_REG) & 0x01))
302 continue;
303 TGA_WRITE_REG(par, 0x01, TGA_INTR_STAT_REG);
304
305 BT463_LOAD_ADDR(par, BT463_WINDOW_TYPE_BASE);
306 TGA_WRITE_REG(par, BT463_REG_ACC<<2, TGA_RAMDAC_SETUP_REG);
307
308 for (i = 0; i < 16; i++) {
309 TGA_WRITE_REG(par, 0x00|(BT463_REG_ACC<<10),
310 TGA_RAMDAC_REG);
311 TGA_WRITE_REG(par, 0x01|(BT463_REG_ACC<<10),
312 TGA_RAMDAC_REG);
313 TGA_WRITE_REG(par, 0x80|(BT463_REG_ACC<<10),
314 TGA_RAMDAC_REG);
315 }
316
317 }
318
319 /* Finally, enable video scan (and pray for the monitor... :-) */
320 TGA_WRITE_REG(par, TGA_VALID_VIDEO, TGA_VALID_REG);
321
322 return 0;
323 }
324
325 #define DIFFCHECK(X) \
326 do { \
327 if (m <= 0x3f) { \
328 int delta = f - (TGA_PLL_BASE_FREQ * (X)) / (r << shift); \
329 if (delta < 0) \
330 delta = -delta; \
331 if (delta < min_diff) \
332 min_diff = delta, vm = m, va = a, vr = r; \
333 } \
334 } while (0)
335
336 static void
337 tgafb_set_pll(struct tga_par *par, int f)
338 {
339 int n, shift, base, min_diff, target;
340 int r,a,m,vm = 34, va = 1, vr = 30;
341
342 for (r = 0 ; r < 12 ; r++)
343 TGA_WRITE_REG(par, !r, TGA_CLOCK_REG);
344
345 if (f > TGA_PLL_MAX_FREQ)
346 f = TGA_PLL_MAX_FREQ;
347
348 if (f >= TGA_PLL_MAX_FREQ / 2)
349 shift = 0;
350 else if (f >= TGA_PLL_MAX_FREQ / 4)
351 shift = 1;
352 else
353 shift = 2;
354
355 TGA_WRITE_REG(par, shift & 1, TGA_CLOCK_REG);
356 TGA_WRITE_REG(par, shift >> 1, TGA_CLOCK_REG);
357
358 for (r = 0 ; r < 10 ; r++)
359 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
360
361 if (f <= 120000) {
362 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
363 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
364 }
365 else if (f <= 200000) {
366 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
367 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
368 }
369 else {
370 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
371 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
372 }
373
374 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
375 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
376 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
377 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
378 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
379 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
380
381 target = (f << shift) / TGA_PLL_BASE_FREQ;
382 min_diff = TGA_PLL_MAX_FREQ;
383
384 r = 7 / target;
385 if (!r) r = 1;
386
387 base = target * r;
388 while (base < 449) {
389 for (n = base < 7 ? 7 : base; n < base + target && n < 449; n++) {
390 m = ((n + 3) / 7) - 1;
391 a = 0;
392 DIFFCHECK((m + 1) * 7);
393 m++;
394 DIFFCHECK((m + 1) * 7);
395 m = (n / 6) - 1;
396 if ((a = n % 6))
397 DIFFCHECK(n);
398 }
399 r++;
400 base += target;
401 }
402
403 vr--;
404
405 for (r = 0; r < 8; r++)
406 TGA_WRITE_REG(par, (vm >> r) & 1, TGA_CLOCK_REG);
407 for (r = 0; r < 8 ; r++)
408 TGA_WRITE_REG(par, (va >> r) & 1, TGA_CLOCK_REG);
409 for (r = 0; r < 7 ; r++)
410 TGA_WRITE_REG(par, (vr >> r) & 1, TGA_CLOCK_REG);
411 TGA_WRITE_REG(par, ((vr >> 7) & 1)|2, TGA_CLOCK_REG);
412 }
413
414
415 /**
416 * tgafb_setcolreg - Optional function. Sets a color register.
417 * @regno: boolean, 0 copy local, 1 get_user() function
418 * @red: frame buffer colormap structure
419 * @green: The green value which can be up to 16 bits wide
420 * @blue: The blue value which can be up to 16 bits wide.
421 * @transp: If supported the alpha value which can be up to 16 bits wide.
422 * @info: frame buffer info structure
423 */
424 static int
425 tgafb_setcolreg(unsigned regno, unsigned red, unsigned green, unsigned blue,
426 unsigned transp, struct fb_info *info)
427 {
428 struct tga_par *par = (struct tga_par *) info->par;
429
430 if (regno > 255)
431 return 1;
432 red >>= 8;
433 green >>= 8;
434 blue >>= 8;
435
436 if (par->tga_type == TGA_TYPE_8PLANE) {
437 BT485_WRITE(par, regno, BT485_ADDR_PAL_WRITE);
438 TGA_WRITE_REG(par, BT485_DATA_PAL, TGA_RAMDAC_SETUP_REG);
439 TGA_WRITE_REG(par, red|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG);
440 TGA_WRITE_REG(par, green|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG);
441 TGA_WRITE_REG(par, blue|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG);
442 } else if (regno < 16) {
443 u32 value = (red << 16) | (green << 8) | blue;
444 ((u32 *)info->pseudo_palette)[regno] = value;
445 }
446
447 return 0;
448 }
449
450
451 /**
452 * tgafb_blank - Optional function. Blanks the display.
453 * @blank_mode: the blank mode we want.
454 * @info: frame buffer structure that represents a single frame buffer
455 */
456 static int
457 tgafb_blank(int blank, struct fb_info *info)
458 {
459 struct tga_par *par = (struct tga_par *) info->par;
460 u32 vhcr, vvcr, vvvr;
461 unsigned long flags;
462
463 local_irq_save(flags);
464
465 vhcr = TGA_READ_REG(par, TGA_HORIZ_REG);
466 vvcr = TGA_READ_REG(par, TGA_VERT_REG);
467 vvvr = TGA_READ_REG(par, TGA_VALID_REG);
468 vvvr &= ~(TGA_VALID_VIDEO | TGA_VALID_BLANK);
469
470 switch (blank) {
471 case FB_BLANK_UNBLANK: /* Unblanking */
472 if (par->vesa_blanked) {
473 TGA_WRITE_REG(par, vhcr & 0xbfffffff, TGA_HORIZ_REG);
474 TGA_WRITE_REG(par, vvcr & 0xbfffffff, TGA_VERT_REG);
475 par->vesa_blanked = 0;
476 }
477 TGA_WRITE_REG(par, vvvr | TGA_VALID_VIDEO, TGA_VALID_REG);
478 break;
479
480 case FB_BLANK_NORMAL: /* Normal blanking */
481 TGA_WRITE_REG(par, vvvr | TGA_VALID_VIDEO | TGA_VALID_BLANK,
482 TGA_VALID_REG);
483 break;
484
485 case FB_BLANK_VSYNC_SUSPEND: /* VESA blank (vsync off) */
486 TGA_WRITE_REG(par, vvcr | 0x40000000, TGA_VERT_REG);
487 TGA_WRITE_REG(par, vvvr | TGA_VALID_BLANK, TGA_VALID_REG);
488 par->vesa_blanked = 1;
489 break;
490
491 case FB_BLANK_HSYNC_SUSPEND: /* VESA blank (hsync off) */
492 TGA_WRITE_REG(par, vhcr | 0x40000000, TGA_HORIZ_REG);
493 TGA_WRITE_REG(par, vvvr | TGA_VALID_BLANK, TGA_VALID_REG);
494 par->vesa_blanked = 1;
495 break;
496
497 case FB_BLANK_POWERDOWN: /* Poweroff */
498 TGA_WRITE_REG(par, vhcr | 0x40000000, TGA_HORIZ_REG);
499 TGA_WRITE_REG(par, vvcr | 0x40000000, TGA_VERT_REG);
500 TGA_WRITE_REG(par, vvvr | TGA_VALID_BLANK, TGA_VALID_REG);
501 par->vesa_blanked = 1;
502 break;
503 }
504
505 local_irq_restore(flags);
506 return 0;
507 }
508
509
510 /*
511 * Acceleration.
512 */
513
514 /**
515 * tgafb_imageblit - REQUIRED function. Can use generic routines if
516 * non acclerated hardware and packed pixel based.
517 * Copies a image from system memory to the screen.
518 *
519 * @info: frame buffer structure that represents a single frame buffer
520 * @image: structure defining the image.
521 */
522 static void
523 tgafb_imageblit(struct fb_info *info, const struct fb_image *image)
524 {
525 static unsigned char const bitrev[256] = {
526 0x00, 0x80, 0x40, 0xc0, 0x20, 0xa0, 0x60, 0xe0,
527 0x10, 0x90, 0x50, 0xd0, 0x30, 0xb0, 0x70, 0xf0,
528 0x08, 0x88, 0x48, 0xc8, 0x28, 0xa8, 0x68, 0xe8,
529 0x18, 0x98, 0x58, 0xd8, 0x38, 0xb8, 0x78, 0xf8,
530 0x04, 0x84, 0x44, 0xc4, 0x24, 0xa4, 0x64, 0xe4,
531 0x14, 0x94, 0x54, 0xd4, 0x34, 0xb4, 0x74, 0xf4,
532 0x0c, 0x8c, 0x4c, 0xcc, 0x2c, 0xac, 0x6c, 0xec,
533 0x1c, 0x9c, 0x5c, 0xdc, 0x3c, 0xbc, 0x7c, 0xfc,
534 0x02, 0x82, 0x42, 0xc2, 0x22, 0xa2, 0x62, 0xe2,
535 0x12, 0x92, 0x52, 0xd2, 0x32, 0xb2, 0x72, 0xf2,
536 0x0a, 0x8a, 0x4a, 0xca, 0x2a, 0xaa, 0x6a, 0xea,
537 0x1a, 0x9a, 0x5a, 0xda, 0x3a, 0xba, 0x7a, 0xfa,
538 0x06, 0x86, 0x46, 0xc6, 0x26, 0xa6, 0x66, 0xe6,
539 0x16, 0x96, 0x56, 0xd6, 0x36, 0xb6, 0x76, 0xf6,
540 0x0e, 0x8e, 0x4e, 0xce, 0x2e, 0xae, 0x6e, 0xee,
541 0x1e, 0x9e, 0x5e, 0xde, 0x3e, 0xbe, 0x7e, 0xfe,
542 0x01, 0x81, 0x41, 0xc1, 0x21, 0xa1, 0x61, 0xe1,
543 0x11, 0x91, 0x51, 0xd1, 0x31, 0xb1, 0x71, 0xf1,
544 0x09, 0x89, 0x49, 0xc9, 0x29, 0xa9, 0x69, 0xe9,
545 0x19, 0x99, 0x59, 0xd9, 0x39, 0xb9, 0x79, 0xf9,
546 0x05, 0x85, 0x45, 0xc5, 0x25, 0xa5, 0x65, 0xe5,
547 0x15, 0x95, 0x55, 0xd5, 0x35, 0xb5, 0x75, 0xf5,
548 0x0d, 0x8d, 0x4d, 0xcd, 0x2d, 0xad, 0x6d, 0xed,
549 0x1d, 0x9d, 0x5d, 0xdd, 0x3d, 0xbd, 0x7d, 0xfd,
550 0x03, 0x83, 0x43, 0xc3, 0x23, 0xa3, 0x63, 0xe3,
551 0x13, 0x93, 0x53, 0xd3, 0x33, 0xb3, 0x73, 0xf3,
552 0x0b, 0x8b, 0x4b, 0xcb, 0x2b, 0xab, 0x6b, 0xeb,
553 0x1b, 0x9b, 0x5b, 0xdb, 0x3b, 0xbb, 0x7b, 0xfb,
554 0x07, 0x87, 0x47, 0xc7, 0x27, 0xa7, 0x67, 0xe7,
555 0x17, 0x97, 0x57, 0xd7, 0x37, 0xb7, 0x77, 0xf7,
556 0x0f, 0x8f, 0x4f, 0xcf, 0x2f, 0xaf, 0x6f, 0xef,
557 0x1f, 0x9f, 0x5f, 0xdf, 0x3f, 0xbf, 0x7f, 0xff
558 };
559
560 struct tga_par *par = (struct tga_par *) info->par;
561 u32 fgcolor, bgcolor, dx, dy, width, height, vxres, vyres, pixelmask;
562 unsigned long rincr, line_length, shift, pos, is8bpp;
563 unsigned long i, j;
564 const unsigned char *data;
565 void __iomem *regs_base;
566 void __iomem *fb_base;
567
568 dx = image->dx;
569 dy = image->dy;
570 width = image->width;
571 height = image->height;
572 vxres = info->var.xres_virtual;
573 vyres = info->var.yres_virtual;
574 line_length = info->fix.line_length;
575 rincr = (width + 7) / 8;
576
577 /* Crop the image to the screen. */
578 if (dx > vxres || dy > vyres)
579 return;
580 if (dx + width > vxres)
581 width = vxres - dx;
582 if (dy + height > vyres)
583 height = vyres - dy;
584
585 /* For copies that aren't pixel expansion, there's little we
586 can do better than the generic code. */
587 /* ??? There is a DMA write mode; I wonder if that could be
588 made to pull the data from the image buffer... */
589 if (image->depth > 1) {
590 cfb_imageblit(info, image);
591 return;
592 }
593
594 regs_base = par->tga_regs_base;
595 fb_base = par->tga_fb_base;
596 is8bpp = info->var.bits_per_pixel == 8;
597
598 /* Expand the color values to fill 32-bits. */
599 /* ??? Would be nice to notice colour changes elsewhere, so
600 that we can do this only when necessary. */
601 fgcolor = image->fg_color;
602 bgcolor = image->bg_color;
603 if (is8bpp) {
604 fgcolor |= fgcolor << 8;
605 fgcolor |= fgcolor << 16;
606 bgcolor |= bgcolor << 8;
607 bgcolor |= bgcolor << 16;
608 } else {
609 if (fgcolor < 16)
610 fgcolor = ((u32 *)info->pseudo_palette)[fgcolor];
611 if (bgcolor < 16)
612 bgcolor = ((u32 *)info->pseudo_palette)[bgcolor];
613 }
614 __raw_writel(fgcolor, regs_base + TGA_FOREGROUND_REG);
615 __raw_writel(bgcolor, regs_base + TGA_BACKGROUND_REG);
616
617 /* Acquire proper alignment; set up the PIXELMASK register
618 so that we only write the proper character cell. */
619 pos = dy * line_length;
620 if (is8bpp) {
621 pos += dx;
622 shift = pos & 3;
623 pos &= -4;
624 } else {
625 pos += dx * 4;
626 shift = (pos & 7) >> 2;
627 pos &= -8;
628 }
629
630 data = (const unsigned char *) image->data;
631
632 /* Enable opaque stipple mode. */
633 __raw_writel((is8bpp
634 ? TGA_MODE_SBM_8BPP | TGA_MODE_OPAQUE_STIPPLE
635 : TGA_MODE_SBM_24BPP | TGA_MODE_OPAQUE_STIPPLE),
636 regs_base + TGA_MODE_REG);
637
638 if (width + shift <= 32) {
639 unsigned long bwidth;
640
641 /* Handle common case of imaging a single character, in
642 a font less than 32 pixels wide. */
643
644 pixelmask = (1 << width) - 1;
645 pixelmask <<= shift;
646 __raw_writel(pixelmask, regs_base + TGA_PIXELMASK_REG);
647 wmb();
648
649 bwidth = (width + 7) / 8;
650
651 for (i = 0; i < height; ++i) {
652 u32 mask = 0;
653
654 /* The image data is bit big endian; we need
655 little endian. */
656 for (j = 0; j < bwidth; ++j)
657 mask |= bitrev[data[j]] << (j * 8);
658
659 __raw_writel(mask << shift, fb_base + pos);
660
661 pos += line_length;
662 data += rincr;
663 }
664 wmb();
665 __raw_writel(0xffffffff, regs_base + TGA_PIXELMASK_REG);
666 } else if (shift == 0) {
667 unsigned long pos0 = pos;
668 const unsigned char *data0 = data;
669 unsigned long bincr = (is8bpp ? 8 : 8*4);
670 unsigned long bwidth;
671
672 /* Handle another common case in which accel_putcs
673 generates a large bitmap, which happens to be aligned.
674 Allow the tail to be misaligned. This case is
675 interesting because we've not got to hold partial
676 bytes across the words being written. */
677
678 wmb();
679
680 bwidth = (width / 8) & -4;
681 for (i = 0; i < height; ++i) {
682 for (j = 0; j < bwidth; j += 4) {
683 u32 mask = 0;
684 mask |= bitrev[data[j+0]] << (0 * 8);
685 mask |= bitrev[data[j+1]] << (1 * 8);
686 mask |= bitrev[data[j+2]] << (2 * 8);
687 mask |= bitrev[data[j+3]] << (3 * 8);
688 __raw_writel(mask, fb_base + pos + j*bincr);
689 }
690 pos += line_length;
691 data += rincr;
692 }
693 wmb();
694
695 pixelmask = (1ul << (width & 31)) - 1;
696 if (pixelmask) {
697 __raw_writel(pixelmask, regs_base + TGA_PIXELMASK_REG);
698 wmb();
699
700 pos = pos0 + bwidth*bincr;
701 data = data0 + bwidth;
702 bwidth = ((width & 31) + 7) / 8;
703
704 for (i = 0; i < height; ++i) {
705 u32 mask = 0;
706 for (j = 0; j < bwidth; ++j)
707 mask |= bitrev[data[j]] << (j * 8);
708 __raw_writel(mask, fb_base + pos);
709 pos += line_length;
710 data += rincr;
711 }
712 wmb();
713 __raw_writel(0xffffffff, regs_base + TGA_PIXELMASK_REG);
714 }
715 } else {
716 unsigned long pos0 = pos;
717 const unsigned char *data0 = data;
718 unsigned long bincr = (is8bpp ? 8 : 8*4);
719 unsigned long bwidth;
720
721 /* Finally, handle the generic case of misaligned start.
722 Here we split the write into 16-bit spans. This allows
723 us to use only one pixel mask, instead of four as would
724 be required by writing 24-bit spans. */
725
726 pixelmask = 0xffff << shift;
727 __raw_writel(pixelmask, regs_base + TGA_PIXELMASK_REG);
728 wmb();
729
730 bwidth = (width / 8) & -2;
731 for (i = 0; i < height; ++i) {
732 for (j = 0; j < bwidth; j += 2) {
733 u32 mask = 0;
734 mask |= bitrev[data[j+0]] << (0 * 8);
735 mask |= bitrev[data[j+1]] << (1 * 8);
736 mask <<= shift;
737 __raw_writel(mask, fb_base + pos + j*bincr);
738 }
739 pos += line_length;
740 data += rincr;
741 }
742 wmb();
743
744 pixelmask = ((1ul << (width & 15)) - 1) << shift;
745 if (pixelmask) {
746 __raw_writel(pixelmask, regs_base + TGA_PIXELMASK_REG);
747 wmb();
748
749 pos = pos0 + bwidth*bincr;
750 data = data0 + bwidth;
751 bwidth = (width & 15) > 8;
752
753 for (i = 0; i < height; ++i) {
754 u32 mask = bitrev[data[0]];
755 if (bwidth)
756 mask |= bitrev[data[1]] << 8;
757 mask <<= shift;
758 __raw_writel(mask, fb_base + pos);
759 pos += line_length;
760 data += rincr;
761 }
762 wmb();
763 }
764 __raw_writel(0xffffffff, regs_base + TGA_PIXELMASK_REG);
765 }
766
767 /* Disable opaque stipple mode. */
768 __raw_writel((is8bpp
769 ? TGA_MODE_SBM_8BPP | TGA_MODE_SIMPLE
770 : TGA_MODE_SBM_24BPP | TGA_MODE_SIMPLE),
771 regs_base + TGA_MODE_REG);
772 }
773
774 /**
775 * tgafb_fillrect - REQUIRED function. Can use generic routines if
776 * non acclerated hardware and packed pixel based.
777 * Draws a rectangle on the screen.
778 *
779 * @info: frame buffer structure that represents a single frame buffer
780 * @rect: structure defining the rectagle and operation.
781 */
782 static void
783 tgafb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
784 {
785 struct tga_par *par = (struct tga_par *) info->par;
786 int is8bpp = info->var.bits_per_pixel == 8;
787 u32 dx, dy, width, height, vxres, vyres, color;
788 unsigned long pos, align, line_length, i, j;
789 void __iomem *regs_base;
790 void __iomem *fb_base;
791
792 dx = rect->dx;
793 dy = rect->dy;
794 width = rect->width;
795 height = rect->height;
796 vxres = info->var.xres_virtual;
797 vyres = info->var.yres_virtual;
798 line_length = info->fix.line_length;
799 regs_base = par->tga_regs_base;
800 fb_base = par->tga_fb_base;
801
802 /* Crop the rectangle to the screen. */
803 if (dx > vxres || dy > vyres || !width || !height)
804 return;
805 if (dx + width > vxres)
806 width = vxres - dx;
807 if (dy + height > vyres)
808 height = vyres - dy;
809
810 pos = dy * line_length + dx * (is8bpp ? 1 : 4);
811
812 /* ??? We could implement ROP_XOR with opaque fill mode
813 and a RasterOp setting of GXxor, but as far as I can
814 tell, this mode is not actually used in the kernel.
815 Thus I am ignoring it for now. */
816 if (rect->rop != ROP_COPY) {
817 cfb_fillrect(info, rect);
818 return;
819 }
820
821 /* Expand the color value to fill 8 pixels. */
822 color = rect->color;
823 if (is8bpp) {
824 color |= color << 8;
825 color |= color << 16;
826 __raw_writel(color, regs_base + TGA_BLOCK_COLOR0_REG);
827 __raw_writel(color, regs_base + TGA_BLOCK_COLOR1_REG);
828 } else {
829 if (color < 16)
830 color = ((u32 *)info->pseudo_palette)[color];
831 __raw_writel(color, regs_base + TGA_BLOCK_COLOR0_REG);
832 __raw_writel(color, regs_base + TGA_BLOCK_COLOR1_REG);
833 __raw_writel(color, regs_base + TGA_BLOCK_COLOR2_REG);
834 __raw_writel(color, regs_base + TGA_BLOCK_COLOR3_REG);
835 __raw_writel(color, regs_base + TGA_BLOCK_COLOR4_REG);
836 __raw_writel(color, regs_base + TGA_BLOCK_COLOR5_REG);
837 __raw_writel(color, regs_base + TGA_BLOCK_COLOR6_REG);
838 __raw_writel(color, regs_base + TGA_BLOCK_COLOR7_REG);
839 }
840
841 /* The DATA register holds the fill mask for block fill mode.
842 Since we're not stippling, this is all ones. */
843 __raw_writel(0xffffffff, regs_base + TGA_DATA_REG);
844
845 /* Enable block fill mode. */
846 __raw_writel((is8bpp
847 ? TGA_MODE_SBM_8BPP | TGA_MODE_BLOCK_FILL
848 : TGA_MODE_SBM_24BPP | TGA_MODE_BLOCK_FILL),
849 regs_base + TGA_MODE_REG);
850 wmb();
851
852 /* We can fill 2k pixels per operation. Notice blocks that fit
853 the width of the screen so that we can take advantage of this
854 and fill more than one line per write. */
855 if (width == line_length)
856 width *= height, height = 1;
857
858 /* The write into the frame buffer must be aligned to 4 bytes,
859 but we are allowed to encode the offset within the word in
860 the data word written. */
861 align = (pos & 3) << 16;
862 pos &= -4;
863
864 if (width <= 2048) {
865 u32 data;
866
867 data = (width - 1) | align;
868
869 for (i = 0; i < height; ++i) {
870 __raw_writel(data, fb_base + pos);
871 pos += line_length;
872 }
873 } else {
874 unsigned long Bpp = (is8bpp ? 1 : 4);
875 unsigned long nwidth = width & -2048;
876 u32 fdata, ldata;
877
878 fdata = (2048 - 1) | align;
879 ldata = ((width & 2047) - 1) | align;
880
881 for (i = 0; i < height; ++i) {
882 for (j = 0; j < nwidth; j += 2048)
883 __raw_writel(fdata, fb_base + pos + j*Bpp);
884 if (j < width)
885 __raw_writel(ldata, fb_base + pos + j*Bpp);
886 pos += line_length;
887 }
888 }
889 wmb();
890
891 /* Disable block fill mode. */
892 __raw_writel((is8bpp
893 ? TGA_MODE_SBM_8BPP | TGA_MODE_SIMPLE
894 : TGA_MODE_SBM_24BPP | TGA_MODE_SIMPLE),
895 regs_base + TGA_MODE_REG);
896 }
897
898 /**
899 * tgafb_copyarea - REQUIRED function. Can use generic routines if
900 * non acclerated hardware and packed pixel based.
901 * Copies on area of the screen to another area.
902 *
903 * @info: frame buffer structure that represents a single frame buffer
904 * @area: structure defining the source and destination.
905 */
906
907 /* Handle the special case of copying entire lines, e.g. during scrolling.
908 We can avoid a lot of needless computation in this case. In the 8bpp
909 case we need to use the COPY64 registers instead of mask writes into
910 the frame buffer to achieve maximum performance. */
911
912 static inline void
913 copyarea_line_8bpp(struct fb_info *info, u32 dy, u32 sy,
914 u32 height, u32 width)
915 {
916 struct tga_par *par = (struct tga_par *) info->par;
917 void __iomem *tga_regs = par->tga_regs_base;
918 unsigned long dpos, spos, i, n64;
919
920 /* Set up the MODE and PIXELSHIFT registers. */
921 __raw_writel(TGA_MODE_SBM_8BPP | TGA_MODE_COPY, tga_regs+TGA_MODE_REG);
922 __raw_writel(0, tga_regs+TGA_PIXELSHIFT_REG);
923 wmb();
924
925 n64 = (height * width) / 64;
926
927 if (dy < sy) {
928 spos = (sy + height) * width;
929 dpos = (dy + height) * width;
930
931 for (i = 0; i < n64; ++i) {
932 spos -= 64;
933 dpos -= 64;
934 __raw_writel(spos, tga_regs+TGA_COPY64_SRC);
935 wmb();
936 __raw_writel(dpos, tga_regs+TGA_COPY64_DST);
937 wmb();
938 }
939 } else {
940 spos = sy * width;
941 dpos = dy * width;
942
943 for (i = 0; i < n64; ++i) {
944 __raw_writel(spos, tga_regs+TGA_COPY64_SRC);
945 wmb();
946 __raw_writel(dpos, tga_regs+TGA_COPY64_DST);
947 wmb();
948 spos += 64;
949 dpos += 64;
950 }
951 }
952
953 /* Reset the MODE register to normal. */
954 __raw_writel(TGA_MODE_SBM_8BPP|TGA_MODE_SIMPLE, tga_regs+TGA_MODE_REG);
955 }
956
957 static inline void
958 copyarea_line_32bpp(struct fb_info *info, u32 dy, u32 sy,
959 u32 height, u32 width)
960 {
961 struct tga_par *par = (struct tga_par *) info->par;
962 void __iomem *tga_regs = par->tga_regs_base;
963 void __iomem *tga_fb = par->tga_fb_base;
964 void __iomem *src;
965 void __iomem *dst;
966 unsigned long i, n16;
967
968 /* Set up the MODE and PIXELSHIFT registers. */
969 __raw_writel(TGA_MODE_SBM_24BPP | TGA_MODE_COPY, tga_regs+TGA_MODE_REG);
970 __raw_writel(0, tga_regs+TGA_PIXELSHIFT_REG);
971 wmb();
972
973 n16 = (height * width) / 16;
974
975 if (dy < sy) {
976 src = tga_fb + (sy + height) * width * 4;
977 dst = tga_fb + (dy + height) * width * 4;
978
979 for (i = 0; i < n16; ++i) {
980 src -= 64;
981 dst -= 64;
982 __raw_writel(0xffff, src);
983 wmb();
984 __raw_writel(0xffff, dst);
985 wmb();
986 }
987 } else {
988 src = tga_fb + sy * width * 4;
989 dst = tga_fb + dy * width * 4;
990
991 for (i = 0; i < n16; ++i) {
992 __raw_writel(0xffff, src);
993 wmb();
994 __raw_writel(0xffff, dst);
995 wmb();
996 src += 64;
997 dst += 64;
998 }
999 }
1000
1001 /* Reset the MODE register to normal. */
1002 __raw_writel(TGA_MODE_SBM_24BPP|TGA_MODE_SIMPLE, tga_regs+TGA_MODE_REG);
1003 }
1004
1005 /* The general case of forward copy in 8bpp mode. */
1006 static inline void
1007 copyarea_foreward_8bpp(struct fb_info *info, u32 dx, u32 dy, u32 sx, u32 sy,
1008 u32 height, u32 width, u32 line_length)
1009 {
1010 struct tga_par *par = (struct tga_par *) info->par;
1011 unsigned long i, copied, left;
1012 unsigned long dpos, spos, dalign, salign, yincr;
1013 u32 smask_first, dmask_first, dmask_last;
1014 int pixel_shift, need_prime, need_second;
1015 unsigned long n64, n32, xincr_first;
1016 void __iomem *tga_regs;
1017 void __iomem *tga_fb;
1018
1019 yincr = line_length;
1020 if (dy > sy) {
1021 dy += height - 1;
1022 sy += height - 1;
1023 yincr = -yincr;
1024 }
1025
1026 /* Compute the offsets and alignments in the frame buffer.
1027 More than anything else, these control how we do copies. */
1028 dpos = dy * line_length + dx;
1029 spos = sy * line_length + sx;
1030 dalign = dpos & 7;
1031 salign = spos & 7;
1032 dpos &= -8;
1033 spos &= -8;
1034
1035 /* Compute the value for the PIXELSHIFT register. This controls
1036 both non-co-aligned source and destination and copy direction. */
1037 if (dalign >= salign)
1038 pixel_shift = dalign - salign;
1039 else
1040 pixel_shift = 8 - (salign - dalign);
1041
1042 /* Figure out if we need an additional priming step for the
1043 residue register. */
1044 need_prime = (salign > dalign);
1045 if (need_prime)
1046 dpos -= 8;
1047
1048 /* Begin by copying the leading unaligned destination. Copy enough
1049 to make the next destination address 32-byte aligned. */
1050 copied = 32 - (dalign + (dpos & 31));
1051 if (copied == 32)
1052 copied = 0;
1053 xincr_first = (copied + 7) & -8;
1054 smask_first = dmask_first = (1ul << copied) - 1;
1055 smask_first <<= salign;
1056 dmask_first <<= dalign + need_prime*8;
1057 if (need_prime && copied > 24)
1058 copied -= 8;
1059 left = width - copied;
1060
1061 /* Care for small copies. */
1062 if (copied > width) {
1063 u32 t;
1064 t = (1ul << width) - 1;
1065 t <<= dalign + need_prime*8;
1066 dmask_first &= t;
1067 left = 0;
1068 }
1069
1070 /* Attempt to use 64-byte copies. This is only possible if the
1071 source and destination are co-aligned at 64 bytes. */
1072 n64 = need_second = 0;
1073 if ((dpos & 63) == (spos & 63)
1074 && (height == 1 || line_length % 64 == 0)) {
1075 /* We may need a 32-byte copy to ensure 64 byte alignment. */
1076 need_second = (dpos + xincr_first) & 63;
1077 if ((need_second & 32) != need_second)
1078 printk(KERN_ERR "tgafb: need_second wrong\n");
1079 if (left >= need_second + 64) {
1080 left -= need_second;
1081 n64 = left / 64;
1082 left %= 64;
1083 } else
1084 need_second = 0;
1085 }
1086
1087 /* Copy trailing full 32-byte sections. This will be the main
1088 loop if the 64 byte loop can't be used. */
1089 n32 = left / 32;
1090 left %= 32;
1091
1092 /* Copy the trailing unaligned destination. */
1093 dmask_last = (1ul << left) - 1;
1094
1095 tga_regs = par->tga_regs_base;
1096 tga_fb = par->tga_fb_base;
1097
1098 /* Set up the MODE and PIXELSHIFT registers. */
1099 __raw_writel(TGA_MODE_SBM_8BPP|TGA_MODE_COPY, tga_regs+TGA_MODE_REG);
1100 __raw_writel(pixel_shift, tga_regs+TGA_PIXELSHIFT_REG);
1101 wmb();
1102
1103 for (i = 0; i < height; ++i) {
1104 unsigned long j;
1105 void __iomem *sfb;
1106 void __iomem *dfb;
1107
1108 sfb = tga_fb + spos;
1109 dfb = tga_fb + dpos;
1110 if (dmask_first) {
1111 __raw_writel(smask_first, sfb);
1112 wmb();
1113 __raw_writel(dmask_first, dfb);
1114 wmb();
1115 sfb += xincr_first;
1116 dfb += xincr_first;
1117 }
1118
1119 if (need_second) {
1120 __raw_writel(0xffffffff, sfb);
1121 wmb();
1122 __raw_writel(0xffffffff, dfb);
1123 wmb();
1124 sfb += 32;
1125 dfb += 32;
1126 }
1127
1128 if (n64 && (((unsigned long)sfb | (unsigned long)dfb) & 63))
1129 printk(KERN_ERR
1130 "tgafb: misaligned copy64 (s:%p, d:%p)\n",
1131 sfb, dfb);
1132
1133 for (j = 0; j < n64; ++j) {
1134 __raw_writel(sfb - tga_fb, tga_regs+TGA_COPY64_SRC);
1135 wmb();
1136 __raw_writel(dfb - tga_fb, tga_regs+TGA_COPY64_DST);
1137 wmb();
1138 sfb += 64;
1139 dfb += 64;
1140 }
1141
1142 for (j = 0; j < n32; ++j) {
1143 __raw_writel(0xffffffff, sfb);
1144 wmb();
1145 __raw_writel(0xffffffff, dfb);
1146 wmb();
1147 sfb += 32;
1148 dfb += 32;
1149 }
1150
1151 if (dmask_last) {
1152 __raw_writel(0xffffffff, sfb);
1153 wmb();
1154 __raw_writel(dmask_last, dfb);
1155 wmb();
1156 }
1157
1158 spos += yincr;
1159 dpos += yincr;
1160 }
1161
1162 /* Reset the MODE register to normal. */
1163 __raw_writel(TGA_MODE_SBM_8BPP|TGA_MODE_SIMPLE, tga_regs+TGA_MODE_REG);
1164 }
1165
1166 /* The (almost) general case of backward copy in 8bpp mode. */
1167 static inline void
1168 copyarea_backward_8bpp(struct fb_info *info, u32 dx, u32 dy, u32 sx, u32 sy,
1169 u32 height, u32 width, u32 line_length,
1170 const struct fb_copyarea *area)
1171 {
1172 struct tga_par *par = (struct tga_par *) info->par;
1173 unsigned long i, left, yincr;
1174 unsigned long depos, sepos, dealign, sealign;
1175 u32 mask_first, mask_last;
1176 unsigned long n32;
1177 void __iomem *tga_regs;
1178 void __iomem *tga_fb;
1179
1180 yincr = line_length;
1181 if (dy > sy) {
1182 dy += height - 1;
1183 sy += height - 1;
1184 yincr = -yincr;
1185 }
1186
1187 /* Compute the offsets and alignments in the frame buffer.
1188 More than anything else, these control how we do copies. */
1189 depos = dy * line_length + dx + width;
1190 sepos = sy * line_length + sx + width;
1191 dealign = depos & 7;
1192 sealign = sepos & 7;
1193
1194 /* ??? The documentation appears to be incorrect (or very
1195 misleading) wrt how pixel shifting works in backward copy
1196 mode, i.e. when PIXELSHIFT is negative. I give up for now.
1197 Do handle the common case of co-aligned backward copies,
1198 but frob everything else back on generic code. */
1199 if (dealign != sealign) {
1200 cfb_copyarea(info, area);
1201 return;
1202 }
1203
1204 /* We begin the copy with the trailing pixels of the
1205 unaligned destination. */
1206 mask_first = (1ul << dealign) - 1;
1207 left = width - dealign;
1208
1209 /* Care for small copies. */
1210 if (dealign > width) {
1211 mask_first ^= (1ul << (dealign - width)) - 1;
1212 left = 0;
1213 }
1214
1215 /* Next copy full words at a time. */
1216 n32 = left / 32;
1217 left %= 32;
1218
1219 /* Finally copy the unaligned head of the span. */
1220 mask_last = -1 << (32 - left);
1221
1222 tga_regs = par->tga_regs_base;
1223 tga_fb = par->tga_fb_base;
1224
1225 /* Set up the MODE and PIXELSHIFT registers. */
1226 __raw_writel(TGA_MODE_SBM_8BPP|TGA_MODE_COPY, tga_regs+TGA_MODE_REG);
1227 __raw_writel(0, tga_regs+TGA_PIXELSHIFT_REG);
1228 wmb();
1229
1230 for (i = 0; i < height; ++i) {
1231 unsigned long j;
1232 void __iomem *sfb;
1233 void __iomem *dfb;
1234
1235 sfb = tga_fb + sepos;
1236 dfb = tga_fb + depos;
1237 if (mask_first) {
1238 __raw_writel(mask_first, sfb);
1239 wmb();
1240 __raw_writel(mask_first, dfb);
1241 wmb();
1242 }
1243
1244 for (j = 0; j < n32; ++j) {
1245 sfb -= 32;
1246 dfb -= 32;
1247 __raw_writel(0xffffffff, sfb);
1248 wmb();
1249 __raw_writel(0xffffffff, dfb);
1250 wmb();
1251 }
1252
1253 if (mask_last) {
1254 sfb -= 32;
1255 dfb -= 32;
1256 __raw_writel(mask_last, sfb);
1257 wmb();
1258 __raw_writel(mask_last, dfb);
1259 wmb();
1260 }
1261
1262 sepos += yincr;
1263 depos += yincr;
1264 }
1265
1266 /* Reset the MODE register to normal. */
1267 __raw_writel(TGA_MODE_SBM_8BPP|TGA_MODE_SIMPLE, tga_regs+TGA_MODE_REG);
1268 }
1269
1270 static void
1271 tgafb_copyarea(struct fb_info *info, const struct fb_copyarea *area)
1272 {
1273 unsigned long dx, dy, width, height, sx, sy, vxres, vyres;
1274 unsigned long line_length, bpp;
1275
1276 dx = area->dx;
1277 dy = area->dy;
1278 width = area->width;
1279 height = area->height;
1280 sx = area->sx;
1281 sy = area->sy;
1282 vxres = info->var.xres_virtual;
1283 vyres = info->var.yres_virtual;
1284 line_length = info->fix.line_length;
1285
1286 /* The top left corners must be in the virtual screen. */
1287 if (dx > vxres || sx > vxres || dy > vyres || sy > vyres)
1288 return;
1289
1290 /* Clip the destination. */
1291 if (dx + width > vxres)
1292 width = vxres - dx;
1293 if (dy + height > vyres)
1294 height = vyres - dy;
1295
1296 /* The source must be completely inside the virtual screen. */
1297 if (sx + width > vxres || sy + height > vyres)
1298 return;
1299
1300 bpp = info->var.bits_per_pixel;
1301
1302 /* Detect copies of the entire line. */
1303 if (width * (bpp >> 3) == line_length) {
1304 if (bpp == 8)
1305 copyarea_line_8bpp(info, dy, sy, height, width);
1306 else
1307 copyarea_line_32bpp(info, dy, sy, height, width);
1308 }
1309
1310 /* ??? The documentation is unclear to me exactly how the pixelshift
1311 register works in 32bpp mode. Since I don't have hardware to test,
1312 give up for now and fall back on the generic routines. */
1313 else if (bpp == 32)
1314 cfb_copyarea(info, area);
1315
1316 /* Detect overlapping source and destination that requires
1317 a backward copy. */
1318 else if (dy == sy && dx > sx && dx < sx + width)
1319 copyarea_backward_8bpp(info, dx, dy, sx, sy, height,
1320 width, line_length, area);
1321 else
1322 copyarea_foreward_8bpp(info, dx, dy, sx, sy, height,
1323 width, line_length);
1324 }
1325
1326
1327 /*
1328 * Initialisation
1329 */
1330
1331 static void
1332 tgafb_init_fix(struct fb_info *info)
1333 {
1334 struct tga_par *par = (struct tga_par *)info->par;
1335 u8 tga_type = par->tga_type;
1336 const char *tga_type_name;
1337
1338 switch (tga_type) {
1339 case TGA_TYPE_8PLANE:
1340 tga_type_name = "Digital ZLXp-E1";
1341 break;
1342 case TGA_TYPE_24PLANE:
1343 tga_type_name = "Digital ZLXp-E2";
1344 break;
1345 case TGA_TYPE_24PLUSZ:
1346 tga_type_name = "Digital ZLXp-E3";
1347 break;
1348 default:
1349 tga_type_name = "Unknown";
1350 break;
1351 }
1352
1353 strlcpy(info->fix.id, tga_type_name, sizeof(info->fix.id));
1354
1355 info->fix.type = FB_TYPE_PACKED_PIXELS;
1356 info->fix.type_aux = 0;
1357 info->fix.visual = (tga_type == TGA_TYPE_8PLANE
1358 ? FB_VISUAL_PSEUDOCOLOR
1359 : FB_VISUAL_TRUECOLOR);
1360
1361 info->fix.line_length = par->xres * (par->bits_per_pixel >> 3);
1362 info->fix.smem_start = (size_t) par->tga_fb_base;
1363 info->fix.smem_len = info->fix.line_length * par->yres;
1364 info->fix.mmio_start = (size_t) par->tga_regs_base;
1365 info->fix.mmio_len = 512;
1366
1367 info->fix.xpanstep = 0;
1368 info->fix.ypanstep = 0;
1369 info->fix.ywrapstep = 0;
1370
1371 info->fix.accel = FB_ACCEL_DEC_TGA;
1372 }
1373
1374 static __devinit int
1375 tgafb_pci_register(struct pci_dev *pdev, const struct pci_device_id *ent)
1376 {
1377 static unsigned int const fb_offset_presets[4] = {
1378 TGA_8PLANE_FB_OFFSET,
1379 TGA_24PLANE_FB_OFFSET,
1380 0xffffffff,
1381 TGA_24PLUSZ_FB_OFFSET
1382 };
1383
1384 struct all_info {
1385 struct fb_info info;
1386 struct tga_par par;
1387 u32 pseudo_palette[16];
1388 } *all;
1389
1390 void __iomem *mem_base;
1391 unsigned long bar0_start, bar0_len;
1392 u8 tga_type;
1393 int ret;
1394
1395 /* Enable device in PCI config. */
1396 if (pci_enable_device(pdev)) {
1397 printk(KERN_ERR "tgafb: Cannot enable PCI device\n");
1398 return -ENODEV;
1399 }
1400
1401 /* Allocate the fb and par structures. */
1402 all = kmalloc(sizeof(*all), GFP_KERNEL);
1403 if (!all) {
1404 printk(KERN_ERR "tgafb: Cannot allocate memory\n");
1405 return -ENOMEM;
1406 }
1407 memset(all, 0, sizeof(*all));
1408 pci_set_drvdata(pdev, all);
1409
1410 /* Request the mem regions. */
1411 bar0_start = pci_resource_start(pdev, 0);
1412 bar0_len = pci_resource_len(pdev, 0);
1413 ret = -ENODEV;
1414 if (!request_mem_region (bar0_start, bar0_len, "tgafb")) {
1415 printk(KERN_ERR "tgafb: cannot reserve FB region\n");
1416 goto err0;
1417 }
1418
1419 /* Map the framebuffer. */
1420 mem_base = ioremap(bar0_start, bar0_len);
1421 if (!mem_base) {
1422 printk(KERN_ERR "tgafb: Cannot map MMIO\n");
1423 goto err1;
1424 }
1425
1426 /* Grab info about the card. */
1427 tga_type = (readl(mem_base) >> 12) & 0x0f;
1428 all->par.pdev = pdev;
1429 all->par.tga_mem_base = mem_base;
1430 all->par.tga_fb_base = mem_base + fb_offset_presets[tga_type];
1431 all->par.tga_regs_base = mem_base + TGA_REGS_OFFSET;
1432 all->par.tga_type = tga_type;
1433 pci_read_config_byte(pdev, PCI_REVISION_ID, &all->par.tga_chip_rev);
1434
1435 /* Setup framebuffer. */
1436 all->info.flags = FBINFO_DEFAULT | FBINFO_HWACCEL_COPYAREA |
1437 FBINFO_HWACCEL_IMAGEBLIT | FBINFO_HWACCEL_FILLRECT;
1438 all->info.fbops = &tgafb_ops;
1439 all->info.screen_base = all->par.tga_fb_base;
1440 all->info.par = &all->par;
1441 all->info.pseudo_palette = all->pseudo_palette;
1442
1443 /* This should give a reasonable default video mode. */
1444
1445 ret = fb_find_mode(&all->info.var, &all->info, mode_option,
1446 NULL, 0, NULL,
1447 tga_type == TGA_TYPE_8PLANE ? 8 : 32);
1448 if (ret == 0 || ret == 4) {
1449 printk(KERN_ERR "tgafb: Could not find valid video mode\n");
1450 ret = -EINVAL;
1451 goto err1;
1452 }
1453
1454 if (fb_alloc_cmap(&all->info.cmap, 256, 0)) {
1455 printk(KERN_ERR "tgafb: Could not allocate color map\n");
1456 ret = -ENOMEM;
1457 goto err1;
1458 }
1459
1460 tgafb_set_par(&all->info);
1461 tgafb_init_fix(&all->info);
1462
1463 all->info.device = &pdev->dev;
1464 if (register_framebuffer(&all->info) < 0) {
1465 printk(KERN_ERR "tgafb: Could not register framebuffer\n");
1466 ret = -EINVAL;
1467 goto err1;
1468 }
1469
1470 printk(KERN_INFO "tgafb: DC21030 [TGA] detected, rev=0x%02x\n",
1471 all->par.tga_chip_rev);
1472 printk(KERN_INFO "tgafb: at PCI bus %d, device %d, function %d\n",
1473 pdev->bus->number, PCI_SLOT(pdev->devfn),
1474 PCI_FUNC(pdev->devfn));
1475 printk(KERN_INFO "fb%d: %s frame buffer device at 0x%lx\n",
1476 all->info.node, all->info.fix.id, bar0_start);
1477
1478 return 0;
1479
1480 err1:
1481 release_mem_region(bar0_start, bar0_len);
1482 err0:
1483 kfree(all);
1484 return ret;
1485 }
1486
1487 #ifdef MODULE
1488 static void __exit
1489 tgafb_pci_unregister(struct pci_dev *pdev)
1490 {
1491 struct fb_info *info = pci_get_drvdata(pdev);
1492 struct tga_par *par = info->par;
1493
1494 if (!info)
1495 return;
1496 unregister_framebuffer(info);
1497 iounmap(par->tga_mem_base);
1498 release_mem_region(pci_resource_start(pdev, 0),
1499 pci_resource_len(pdev, 0));
1500 kfree(info);
1501 }
1502
1503 static void __exit
1504 tgafb_exit(void)
1505 {
1506 pci_unregister_driver(&tgafb_driver);
1507 }
1508 #endif /* MODULE */
1509
1510 #ifndef MODULE
1511 int __init
1512 tgafb_setup(char *arg)
1513 {
1514 char *this_opt;
1515
1516 if (arg && *arg) {
1517 while ((this_opt = strsep(&arg, ","))) {
1518 if (!*this_opt)
1519 continue;
1520 if (!strncmp(this_opt, "mode:", 5))
1521 mode_option = this_opt+5;
1522 else
1523 printk(KERN_ERR
1524 "tgafb: unknown parameter %s\n",
1525 this_opt);
1526 }
1527 }
1528
1529 return 0;
1530 }
1531 #endif /* !MODULE */
1532
1533 int __init
1534 tgafb_init(void)
1535 {
1536 #ifndef MODULE
1537 char *option = NULL;
1538
1539 if (fb_get_options("tgafb", &option))
1540 return -ENODEV;
1541 tgafb_setup(option);
1542 #endif
1543 return pci_register_driver(&tgafb_driver);
1544 }
1545
1546 /*
1547 * Modularisation
1548 */
1549
1550 module_init(tgafb_init);
1551
1552 #ifdef MODULE
1553 module_exit(tgafb_exit);
1554 #endif
1555
1556 MODULE_DESCRIPTION("framebuffer driver for TGA chipset");
1557 MODULE_LICENSE("GPL");
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