drivers/video/aty/xlinit.c

   1 /*
   2  *  ATI Rage XL Initialization. Support for Xpert98 and Victoria
   3  *  PCI cards.
   4  *
   5  *  Copyright (C) 2002 MontaVista Software Inc.
   6  *  Author: MontaVista Software, Inc.
   7  *              stevel@mvista.com or source@mvista.com
   8  *
   9  *  This program is free software; you can redistribute  it and/or modify it
  10  *  under  the terms of  the GNU General  Public License as published by the
  11  *  Free Software Foundation;  either version 2 of the  License, or (at your
  12  *  option) any later version.
  13  *
  14  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
  15  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  16  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  17  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
  18  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  19  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  20  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  21  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  22  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  23  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  24  *
  25  *  You should have received a copy of the  GNU General Public License along
  26  *  with this program; if not, write  to the Free Software Foundation, Inc.,
  27  *  675 Mass Ave, Cambridge, MA 02139, USA.
  28  */
  29 #include <linux/config.h>
  30 #include <linux/module.h>
  31 #include <linux/kernel.h>
  32 #include <linux/errno.h>
  33 #include <linux/string.h>
  34 #include <linux/mm.h>
  35 #include <linux/slab.h>
  36 #include <linux/vmalloc.h>
  37 #include <linux/delay.h>
  38 #include <linux/fb.h>
  39 #include <linux/init.h>
  40 #include <linux/pci.h>
  41 #include <asm/io.h>
  42 #include <video/mach64.h>
  43 #include "atyfb.h"
  44
  45 #define MPLL_GAIN       0xad
  46 #define VPLL_GAIN       0xd5
  47
  48 enum {
  49         VICTORIA = 0,
  50         XPERT98,
  51         NUM_XL_CARDS
  52 };
  53
  54 extern const struct aty_pll_ops aty_pll_ct;
  55
  56 #define DEFAULT_CARD XPERT98
  57 static int xl_card = DEFAULT_CARD;
  58
  59 static const struct xl_card_cfg_t {
  60         int ref_crystal; // 10^4 Hz
  61         int mem_type;
  62         int mem_size;
  63         u32 mem_cntl;
  64         u32 ext_mem_cntl;
  65         u32 mem_addr_config;
  66         u32 bus_cntl;
  67         u32 dac_cntl;
  68         u32 hw_debug;
  69         u32 custom_macro_cntl;
  70         u8  dll2_cntl;
  71         u8  pll_yclk_cntl;
  72 } card_cfg[NUM_XL_CARDS] = {
  73         // VICTORIA
  74         {       2700, SDRAM, 0x800000,
  75                 0x10757A3B, 0x64000C81, 0x00110202, 0x7b33A040,
  76                 0x82010102, 0x48803800, 0x005E0179,
  77                 0x50, 0x25
  78         },
  79         // XPERT98
  80         {       1432,  WRAM, 0x800000,
  81                 0x00165A2B, 0xE0000CF1, 0x00200213, 0x7333A001,
  82                 0x8000000A, 0x48833800, 0x007F0779,
  83                 0x10, 0x19
  84         }
  85 };
  86
  87 typedef struct {
  88         u8 lcd_reg;
  89         u32 val;
  90 } lcd_tbl_t;
  91
  92 static const lcd_tbl_t lcd_tbl[] = {
  93         { 0x01, 0x000520C0 },
  94         { 0x08, 0x02000408 },
  95         { 0x03, 0x00000F00 },
  96         { 0x00, 0x00000000 },
  97         { 0x02, 0x00000000 },
  98         { 0x04, 0x00000000 },
  99         { 0x05, 0x00000000 },
 100         { 0x06, 0x00000000 },
 101         { 0x33, 0x00000000 },
 102         { 0x34, 0x00000000 },
 103         { 0x35, 0x00000000 },
 104         { 0x36, 0x00000000 },
 105         { 0x37, 0x00000000 }
 106 };
 107
 108 static void reset_gui(struct atyfb_par *par)
 109 {
 110         aty_st_8(GEN_TEST_CNTL+1, 0x01, par);
 111         aty_st_8(GEN_TEST_CNTL+1, 0x00, par);
 112         aty_st_8(GEN_TEST_CNTL+1, 0x02, par);
 113         mdelay(5);
 114 }
 115
 116 static void reset_sdram(struct atyfb_par *par)
 117 {
 118         u8 temp;
 119
 120         temp = aty_ld_8(EXT_MEM_CNTL, par);
 121         temp |= 0x02;
 122         aty_st_8(EXT_MEM_CNTL, temp, par); // MEM_SDRAM_RESET = 1b
 123         temp |= 0x08;
 124         aty_st_8(EXT_MEM_CNTL, temp, par); // MEM_CYC_TEST    = 10b
 125         temp |= 0x0c;
 126         aty_st_8(EXT_MEM_CNTL, temp, par); // MEM_CYC_TEST    = 11b
 127         mdelay(5);
 128         temp &= 0xf3;
 129         aty_st_8(EXT_MEM_CNTL, temp, par); // MEM_CYC_TEST    = 00b
 130         temp &= 0xfd;
 131         aty_st_8(EXT_MEM_CNTL, temp, par); // MEM_SDRAM_REST  = 0b
 132         mdelay(5);
 133 }
 134
 135 static void init_dll(struct atyfb_par *par)
 136 {
 137         // enable DLL
 138         aty_st_pll_ct(PLL_GEN_CNTL,
 139                    aty_ld_pll_ct(PLL_GEN_CNTL, par) & 0x7f,
 140                    par);
 141
 142         // reset DLL
 143         aty_st_pll_ct(DLL_CNTL, 0x82, par);
 144         aty_st_pll_ct(DLL_CNTL, 0xE2, par);
 145         mdelay(5);
 146         aty_st_pll_ct(DLL_CNTL, 0x82, par);
 147         mdelay(6);
 148 }
 149
 150 static void reset_clocks(struct atyfb_par *par, struct pll_ct *pll,
 151                          int hsync_enb)
 152 {
 153         reset_gui(par);
 154         aty_st_pll_ct(MCLK_FB_DIV, pll->mclk_fb_div, par);
 155         aty_st_pll_ct(SCLK_FB_DIV, pll->sclk_fb_div, par);
 156
 157         mdelay(15);
 158         init_dll(par);
 159         aty_st_8(GEN_TEST_CNTL+1, 0x00, par);
 160         mdelay(5);
 161         aty_st_8(CRTC_GEN_CNTL+3, 0x04, par);
 162         mdelay(6);
 163         reset_sdram(par);
 164         aty_st_8(CRTC_GEN_CNTL+3,
 165                  hsync_enb ? 0x00 : 0x04, par);
 166
 167         aty_st_pll_ct(SPLL_CNTL2, pll->spll_cntl2, par);
 168         aty_st_pll_ct(PLL_GEN_CNTL, pll->pll_gen_cntl, par);
 169         aty_st_pll_ct(PLL_VCLK_CNTL, pll->pll_vclk_cntl, par);
 170 }
 171
 172 int atyfb_xl_init(struct fb_info *info)
 173 {
 174         const struct xl_card_cfg_t * card = &card_cfg[xl_card];
 175         struct atyfb_par *par = (struct atyfb_par *) info->par;
 176         union aty_pll pll;
 177         int i, err;
 178         u32 temp;
 179
 180         aty_st_8(CONFIG_STAT0, 0x85, par);
 181         mdelay(10);
 182
 183         /*
 184          * The following needs to be set before the call
 185          * to var_to_pll() below. They'll be re-set again
 186          * to the same values in aty_init().
 187          */
 188         par->ref_clk_per = 100000000UL/card->ref_crystal;
 189         par->ram_type = card->mem_type;
 190         info->fix.smem_len = card->mem_size;
 191         if (xl_card == VICTORIA) {
 192                 // the MCLK, XCLK are 120MHz on victoria card
 193                 par->mclk_per = 1000000/120;
 194                 par->xclk_per = 1000000/120;
 195                 par->features &= ~M64F_MFB_FORCE_4;
 196         }
 197
 198         /*
 199          * Calculate mclk and xclk dividers, etc. The passed
 200          * pixclock and bpp values don't matter yet, the vclk
 201          * isn't programmed until later.
 202          */
 203         if ((err = aty_pll_ct.var_to_pll(info, 39726, 8, &pll)))
 204                 return err;
 205
 206         aty_st_pll_ct(LVDS_CNTL0, 0x00, par);
 207         aty_st_pll_ct(DLL2_CNTL, card->dll2_cntl, par);
 208         aty_st_pll_ct(V2PLL_CNTL, 0x10, par);
 209         aty_st_pll_ct(MPLL_CNTL, MPLL_GAIN, par);
 210         aty_st_pll_ct(VPLL_CNTL, VPLL_GAIN, par);
 211         aty_st_pll_ct(PLL_VCLK_CNTL, 0x00, par);
 212         aty_st_pll_ct(VFC_CNTL, 0x1B, par);
 213         aty_st_pll_ct(PLL_REF_DIV, pll.ct.pll_ref_div, par);
 214         aty_st_pll_ct(PLL_EXT_CNTL, pll.ct.pll_ext_cntl, par);
 215         aty_st_pll_ct(SPLL_CNTL2, 0x03, par);
 216         aty_st_pll_ct(PLL_GEN_CNTL, 0x44, par);
 217
 218         reset_clocks(par, &pll.ct, 0);
 219         mdelay(10);
 220
 221         aty_st_pll_ct(VCLK_POST_DIV, 0x03, par);
 222         aty_st_pll_ct(VCLK0_FB_DIV, 0xDA, par);
 223         aty_st_pll_ct(VCLK_POST_DIV, 0x0F, par);
 224         aty_st_pll_ct(VCLK1_FB_DIV, 0xF5, par);
 225         aty_st_pll_ct(VCLK_POST_DIV, 0x3F, par);
 226         aty_st_pll_ct(PLL_EXT_CNTL, 0x40 | pll.ct.pll_ext_cntl, par);
 227         aty_st_pll_ct(VCLK2_FB_DIV, 0x00, par);
 228         aty_st_pll_ct(VCLK_POST_DIV, 0xFF, par);
 229         aty_st_pll_ct(PLL_EXT_CNTL, 0xC0 | pll.ct.pll_ext_cntl, par);
 230         aty_st_pll_ct(VCLK3_FB_DIV, 0x00, par);
 231
 232         aty_st_8(BUS_CNTL, 0x01, par);
 233         aty_st_le32(BUS_CNTL, card->bus_cntl | 0x08000000, par);
 234
 235         aty_st_le32(CRTC_GEN_CNTL, 0x04000200, par);
 236         aty_st_le16(CONFIG_STAT0, 0x0020, par);
 237         aty_st_le32(MEM_CNTL, 0x10151A33, par);
 238         aty_st_le32(EXT_MEM_CNTL, 0xE0000C01, par);
 239         aty_st_le16(CRTC_GEN_CNTL+2, 0x0000, par);
 240         aty_st_le32(DAC_CNTL, card->dac_cntl, par);
 241         aty_st_le16(GEN_TEST_CNTL, 0x0100, par);
 242         aty_st_le32(CUSTOM_MACRO_CNTL, 0x003C0171, par);
 243         aty_st_le32(MEM_BUF_CNTL, 0x00382848, par);
 244
 245         aty_st_le32(HW_DEBUG, card->hw_debug, par);
 246         aty_st_le16(MEM_ADDR_CONFIG, 0x0000, par);
 247         aty_st_le16(GP_IO+2, 0x0000, par);
 248         aty_st_le16(GEN_TEST_CNTL, 0x0000, par);
 249         aty_st_le16(EXT_DAC_REGS+2, 0x0000, par);
 250         aty_st_le32(CRTC_INT_CNTL, 0x00000000, par);
 251         aty_st_le32(TIMER_CONFIG, 0x00000000, par);
 252         aty_st_le32(0xEC, 0x00000000, par);
 253         aty_st_le32(0xFC, 0x00000000, par);
 254
 255         for (i=0; i<sizeof(lcd_tbl)/sizeof(lcd_tbl_t); i++) {
 256                 aty_st_lcd(lcd_tbl[i].lcd_reg, lcd_tbl[i].val, par);
 257         }
 258
 259         aty_st_le16(CONFIG_STAT0, 0x00A4, par);
 260         mdelay(10);
 261
 262         aty_st_8(BUS_CNTL+1, 0xA0, par);
 263         mdelay(10);
 264
 265         reset_clocks(par, &pll.ct, 1);
 266         mdelay(10);
 267
 268         // something about power management
 269         aty_st_8(LCD_INDEX, 0x08, par);
 270         aty_st_8(LCD_DATA, 0x0A, par);
 271         aty_st_8(LCD_INDEX, 0x08, par);
 272         aty_st_8(LCD_DATA+3, 0x02, par);
 273         aty_st_8(LCD_INDEX, 0x08, par);
 274         aty_st_8(LCD_DATA, 0x0B, par);
 275         mdelay(2);
 276
 277         // enable display requests, enable CRTC
 278         aty_st_8(CRTC_GEN_CNTL+3, 0x02, par);
 279         // disable display
 280         aty_st_8(CRTC_GEN_CNTL, 0x40, par);
 281         // disable display requests, disable CRTC
 282         aty_st_8(CRTC_GEN_CNTL+3, 0x04, par);
 283         mdelay(10);
 284
 285         aty_st_pll_ct(PLL_YCLK_CNTL, 0x25, par);
 286
 287         aty_st_le16(CUSTOM_MACRO_CNTL, 0x0179, par);
 288         aty_st_le16(CUSTOM_MACRO_CNTL+2, 0x005E, par);
 289         aty_st_le16(CUSTOM_MACRO_CNTL+2, card->custom_macro_cntl>>16, par);
 290         aty_st_8(CUSTOM_MACRO_CNTL+1,
 291                  (card->custom_macro_cntl>>8) & 0xff, par);
 292
 293         aty_st_le32(MEM_ADDR_CONFIG, card->mem_addr_config, par);
 294         aty_st_le32(MEM_CNTL, card->mem_cntl, par);
 295         aty_st_le32(EXT_MEM_CNTL, card->ext_mem_cntl, par);
 296
 297         aty_st_8(CONFIG_STAT0, 0xA0 | card->mem_type, par);
 298
 299         aty_st_pll_ct(PLL_YCLK_CNTL, 0x01, par);
 300         mdelay(15);
 301         aty_st_pll_ct(PLL_YCLK_CNTL, card->pll_yclk_cntl, par);
 302         mdelay(1);
 303
 304         reset_clocks(par, &pll.ct, 0);
 305         mdelay(50);
 306         reset_clocks(par, &pll.ct, 0);
 307         mdelay(50);
 308
 309         // enable extended register block
 310         aty_st_8(BUS_CNTL+3, 0x7B, par);
 311         mdelay(1);
 312         // disable extended register block
 313         aty_st_8(BUS_CNTL+3, 0x73, par);
 314
 315         aty_st_8(CONFIG_STAT0, 0x80 | card->mem_type, par);
 316
 317         // disable display requests, disable CRTC
 318         aty_st_8(CRTC_GEN_CNTL+3, 0x04, par);
 319         // disable mapping registers in VGA aperture
 320         aty_st_8(CONFIG_CNTL, aty_ld_8(CONFIG_CNTL, par) & ~0x04, par);
 321         mdelay(50);
 322         // enable display requests, enable CRTC
 323         aty_st_8(CRTC_GEN_CNTL+3, 0x02, par);
 324
 325         // make GPIO's 14,15,16 all inputs
 326         aty_st_8(LCD_INDEX, 0x07, par);
 327         aty_st_8(LCD_DATA+3, 0x00, par);
 328
 329         // enable the display
 330         aty_st_8(CRTC_GEN_CNTL, 0x00, par);
 331         mdelay(17);
 332         // reset the memory controller
 333         aty_st_8(GEN_TEST_CNTL+1, 0x02, par);
 334         mdelay(15);
 335         aty_st_8(GEN_TEST_CNTL+1, 0x00, par);
 336         mdelay(30);
 337
 338         // enable extended register block
 339         aty_st_8(BUS_CNTL+3,
 340                  (u8)(aty_ld_8(BUS_CNTL+3, par) | 0x08),
 341                  par);
 342         // set FIFO size to 512 (PIO)
 343         aty_st_le32(GUI_CNTL,
 344                     aty_ld_le32(GUI_CNTL, par) & ~0x3,
 345                     par);
 346
 347         // enable CRT and disable lcd
 348         aty_st_8(LCD_INDEX, 0x01, par);
 349         temp = aty_ld_le32(LCD_DATA, par);
 350         temp = (temp | 0x01) & ~0x02;
 351         aty_st_le32(LCD_DATA, temp, par);
 352         return 0;
 353 }
 354