drivers/serial/mpsc.h

   1 /*
   2  * drivers/serial/mpsc.h
   3  *
   4  * Author: Mark A. Greer <mgreer@mvista.com>
   5  *
   6  * 2004 (c) MontaVista, Software, Inc.  This file is licensed under
   7  * the terms of the GNU General Public License version 2.  This program
   8  * is licensed "as is" without any warranty of any kind, whether express
   9  * or implied.
  10  */
  11
  12 #ifndef __MPSC_H__
  13 #define __MPSC_H__
  14
  15 #include <linux/config.h>
  16 #include <linux/module.h>
  17 #include <linux/moduleparam.h>
  18 #include <linux/tty.h>
  19 #include <linux/tty_flip.h>
  20 #include <linux/ioport.h>
  21 #include <linux/init.h>
  22 #include <linux/console.h>
  23 #include <linux/sysrq.h>
  24 #include <linux/serial.h>
  25 #include <linux/serial_core.h>
  26 #include <linux/delay.h>
  27 #include <linux/device.h>
  28 #include <linux/dma-mapping.h>
  29 #include <linux/mv643xx.h>
  30
  31 #include <asm/io.h>
  32 #include <asm/irq.h>
  33
  34 #if defined(CONFIG_SERIAL_MPSC_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  35 #define SUPPORT_SYSRQ
  36 #endif
  37
  38 #define MPSC_NUM_CTLRS          2
  39
  40 /*
  41  * Descriptors and buffers must be cache line aligned.
  42  * Buffers lengths must be multiple of cache line size.
  43  * Number of Tx & Rx descriptors must be powers of 2.
  44  */
  45 #define MPSC_RXR_ENTRIES        32
  46 #define MPSC_RXRE_SIZE          dma_get_cache_alignment()
  47 #define MPSC_RXR_SIZE           (MPSC_RXR_ENTRIES * MPSC_RXRE_SIZE)
  48 #define MPSC_RXBE_SIZE          dma_get_cache_alignment()
  49 #define MPSC_RXB_SIZE           (MPSC_RXR_ENTRIES * MPSC_RXBE_SIZE)
  50
  51 #define MPSC_TXR_ENTRIES        32
  52 #define MPSC_TXRE_SIZE          dma_get_cache_alignment()
  53 #define MPSC_TXR_SIZE           (MPSC_TXR_ENTRIES * MPSC_TXRE_SIZE)
  54 #define MPSC_TXBE_SIZE          dma_get_cache_alignment()
  55 #define MPSC_TXB_SIZE           (MPSC_TXR_ENTRIES * MPSC_TXBE_SIZE)
  56
  57 #define MPSC_DMA_ALLOC_SIZE     (MPSC_RXR_SIZE + MPSC_RXB_SIZE +        \
  58                                 MPSC_TXR_SIZE + MPSC_TXB_SIZE +         \
  59                                 dma_get_cache_alignment() /* for alignment */)
  60
  61 /* Rx and Tx Ring entry descriptors -- assume entry size is <= cacheline size */
  62 struct mpsc_rx_desc {
  63         u16 bufsize;
  64         u16 bytecnt;
  65         u32 cmdstat;
  66         u32 link;
  67         u32 buf_ptr;
  68 } __attribute((packed));
  69
  70 struct mpsc_tx_desc {
  71         u16 bytecnt;
  72         u16 shadow;
  73         u32 cmdstat;
  74         u32 link;
  75         u32 buf_ptr;
  76 } __attribute((packed));
  77
  78 /*
  79  * Some regs that have the erratum that you can't read them are are shared
  80  * between the two MPSC controllers.  This struct contains those shared regs.
  81  */
  82 struct mpsc_shared_regs {
  83         phys_addr_t mpsc_routing_base_p;
  84         phys_addr_t sdma_intr_base_p;
  85
  86         void *mpsc_routing_base;
  87         void *sdma_intr_base;
  88
  89         u32 MPSC_MRR_m;
  90         u32 MPSC_RCRR_m;
  91         u32 MPSC_TCRR_m;
  92         u32 SDMA_INTR_CAUSE_m;
  93         u32 SDMA_INTR_MASK_m;
  94 };
  95
  96 /* The main driver data structure */
  97 struct mpsc_port_info {
  98         struct uart_port port;  /* Overlay uart_port structure */
  99
 100         /* Internal driver state for this ctlr */
 101         u8 ready;
 102         u8 rcv_data;
 103         tcflag_t c_iflag;       /* save termios->c_iflag */
 104         tcflag_t c_cflag;       /* save termios->c_cflag */
 105
 106         /* Info passed in from platform */
 107         u8 mirror_regs;         /* Need to mirror regs? */
 108         u8 cache_mgmt;          /* Need manual cache mgmt? */
 109         u8 brg_can_tune;        /* BRG has baud tuning? */
 110         u32 brg_clk_src;
 111         u16 mpsc_max_idle;
 112         int default_baud;
 113         int default_bits;
 114         int default_parity;
 115         int default_flow;
 116
 117         /* Physical addresses of various blocks of registers (from platform) */
 118         phys_addr_t mpsc_base_p;
 119         phys_addr_t sdma_base_p;
 120         phys_addr_t brg_base_p;
 121
 122         /* Virtual addresses of various blocks of registers (from platform) */
 123         void *mpsc_base;
 124         void *sdma_base;
 125         void *brg_base;
 126
 127         /* Descriptor ring and buffer allocations */
 128         void *dma_region;
 129         dma_addr_t dma_region_p;
 130
 131         dma_addr_t rxr;         /* Rx descriptor ring */
 132         dma_addr_t rxr_p;       /* Phys addr of rxr */
 133         u8 *rxb;                /* Rx Ring I/O buf */
 134         u8 *rxb_p;              /* Phys addr of rxb */
 135         u32 rxr_posn;           /* First desc w/ Rx data */
 136
 137         dma_addr_t txr;         /* Tx descriptor ring */
 138         dma_addr_t txr_p;       /* Phys addr of txr */
 139         u8 *txb;                /* Tx Ring I/O buf */
 140         u8 *txb_p;              /* Phys addr of txb */
 141         int txr_head;           /* Where new data goes */
 142         int txr_tail;           /* Where sent data comes off */
 143
 144         /* Mirrored values of regs we can't read (if 'mirror_regs' set) */
 145         u32 MPSC_MPCR_m;
 146         u32 MPSC_CHR_1_m;
 147         u32 MPSC_CHR_2_m;
 148         u32 MPSC_CHR_10_m;
 149         u32 BRG_BCR_m;
 150         struct mpsc_shared_regs *shared_regs;
 151 };
 152
 153 /* Hooks to platform-specific code */
 154 int mpsc_platform_register_driver(void);
 155 void mpsc_platform_unregister_driver(void);
 156
 157 /* Hooks back in to mpsc common to be called by platform-specific code */
 158 struct mpsc_port_info *mpsc_device_probe(int index);
 159 struct mpsc_port_info *mpsc_device_remove(int index);
 160
 161 /*
 162  *****************************************************************************
 163  *
 164  *      Multi-Protocol Serial Controller Interface Registers
 165  *
 166  *****************************************************************************
 167  */
 168
 169 /* Main Configuratino Register Offsets */
 170 #define MPSC_MMCRL                      0x0000
 171 #define MPSC_MMCRH                      0x0004
 172 #define MPSC_MPCR                       0x0008
 173 #define MPSC_CHR_1                      0x000c
 174 #define MPSC_CHR_2                      0x0010
 175 #define MPSC_CHR_3                      0x0014
 176 #define MPSC_CHR_4                      0x0018
 177 #define MPSC_CHR_5                      0x001c
 178 #define MPSC_CHR_6                      0x0020
 179 #define MPSC_CHR_7                      0x0024
 180 #define MPSC_CHR_8                      0x0028
 181 #define MPSC_CHR_9                      0x002c
 182 #define MPSC_CHR_10                     0x0030
 183 #define MPSC_CHR_11                     0x0034
 184
 185 #define MPSC_MPCR_FRZ                   (1 << 9)
 186 #define MPSC_MPCR_CL_5                  0
 187 #define MPSC_MPCR_CL_6                  1
 188 #define MPSC_MPCR_CL_7                  2
 189 #define MPSC_MPCR_CL_8                  3
 190 #define MPSC_MPCR_SBL_1                 0
 191 #define MPSC_MPCR_SBL_2                 1
 192
 193 #define MPSC_CHR_2_TEV                  (1<<1)
 194 #define MPSC_CHR_2_TA                   (1<<7)
 195 #define MPSC_CHR_2_TTCS                 (1<<9)
 196 #define MPSC_CHR_2_REV                  (1<<17)
 197 #define MPSC_CHR_2_RA                   (1<<23)
 198 #define MPSC_CHR_2_CRD                  (1<<25)
 199 #define MPSC_CHR_2_EH                   (1<<31)
 200 #define MPSC_CHR_2_PAR_ODD              0
 201 #define MPSC_CHR_2_PAR_SPACE            1
 202 #define MPSC_CHR_2_PAR_EVEN             2
 203 #define MPSC_CHR_2_PAR_MARK             3
 204
 205 /* MPSC Signal Routing */
 206 #define MPSC_MRR                        0x0000
 207 #define MPSC_RCRR                       0x0004
 208 #define MPSC_TCRR                       0x0008
 209
 210 /*
 211  *****************************************************************************
 212  *
 213  *      Serial DMA Controller Interface Registers
 214  *
 215  *****************************************************************************
 216  */
 217
 218 #define SDMA_SDC                        0x0000
 219 #define SDMA_SDCM                       0x0008
 220 #define SDMA_RX_DESC                    0x0800
 221 #define SDMA_RX_BUF_PTR                 0x0808
 222 #define SDMA_SCRDP                      0x0810
 223 #define SDMA_TX_DESC                    0x0c00
 224 #define SDMA_SCTDP                      0x0c10
 225 #define SDMA_SFTDP                      0x0c14
 226
 227 #define SDMA_DESC_CMDSTAT_PE            (1<<0)
 228 #define SDMA_DESC_CMDSTAT_CDL           (1<<1)
 229 #define SDMA_DESC_CMDSTAT_FR            (1<<3)
 230 #define SDMA_DESC_CMDSTAT_OR            (1<<6)
 231 #define SDMA_DESC_CMDSTAT_BR            (1<<9)
 232 #define SDMA_DESC_CMDSTAT_MI            (1<<10)
 233 #define SDMA_DESC_CMDSTAT_A             (1<<11)
 234 #define SDMA_DESC_CMDSTAT_AM            (1<<12)
 235 #define SDMA_DESC_CMDSTAT_CT            (1<<13)
 236 #define SDMA_DESC_CMDSTAT_C             (1<<14)
 237 #define SDMA_DESC_CMDSTAT_ES            (1<<15)
 238 #define SDMA_DESC_CMDSTAT_L             (1<<16)
 239 #define SDMA_DESC_CMDSTAT_F             (1<<17)
 240 #define SDMA_DESC_CMDSTAT_P             (1<<18)
 241 #define SDMA_DESC_CMDSTAT_EI            (1<<23)
 242 #define SDMA_DESC_CMDSTAT_O             (1<<31)
 243
 244 #define SDMA_DESC_DFLT                  (SDMA_DESC_CMDSTAT_O |  \
 245                                         SDMA_DESC_CMDSTAT_EI)
 246
 247 #define SDMA_SDC_RFT                    (1<<0)
 248 #define SDMA_SDC_SFM                    (1<<1)
 249 #define SDMA_SDC_BLMR                   (1<<6)
 250 #define SDMA_SDC_BLMT                   (1<<7)
 251 #define SDMA_SDC_POVR                   (1<<8)
 252 #define SDMA_SDC_RIFB                   (1<<9)
 253
 254 #define SDMA_SDCM_ERD                   (1<<7)
 255 #define SDMA_SDCM_AR                    (1<<15)
 256 #define SDMA_SDCM_STD                   (1<<16)
 257 #define SDMA_SDCM_TXD                   (1<<23)
 258 #define SDMA_SDCM_AT                    (1<<31)
 259
 260 #define SDMA_0_CAUSE_RXBUF              (1<<0)
 261 #define SDMA_0_CAUSE_RXERR              (1<<1)
 262 #define SDMA_0_CAUSE_TXBUF              (1<<2)
 263 #define SDMA_0_CAUSE_TXEND              (1<<3)
 264 #define SDMA_1_CAUSE_RXBUF              (1<<8)
 265 #define SDMA_1_CAUSE_RXERR              (1<<9)
 266 #define SDMA_1_CAUSE_TXBUF              (1<<10)
 267 #define SDMA_1_CAUSE_TXEND              (1<<11)
 268
 269 #define SDMA_CAUSE_RX_MASK      (SDMA_0_CAUSE_RXBUF | SDMA_0_CAUSE_RXERR | \
 270         SDMA_1_CAUSE_RXBUF | SDMA_1_CAUSE_RXERR)
 271 #define SDMA_CAUSE_TX_MASK      (SDMA_0_CAUSE_TXBUF | SDMA_0_CAUSE_TXEND | \
 272         SDMA_1_CAUSE_TXBUF | SDMA_1_CAUSE_TXEND)
 273
 274 /* SDMA Interrupt registers */
 275 #define SDMA_INTR_CAUSE                 0x0000
 276 #define SDMA_INTR_MASK                  0x0080
 277
 278 /*
 279  *****************************************************************************
 280  *
 281  *      Baud Rate Generator Interface Registers
 282  *
 283  *****************************************************************************
 284  */
 285
 286 #define BRG_BCR                         0x0000
 287 #define BRG_BTR                         0x0004
 288
 289 #endif                          /* __MPSC_H__ */