Linux-2.6.12-rc2
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / serial / cpm_uart / cpm_uart_cpm1.c
blobde26cf7b003cd89d807f02b87c008159ba72bce8
1 /*
2 * linux/drivers/serial/cpm_uart.c
4 * Driver for CPM (SCC/SMC) serial ports; CPM1 definitions
6 * Maintainer: Kumar Gala (kumar.gala@freescale.com) (CPM2)
7 * Pantelis Antoniou (panto@intracom.gr) (CPM1)
8 *
9 * Copyright (C) 2004 Freescale Semiconductor, Inc.
10 * (C) 2004 Intracom, S.A.
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
28 #include <linux/config.h>
29 #include <linux/module.h>
30 #include <linux/tty.h>
31 #include <linux/ioport.h>
32 #include <linux/init.h>
33 #include <linux/serial.h>
34 #include <linux/console.h>
35 #include <linux/sysrq.h>
36 #include <linux/device.h>
37 #include <linux/bootmem.h>
38 #include <linux/dma-mapping.h>
40 #include <asm/io.h>
41 #include <asm/irq.h>
43 #include <linux/serial_core.h>
44 #include <linux/kernel.h>
46 #include "cpm_uart.h"
48 /**************************************************************/
50 void cpm_line_cr_cmd(int line, int cmd)
52 ushort val;
53 volatile cpm8xx_t *cp = cpmp;
55 switch (line) {
56 case UART_SMC1:
57 val = mk_cr_cmd(CPM_CR_CH_SMC1, cmd) | CPM_CR_FLG;
58 break;
59 case UART_SMC2:
60 val = mk_cr_cmd(CPM_CR_CH_SMC2, cmd) | CPM_CR_FLG;
61 break;
62 case UART_SCC1:
63 val = mk_cr_cmd(CPM_CR_CH_SCC1, cmd) | CPM_CR_FLG;
64 break;
65 case UART_SCC2:
66 val = mk_cr_cmd(CPM_CR_CH_SCC2, cmd) | CPM_CR_FLG;
67 break;
68 case UART_SCC3:
69 val = mk_cr_cmd(CPM_CR_CH_SCC3, cmd) | CPM_CR_FLG;
70 break;
71 case UART_SCC4:
72 val = mk_cr_cmd(CPM_CR_CH_SCC4, cmd) | CPM_CR_FLG;
73 break;
74 default:
75 return;
78 cp->cp_cpcr = val;
79 while (cp->cp_cpcr & CPM_CR_FLG) ;
82 void smc1_lineif(struct uart_cpm_port *pinfo)
84 volatile cpm8xx_t *cp = cpmp;
85 unsigned int iobits = 0x000000c0;
87 if (!pinfo->is_portb) {
88 cp->cp_pbpar |= iobits;
89 cp->cp_pbdir &= ~iobits;
90 cp->cp_pbodr &= ~iobits;
91 } else {
92 ((immap_t *)IMAP_ADDR)->im_ioport.iop_papar |= iobits;
93 ((immap_t *)IMAP_ADDR)->im_ioport.iop_padir &= ~iobits;
94 ((immap_t *)IMAP_ADDR)->im_ioport.iop_paodr &= ~iobits;
97 pinfo->brg = 1;
100 void smc2_lineif(struct uart_cpm_port *pinfo)
102 /* XXX SMC2: insert port configuration here */
103 pinfo->brg = 2;
106 void scc1_lineif(struct uart_cpm_port *pinfo)
108 /* XXX SCC1: insert port configuration here */
109 pinfo->brg = 1;
112 void scc2_lineif(struct uart_cpm_port *pinfo)
114 /* XXX SCC2: insert port configuration here */
115 pinfo->brg = 2;
118 void scc3_lineif(struct uart_cpm_port *pinfo)
120 /* XXX SCC3: insert port configuration here */
121 pinfo->brg = 3;
124 void scc4_lineif(struct uart_cpm_port *pinfo)
126 /* XXX SCC4: insert port configuration here */
127 pinfo->brg = 4;
131 * Allocate DP-Ram and memory buffers. We need to allocate a transmit and
132 * receive buffer descriptors from dual port ram, and a character
133 * buffer area from host mem. If we are allocating for the console we need
134 * to do it from bootmem
136 int cpm_uart_allocbuf(struct uart_cpm_port *pinfo, unsigned int is_con)
138 int dpmemsz, memsz;
139 u8 *dp_mem;
140 uint dp_offset;
141 u8 *mem_addr;
142 dma_addr_t dma_addr = 0;
144 pr_debug("CPM uart[%d]:allocbuf\n", pinfo->port.line);
146 dpmemsz = sizeof(cbd_t) * (pinfo->rx_nrfifos + pinfo->tx_nrfifos);
147 dp_offset = cpm_dpalloc(dpmemsz, 8);
148 if (IS_DPERR(dp_offset)) {
149 printk(KERN_ERR
150 "cpm_uart_cpm1.c: could not allocate buffer descriptors\n");
151 return -ENOMEM;
153 dp_mem = cpm_dpram_addr(dp_offset);
155 memsz = L1_CACHE_ALIGN(pinfo->rx_nrfifos * pinfo->rx_fifosize) +
156 L1_CACHE_ALIGN(pinfo->tx_nrfifos * pinfo->tx_fifosize);
157 if (is_con) {
158 mem_addr = (u8 *) m8xx_cpm_hostalloc(memsz);
159 dma_addr = 0;
160 } else
161 mem_addr = dma_alloc_coherent(NULL, memsz, &dma_addr,
162 GFP_KERNEL);
164 if (mem_addr == NULL) {
165 cpm_dpfree(dp_offset);
166 printk(KERN_ERR
167 "cpm_uart_cpm1.c: could not allocate coherent memory\n");
168 return -ENOMEM;
171 pinfo->dp_addr = dp_offset;
172 pinfo->mem_addr = mem_addr;
173 pinfo->dma_addr = dma_addr;
175 pinfo->rx_buf = mem_addr;
176 pinfo->tx_buf = pinfo->rx_buf + L1_CACHE_ALIGN(pinfo->rx_nrfifos
177 * pinfo->rx_fifosize);
179 pinfo->rx_bd_base = (volatile cbd_t *)dp_mem;
180 pinfo->tx_bd_base = pinfo->rx_bd_base + pinfo->rx_nrfifos;
182 return 0;
185 void cpm_uart_freebuf(struct uart_cpm_port *pinfo)
187 dma_free_coherent(NULL, L1_CACHE_ALIGN(pinfo->rx_nrfifos *
188 pinfo->rx_fifosize) +
189 L1_CACHE_ALIGN(pinfo->tx_nrfifos *
190 pinfo->tx_fifosize), pinfo->mem_addr,
191 pinfo->dma_addr);
193 cpm_dpfree(pinfo->dp_addr);
196 /* Setup any dynamic params in the uart desc */
197 int cpm_uart_init_portdesc(void)
199 pr_debug("CPM uart[-]:init portdesc\n");
201 cpm_uart_nr = 0;
202 #ifdef CONFIG_SERIAL_CPM_SMC1
203 cpm_uart_ports[UART_SMC1].smcp = &cpmp->cp_smc[0];
205 * Is SMC1 being relocated?
207 # ifdef CONFIG_I2C_SPI_SMC1_UCODE_PATCH
208 cpm_uart_ports[UART_SMC1].smcup =
209 (smc_uart_t *) & cpmp->cp_dparam[0x3C0];
210 # else
211 cpm_uart_ports[UART_SMC1].smcup =
212 (smc_uart_t *) & cpmp->cp_dparam[PROFF_SMC1];
213 # endif
214 cpm_uart_ports[UART_SMC1].port.mapbase =
215 (unsigned long)&cpmp->cp_smc[0];
216 cpm_uart_ports[UART_SMC1].smcp->smc_smcm |= (SMCM_RX | SMCM_TX);
217 cpm_uart_ports[UART_SMC1].smcp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
218 cpm_uart_ports[UART_SMC1].port.uartclk = (((bd_t *) __res)->bi_intfreq);
219 cpm_uart_port_map[cpm_uart_nr++] = UART_SMC1;
220 #endif
222 #ifdef CONFIG_SERIAL_CPM_SMC2
223 cpm_uart_ports[UART_SMC2].smcp = &cpmp->cp_smc[1];
224 cpm_uart_ports[UART_SMC2].smcup =
225 (smc_uart_t *) & cpmp->cp_dparam[PROFF_SMC2];
226 cpm_uart_ports[UART_SMC2].port.mapbase =
227 (unsigned long)&cpmp->cp_smc[1];
228 cpm_uart_ports[UART_SMC2].smcp->smc_smcm |= (SMCM_RX | SMCM_TX);
229 cpm_uart_ports[UART_SMC2].smcp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
230 cpm_uart_ports[UART_SMC2].port.uartclk = (((bd_t *) __res)->bi_intfreq);
231 cpm_uart_port_map[cpm_uart_nr++] = UART_SMC2;
232 #endif
234 #ifdef CONFIG_SERIAL_CPM_SCC1
235 cpm_uart_ports[UART_SCC1].sccp = &cpmp->cp_scc[0];
236 cpm_uart_ports[UART_SCC1].sccup =
237 (scc_uart_t *) & cpmp->cp_dparam[PROFF_SCC1];
238 cpm_uart_ports[UART_SCC1].port.mapbase =
239 (unsigned long)&cpmp->cp_scc[0];
240 cpm_uart_ports[UART_SCC1].sccp->scc_sccm &=
241 ~(UART_SCCM_TX | UART_SCCM_RX);
242 cpm_uart_ports[UART_SCC1].sccp->scc_gsmrl &=
243 ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
244 cpm_uart_ports[UART_SCC1].port.uartclk = (((bd_t *) __res)->bi_intfreq);
245 cpm_uart_port_map[cpm_uart_nr++] = UART_SCC1;
246 #endif
248 #ifdef CONFIG_SERIAL_CPM_SCC2
249 cpm_uart_ports[UART_SCC2].sccp = &cpmp->cp_scc[1];
250 cpm_uart_ports[UART_SCC2].sccup =
251 (scc_uart_t *) & cpmp->cp_dparam[PROFF_SCC2];
252 cpm_uart_ports[UART_SCC2].port.mapbase =
253 (unsigned long)&cpmp->cp_scc[1];
254 cpm_uart_ports[UART_SCC2].sccp->scc_sccm &=
255 ~(UART_SCCM_TX | UART_SCCM_RX);
256 cpm_uart_ports[UART_SCC2].sccp->scc_gsmrl &=
257 ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
258 cpm_uart_ports[UART_SCC2].port.uartclk = (((bd_t *) __res)->bi_intfreq);
259 cpm_uart_port_map[cpm_uart_nr++] = UART_SCC2;
260 #endif
262 #ifdef CONFIG_SERIAL_CPM_SCC3
263 cpm_uart_ports[UART_SCC3].sccp = &cpmp->cp_scc[2];
264 cpm_uart_ports[UART_SCC3].sccup =
265 (scc_uart_t *) & cpmp->cp_dparam[PROFF_SCC3];
266 cpm_uart_ports[UART_SCC3].port.mapbase =
267 (unsigned long)&cpmp->cp_scc[2];
268 cpm_uart_ports[UART_SCC3].sccp->scc_sccm &=
269 ~(UART_SCCM_TX | UART_SCCM_RX);
270 cpm_uart_ports[UART_SCC3].sccp->scc_gsmrl &=
271 ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
272 cpm_uart_ports[UART_SCC3].port.uartclk = (((bd_t *) __res)->bi_intfreq);
273 cpm_uart_port_map[cpm_uart_nr++] = UART_SCC3;
274 #endif
276 #ifdef CONFIG_SERIAL_CPM_SCC4
277 cpm_uart_ports[UART_SCC4].sccp = &cpmp->cp_scc[3];
278 cpm_uart_ports[UART_SCC4].sccup =
279 (scc_uart_t *) & cpmp->cp_dparam[PROFF_SCC4];
280 cpm_uart_ports[UART_SCC4].port.mapbase =
281 (unsigned long)&cpmp->cp_scc[3];
282 cpm_uart_ports[UART_SCC4].sccp->scc_sccm &=
283 ~(UART_SCCM_TX | UART_SCCM_RX);
284 cpm_uart_ports[UART_SCC4].sccp->scc_gsmrl &=
285 ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
286 cpm_uart_ports[UART_SCC4].port.uartclk = (((bd_t *) __res)->bi_intfreq);
287 cpm_uart_port_map[cpm_uart_nr++] = UART_SCC4;
288 #endif
289 return 0;