drivers/scsi/sym53c8xx_2/sym_defs.h

   1 /*
   2  * Device driver for the SYMBIOS/LSILOGIC 53C8XX and 53C1010 family
   3  * of PCI-SCSI IO processors.
   4  *
   5  * Copyright (C) 1999-2001  Gerard Roudier <groudier@free.fr>
   6  *
   7  * This driver is derived from the Linux sym53c8xx driver.
   8  * Copyright (C) 1998-2000  Gerard Roudier
   9  *
  10  * The sym53c8xx driver is derived from the ncr53c8xx driver that had been
  11  * a port of the FreeBSD ncr driver to Linux-1.2.13.
  12  *
  13  * The original ncr driver has been written for 386bsd and FreeBSD by
  14  *         Wolfgang Stanglmeier        <wolf@cologne.de>
  15  *         Stefan Esser                <se@mi.Uni-Koeln.de>
  16  * Copyright (C) 1994  Wolfgang Stanglmeier
  17  *
  18  * Other major contributions:
  19  *
  20  * NVRAM detection and reading.
  21  * Copyright (C) 1997 Richard Waltham <dormouse@farsrobt.demon.co.uk>
  22  *
  23  *-----------------------------------------------------------------------------
  24  *
  25  * This program is free software; you can redistribute it and/or modify
  26  * it under the terms of the GNU General Public License as published by
  27  * the Free Software Foundation; either version 2 of the License, or
  28  * (at your option) any later version.
  29  *
  30  * This program is distributed in the hope that it will be useful,
  31  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  32  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  33  * GNU General Public License for more details.
  34  *
  35  * You should have received a copy of the GNU General Public License
  36  * along with this program; if not, write to the Free Software
  37  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  38  */
  39
  40 #ifndef SYM_DEFS_H
  41 #define SYM_DEFS_H
  42
  43 #define SYM_VERSION "2.2.0"
  44 #define SYM_DRIVER_NAME "sym-" SYM_VERSION
  45
  46 /*
  47  *      SYM53C8XX device features descriptor.
  48  */
  49 struct sym_chip {
  50         u_short device_id;
  51         u_short revision_id;
  52         char    *name;
  53         u_char  burst_max;      /* log-base-2 of max burst */
  54         u_char  offset_max;
  55         u_char  nr_divisor;
  56         u_char  lp_probe_bit;
  57         u_int   features;
  58 #define FE_LED0         (1<<0)
  59 #define FE_WIDE         (1<<1)    /* Wide data transfers */
  60 #define FE_ULTRA        (1<<2)    /* Ultra speed 20Mtrans/sec */
  61 #define FE_ULTRA2       (1<<3)    /* Ultra 2 - 40 Mtrans/sec */
  62 #define FE_DBLR         (1<<4)    /* Clock doubler present */
  63 #define FE_QUAD         (1<<5)    /* Clock quadrupler present */
  64 #define FE_ERL          (1<<6)    /* Enable read line */
  65 #define FE_CLSE         (1<<7)    /* Cache line size enable */
  66 #define FE_WRIE         (1<<8)    /* Write & Invalidate enable */
  67 #define FE_ERMP         (1<<9)    /* Enable read multiple */
  68 #define FE_BOF          (1<<10)   /* Burst opcode fetch */
  69 #define FE_DFS          (1<<11)   /* DMA fifo size */
  70 #define FE_PFEN         (1<<12)   /* Prefetch enable */
  71 #define FE_LDSTR        (1<<13)   /* Load/Store supported */
  72 #define FE_RAM          (1<<14)   /* On chip RAM present */
  73 #define FE_VARCLK       (1<<15)   /* Clock frequency may vary */
  74 #define FE_RAM8K        (1<<16)   /* On chip RAM sized 8Kb */
  75 #define FE_64BIT        (1<<17)   /* 64-bit PCI BUS interface */
  76 #define FE_IO256        (1<<18)   /* Requires full 256 bytes in PCI space */
  77 #define FE_NOPM         (1<<19)   /* Scripts handles phase mismatch */
  78 #define FE_LEDC         (1<<20)   /* Hardware control of LED */
  79 #define FE_ULTRA3       (1<<21)   /* Ultra 3 - 80 Mtrans/sec DT */
  80 #define FE_66MHZ        (1<<22)   /* 66MHz PCI support */
  81 #define FE_CRC          (1<<23)   /* CRC support */
  82 #define FE_DIFF         (1<<24)   /* SCSI HVD support */
  83 #define FE_DFBC         (1<<25)   /* Have DFBC register */
  84 #define FE_LCKFRQ       (1<<26)   /* Have LCKFRQ */
  85 #define FE_C10          (1<<27)   /* Various C10 core (mis)features */
  86 #define FE_U3EN         (1<<28)   /* U3EN bit usable */
  87 #define FE_DAC          (1<<29)   /* Support PCI DAC (64 bit addressing) */
  88 #define FE_ISTAT1       (1<<30)   /* Have ISTAT1, MBOX0, MBOX1 registers */
  89
  90 #define FE_CACHE_SET    (FE_ERL|FE_CLSE|FE_WRIE|FE_ERMP)
  91 #define FE_CACHE0_SET   (FE_CACHE_SET & ~FE_ERL)
  92 };
  93
  94 /*
  95  *      SYM53C8XX IO register data structure.
  96  */
  97 struct sym_reg {
  98 /*00*/  u8      nc_scntl0;      /* full arb., ena parity, par->ATN  */
  99
 100 /*01*/  u8      nc_scntl1;      /* no reset                         */
 101         #define   ISCON   0x10  /* connected to scsi                */
 102         #define   CRST    0x08  /* force reset                      */
 103         #define   IARB    0x02  /* immediate arbitration            */
 104
 105 /*02*/  u8      nc_scntl2;      /* no disconnect expected           */
 106         #define   SDU     0x80  /* cmd: disconnect will raise error */
 107         #define   CHM     0x40  /* sta: chained mode                */
 108         #define   WSS     0x08  /* sta: wide scsi send           [W]*/
 109         #define   WSR     0x01  /* sta: wide scsi received       [W]*/
 110
 111 /*03*/  u8      nc_scntl3;      /* cnf system clock dependent       */
 112         #define   EWS     0x08  /* cmd: enable wide scsi         [W]*/
 113         #define   ULTRA   0x80  /* cmd: ULTRA enable                */
 114                                 /* bits 0-2, 7 rsvd for C1010       */
 115
 116 /*04*/  u8      nc_scid;        /* cnf host adapter scsi address    */
 117         #define   RRE     0x40  /* r/w:e enable response to resel.  */
 118         #define   SRE     0x20  /* r/w:e enable response to select  */
 119
 120 /*05*/  u8      nc_sxfer;       /* ### Sync speed and count         */
 121                                 /* bits 6-7 rsvd for C1010          */
 122
 123 /*06*/  u8      nc_sdid;        /* ### Destination-ID               */
 124
 125 /*07*/  u8      nc_gpreg;       /* ??? IO-Pins                      */
 126
 127 /*08*/  u8      nc_sfbr;        /* ### First byte received          */
 128
 129 /*09*/  u8      nc_socl;
 130         #define   CREQ    0x80  /* r/w: SCSI-REQ                    */
 131         #define   CACK    0x40  /* r/w: SCSI-ACK                    */
 132         #define   CBSY    0x20  /* r/w: SCSI-BSY                    */
 133         #define   CSEL    0x10  /* r/w: SCSI-SEL                    */
 134         #define   CATN    0x08  /* r/w: SCSI-ATN                    */
 135         #define   CMSG    0x04  /* r/w: SCSI-MSG                    */
 136         #define   CC_D    0x02  /* r/w: SCSI-C_D                    */
 137         #define   CI_O    0x01  /* r/w: SCSI-I_O                    */
 138
 139 /*0a*/  u8      nc_ssid;
 140
 141 /*0b*/  u8      nc_sbcl;
 142
 143 /*0c*/  u8      nc_dstat;
 144         #define   DFE     0x80  /* sta: dma fifo empty              */
 145         #define   MDPE    0x40  /* int: master data parity error    */
 146         #define   BF      0x20  /* int: script: bus fault           */
 147         #define   ABRT    0x10  /* int: script: command aborted     */
 148         #define   SSI     0x08  /* int: script: single step         */
 149         #define   SIR     0x04  /* int: script: interrupt instruct. */
 150         #define   IID     0x01  /* int: script: illegal instruct.   */
 151
 152 /*0d*/  u8      nc_sstat0;
 153         #define   ILF     0x80  /* sta: data in SIDL register lsb   */
 154         #define   ORF     0x40  /* sta: data in SODR register lsb   */
 155         #define   OLF     0x20  /* sta: data in SODL register lsb   */
 156         #define   AIP     0x10  /* sta: arbitration in progress     */
 157         #define   LOA     0x08  /* sta: arbitration lost            */
 158         #define   WOA     0x04  /* sta: arbitration won             */
 159         #define   IRST    0x02  /* sta: scsi reset signal           */
 160         #define   SDP     0x01  /* sta: scsi parity signal          */
 161
 162 /*0e*/  u8      nc_sstat1;
 163         #define   FF3210  0xf0  /* sta: bytes in the scsi fifo      */
 164
 165 /*0f*/  u8      nc_sstat2;
 166         #define   ILF1    0x80  /* sta: data in SIDL register msb[W]*/
 167         #define   ORF1    0x40  /* sta: data in SODR register msb[W]*/
 168         #define   OLF1    0x20  /* sta: data in SODL register msb[W]*/
 169         #define   DM      0x04  /* sta: DIFFSENS mismatch (895/6 only) */
 170         #define   LDSC    0x02  /* sta: disconnect & reconnect      */
 171
 172 /*10*/  u8      nc_dsa;         /* --> Base page                    */
 173 /*11*/  u8      nc_dsa1;
 174 /*12*/  u8      nc_dsa2;
 175 /*13*/  u8      nc_dsa3;
 176
 177 /*14*/  u8      nc_istat;       /* --> Main Command and status      */
 178         #define   CABRT   0x80  /* cmd: abort current operation     */
 179         #define   SRST    0x40  /* mod: reset chip                  */
 180         #define   SIGP    0x20  /* r/w: message from host to script */
 181         #define   SEM     0x10  /* r/w: message between host + script  */
 182         #define   CON     0x08  /* sta: connected to scsi           */
 183         #define   INTF    0x04  /* sta: int on the fly (reset by wr)*/
 184         #define   SIP     0x02  /* sta: scsi-interrupt              */
 185         #define   DIP     0x01  /* sta: host/script interrupt       */
 186
 187 /*15*/  u8      nc_istat1;      /* 896 only */
 188         #define   FLSH    0x04  /* sta: chip is flushing            */
 189         #define   SCRUN   0x02  /* sta: scripts are running         */
 190         #define   SIRQD   0x01  /* r/w: disable INT pin             */
 191
 192 /*16*/  u8      nc_mbox0;       /* 896 only */
 193 /*17*/  u8      nc_mbox1;       /* 896 only */
 194
 195 /*18*/  u8      nc_ctest0;
 196 /*19*/  u8      nc_ctest1;
 197
 198 /*1a*/  u8      nc_ctest2;
 199         #define   CSIGP   0x40
 200                                 /* bits 0-2,7 rsvd for C1010        */
 201
 202 /*1b*/  u8      nc_ctest3;
 203         #define   FLF     0x08  /* cmd: flush dma fifo              */
 204         #define   CLF     0x04  /* cmd: clear dma fifo              */
 205         #define   FM      0x02  /* mod: fetch pin mode              */
 206         #define   WRIE    0x01  /* mod: write and invalidate enable */
 207                                 /* bits 4-7 rsvd for C1010          */
 208
 209 /*1c*/  u32     nc_temp;        /* ### Temporary stack              */
 210
 211 /*20*/  u8      nc_dfifo;
 212 /*21*/  u8      nc_ctest4;
 213         #define   BDIS    0x80  /* mod: burst disable               */
 214         #define   MPEE    0x08  /* mod: master parity error enable  */
 215
 216 /*22*/  u8      nc_ctest5;
 217         #define   DFS     0x20  /* mod: dma fifo size               */
 218                                 /* bits 0-1, 3-7 rsvd for C1010     */
 219
 220 /*23*/  u8      nc_ctest6;
 221
 222 /*24*/  u32     nc_dbc;         /* ### Byte count and command       */
 223 /*28*/  u32     nc_dnad;        /* ### Next command register        */
 224 /*2c*/  u32     nc_dsp;         /* --> Script Pointer               */
 225 /*30*/  u32     nc_dsps;        /* --> Script pointer save/opcode#2 */
 226
 227 /*34*/  u8      nc_scratcha;    /* Temporary register a            */
 228 /*35*/  u8      nc_scratcha1;
 229 /*36*/  u8      nc_scratcha2;
 230 /*37*/  u8      nc_scratcha3;
 231
 232 /*38*/  u8      nc_dmode;
 233         #define   BL_2    0x80  /* mod: burst length shift value +2 */
 234         #define   BL_1    0x40  /* mod: burst length shift value +1 */
 235         #define   ERL     0x08  /* mod: enable read line            */
 236         #define   ERMP    0x04  /* mod: enable read multiple        */
 237         #define   BOF     0x02  /* mod: burst op code fetch         */
 238
 239 /*39*/  u8      nc_dien;
 240 /*3a*/  u8      nc_sbr;
 241
 242 /*3b*/  u8      nc_dcntl;       /* --> Script execution control     */
 243         #define   CLSE    0x80  /* mod: cache line size enable      */
 244         #define   PFF     0x40  /* cmd: pre-fetch flush             */
 245         #define   PFEN    0x20  /* mod: pre-fetch enable            */
 246         #define   SSM     0x10  /* mod: single step mode            */
 247         #define   IRQM    0x08  /* mod: irq mode (1 = totem pole !) */
 248         #define   STD     0x04  /* cmd: start dma mode              */
 249         #define   IRQD    0x02  /* mod: irq disable                 */
 250         #define   NOCOM   0x01  /* cmd: protect sfbr while reselect */
 251                                 /* bits 0-1 rsvd for C1010          */
 252
 253 /*3c*/  u32     nc_adder;
 254
 255 /*40*/  u16     nc_sien;        /* -->: interrupt enable            */
 256 /*42*/  u16     nc_sist;        /* <--: interrupt status            */
 257         #define   SBMC    0x1000/* sta: SCSI Bus Mode Change (895/6 only) */
 258         #define   STO     0x0400/* sta: timeout (select)            */
 259         #define   GEN     0x0200/* sta: timeout (general)           */
 260         #define   HTH     0x0100/* sta: timeout (handshake)         */
 261         #define   MA      0x80  /* sta: phase mismatch              */
 262         #define   CMP     0x40  /* sta: arbitration complete        */
 263         #define   SEL     0x20  /* sta: selected by another device  */
 264         #define   RSL     0x10  /* sta: reselected by another device*/
 265         #define   SGE     0x08  /* sta: gross error (over/underflow)*/
 266         #define   UDC     0x04  /* sta: unexpected disconnect       */
 267         #define   RST     0x02  /* sta: scsi bus reset detected     */
 268         #define   PAR     0x01  /* sta: scsi parity error           */
 269
 270 /*44*/  u8      nc_slpar;
 271 /*45*/  u8      nc_swide;
 272 /*46*/  u8      nc_macntl;
 273 /*47*/  u8      nc_gpcntl;
 274 /*48*/  u8      nc_stime0;      /* cmd: timeout for select&handshake*/
 275 /*49*/  u8      nc_stime1;      /* cmd: timeout user defined        */
 276 /*4a*/  u16     nc_respid;      /* sta: Reselect-IDs                */
 277
 278 /*4c*/  u8      nc_stest0;
 279
 280 /*4d*/  u8      nc_stest1;
 281         #define   SCLK    0x80  /* Use the PCI clock as SCSI clock      */
 282         #define   DBLEN   0x08  /* clock doubler running                */
 283         #define   DBLSEL  0x04  /* clock doubler selected               */
 284
 285
 286 /*4e*/  u8      nc_stest2;
 287         #define   ROF     0x40  /* reset scsi offset (after gross error!) */
 288         #define   EXT     0x02  /* extended filtering                     */
 289
 290 /*4f*/  u8      nc_stest3;
 291         #define   TE     0x80   /* c: tolerAnt enable */
 292         #define   HSC    0x20   /* c: Halt SCSI Clock */
 293         #define   CSF    0x02   /* c: clear scsi fifo */
 294
 295 /*50*/  u16     nc_sidl;        /* Lowlevel: latched from scsi data */
 296 /*52*/  u8      nc_stest4;
 297         #define   SMODE  0xc0   /* SCSI bus mode      (895/6 only) */
 298         #define    SMODE_HVD 0x40       /* High Voltage Differential       */
 299         #define    SMODE_SE  0x80       /* Single Ended                    */
 300         #define    SMODE_LVD 0xc0       /* Low Voltage Differential        */
 301         #define   LCKFRQ 0x20   /* Frequency Lock (895/6 only)     */
 302                                 /* bits 0-5 rsvd for C1010         */
 303
 304 /*53*/  u8      nc_53_;
 305 /*54*/  u16     nc_sodl;        /* Lowlevel: data out to scsi data  */
 306 /*56*/  u8      nc_ccntl0;      /* Chip Control 0 (896)             */
 307         #define   ENPMJ  0x80   /* Enable Phase Mismatch Jump       */
 308         #define   PMJCTL 0x40   /* Phase Mismatch Jump Control      */
 309         #define   ENNDJ  0x20   /* Enable Non Data PM Jump          */
 310         #define   DISFC  0x10   /* Disable Auto FIFO Clear          */
 311         #define   DILS   0x02   /* Disable Internal Load/Store      */
 312         #define   DPR    0x01   /* Disable Pipe Req                 */
 313
 314 /*57*/  u8      nc_ccntl1;      /* Chip Control 1 (896)             */
 315         #define   ZMOD   0x80   /* High Impedance Mode              */
 316         #define   DDAC   0x08   /* Disable Dual Address Cycle       */
 317         #define   XTIMOD 0x04   /* 64-bit Table Ind. Indexing Mode  */
 318         #define   EXTIBMV 0x02  /* Enable 64-bit Table Ind. BMOV    */
 319         #define   EXDBMV 0x01   /* Enable 64-bit Direct BMOV        */
 320
 321 /*58*/  u16     nc_sbdl;        /* Lowlevel: data from scsi data    */
 322 /*5a*/  u16     nc_5a_;
 323
 324 /*5c*/  u8      nc_scr0;        /* Working register B               */
 325 /*5d*/  u8      nc_scr1;
 326 /*5e*/  u8      nc_scr2;
 327 /*5f*/  u8      nc_scr3;
 328
 329 /*60*/  u8      nc_scrx[64];    /* Working register C-R             */
 330 /*a0*/  u32     nc_mmrs;        /* Memory Move Read Selector        */
 331 /*a4*/  u32     nc_mmws;        /* Memory Move Write Selector       */
 332 /*a8*/  u32     nc_sfs;         /* Script Fetch Selector            */
 333 /*ac*/  u32     nc_drs;         /* DSA Relative Selector            */
 334 /*b0*/  u32     nc_sbms;        /* Static Block Move Selector       */
 335 /*b4*/  u32     nc_dbms;        /* Dynamic Block Move Selector      */
 336 /*b8*/  u32     nc_dnad64;      /* DMA Next Address 64              */
 337 /*bc*/  u16     nc_scntl4;      /* C1010 only                       */
 338         #define   U3EN    0x80  /* Enable Ultra 3                   */
 339         #define   AIPCKEN 0x40  /* AIP checking enable              */
 340                                 /* Also enable AIP generation on C10-33*/
 341         #define   XCLKH_DT 0x08 /* Extra clock of data hold on DT edge */
 342         #define   XCLKH_ST 0x04 /* Extra clock of data hold on ST edge */
 343         #define   XCLKS_DT 0x02 /* Extra clock of data set  on DT edge */
 344         #define   XCLKS_ST 0x01 /* Extra clock of data set  on ST edge */
 345 /*be*/  u8      nc_aipcntl0;    /* AIP Control 0 C1010 only         */
 346 /*bf*/  u8      nc_aipcntl1;    /* AIP Control 1 C1010 only         */
 347         #define DISAIP  0x08    /* Disable AIP generation C10-66 only  */
 348 /*c0*/  u32     nc_pmjad1;      /* Phase Mismatch Jump Address 1    */
 349 /*c4*/  u32     nc_pmjad2;      /* Phase Mismatch Jump Address 2    */
 350 /*c8*/  u8      nc_rbc;         /* Remaining Byte Count             */
 351 /*c9*/  u8      nc_rbc1;
 352 /*ca*/  u8      nc_rbc2;
 353 /*cb*/  u8      nc_rbc3;
 354
 355 /*cc*/  u8      nc_ua;          /* Updated Address                  */
 356 /*cd*/  u8      nc_ua1;
 357 /*ce*/  u8      nc_ua2;
 358 /*cf*/  u8      nc_ua3;
 359 /*d0*/  u32     nc_esa;         /* Entry Storage Address            */
 360 /*d4*/  u8      nc_ia;          /* Instruction Address              */
 361 /*d5*/  u8      nc_ia1;
 362 /*d6*/  u8      nc_ia2;
 363 /*d7*/  u8      nc_ia3;
 364 /*d8*/  u32     nc_sbc;         /* SCSI Byte Count (3 bytes only)   */
 365 /*dc*/  u32     nc_csbc;        /* Cumulative SCSI Byte Count       */
 366                                 /* Following for C1010 only         */
 367 /*e0*/  u16    nc_crcpad;       /* CRC Value                        */
 368 /*e2*/  u8     nc_crccntl0;     /* CRC control register             */
 369         #define   SNDCRC  0x10  /* Send CRC Request                 */
 370 /*e3*/  u8     nc_crccntl1;     /* CRC control register             */
 371 /*e4*/  u32    nc_crcdata;      /* CRC data register                */
 372 /*e8*/  u32    nc_e8_;
 373 /*ec*/  u32    nc_ec_;
 374 /*f0*/  u16    nc_dfbc;         /* DMA FIFO byte count              */
 375 };
 376
 377 /*-----------------------------------------------------------
 378  *
 379  *      Utility macros for the script.
 380  *
 381  *-----------------------------------------------------------
 382  */
 383
 384 #define REGJ(p,r) (offsetof(struct sym_reg, p ## r))
 385 #define REG(r) REGJ (nc_, r)
 386
 387 /*-----------------------------------------------------------
 388  *
 389  *      SCSI phases
 390  *
 391  *-----------------------------------------------------------
 392  */
 393
 394 #define SCR_DATA_OUT    0x00000000
 395 #define SCR_DATA_IN     0x01000000
 396 #define SCR_COMMAND     0x02000000
 397 #define SCR_STATUS      0x03000000
 398 #define SCR_DT_DATA_OUT 0x04000000
 399 #define SCR_DT_DATA_IN  0x05000000
 400 #define SCR_MSG_OUT     0x06000000
 401 #define SCR_MSG_IN      0x07000000
 402 /* DT phases are illegal for non Ultra3 mode */
 403 #define SCR_ILG_OUT     0x04000000
 404 #define SCR_ILG_IN      0x05000000
 405
 406 /*-----------------------------------------------------------
 407  *
 408  *      Data transfer via SCSI.
 409  *
 410  *-----------------------------------------------------------
 411  *
 412  *      MOVE_ABS (LEN)
 413  *      <<start address>>
 414  *
 415  *      MOVE_IND (LEN)
 416  *      <<dnad_offset>>
 417  *
 418  *      MOVE_TBL
 419  *      <<dnad_offset>>
 420  *
 421  *-----------------------------------------------------------
 422  */
 423
 424 #define OPC_MOVE          0x08000000
 425
 426 #define SCR_MOVE_ABS(l) ((0x00000000 | OPC_MOVE) | (l))
 427 /* #define SCR_MOVE_IND(l) ((0x20000000 | OPC_MOVE) | (l)) */
 428 #define SCR_MOVE_TBL     (0x10000000 | OPC_MOVE)
 429
 430 #define SCR_CHMOV_ABS(l) ((0x00000000) | (l))
 431 /* #define SCR_CHMOV_IND(l) ((0x20000000) | (l)) */
 432 #define SCR_CHMOV_TBL     (0x10000000)
 433
 434 #ifdef SYM_CONF_TARGET_ROLE_SUPPORT
 435 /* We steal the `indirect addressing' flag for target mode MOVE in scripts */
 436
 437 #define OPC_TCHMOVE        0x08000000
 438
 439 #define SCR_TCHMOVE_ABS(l) ((0x20000000 | OPC_TCHMOVE) | (l))
 440 #define SCR_TCHMOVE_TBL     (0x30000000 | OPC_TCHMOVE)
 441
 442 #define SCR_TMOV_ABS(l)    ((0x20000000) | (l))
 443 #define SCR_TMOV_TBL        (0x30000000)
 444 #endif
 445
 446 struct sym_tblmove {
 447         u32  size;
 448         u32  addr;
 449 };
 450
 451 /*-----------------------------------------------------------
 452  *
 453  *      Selection
 454  *
 455  *-----------------------------------------------------------
 456  *
 457  *      SEL_ABS | SCR_ID (0..15)    [ | REL_JMP]
 458  *      <<alternate_address>>
 459  *
 460  *      SEL_TBL | << dnad_offset>>  [ | REL_JMP]
 461  *      <<alternate_address>>
 462  *
 463  *-----------------------------------------------------------
 464  */
 465
 466 #define SCR_SEL_ABS     0x40000000
 467 #define SCR_SEL_ABS_ATN 0x41000000
 468 #define SCR_SEL_TBL     0x42000000
 469 #define SCR_SEL_TBL_ATN 0x43000000
 470
 471 #ifdef SYM_CONF_TARGET_ROLE_SUPPORT
 472 #define SCR_RESEL_ABS     0x40000000
 473 #define SCR_RESEL_ABS_ATN 0x41000000
 474 #define SCR_RESEL_TBL     0x42000000
 475 #define SCR_RESEL_TBL_ATN 0x43000000
 476 #endif
 477
 478 struct sym_tblsel {
 479         u_char  sel_scntl4;     /* C1010 only */
 480         u_char  sel_sxfer;
 481         u_char  sel_id;
 482         u_char  sel_scntl3;
 483 };
 484
 485 #define SCR_JMP_REL     0x04000000
 486 #define SCR_ID(id)      (((u32)(id)) << 16)
 487
 488 /*-----------------------------------------------------------
 489  *
 490  *      Waiting for Disconnect or Reselect
 491  *
 492  *-----------------------------------------------------------
 493  *
 494  *      WAIT_DISC
 495  *      dummy: <<alternate_address>>
 496  *
 497  *      WAIT_RESEL
 498  *      <<alternate_address>>
 499  *
 500  *-----------------------------------------------------------
 501  */
 502
 503 #define SCR_WAIT_DISC   0x48000000
 504 #define SCR_WAIT_RESEL  0x50000000
 505
 506 #ifdef SYM_CONF_TARGET_ROLE_SUPPORT
 507 #define SCR_DISCONNECT  0x48000000
 508 #endif
 509
 510 /*-----------------------------------------------------------
 511  *
 512  *      Bit Set / Reset
 513  *
 514  *-----------------------------------------------------------
 515  *
 516  *      SET (flags {|.. })
 517  *
 518  *      CLR (flags {|.. })
 519  *
 520  *-----------------------------------------------------------
 521  */
 522
 523 #define SCR_SET(f)     (0x58000000 | (f))
 524 #define SCR_CLR(f)     (0x60000000 | (f))
 525
 526 #define SCR_CARRY       0x00000400
 527 #define SCR_TRG         0x00000200
 528 #define SCR_ACK         0x00000040
 529 #define SCR_ATN         0x00000008
 530
 531
 532 /*-----------------------------------------------------------
 533  *
 534  *      Memory to memory move
 535  *
 536  *-----------------------------------------------------------
 537  *
 538  *      COPY (bytecount)
 539  *      << source_address >>
 540  *      << destination_address >>
 541  *
 542  *      SCR_COPY   sets the NO FLUSH option by default.
 543  *      SCR_COPY_F does not set this option.
 544  *
 545  *      For chips which do not support this option,
 546  *      sym_fw_bind_script() will remove this bit.
 547  *
 548  *-----------------------------------------------------------
 549  */
 550
 551 #define SCR_NO_FLUSH 0x01000000
 552
 553 #define SCR_COPY(n) (0xc0000000 | SCR_NO_FLUSH | (n))
 554 #define SCR_COPY_F(n) (0xc0000000 | (n))
 555
 556 /*-----------------------------------------------------------
 557  *
 558  *      Register move and binary operations
 559  *
 560  *-----------------------------------------------------------
 561  *
 562  *      SFBR_REG (reg, op, data)        reg  = SFBR op data
 563  *      << 0 >>
 564  *
 565  *      REG_SFBR (reg, op, data)        SFBR = reg op data
 566  *      << 0 >>
 567  *
 568  *      REG_REG  (reg, op, data)        reg  = reg op data
 569  *      << 0 >>
 570  *
 571  *-----------------------------------------------------------
 572  *
 573  *      On 825A, 875, 895 and 896 chips the content
 574  *      of SFBR register can be used as data (SCR_SFBR_DATA).
 575  *      The 896 has additionnal IO registers starting at
 576  *      offset 0x80. Bit 7 of register offset is stored in
 577  *      bit 7 of the SCRIPTS instruction first DWORD.
 578  *
 579  *-----------------------------------------------------------
 580  */
 581
 582 #define SCR_REG_OFS(ofs) ((((ofs) & 0x7f) << 16ul) + ((ofs) & 0x80))
 583
 584 #define SCR_SFBR_REG(reg,op,data) \
 585         (0x68000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
 586
 587 #define SCR_REG_SFBR(reg,op,data) \
 588         (0x70000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
 589
 590 #define SCR_REG_REG(reg,op,data) \
 591         (0x78000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
 592
 593
 594 #define      SCR_LOAD   0x00000000
 595 #define      SCR_SHL    0x01000000
 596 #define      SCR_OR     0x02000000
 597 #define      SCR_XOR    0x03000000
 598 #define      SCR_AND    0x04000000
 599 #define      SCR_SHR    0x05000000
 600 #define      SCR_ADD    0x06000000
 601 #define      SCR_ADDC   0x07000000
 602
 603 #define      SCR_SFBR_DATA   (0x00800000>>8ul)  /* Use SFBR as data */
 604
 605 /*-----------------------------------------------------------
 606  *
 607  *      FROM_REG (reg)            SFBR = reg
 608  *      << 0 >>
 609  *
 610  *      TO_REG   (reg)            reg  = SFBR
 611  *      << 0 >>
 612  *
 613  *      LOAD_REG (reg, data)      reg  = <data>
 614  *      << 0 >>
 615  *
 616  *      LOAD_SFBR(data)           SFBR = <data>
 617  *      << 0 >>
 618  *
 619  *-----------------------------------------------------------
 620  */
 621
 622 #define SCR_FROM_REG(reg) \
 623         SCR_REG_SFBR(reg,SCR_OR,0)
 624
 625 #define SCR_TO_REG(reg) \
 626         SCR_SFBR_REG(reg,SCR_OR,0)
 627
 628 #define SCR_LOAD_REG(reg,data) \
 629         SCR_REG_REG(reg,SCR_LOAD,data)
 630
 631 #define SCR_LOAD_SFBR(data) \
 632         (SCR_REG_SFBR (gpreg, SCR_LOAD, data))
 633
 634 /*-----------------------------------------------------------
 635  *
 636  *      LOAD  from memory   to register.
 637  *      STORE from register to memory.
 638  *
 639  *      Only supported by 810A, 860, 825A, 875, 895 and 896.
 640  *
 641  *-----------------------------------------------------------
 642  *
 643  *      LOAD_ABS (LEN)
 644  *      <<start address>>
 645  *
 646  *      LOAD_REL (LEN)        (DSA relative)
 647  *      <<dsa_offset>>
 648  *
 649  *-----------------------------------------------------------
 650  */
 651
 652 #define SCR_REG_OFS2(ofs) (((ofs) & 0xff) << 16ul)
 653 #define SCR_NO_FLUSH2   0x02000000
 654 #define SCR_DSA_REL2    0x10000000
 655
 656 #define SCR_LOAD_R(reg, how, n) \
 657         (0xe1000000 | how | (SCR_REG_OFS2(REG(reg))) | (n))
 658
 659 #define SCR_STORE_R(reg, how, n) \
 660         (0xe0000000 | how | (SCR_REG_OFS2(REG(reg))) | (n))
 661
 662 #define SCR_LOAD_ABS(reg, n)    SCR_LOAD_R(reg, SCR_NO_FLUSH2, n)
 663 #define SCR_LOAD_REL(reg, n)    SCR_LOAD_R(reg, SCR_NO_FLUSH2|SCR_DSA_REL2, n)
 664 #define SCR_LOAD_ABS_F(reg, n)  SCR_LOAD_R(reg, 0, n)
 665 #define SCR_LOAD_REL_F(reg, n)  SCR_LOAD_R(reg, SCR_DSA_REL2, n)
 666
 667 #define SCR_STORE_ABS(reg, n)   SCR_STORE_R(reg, SCR_NO_FLUSH2, n)
 668 #define SCR_STORE_REL(reg, n)   SCR_STORE_R(reg, SCR_NO_FLUSH2|SCR_DSA_REL2,n)
 669 #define SCR_STORE_ABS_F(reg, n) SCR_STORE_R(reg, 0, n)
 670 #define SCR_STORE_REL_F(reg, n) SCR_STORE_R(reg, SCR_DSA_REL2, n)
 671
 672
 673 /*-----------------------------------------------------------
 674  *
 675  *      Waiting for Disconnect or Reselect
 676  *
 677  *-----------------------------------------------------------
 678  *
 679  *      JUMP            [ | IFTRUE/IFFALSE ( ... ) ]
 680  *      <<address>>
 681  *
 682  *      JUMPR           [ | IFTRUE/IFFALSE ( ... ) ]
 683  *      <<distance>>
 684  *
 685  *      CALL            [ | IFTRUE/IFFALSE ( ... ) ]
 686  *      <<address>>
 687  *
 688  *      CALLR           [ | IFTRUE/IFFALSE ( ... ) ]
 689  *      <<distance>>
 690  *
 691  *      RETURN          [ | IFTRUE/IFFALSE ( ... ) ]
 692  *      <<dummy>>
 693  *
 694  *      INT             [ | IFTRUE/IFFALSE ( ... ) ]
 695  *      <<ident>>
 696  *
 697  *      INT_FLY         [ | IFTRUE/IFFALSE ( ... ) ]
 698  *      <<ident>>
 699  *
 700  *      Conditions:
 701  *           WHEN (phase)
 702  *           IF   (phase)
 703  *           CARRYSET
 704  *           DATA (data, mask)
 705  *
 706  *-----------------------------------------------------------
 707  */
 708
 709 #define SCR_NO_OP       0x80000000
 710 #define SCR_JUMP        0x80080000
 711 #define SCR_JUMP64      0x80480000
 712 #define SCR_JUMPR       0x80880000
 713 #define SCR_CALL        0x88080000
 714 #define SCR_CALLR       0x88880000
 715 #define SCR_RETURN      0x90080000
 716 #define SCR_INT         0x98080000
 717 #define SCR_INT_FLY     0x98180000
 718
 719 #define IFFALSE(arg)   (0x00080000 | (arg))
 720 #define IFTRUE(arg)    (0x00000000 | (arg))
 721
 722 #define WHEN(phase)    (0x00030000 | (phase))
 723 #define IF(phase)      (0x00020000 | (phase))
 724
 725 #define DATA(D)        (0x00040000 | ((D) & 0xff))
 726 #define MASK(D,M)      (0x00040000 | (((M ^ 0xff) & 0xff) << 8ul)|((D) & 0xff))
 727
 728 #define CARRYSET       (0x00200000)
 729
 730 /*-----------------------------------------------------------
 731  *
 732  *      SCSI  constants.
 733  *
 734  *-----------------------------------------------------------
 735  */
 736
 737 /*
 738  *      Messages
 739  */
 740
 741 #define M_COMPLETE      COMMAND_COMPLETE
 742 #define M_EXTENDED      EXTENDED_MESSAGE
 743 #define M_SAVE_DP       SAVE_POINTERS
 744 #define M_RESTORE_DP    RESTORE_POINTERS
 745 #define M_DISCONNECT    DISCONNECT
 746 #define M_ID_ERROR      INITIATOR_ERROR
 747 #define M_ABORT         ABORT_TASK_SET
 748 #define M_REJECT        MESSAGE_REJECT
 749 #define M_NOOP          NOP
 750 #define M_PARITY        MSG_PARITY_ERROR
 751 #define M_LCOMPLETE     LINKED_CMD_COMPLETE
 752 #define M_FCOMPLETE     LINKED_FLG_CMD_COMPLETE
 753 #define M_RESET         TARGET_RESET
 754 #define M_ABORT_TAG     ABORT_TASK
 755 #define M_CLEAR_QUEUE   CLEAR_TASK_SET
 756 #define M_INIT_REC      INITIATE_RECOVERY
 757 #define M_REL_REC       RELEASE_RECOVERY
 758 #define M_TERMINATE     (0x11)
 759 #define M_SIMPLE_TAG    SIMPLE_QUEUE_TAG
 760 #define M_HEAD_TAG      HEAD_OF_QUEUE_TAG
 761 #define M_ORDERED_TAG   ORDERED_QUEUE_TAG
 762 #define M_IGN_RESIDUE   IGNORE_WIDE_RESIDUE
 763
 764 #define M_X_MODIFY_DP   EXTENDED_MODIFY_DATA_POINTER
 765 #define M_X_SYNC_REQ    EXTENDED_SDTR
 766 #define M_X_WIDE_REQ    EXTENDED_WDTR
 767 #define M_X_PPR_REQ     EXTENDED_PPR
 768
 769 /*
 770  *      PPR protocol options
 771  */
 772 #define PPR_OPT_IU      (0x01)
 773 #define PPR_OPT_DT      (0x02)
 774 #define PPR_OPT_QAS     (0x04)
 775 #define PPR_OPT_MASK    (0x07)
 776
 777 /*
 778  *      Status
 779  */
 780
 781 #define S_GOOD          SAM_STAT_GOOD
 782 #define S_CHECK_COND    SAM_STAT_CHECK_CONDITION
 783 #define S_COND_MET      SAM_STAT_CONDITION_MET
 784 #define S_BUSY          SAM_STAT_BUSY
 785 #define S_INT           SAM_STAT_INTERMEDIATE
 786 #define S_INT_COND_MET  SAM_STAT_INTERMEDIATE_CONDITION_MET
 787 #define S_CONFLICT      SAM_STAT_RESERVATION_CONFLICT
 788 #define S_TERMINATED    SAM_STAT_COMMAND_TERMINATED
 789 #define S_QUEUE_FULL    SAM_STAT_TASK_SET_FULL
 790 #define S_ILLEGAL       (0xff)
 791
 792 #endif /* defined SYM_DEFS_H */