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Linux-2.6.12-rc2
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / scsi / sata_nv.c
blob69009f853a4917f54a88aa0c2cf3e6fb0428c8f7
1 /*
2 * sata_nv.c - NVIDIA nForce SATA
3 *
4 * Copyright 2004 NVIDIA Corp. All rights reserved.
5 * Copyright 2004 Andrew Chew
6 *
7 * The contents of this file are subject to the Open
8 * Software License version 1.1 that can be found at
9 * http://www.opensource.org/licenses/osl-1.1.txt and is included herein
10 * by reference.
11 *
12 * Alternatively, the contents of this file may be used under the terms
13 * of the GNU General Public License version 2 (the "GPL") as distributed
14 * in the kernel source COPYING file, in which case the provisions of
15 * the GPL are applicable instead of the above. If you wish to allow
16 * the use of your version of this file only under the terms of the
17 * GPL and not to allow others to use your version of this file under
18 * the OSL, indicate your decision by deleting the provisions above and
19 * replace them with the notice and other provisions required by the GPL.
20 * If you do not delete the provisions above, a recipient may use your
21 * version of this file under either the OSL or the GPL.
22 *
23 * 0.06
24 * - Added generic SATA support by using a pci_device_id that filters on
25 * the IDE storage class code.
26 *
27 * 0.03
28 * - Fixed a bug where the hotplug handlers for non-CK804/MCP04 were using
29 * mmio_base, which is only set for the CK804/MCP04 case.
30 *
31 * 0.02
32 * - Added support for CK804 SATA controller.
33 *
34 * 0.01
35 * - Initial revision.
36 */
37
38 #include <linux/config.h>
39 #include <linux/kernel.h>
40 #include <linux/module.h>
41 #include <linux/pci.h>
42 #include <linux/init.h>
43 #include <linux/blkdev.h>
44 #include <linux/delay.h>
45 #include <linux/interrupt.h>
46 #include "scsi.h"
47 #include <scsi/scsi_host.h>
48 #include <linux/libata.h>
49
50 #define DRV_NAME "sata_nv"
51 #define DRV_VERSION "0.6"
52
53 #define NV_PORTS 2
54 #define NV_PIO_MASK 0x1f
55 #define NV_MWDMA_MASK 0x07
56 #define NV_UDMA_MASK 0x7f
57 #define NV_PORT0_SCR_REG_OFFSET 0x00
58 #define NV_PORT1_SCR_REG_OFFSET 0x40
59
60 #define NV_INT_STATUS 0x10
61 #define NV_INT_STATUS_CK804 0x440
62 #define NV_INT_STATUS_PDEV_INT 0x01
63 #define NV_INT_STATUS_PDEV_PM 0x02
64 #define NV_INT_STATUS_PDEV_ADDED 0x04
65 #define NV_INT_STATUS_PDEV_REMOVED 0x08
66 #define NV_INT_STATUS_SDEV_INT 0x10
67 #define NV_INT_STATUS_SDEV_PM 0x20
68 #define NV_INT_STATUS_SDEV_ADDED 0x40
69 #define NV_INT_STATUS_SDEV_REMOVED 0x80
70 #define NV_INT_STATUS_PDEV_HOTPLUG (NV_INT_STATUS_PDEV_ADDED | \
71 NV_INT_STATUS_PDEV_REMOVED)
72 #define NV_INT_STATUS_SDEV_HOTPLUG (NV_INT_STATUS_SDEV_ADDED | \
73 NV_INT_STATUS_SDEV_REMOVED)
74 #define NV_INT_STATUS_HOTPLUG (NV_INT_STATUS_PDEV_HOTPLUG | \
75 NV_INT_STATUS_SDEV_HOTPLUG)
76
77 #define NV_INT_ENABLE 0x11
78 #define NV_INT_ENABLE_CK804 0x441
79 #define NV_INT_ENABLE_PDEV_MASK 0x01
80 #define NV_INT_ENABLE_PDEV_PM 0x02
81 #define NV_INT_ENABLE_PDEV_ADDED 0x04
82 #define NV_INT_ENABLE_PDEV_REMOVED 0x08
83 #define NV_INT_ENABLE_SDEV_MASK 0x10
84 #define NV_INT_ENABLE_SDEV_PM 0x20
85 #define NV_INT_ENABLE_SDEV_ADDED 0x40
86 #define NV_INT_ENABLE_SDEV_REMOVED 0x80
87 #define NV_INT_ENABLE_PDEV_HOTPLUG (NV_INT_ENABLE_PDEV_ADDED | \
88 NV_INT_ENABLE_PDEV_REMOVED)
89 #define NV_INT_ENABLE_SDEV_HOTPLUG (NV_INT_ENABLE_SDEV_ADDED | \
90 NV_INT_ENABLE_SDEV_REMOVED)
91 #define NV_INT_ENABLE_HOTPLUG (NV_INT_ENABLE_PDEV_HOTPLUG | \
92 NV_INT_ENABLE_SDEV_HOTPLUG)
93
94 #define NV_INT_CONFIG 0x12
95 #define NV_INT_CONFIG_METHD 0x01 // 0 = INT, 1 = SMI
96
97 // For PCI config register 20
98 #define NV_MCP_SATA_CFG_20 0x50
99 #define NV_MCP_SATA_CFG_20_SATA_SPACE_EN 0x04
100
101 static int nv_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
102 static irqreturn_t nv_interrupt (int irq, void *dev_instance,
103 struct pt_regs *regs);
104 static u32 nv_scr_read (struct ata_port *ap, unsigned int sc_reg);
105 static void nv_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
106 static void nv_host_stop (struct ata_host_set *host_set);
107 static void nv_enable_hotplug(struct ata_probe_ent *probe_ent);
108 static void nv_disable_hotplug(struct ata_host_set *host_set);
109 static void nv_check_hotplug(struct ata_host_set *host_set);
110 static void nv_enable_hotplug_ck804(struct ata_probe_ent *probe_ent);
111 static void nv_disable_hotplug_ck804(struct ata_host_set *host_set);
112 static void nv_check_hotplug_ck804(struct ata_host_set *host_set);
113
114 enum nv_host_type
115 {
116 GENERIC,
117 NFORCE2,
118 NFORCE3,
119 CK804
120 };
121
122 static struct pci_device_id nv_pci_tbl[] = {
123 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_SATA,
124 PCI_ANY_ID, PCI_ANY_ID, 0, 0, NFORCE2 },
125 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA,
126 PCI_ANY_ID, PCI_ANY_ID, 0, 0, NFORCE3 },
127 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA2,
128 PCI_ANY_ID, PCI_ANY_ID, 0, 0, NFORCE3 },
129 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA,
130 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CK804 },
131 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA2,
132 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CK804 },
133 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA,
134 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CK804 },
135 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA2,
136 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CK804 },
137 { PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
138 PCI_ANY_ID, PCI_ANY_ID,
139 PCI_CLASS_STORAGE_IDE<<8, 0xffff00, GENERIC },
140 { 0, } /* terminate list */
141 };
142
143 #define NV_HOST_FLAGS_SCR_MMIO 0x00000001
144
145 struct nv_host_desc
146 {
147 enum nv_host_type host_type;
148 void (*enable_hotplug)(struct ata_probe_ent *probe_ent);
149 void (*disable_hotplug)(struct ata_host_set *host_set);
150 void (*check_hotplug)(struct ata_host_set *host_set);
151
152 };
153 static struct nv_host_desc nv_device_tbl[] = {
154 {
155 .host_type = GENERIC,
156 .enable_hotplug = NULL,
157 .disable_hotplug= NULL,
158 .check_hotplug = NULL,
159 },
160 {
161 .host_type = NFORCE2,
162 .enable_hotplug = nv_enable_hotplug,
163 .disable_hotplug= nv_disable_hotplug,
164 .check_hotplug = nv_check_hotplug,
165 },
166 {
167 .host_type = NFORCE3,
168 .enable_hotplug = nv_enable_hotplug,
169 .disable_hotplug= nv_disable_hotplug,
170 .check_hotplug = nv_check_hotplug,
171 },
172 { .host_type = CK804,
173 .enable_hotplug = nv_enable_hotplug_ck804,
174 .disable_hotplug= nv_disable_hotplug_ck804,
175 .check_hotplug = nv_check_hotplug_ck804,
176 },
177 };
178
179 struct nv_host
180 {
181 struct nv_host_desc *host_desc;
182 unsigned long host_flags;
183 };
184
185 static struct pci_driver nv_pci_driver = {
186 .name = DRV_NAME,
187 .id_table = nv_pci_tbl,
188 .probe = nv_init_one,
189 .remove = ata_pci_remove_one,
190 };
191
192 static Scsi_Host_Template nv_sht = {
193 .module = THIS_MODULE,
194 .name = DRV_NAME,
195 .ioctl = ata_scsi_ioctl,
196 .queuecommand = ata_scsi_queuecmd,
197 .eh_strategy_handler = ata_scsi_error,
198 .can_queue = ATA_DEF_QUEUE,
199 .this_id = ATA_SHT_THIS_ID,
200 .sg_tablesize = LIBATA_MAX_PRD,
201 .max_sectors = ATA_MAX_SECTORS,
202 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
203 .emulated = ATA_SHT_EMULATED,
204 .use_clustering = ATA_SHT_USE_CLUSTERING,
205 .proc_name = DRV_NAME,
206 .dma_boundary = ATA_DMA_BOUNDARY,
207 .slave_configure = ata_scsi_slave_config,
208 .bios_param = ata_std_bios_param,
209 .ordered_flush = 1,
210 };
211
212 static struct ata_port_operations nv_ops = {
213 .port_disable = ata_port_disable,
214 .tf_load = ata_tf_load,
215 .tf_read = ata_tf_read,
216 .exec_command = ata_exec_command,
217 .check_status = ata_check_status,
218 .dev_select = ata_std_dev_select,
219 .phy_reset = sata_phy_reset,
220 .bmdma_setup = ata_bmdma_setup,
221 .bmdma_start = ata_bmdma_start,
222 .bmdma_stop = ata_bmdma_stop,
223 .bmdma_status = ata_bmdma_status,
224 .qc_prep = ata_qc_prep,
225 .qc_issue = ata_qc_issue_prot,
226 .eng_timeout = ata_eng_timeout,
227 .irq_handler = nv_interrupt,
228 .irq_clear = ata_bmdma_irq_clear,
229 .scr_read = nv_scr_read,
230 .scr_write = nv_scr_write,
231 .port_start = ata_port_start,
232 .port_stop = ata_port_stop,
233 .host_stop = nv_host_stop,
234 };
235
236 /* FIXME: The hardware provides the necessary SATA PHY controls
237 * to support ATA_FLAG_SATA_RESET. However, it is currently
238 * necessary to disable that flag, to solve misdetection problems.
239 * See http://bugme.osdl.org/show_bug.cgi?id=3352 for more info.
240 *
241 * This problem really needs to be investigated further. But in the
242 * meantime, we avoid ATA_FLAG_SATA_RESET to get people working.
243 */
244 static struct ata_port_info nv_port_info = {
245 .sht = &nv_sht,
246 .host_flags = ATA_FLAG_SATA |
247 /* ATA_FLAG_SATA_RESET | */
248 ATA_FLAG_SRST |
249 ATA_FLAG_NO_LEGACY,
250 .pio_mask = NV_PIO_MASK,
251 .mwdma_mask = NV_MWDMA_MASK,
252 .udma_mask = NV_UDMA_MASK,
253 .port_ops = &nv_ops,
254 };
255
256 MODULE_AUTHOR("NVIDIA");
257 MODULE_DESCRIPTION("low-level driver for NVIDIA nForce SATA controller");
258 MODULE_LICENSE("GPL");
259 MODULE_DEVICE_TABLE(pci, nv_pci_tbl);
260 MODULE_VERSION(DRV_VERSION);
261
262 static irqreturn_t nv_interrupt (int irq, void *dev_instance,
263 struct pt_regs *regs)
264 {
265 struct ata_host_set *host_set = dev_instance;
266 struct nv_host *host = host_set->private_data;
267 unsigned int i;
268 unsigned int handled = 0;
269 unsigned long flags;
270
271 spin_lock_irqsave(&host_set->lock, flags);
272
273 for (i = 0; i < host_set->n_ports; i++) {
274 struct ata_port *ap;
275
276 ap = host_set->ports[i];
277 if (ap && (!(ap->flags & ATA_FLAG_PORT_DISABLED))) {
278 struct ata_queued_cmd *qc;
279
280 qc = ata_qc_from_tag(ap, ap->active_tag);
281 if (qc && (!(qc->tf.ctl & ATA_NIEN)))
282 handled += ata_host_intr(ap, qc);
283 }
284
285 }
286
287 if (host->host_desc->check_hotplug)
288 host->host_desc->check_hotplug(host_set);
289
290 spin_unlock_irqrestore(&host_set->lock, flags);
291
292 return IRQ_RETVAL(handled);
293 }
294
295 static u32 nv_scr_read (struct ata_port *ap, unsigned int sc_reg)
296 {
297 struct ata_host_set *host_set = ap->host_set;
298 struct nv_host *host = host_set->private_data;
299
300 if (sc_reg > SCR_CONTROL)
301 return 0xffffffffU;
302
303 if (host->host_flags & NV_HOST_FLAGS_SCR_MMIO)
304 return readl((void*)ap->ioaddr.scr_addr + (sc_reg * 4));
305 else
306 return inl(ap->ioaddr.scr_addr + (sc_reg * 4));
307 }
308
309 static void nv_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
310 {
311 struct ata_host_set *host_set = ap->host_set;
312 struct nv_host *host = host_set->private_data;
313
314 if (sc_reg > SCR_CONTROL)
315 return;
316
317 if (host->host_flags & NV_HOST_FLAGS_SCR_MMIO)
318 writel(val, (void*)ap->ioaddr.scr_addr + (sc_reg * 4));
319 else
320 outl(val, ap->ioaddr.scr_addr + (sc_reg * 4));
321 }
322
323 static void nv_host_stop (struct ata_host_set *host_set)
324 {
325 struct nv_host *host = host_set->private_data;
326
327 // Disable hotplug event interrupts.
328 if (host->host_desc->disable_hotplug)
329 host->host_desc->disable_hotplug(host_set);
330
331 kfree(host);
332 }
333
334 static int nv_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
335 {
336 static int printed_version = 0;
337 struct nv_host *host;
338 struct ata_port_info *ppi;
339 struct ata_probe_ent *probe_ent;
340 int pci_dev_busy = 0;
341 int rc;
342 u32 bar;
343
344 // Make sure this is a SATA controller by counting the number of bars
345 // (NVIDIA SATA controllers will always have six bars). Otherwise,
346 // it's an IDE controller and we ignore it.
347 for (bar=0; bar<6; bar++)
348 if (pci_resource_start(pdev, bar) == 0)
349 return -ENODEV;
350
351 if (!printed_version++)
352 printk(KERN_DEBUG DRV_NAME " version " DRV_VERSION "\n");
353
354 rc = pci_enable_device(pdev);
355 if (rc)
356 goto err_out;
357
358 rc = pci_request_regions(pdev, DRV_NAME);
359 if (rc) {
360 pci_dev_busy = 1;
361 goto err_out_disable;
362 }
363
364 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
365 if (rc)
366 goto err_out_regions;
367 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
368 if (rc)
369 goto err_out_regions;
370
371 rc = -ENOMEM;
372
373 ppi = &nv_port_info;
374 probe_ent = ata_pci_init_native_mode(pdev, &ppi);
375 if (!probe_ent)
376 goto err_out_regions;
377
378 host = kmalloc(sizeof(struct nv_host), GFP_KERNEL);
379 if (!host)
380 goto err_out_free_ent;
381
382 memset(host, 0, sizeof(struct nv_host));
383 host->host_desc = &nv_device_tbl[ent->driver_data];
384
385 probe_ent->private_data = host;
386
387 if (pci_resource_flags(pdev, 5) & IORESOURCE_MEM)
388 host->host_flags |= NV_HOST_FLAGS_SCR_MMIO;
389
390 if (host->host_flags & NV_HOST_FLAGS_SCR_MMIO) {
391 unsigned long base;
392
393 probe_ent->mmio_base = ioremap(pci_resource_start(pdev, 5),
394 pci_resource_len(pdev, 5));
395 if (probe_ent->mmio_base == NULL) {
396 rc = -EIO;
397 goto err_out_free_host;
398 }
399
400 base = (unsigned long)probe_ent->mmio_base;
401
402 probe_ent->port[0].scr_addr =
403 base + NV_PORT0_SCR_REG_OFFSET;
404 probe_ent->port[1].scr_addr =
405 base + NV_PORT1_SCR_REG_OFFSET;
406 } else {
407
408 probe_ent->port[0].scr_addr =
409 pci_resource_start(pdev, 5) | NV_PORT0_SCR_REG_OFFSET;
410 probe_ent->port[1].scr_addr =
411 pci_resource_start(pdev, 5) | NV_PORT1_SCR_REG_OFFSET;
412 }
413
414 pci_set_master(pdev);
415
416 rc = ata_device_add(probe_ent);
417 if (rc != NV_PORTS)
418 goto err_out_iounmap;
419
420 // Enable hotplug event interrupts.
421 if (host->host_desc->enable_hotplug)
422 host->host_desc->enable_hotplug(probe_ent);
423
424 kfree(probe_ent);
425
426 return 0;
427
428 err_out_iounmap:
429 if (host->host_flags & NV_HOST_FLAGS_SCR_MMIO)
430 iounmap(probe_ent->mmio_base);
431 err_out_free_host:
432 kfree(host);
433 err_out_free_ent:
434 kfree(probe_ent);
435 err_out_regions:
436 pci_release_regions(pdev);
437 err_out_disable:
438 if (!pci_dev_busy)
439 pci_disable_device(pdev);
440 err_out:
441 return rc;
442 }
443
444 static void nv_enable_hotplug(struct ata_probe_ent *probe_ent)
445 {
446 u8 intr_mask;
447
448 outb(NV_INT_STATUS_HOTPLUG,
449 probe_ent->port[0].scr_addr + NV_INT_STATUS);
450
451 intr_mask = inb(probe_ent->port[0].scr_addr + NV_INT_ENABLE);
452 intr_mask |= NV_INT_ENABLE_HOTPLUG;
453
454 outb(intr_mask, probe_ent->port[0].scr_addr + NV_INT_ENABLE);
455 }
456
457 static void nv_disable_hotplug(struct ata_host_set *host_set)
458 {
459 u8 intr_mask;
460
461 intr_mask = inb(host_set->ports[0]->ioaddr.scr_addr + NV_INT_ENABLE);
462
463 intr_mask &= ~(NV_INT_ENABLE_HOTPLUG);
464
465 outb(intr_mask, host_set->ports[0]->ioaddr.scr_addr + NV_INT_ENABLE);
466 }
467
468 static void nv_check_hotplug(struct ata_host_set *host_set)
469 {
470 u8 intr_status;
471
472 intr_status = inb(host_set->ports[0]->ioaddr.scr_addr + NV_INT_STATUS);
473
474 // Clear interrupt status.
475 outb(0xff, host_set->ports[0]->ioaddr.scr_addr + NV_INT_STATUS);
476
477 if (intr_status & NV_INT_STATUS_HOTPLUG) {
478 if (intr_status & NV_INT_STATUS_PDEV_ADDED)
479 printk(KERN_WARNING "nv_sata: "
480 "Primary device added\n");
481
482 if (intr_status & NV_INT_STATUS_PDEV_REMOVED)
483 printk(KERN_WARNING "nv_sata: "
484 "Primary device removed\n");
485
486 if (intr_status & NV_INT_STATUS_SDEV_ADDED)
487 printk(KERN_WARNING "nv_sata: "
488 "Secondary device added\n");
489
490 if (intr_status & NV_INT_STATUS_SDEV_REMOVED)
491 printk(KERN_WARNING "nv_sata: "
492 "Secondary device removed\n");
493 }
494 }
495
496 static void nv_enable_hotplug_ck804(struct ata_probe_ent *probe_ent)
497 {
498 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
499 u8 intr_mask;
500 u8 regval;
501
502 pci_read_config_byte(pdev, NV_MCP_SATA_CFG_20, &regval);
503 regval |= NV_MCP_SATA_CFG_20_SATA_SPACE_EN;
504 pci_write_config_byte(pdev, NV_MCP_SATA_CFG_20, regval);
505
506 writeb(NV_INT_STATUS_HOTPLUG, probe_ent->mmio_base + NV_INT_STATUS_CK804);
507
508 intr_mask = readb(probe_ent->mmio_base + NV_INT_ENABLE_CK804);
509 intr_mask |= NV_INT_ENABLE_HOTPLUG;
510
511 writeb(intr_mask, probe_ent->mmio_base + NV_INT_ENABLE_CK804);
512 }
513
514 static void nv_disable_hotplug_ck804(struct ata_host_set *host_set)
515 {
516 struct pci_dev *pdev = to_pci_dev(host_set->dev);
517 u8 intr_mask;
518 u8 regval;
519
520 intr_mask = readb(host_set->mmio_base + NV_INT_ENABLE_CK804);
521
522 intr_mask &= ~(NV_INT_ENABLE_HOTPLUG);
523
524 writeb(intr_mask, host_set->mmio_base + NV_INT_ENABLE_CK804);
525
526 pci_read_config_byte(pdev, NV_MCP_SATA_CFG_20, &regval);
527 regval &= ~NV_MCP_SATA_CFG_20_SATA_SPACE_EN;
528 pci_write_config_byte(pdev, NV_MCP_SATA_CFG_20, regval);
529 }
530
531 static void nv_check_hotplug_ck804(struct ata_host_set *host_set)
532 {
533 u8 intr_status;
534
535 intr_status = readb(host_set->mmio_base + NV_INT_STATUS_CK804);
536
537 // Clear interrupt status.
538 writeb(0xff, host_set->mmio_base + NV_INT_STATUS_CK804);
539
540 if (intr_status & NV_INT_STATUS_HOTPLUG) {
541 if (intr_status & NV_INT_STATUS_PDEV_ADDED)
542 printk(KERN_WARNING "nv_sata: "
543 "Primary device added\n");
544
545 if (intr_status & NV_INT_STATUS_PDEV_REMOVED)
546 printk(KERN_WARNING "nv_sata: "
547 "Primary device removed\n");
548
549 if (intr_status & NV_INT_STATUS_SDEV_ADDED)
550 printk(KERN_WARNING "nv_sata: "
551 "Secondary device added\n");
552
553 if (intr_status & NV_INT_STATUS_SDEV_REMOVED)
554 printk(KERN_WARNING "nv_sata: "
555 "Secondary device removed\n");
556 }
557 }
558
559 static int __init nv_init(void)
560 {
561 return pci_module_init(&nv_pci_driver);
562 }
563
564 static void __exit nv_exit(void)
565 {
566 pci_unregister_driver(&nv_pci_driver);
567 }
568
569 module_init(nv_init);
570 module_exit(nv_exit);
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