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Linux-2.6.12-rc2
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / sbus / char / bpp.c
blob8f0f46907a81a11788a1f321970922ab5aa78350
1 /*
2 * drivers/sbus/char/bpp.c
3 *
4 * Copyright (c) 1995 Picture Elements
5 * Stephen Williams (steve@icarus.com)
6 * Gus Baldauf (gbaldauf@ix.netcom.com)
7 *
8 * Linux/SPARC port by Peter Zaitcev.
9 * Integration into SPARC tree by Tom Dyas.
10 */
11
12
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/fs.h>
16 #include <linux/errno.h>
17 #include <linux/sched.h>
18 #include <linux/smp_lock.h>
19 #include <linux/spinlock.h>
20 #include <linux/timer.h>
21 #include <linux/ioport.h>
22 #include <linux/major.h>
23 #include <linux/devfs_fs_kernel.h>
24
25 #include <asm/uaccess.h>
26 #include <asm/io.h>
27
28 #if defined(__i386__)
29 # include <asm/system.h>
30 #endif
31
32 #if defined(__sparc__)
33 # include <linux/init.h>
34 # include <linux/delay.h> /* udelay() */
35
36 # include <asm/oplib.h> /* OpenProm Library */
37 # include <asm/sbus.h>
38 #endif
39
40 #include <asm/bpp.h>
41
42 #define BPP_PROBE_CODE 0x55
43 #define BPP_DELAY 100
44
45 static const unsigned BPP_MAJOR = LP_MAJOR;
46 static const char* dev_name = "bpp";
47
48 /* When switching from compatibility to a mode where I can read, try
49 the following mode first. */
50
51 /* const unsigned char DEFAULT_ECP = 0x10; */
52 static const unsigned char DEFAULT_ECP = 0x30;
53 static const unsigned char DEFAULT_NIBBLE = 0x00;
54
55 /*
56 * These are 1284 time constraints, in units of jiffies.
57 */
58
59 static const unsigned long TIME_PSetup = 1;
60 static const unsigned long TIME_PResponse = 6;
61 static const unsigned long TIME_IDLE_LIMIT = 2000;
62
63 /*
64 * One instance per supported subdevice...
65 */
66 # define BPP_NO 3
67
68 enum IEEE_Mode { COMPATIBILITY, NIBBLE, ECP, ECP_RLE, EPP };
69
70 struct inst {
71 unsigned present : 1; /* True if the hardware exists */
72 unsigned enhanced : 1; /* True if the hardware in "enhanced" */
73 unsigned opened : 1; /* True if the device is opened already */
74 unsigned run_flag : 1; /* True if waiting for a repeate byte */
75
76 unsigned char direction; /* 0 --> out, 0x20 --> IN */
77 unsigned char pp_state; /* State of host controlled pins. */
78 enum IEEE_Mode mode;
79
80 unsigned char run_length;
81 unsigned char repeat_byte;
82
83 /* These members manage timeouts for programmed delays */
84 wait_queue_head_t wait_queue;
85 struct timer_list timer_list;
86 };
87
88 static struct inst instances[BPP_NO];
89
90 #if defined(__i386__)
91
92 static const unsigned short base_addrs[BPP_NO] = { 0x278, 0x378, 0x3bc };
93
94 /*
95 * These are for data access.
96 * Control lines accesses are hidden in set_bits() and get_bits().
97 * The exception is the probe procedure, which is system-dependent.
98 */
99 #define bpp_outb_p(data, base) outb_p((data), (base))
100 #define bpp_inb(base) inb(base)
101 #define bpp_inb_p(base) inb_p(base)
102
103 /*
104 * This method takes the pin values mask and sets the hardware pins to
105 * the requested value: 1 == high voltage, 0 == low voltage. This
106 * burries the annoying PC bit inversion and preserves the direction
107 * flag.
108 */
109 static void set_pins(unsigned short pins, unsigned minor)
110 {
111 unsigned char bits = instances[minor].direction; /* == 0x20 */
112
113 if (! (pins & BPP_PP_nStrobe)) bits |= 1;
114 if (! (pins & BPP_PP_nAutoFd)) bits |= 2;
115 if ( pins & BPP_PP_nInit) bits |= 4;
116 if (! (pins & BPP_PP_nSelectIn)) bits |= 8;
117
118 instances[minor].pp_state = bits;
119
120 outb_p(bits, base_addrs[minor]+2);
121 }
122
123 static unsigned short get_pins(unsigned minor)
124 {
125 unsigned short bits = 0;
126
127 unsigned value = instances[minor].pp_state;
128 if (! (value & 0x01)) bits |= BPP_PP_nStrobe;
129 if (! (value & 0x02)) bits |= BPP_PP_nAutoFd;
130 if (value & 0x04) bits |= BPP_PP_nInit;
131 if (! (value & 0x08)) bits |= BPP_PP_nSelectIn;
132
133 value = inb_p(base_addrs[minor]+1);
134 if (value & 0x08) bits |= BPP_GP_nFault;
135 if (value & 0x10) bits |= BPP_GP_Select;
136 if (value & 0x20) bits |= BPP_GP_PError;
137 if (value & 0x40) bits |= BPP_GP_nAck;
138 if (! (value & 0x80)) bits |= BPP_GP_Busy;
139
140 return bits;
141 }
142
143 #endif /* __i386__ */
144
145 #if defined(__sparc__)
146
147 /*
148 * Register block
149 */
150 /* DMA registers */
151 #define BPP_CSR 0x00
152 #define BPP_ADDR 0x04
153 #define BPP_BCNT 0x08
154 #define BPP_TST_CSR 0x0C
155 /* Parallel Port registers */
156 #define BPP_HCR 0x10
157 #define BPP_OCR 0x12
158 #define BPP_DR 0x14
159 #define BPP_TCR 0x15
160 #define BPP_OR 0x16
161 #define BPP_IR 0x17
162 #define BPP_ICR 0x18
163 #define BPP_SIZE 0x1A
164
165 /* BPP_CSR. Bits of type RW1 are cleared with writting '1'. */
166 #define P_DEV_ID_MASK 0xf0000000 /* R */
167 #define P_DEV_ID_ZEBRA 0x40000000
168 #define P_DEV_ID_L64854 0xa0000000 /* == NCR 89C100+89C105. Pity. */
169 #define P_NA_LOADED 0x08000000 /* R NA wirtten but was not used */
170 #define P_A_LOADED 0x04000000 /* R */
171 #define P_DMA_ON 0x02000000 /* R DMA is not disabled */
172 #define P_EN_NEXT 0x01000000 /* RW */
173 #define P_TCI_DIS 0x00800000 /* RW TCI forbidden from interrupts */
174 #define P_DIAG 0x00100000 /* RW Disables draining and resetting
175 of P-FIFO on loading of P_ADDR*/
176 #define P_BURST_SIZE 0x000c0000 /* RW SBus burst size */
177 #define P_BURST_8 0x00000000
178 #define P_BURST_4 0x00040000
179 #define P_BURST_1 0x00080000 /* "No burst" write */
180 #define P_TC 0x00004000 /* RW1 Term Count, can be cleared when
181 P_EN_NEXT=1 */
182 #define P_EN_CNT 0x00002000 /* RW */
183 #define P_EN_DMA 0x00000200 /* RW */
184 #define P_WRITE 0x00000100 /* R DMA dir, 1=to ram, 0=to port */
185 #define P_RESET 0x00000080 /* RW */
186 #define P_SLAVE_ERR 0x00000040 /* RW1 Access size error */
187 #define P_INVALIDATE 0x00000020 /* W Drop P-FIFO */
188 #define P_INT_EN 0x00000010 /* RW OK to P_INT_PEND||P_ERR_PEND */
189 #define P_DRAINING 0x0000000c /* R P-FIFO is draining to memory */
190 #define P_ERR_PEND 0x00000002 /* R */
191 #define P_INT_PEND 0x00000001 /* R */
192
193 /* BPP_HCR. Time is in increments of SBus clock. */
194 #define P_HCR_TEST 0x8000 /* Allows buried counters to be read */
195 #define P_HCR_DSW 0x7f00 /* Data strobe width (in ticks) */
196 #define P_HCR_DDS 0x007f /* Data setup before strobe (in ticks) */
197
198 /* BPP_OCR. */
199 #define P_OCR_MEM_CLR 0x8000
200 #define P_OCR_DATA_SRC 0x4000 /* ) */
201 #define P_OCR_DS_DSEL 0x2000 /* ) Bidirectional */
202 #define P_OCR_BUSY_DSEL 0x1000 /* ) selects */
203 #define P_OCR_ACK_DSEL 0x0800 /* ) */
204 #define P_OCR_EN_DIAG 0x0400
205 #define P_OCR_BUSY_OP 0x0200 /* Busy operation */
206 #define P_OCR_ACK_OP 0x0100 /* Ack operation */
207 #define P_OCR_SRST 0x0080 /* Reset state machines. Not selfcleaning. */
208 #define P_OCR_IDLE 0x0008 /* PP data transfer state machine is idle */
209 #define P_OCR_V_ILCK 0x0002 /* Versatec faded. Zebra only. */
210 #define P_OCR_EN_VER 0x0001 /* Enable Versatec (0 - enable). Zebra only. */
211
212 /* BPP_TCR */
213 #define P_TCR_DIR 0x08
214 #define P_TCR_BUSY 0x04
215 #define P_TCR_ACK 0x02
216 #define P_TCR_DS 0x01 /* Strobe */
217
218 /* BPP_OR */
219 #define P_OR_V3 0x20 /* ) */
220 #define P_OR_V2 0x10 /* ) on Zebra only */
221 #define P_OR_V1 0x08 /* ) */
222 #define P_OR_INIT 0x04
223 #define P_OR_AFXN 0x02 /* Auto Feed */
224 #define P_OR_SLCT_IN 0x01
225
226 /* BPP_IR */
227 #define P_IR_PE 0x04
228 #define P_IR_SLCT 0x02
229 #define P_IR_ERR 0x01
230
231 /* BPP_ICR */
232 #define P_DS_IRQ 0x8000 /* RW1 */
233 #define P_ACK_IRQ 0x4000 /* RW1 */
234 #define P_BUSY_IRQ 0x2000 /* RW1 */
235 #define P_PE_IRQ 0x1000 /* RW1 */
236 #define P_SLCT_IRQ 0x0800 /* RW1 */
237 #define P_ERR_IRQ 0x0400 /* RW1 */
238 #define P_DS_IRQ_EN 0x0200 /* RW Always on rising edge */
239 #define P_ACK_IRQ_EN 0x0100 /* RW Always on rising edge */
240 #define P_BUSY_IRP 0x0080 /* RW 1= rising edge */
241 #define P_BUSY_IRQ_EN 0x0040 /* RW */
242 #define P_PE_IRP 0x0020 /* RW 1= rising edge */
243 #define P_PE_IRQ_EN 0x0010 /* RW */
244 #define P_SLCT_IRP 0x0008 /* RW 1= rising edge */
245 #define P_SLCT_IRQ_EN 0x0004 /* RW */
246 #define P_ERR_IRP 0x0002 /* RW1 1= rising edge */
247 #define P_ERR_IRQ_EN 0x0001 /* RW */
248
249 static void __iomem *base_addrs[BPP_NO];
250
251 #define bpp_outb_p(data, base) sbus_writeb(data, (base) + BPP_DR)
252 #define bpp_inb_p(base) sbus_readb((base) + BPP_DR)
253 #define bpp_inb(base) sbus_readb((base) + BPP_DR)
254
255 static void set_pins(unsigned short pins, unsigned minor)
256 {
257 void __iomem *base = base_addrs[minor];
258 unsigned char bits_tcr = 0, bits_or = 0;
259
260 if (instances[minor].direction & 0x20) bits_tcr |= P_TCR_DIR;
261 if ( pins & BPP_PP_nStrobe) bits_tcr |= P_TCR_DS;
262
263 if ( pins & BPP_PP_nAutoFd) bits_or |= P_OR_AFXN;
264 if (! (pins & BPP_PP_nInit)) bits_or |= P_OR_INIT;
265 if (! (pins & BPP_PP_nSelectIn)) bits_or |= P_OR_SLCT_IN;
266
267 sbus_writeb(bits_or, base + BPP_OR);
268 sbus_writeb(bits_tcr, base + BPP_TCR);
269 }
270
271 /*
272 * i386 people read output pins from a software image.
273 * We may get them back from hardware.
274 * Again, inversion of pins must he buried here.
275 */
276 static unsigned short get_pins(unsigned minor)
277 {
278 void __iomem *base = base_addrs[minor];
279 unsigned short bits = 0;
280 unsigned value_tcr = sbus_readb(base + BPP_TCR);
281 unsigned value_ir = sbus_readb(base + BPP_IR);
282 unsigned value_or = sbus_readb(base + BPP_OR);
283
284 if (value_tcr & P_TCR_DS) bits |= BPP_PP_nStrobe;
285 if (value_or & P_OR_AFXN) bits |= BPP_PP_nAutoFd;
286 if (! (value_or & P_OR_INIT)) bits |= BPP_PP_nInit;
287 if (! (value_or & P_OR_SLCT_IN)) bits |= BPP_PP_nSelectIn;
288
289 if (value_ir & P_IR_ERR) bits |= BPP_GP_nFault;
290 if (! (value_ir & P_IR_SLCT)) bits |= BPP_GP_Select;
291 if (! (value_ir & P_IR_PE)) bits |= BPP_GP_PError;
292 if (! (value_tcr & P_TCR_ACK)) bits |= BPP_GP_nAck;
293 if (value_tcr & P_TCR_BUSY) bits |= BPP_GP_Busy;
294
295 return bits;
296 }
297
298 #endif /* __sparc__ */
299
300 static void bpp_wake_up(unsigned long val)
301 { wake_up(&instances[val].wait_queue); }
302
303 static void snooze(unsigned long snooze_time, unsigned minor)
304 {
305 init_timer(&instances[minor].timer_list);
306 instances[minor].timer_list.expires = jiffies + snooze_time + 1;
307 instances[minor].timer_list.data = minor;
308 add_timer(&instances[minor].timer_list);
309 sleep_on (&instances[minor].wait_queue);
310 }
311
312 static int wait_for(unsigned short set, unsigned short clr,
313 unsigned long delay, unsigned minor)
314 {
315 unsigned short pins = get_pins(minor);
316
317 unsigned long extime = 0;
318
319 /*
320 * Try a real fast scan for the first jiffy, in case the device
321 * responds real good. The first while loop guesses an expire
322 * time accounting for possible wraparound of jiffies.
323 */
324 while (time_after_eq(jiffies, extime)) extime = jiffies + 1;
325 while ( (time_before(jiffies, extime))
326 && (((pins & set) != set) || ((pins & clr) != 0)) ) {
327 pins = get_pins(minor);
328 }
329
330 delay -= 1;
331
332 /*
333 * If my delay expired or the pins are still not where I want
334 * them, then resort to using the timer and greatly reduce my
335 * sample rate. If the peripheral is going to be slow, this will
336 * give the CPU up to some more worthy process.
337 */
338 while ( delay && (((pins & set) != set) || ((pins & clr) != 0)) ) {
339
340 snooze(1, minor);
341 pins = get_pins(minor);
342 delay -= 1;
343 }
344
345 if (delay == 0) return -1;
346 else return pins;
347 }
348
349 /*
350 * Return ZERO(0) If the negotiation succeeds, an errno otherwise. An
351 * errno means something broke, and I do not yet know how to fix it.
352 */
353 static int negotiate(unsigned char mode, unsigned minor)
354 {
355 int rc;
356 unsigned short pins = get_pins(minor);
357 if (pins & BPP_PP_nSelectIn) return -EIO;
358
359
360 /* Event 0: Write the mode to the data lines */
361 bpp_outb_p(mode, base_addrs[minor]);
362
363 snooze(TIME_PSetup, minor);
364
365 /* Event 1: Strobe the mode code into the peripheral */
366 set_pins(BPP_PP_nSelectIn|BPP_PP_nStrobe|BPP_PP_nInit, minor);
367
368 /* Wait for Event 2: Peripheral responds as a 1284 device. */
369 rc = wait_for(BPP_GP_PError|BPP_GP_Select|BPP_GP_nFault,
370 BPP_GP_nAck,
371 TIME_PResponse,
372 minor);
373
374 if (rc == -1) return -ETIMEDOUT;
375
376 /* Event 3: latch extensibility request */
377 set_pins(BPP_PP_nSelectIn|BPP_PP_nInit, minor);
378
379 /* ... quick nap while peripheral ponders the byte i'm sending...*/
380 snooze(1, minor);
381
382 /* Event 4: restore strobe, to ACK peripheral's response. */
383 set_pins(BPP_PP_nSelectIn|BPP_PP_nAutoFd|BPP_PP_nStrobe|BPP_PP_nInit, minor);
384
385 /* Wait for Event 6: Peripheral latches response bits */
386 rc = wait_for(BPP_GP_nAck, 0, TIME_PSetup+TIME_PResponse, minor);
387 if (rc == -1) return -EIO;
388
389 /* A 1284 device cannot refuse nibble mode */
390 if (mode == DEFAULT_NIBBLE) return 0;
391
392 if (pins & BPP_GP_Select) return 0;
393
394 return -EPROTONOSUPPORT;
395 }
396
397 static int terminate(unsigned minor)
398 {
399 int rc;
400
401 /* Event 22: Request termination of 1284 mode */
402 set_pins(BPP_PP_nAutoFd|BPP_PP_nStrobe|BPP_PP_nInit, minor);
403
404 /* Wait for Events 23 and 24: ACK termination request. */
405 rc = wait_for(BPP_GP_Busy|BPP_GP_nFault,
406 BPP_GP_nAck,
407 TIME_PSetup+TIME_PResponse,
408 minor);
409
410 instances[minor].direction = 0;
411 instances[minor].mode = COMPATIBILITY;
412
413 if (rc == -1) {
414 return -EIO;
415 }
416
417 /* Event 25: Handshake by lowering nAutoFd */
418 set_pins(BPP_PP_nStrobe|BPP_PP_nInit, minor);
419
420 /* Event 26: Peripheral wiggles lines... */
421
422 /* Event 27: Peripheral sets nAck HIGH to ack handshake */
423 rc = wait_for(BPP_GP_nAck, 0, TIME_PResponse, minor);
424 if (rc == -1) {
425 set_pins(BPP_PP_nAutoFd|BPP_PP_nStrobe|BPP_PP_nInit, minor);
426 return -EIO;
427 }
428
429 /* Event 28: Finish phase by raising nAutoFd */
430 set_pins(BPP_PP_nAutoFd|BPP_PP_nStrobe|BPP_PP_nInit, minor);
431
432 return 0;
433 }
434
435 static DEFINE_SPINLOCK(bpp_open_lock);
436
437 /*
438 * Allow only one process to open the device at a time.
439 */
440 static int bpp_open(struct inode *inode, struct file *f)
441 {
442 unsigned minor = iminor(inode);
443 int ret;
444
445 spin_lock(&bpp_open_lock);
446 ret = 0;
447 if (minor >= BPP_NO) {
448 ret = -ENODEV;
449 } else {
450 if (! instances[minor].present) {
451 ret = -ENODEV;
452 } else {
453 if (instances[minor].opened)
454 ret = -EBUSY;
455 else
456 instances[minor].opened = 1;
457 }
458 }
459 spin_unlock(&bpp_open_lock);
460
461 return ret;
462 }
463
464 /*
465 * When the process closes the device, this method is called to clean
466 * up and reset the hardware. Always leave the device in compatibility
467 * mode as this is a reasonable place to clean up from messes made by
468 * ioctls, or other mayhem.
469 */
470 static int bpp_release(struct inode *inode, struct file *f)
471 {
472 unsigned minor = iminor(inode);
473
474 spin_lock(&bpp_open_lock);
475 instances[minor].opened = 0;
476
477 if (instances[minor].mode != COMPATIBILITY)
478 terminate(minor);
479
480 spin_unlock(&bpp_open_lock);
481
482 return 0;
483 }
484
485 static long read_nibble(unsigned minor, char __user *c, unsigned long cnt)
486 {
487 unsigned long remaining = cnt;
488 long rc;
489
490 while (remaining > 0) {
491 unsigned char byte = 0;
492 int pins;
493
494 /* Event 7: request nibble */
495 set_pins(BPP_PP_nSelectIn|BPP_PP_nStrobe, minor);
496
497 /* Wait for event 9: Peripher strobes first nibble */
498 pins = wait_for(0, BPP_GP_nAck, TIME_IDLE_LIMIT, minor);
499 if (pins == -1) return -ETIMEDOUT;
500
501 /* Event 10: I handshake nibble */
502 set_pins(BPP_PP_nSelectIn|BPP_PP_nStrobe|BPP_PP_nAutoFd, minor);
503 if (pins & BPP_GP_nFault) byte |= 0x01;
504 if (pins & BPP_GP_Select) byte |= 0x02;
505 if (pins & BPP_GP_PError) byte |= 0x04;
506 if (pins & BPP_GP_Busy) byte |= 0x08;
507
508 /* Wait for event 11: Peripheral handshakes nibble */
509 rc = wait_for(BPP_GP_nAck, 0, TIME_PResponse, minor);
510
511 /* Event 7: request nibble */
512 set_pins(BPP_PP_nSelectIn|BPP_PP_nStrobe, minor);
513
514 /* Wait for event 9: Peripher strobes first nibble */
515 pins = wait_for(0, BPP_GP_nAck, TIME_PResponse, minor);
516 if (rc == -1) return -ETIMEDOUT;
517
518 /* Event 10: I handshake nibble */
519 set_pins(BPP_PP_nSelectIn|BPP_PP_nStrobe|BPP_PP_nAutoFd, minor);
520 if (pins & BPP_GP_nFault) byte |= 0x10;
521 if (pins & BPP_GP_Select) byte |= 0x20;
522 if (pins & BPP_GP_PError) byte |= 0x40;
523 if (pins & BPP_GP_Busy) byte |= 0x80;
524
525 if (put_user(byte, c))
526 return -EFAULT;
527 c += 1;
528 remaining -= 1;
529
530 /* Wait for event 11: Peripheral handshakes nibble */
531 rc = wait_for(BPP_GP_nAck, 0, TIME_PResponse, minor);
532 if (rc == -1) return -EIO;
533 }
534
535 return cnt - remaining;
536 }
537
538 static long read_ecp(unsigned minor, char __user *c, unsigned long cnt)
539 {
540 unsigned long remaining;
541 long rc;
542
543 /* Turn ECP mode from forward to reverse if needed. */
544 if (! instances[minor].direction) {
545 unsigned short pins = get_pins(minor);
546
547 /* Event 38: Turn the bus around */
548 instances[minor].direction = 0x20;
549 pins &= ~BPP_PP_nAutoFd;
550 set_pins(pins, minor);
551
552 /* Event 39: Set pins for reverse mode. */
553 snooze(TIME_PSetup, minor);
554 set_pins(BPP_PP_nStrobe|BPP_PP_nSelectIn, minor);
555
556 /* Wait for event 40: Peripheral ready to be strobed */
557 rc = wait_for(0, BPP_GP_PError, TIME_PResponse, minor);
558 if (rc == -1) return -ETIMEDOUT;
559 }
560
561 remaining = cnt;
562
563 while (remaining > 0) {
564
565 /* If there is a run length for a repeated byte, repeat */
566 /* that byte a few times. */
567 if (instances[minor].run_length && !instances[minor].run_flag) {
568
569 char buffer[128];
570 unsigned idx;
571 unsigned repeat = remaining < instances[minor].run_length
572 ? remaining
573 : instances[minor].run_length;
574
575 for (idx = 0 ; idx < repeat ; idx += 1)
576 buffer[idx] = instances[minor].repeat_byte;
577
578 if (copy_to_user(c, buffer, repeat))
579 return -EFAULT;
580 remaining -= repeat;
581 c += repeat;
582 instances[minor].run_length -= repeat;
583 }
584
585 if (remaining == 0) break;
586
587
588 /* Wait for Event 43: Data active on the bus. */
589 rc = wait_for(0, BPP_GP_nAck, TIME_IDLE_LIMIT, minor);
590 if (rc == -1) break;
591
592 if (rc & BPP_GP_Busy) {
593 /* OK, this is data. read it in. */
594 unsigned char byte = bpp_inb(base_addrs[minor]);
595 if (put_user(byte, c))
596 return -EFAULT;
597 c += 1;
598 remaining -= 1;
599
600 if (instances[minor].run_flag) {
601 instances[minor].repeat_byte = byte;
602 instances[minor].run_flag = 0;
603 }
604
605 } else {
606 unsigned char byte = bpp_inb(base_addrs[minor]);
607 if (byte & 0x80) {
608 printk("bpp%d: "
609 "Ignoring ECP channel %u from device.\n",
610 minor, byte & 0x7f);
611 } else {
612 instances[minor].run_length = byte;
613 instances[minor].run_flag = 1;
614 }
615 }
616
617 /* Event 44: I got it. */
618 set_pins(BPP_PP_nStrobe|BPP_PP_nAutoFd|BPP_PP_nSelectIn, minor);
619
620 /* Wait for event 45: peripheral handshake */
621 rc = wait_for(BPP_GP_nAck, 0, TIME_PResponse, minor);
622 if (rc == -1) return -ETIMEDOUT;
623
624 /* Event 46: Finish handshake */
625 set_pins(BPP_PP_nStrobe|BPP_PP_nSelectIn, minor);
626
627 }
628
629
630 return cnt - remaining;
631 }
632
633 static ssize_t bpp_read(struct file *f, char __user *c, size_t cnt, loff_t * ppos)
634 {
635 long rc;
636 unsigned minor = iminor(f->f_dentry->d_inode);
637 if (minor >= BPP_NO) return -ENODEV;
638 if (!instances[minor].present) return -ENODEV;
639
640 switch (instances[minor].mode) {
641
642 default:
643 if (instances[minor].mode != COMPATIBILITY)
644 terminate(minor);
645
646 if (instances[minor].enhanced) {
647 /* For now, do all reads with ECP-RLE mode */
648 unsigned short pins;
649
650 rc = negotiate(DEFAULT_ECP, minor);
651 if (rc < 0) break;
652
653 instances[minor].mode = ECP_RLE;
654
655 /* Event 30: set nAutoFd low to setup for ECP mode */
656 pins = get_pins(minor);
657 pins &= ~BPP_PP_nAutoFd;
658 set_pins(pins, minor);
659
660 /* Wait for Event 31: peripheral ready */
661 rc = wait_for(BPP_GP_PError, 0, TIME_PResponse, minor);
662 if (rc == -1) return -ETIMEDOUT;
663
664 rc = read_ecp(minor, c, cnt);
665
666 } else {
667 rc = negotiate(DEFAULT_NIBBLE, minor);
668 if (rc < 0) break;
669
670 instances[minor].mode = NIBBLE;
671
672 rc = read_nibble(minor, c, cnt);
673 }
674 break;
675
676 case NIBBLE:
677 rc = read_nibble(minor, c, cnt);
678 break;
679
680 case ECP:
681 case ECP_RLE:
682 rc = read_ecp(minor, c, cnt);
683 break;
684
685 }
686
687
688 return rc;
689 }
690
691 /*
692 * Compatibility mode handshaking is a matter of writing data,
693 * strobing it, and waiting for the printer to stop being busy.
694 */
695 static long write_compat(unsigned minor, const char __user *c, unsigned long cnt)
696 {
697 long rc;
698 unsigned short pins = get_pins(minor);
699
700 unsigned long remaining = cnt;
701
702
703 while (remaining > 0) {
704 unsigned char byte;
705
706 if (get_user(byte, c))
707 return -EFAULT;
708 c += 1;
709
710 rc = wait_for(BPP_GP_nAck, BPP_GP_Busy, TIME_IDLE_LIMIT, minor);
711 if (rc == -1) return -ETIMEDOUT;
712
713 bpp_outb_p(byte, base_addrs[minor]);
714 remaining -= 1;
715 /* snooze(1, minor); */
716
717 pins &= ~BPP_PP_nStrobe;
718 set_pins(pins, minor);
719
720 rc = wait_for(BPP_GP_Busy, 0, TIME_PResponse, minor);
721
722 pins |= BPP_PP_nStrobe;
723 set_pins(pins, minor);
724 }
725
726 return cnt - remaining;
727 }
728
729 /*
730 * Write data using ECP mode. Watch out that the port may be set up
731 * for reading. If so, turn the port around.
732 */
733 static long write_ecp(unsigned minor, const char __user *c, unsigned long cnt)
734 {
735 unsigned short pins = get_pins(minor);
736 unsigned long remaining = cnt;
737
738 if (instances[minor].direction) {
739 int rc;
740
741 /* Event 47 Request bus be turned around */
742 pins |= BPP_PP_nInit;
743 set_pins(pins, minor);
744
745 /* Wait for Event 49: Peripheral relinquished bus */
746 rc = wait_for(BPP_GP_PError, 0, TIME_PResponse, minor);
747
748 pins |= BPP_PP_nAutoFd;
749 instances[minor].direction = 0;
750 set_pins(pins, minor);
751 }
752
753 while (remaining > 0) {
754 unsigned char byte;
755 int rc;
756
757 if (get_user(byte, c))
758 return -EFAULT;
759
760 rc = wait_for(0, BPP_GP_Busy, TIME_PResponse, minor);
761 if (rc == -1) return -ETIMEDOUT;
762
763 c += 1;
764
765 bpp_outb_p(byte, base_addrs[minor]);
766
767 pins &= ~BPP_PP_nStrobe;
768 set_pins(pins, minor);
769
770 pins |= BPP_PP_nStrobe;
771 rc = wait_for(BPP_GP_Busy, 0, TIME_PResponse, minor);
772 if (rc == -1) return -EIO;
773
774 set_pins(pins, minor);
775 }
776
777 return cnt - remaining;
778 }
779
780 /*
781 * Write to the peripheral. Be sensitive of the current mode. If I'm
782 * in a mode that can be turned around (ECP) then just do
783 * that. Otherwise, terminate and do my writing in compat mode. This
784 * is the safest course as any device can handle it.
785 */
786 static ssize_t bpp_write(struct file *f, const char __user *c, size_t cnt, loff_t * ppos)
787 {
788 long errno = 0;
789 unsigned minor = iminor(f->f_dentry->d_inode);
790 if (minor >= BPP_NO) return -ENODEV;
791 if (!instances[minor].present) return -ENODEV;
792
793 switch (instances[minor].mode) {
794
795 case ECP:
796 case ECP_RLE:
797 errno = write_ecp(minor, c, cnt);
798 break;
799 case COMPATIBILITY:
800 errno = write_compat(minor, c, cnt);
801 break;
802 default:
803 terminate(minor);
804 errno = write_compat(minor, c, cnt);
805 }
806
807 return errno;
808 }
809
810 static int bpp_ioctl(struct inode *inode, struct file *f, unsigned int cmd,
811 unsigned long arg)
812 {
813 int errno = 0;
814
815 unsigned minor = iminor(inode);
816 if (minor >= BPP_NO) return -ENODEV;
817 if (!instances[minor].present) return -ENODEV;
818
819
820 switch (cmd) {
821
822 case BPP_PUT_PINS:
823 set_pins(arg, minor);
824 break;
825
826 case BPP_GET_PINS:
827 errno = get_pins(minor);
828 break;
829
830 case BPP_PUT_DATA:
831 bpp_outb_p(arg, base_addrs[minor]);
832 break;
833
834 case BPP_GET_DATA:
835 errno = bpp_inb_p(base_addrs[minor]);
836 break;
837
838 case BPP_SET_INPUT:
839 if (arg)
840 if (instances[minor].enhanced) {
841 unsigned short bits = get_pins(minor);
842 instances[minor].direction = 0x20;
843 set_pins(bits, minor);
844 } else {
845 errno = -ENOTTY;
846 }
847 else {
848 unsigned short bits = get_pins(minor);
849 instances[minor].direction = 0x00;
850 set_pins(bits, minor);
851 }
852 break;
853
854 default:
855 errno = -EINVAL;
856 }
857
858 return errno;
859 }
860
861 static struct file_operations bpp_fops = {
862 .owner = THIS_MODULE,
863 .read = bpp_read,
864 .write = bpp_write,
865 .ioctl = bpp_ioctl,
866 .open = bpp_open,
867 .release = bpp_release,
868 };
869
870 #if defined(__i386__)
871
872 #define collectLptPorts() {}
873
874 static void probeLptPort(unsigned idx)
875 {
876 unsigned int testvalue;
877 const unsigned short lpAddr = base_addrs[idx];
878
879 instances[idx].present = 0;
880 instances[idx].enhanced = 0;
881 instances[idx].direction = 0;
882 instances[idx].mode = COMPATIBILITY;
883 instances[idx].wait_queue = 0;
884 instances[idx].run_length = 0;
885 instances[idx].run_flag = 0;
886 init_timer(&instances[idx].timer_list);
887 instances[idx].timer_list.function = bpp_wake_up;
888 if (!request_region(lpAddr,3, dev_name)) return;
889
890 /*
891 * First, make sure the instance exists. Do this by writing to
892 * the data latch and reading the value back. If the port *is*
893 * present, test to see if it supports extended-mode
894 * operation. This will be required for IEEE1284 reverse
895 * transfers.
896 */
897
898 outb_p(BPP_PROBE_CODE, lpAddr);
899 for (testvalue=0; testvalue<BPP_DELAY; testvalue++)
900 ;
901 testvalue = inb_p(lpAddr);
902 if (testvalue == BPP_PROBE_CODE) {
903 unsigned save;
904 instances[idx].present = 1;
905
906 save = inb_p(lpAddr+2);
907 for (testvalue=0; testvalue<BPP_DELAY; testvalue++)
908 ;
909 outb_p(save|0x20, lpAddr+2);
910 for (testvalue=0; testvalue<BPP_DELAY; testvalue++)
911 ;
912 outb_p(~BPP_PROBE_CODE, lpAddr);
913 for (testvalue=0; testvalue<BPP_DELAY; testvalue++)
914 ;
915 testvalue = inb_p(lpAddr);
916 if ((testvalue&0xff) == (0xff&~BPP_PROBE_CODE))
917 instances[idx].enhanced = 0;
918 else
919 instances[idx].enhanced = 1;
920 outb_p(save, lpAddr+2);
921 }
922 else {
923 release_region(lpAddr,3);
924 }
925 /*
926 * Leave the port in compat idle mode.
927 */
928 set_pins(BPP_PP_nAutoFd|BPP_PP_nStrobe|BPP_PP_nInit, idx);
929
930 printk("bpp%d: Port at 0x%03x: Enhanced mode %s\n", idx, base_addrs[idx],
931 instances[idx].enhanced? "SUPPORTED" : "UNAVAILABLE");
932 }
933
934 static inline void freeLptPort(int idx)
935 {
936 release_region(base_addrs[idx], 3);
937 }
938
939 #endif
940
941 #if defined(__sparc__)
942
943 static void __iomem *map_bpp(struct sbus_dev *dev, int idx)
944 {
945 return sbus_ioremap(&dev->resource[0], 0, BPP_SIZE, "bpp");
946 }
947
948 static int collectLptPorts(void)
949 {
950 struct sbus_bus *bus;
951 struct sbus_dev *dev;
952 int count;
953
954 count = 0;
955 for_all_sbusdev(dev, bus) {
956 if (strcmp(dev->prom_name, "SUNW,bpp") == 0) {
957 if (count >= BPP_NO) {
958 printk(KERN_NOTICE
959 "bpp: More than %d bpp ports,"
960 " rest is ignored\n", BPP_NO);
961 return count;
962 }
963 base_addrs[count] = map_bpp(dev, count);
964 count++;
965 }
966 }
967 return count;
968 }
969
970 static void probeLptPort(unsigned idx)
971 {
972 void __iomem *rp = base_addrs[idx];
973 __u32 csr;
974 char *brand;
975
976 instances[idx].present = 0;
977 instances[idx].enhanced = 0;
978 instances[idx].direction = 0;
979 instances[idx].mode = COMPATIBILITY;
980 init_waitqueue_head(&instances[idx].wait_queue);
981 instances[idx].run_length = 0;
982 instances[idx].run_flag = 0;
983 init_timer(&instances[idx].timer_list);
984 instances[idx].timer_list.function = bpp_wake_up;
985
986 if (!rp) return;
987
988 instances[idx].present = 1;
989 instances[idx].enhanced = 1; /* Sure */
990
991 csr = sbus_readl(rp + BPP_CSR);
992 if ((csr & P_DRAINING) != 0 && (csr & P_ERR_PEND) == 0) {
993 udelay(20);
994 csr = sbus_readl(rp + BPP_CSR);
995 if ((csr & P_DRAINING) != 0 && (csr & P_ERR_PEND) == 0) {
996 printk("bpp%d: DRAINING still active (0x%08x)\n", idx, csr);
997 }
998 }
999 printk("bpp%d: reset with 0x%08x ..", idx, csr);
1000 sbus_writel((csr | P_RESET) & ~P_INT_EN, rp + BPP_CSR);
1001 udelay(500);
1002 sbus_writel(sbus_readl(rp + BPP_CSR) & ~P_RESET, rp + BPP_CSR);
1003 csr = sbus_readl(rp + BPP_CSR);
1004 printk(" done with csr=0x%08x ocr=0x%04x\n",
1005 csr, sbus_readw(rp + BPP_OCR));
1006
1007 switch (csr & P_DEV_ID_MASK) {
1008 case P_DEV_ID_ZEBRA:
1009 brand = "Zebra";
1010 break;
1011 case P_DEV_ID_L64854:
1012 brand = "DMA2";
1013 break;
1014 default:
1015 brand = "Unknown";
1016 }
1017 printk("bpp%d: %s at %p\n", idx, brand, rp);
1018
1019 /*
1020 * Leave the port in compat idle mode.
1021 */
1022 set_pins(BPP_PP_nAutoFd|BPP_PP_nStrobe|BPP_PP_nInit, idx);
1023
1024 return;
1025 }
1026
1027 static inline void freeLptPort(int idx)
1028 {
1029 sbus_iounmap(base_addrs[idx], BPP_SIZE);
1030 }
1031
1032 #endif
1033
1034 static int __init bpp_init(void)
1035 {
1036 int rc;
1037 unsigned idx;
1038
1039 rc = collectLptPorts();
1040 if (rc == 0)
1041 return -ENODEV;
1042
1043 rc = register_chrdev(BPP_MAJOR, dev_name, &bpp_fops);
1044 if (rc < 0)
1045 return rc;
1046
1047 for (idx = 0; idx < BPP_NO; idx++) {
1048 instances[idx].opened = 0;
1049 probeLptPort(idx);
1050 }
1051 devfs_mk_dir("bpp");
1052 for (idx = 0; idx < BPP_NO; idx++) {
1053 devfs_mk_cdev(MKDEV(BPP_MAJOR, idx),
1054 S_IFCHR | S_IRUSR | S_IWUSR, "bpp/%d", idx);
1055 }
1056
1057 return 0;
1058 }
1059
1060 static void __exit bpp_cleanup(void)
1061 {
1062 unsigned idx;
1063
1064 for (idx = 0; idx < BPP_NO; idx++)
1065 devfs_remove("bpp/%d", idx);
1066 devfs_remove("bpp");
1067 unregister_chrdev(BPP_MAJOR, dev_name);
1068
1069 for (idx = 0; idx < BPP_NO; idx++) {
1070 if (instances[idx].present)
1071 freeLptPort(idx);
1072 }
1073 }
1074
1075 module_init(bpp_init);
1076 module_exit(bpp_cleanup);
1077
1078 MODULE_LICENSE("GPL");
1079
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