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Linux-2.6.12-rc2
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / sunhme.c
blobd837b3c357231b3640a7bd6d536e4c9d8d6dbaa4
1 /* $Id: sunhme.c,v 1.124 2002/01/15 06:25:51 davem Exp $
2 * sunhme.c: Sparc HME/BigMac 10/100baseT half/full duplex auto switching,
3 * auto carrier detecting ethernet driver. Also known as the
4 * "Happy Meal Ethernet" found on SunSwift SBUS cards.
5 *
6 * Copyright (C) 1996, 1998, 1999, 2002, 2003 David S. Miller (davem@redhat.com)
7 *
8 * Changes :
9 * 2000/11/11 Willy Tarreau <willy AT meta-x.org>
10 * - port to non-sparc architectures. Tested only on x86 and
11 * only currently works with QFE PCI cards.
12 * - ability to specify the MAC address at module load time by passing this
13 * argument : macaddr=0x00,0x10,0x20,0x30,0x40,0x50
14 */
15
16 static char version[] =
17 "sunhme.c:v2.02 24/Aug/2003 David S. Miller (davem@redhat.com)\n";
18
19 #include <linux/config.h>
20 #include <linux/module.h>
21 #include <linux/kernel.h>
22 #include <linux/types.h>
23 #include <linux/fcntl.h>
24 #include <linux/interrupt.h>
25 #include <linux/ioport.h>
26 #include <linux/in.h>
27 #include <linux/slab.h>
28 #include <linux/string.h>
29 #include <linux/delay.h>
30 #include <linux/init.h>
31 #include <linux/ethtool.h>
32 #include <linux/mii.h>
33 #include <linux/crc32.h>
34 #include <linux/random.h>
35 #include <linux/errno.h>
36 #include <linux/netdevice.h>
37 #include <linux/etherdevice.h>
38 #include <linux/skbuff.h>
39 #include <linux/bitops.h>
40
41 #include <asm/system.h>
42 #include <asm/io.h>
43 #include <asm/dma.h>
44 #include <asm/byteorder.h>
45
46 #ifdef __sparc__
47 #include <asm/idprom.h>
48 #include <asm/sbus.h>
49 #include <asm/openprom.h>
50 #include <asm/oplib.h>
51 #include <asm/auxio.h>
52 #ifndef __sparc_v9__
53 #include <asm/io-unit.h>
54 #endif
55 #endif
56 #include <asm/uaccess.h>
57
58 #include <asm/pgtable.h>
59 #include <asm/irq.h>
60
61 #ifdef CONFIG_PCI
62 #include <linux/pci.h>
63 #ifdef __sparc__
64 #include <asm/pbm.h>
65 #endif
66 #endif
67
68 #include "sunhme.h"
69
70
71 #define DRV_NAME "sunhme"
72
73 static int macaddr[6];
74
75 /* accept MAC address of the form macaddr=0x08,0x00,0x20,0x30,0x40,0x50 */
76 module_param_array(macaddr, int, NULL, 0);
77 MODULE_PARM_DESC(macaddr, "Happy Meal MAC address to set");
78 MODULE_LICENSE("GPL");
79
80 static struct happy_meal *root_happy_dev;
81
82 #ifdef CONFIG_SBUS
83 static struct quattro *qfe_sbus_list;
84 #endif
85
86 #ifdef CONFIG_PCI
87 static struct quattro *qfe_pci_list;
88 #endif
89
90 #undef HMEDEBUG
91 #undef SXDEBUG
92 #undef RXDEBUG
93 #undef TXDEBUG
94 #undef TXLOGGING
95
96 #ifdef TXLOGGING
97 struct hme_tx_logent {
98 unsigned int tstamp;
99 int tx_new, tx_old;
100 unsigned int action;
101 #define TXLOG_ACTION_IRQ 0x01
102 #define TXLOG_ACTION_TXMIT 0x02
103 #define TXLOG_ACTION_TBUSY 0x04
104 #define TXLOG_ACTION_NBUFS 0x08
105 unsigned int status;
106 };
107 #define TX_LOG_LEN 128
108 static struct hme_tx_logent tx_log[TX_LOG_LEN];
109 static int txlog_cur_entry;
110 static __inline__ void tx_add_log(struct happy_meal *hp, unsigned int a, unsigned int s)
111 {
112 struct hme_tx_logent *tlp;
113 unsigned long flags;
114
115 save_and_cli(flags);
116 tlp = &tx_log[txlog_cur_entry];
117 tlp->tstamp = (unsigned int)jiffies;
118 tlp->tx_new = hp->tx_new;
119 tlp->tx_old = hp->tx_old;
120 tlp->action = a;
121 tlp->status = s;
122 txlog_cur_entry = (txlog_cur_entry + 1) & (TX_LOG_LEN - 1);
123 restore_flags(flags);
124 }
125 static __inline__ void tx_dump_log(void)
126 {
127 int i, this;
128
129 this = txlog_cur_entry;
130 for (i = 0; i < TX_LOG_LEN; i++) {
131 printk("TXLOG[%d]: j[%08x] tx[N(%d)O(%d)] action[%08x] stat[%08x]\n", i,
132 tx_log[this].tstamp,
133 tx_log[this].tx_new, tx_log[this].tx_old,
134 tx_log[this].action, tx_log[this].status);
135 this = (this + 1) & (TX_LOG_LEN - 1);
136 }
137 }
138 static __inline__ void tx_dump_ring(struct happy_meal *hp)
139 {
140 struct hmeal_init_block *hb = hp->happy_block;
141 struct happy_meal_txd *tp = &hb->happy_meal_txd[0];
142 int i;
143
144 for (i = 0; i < TX_RING_SIZE; i+=4) {
145 printk("TXD[%d..%d]: [%08x:%08x] [%08x:%08x] [%08x:%08x] [%08x:%08x]\n",
146 i, i + 4,
147 le32_to_cpu(tp[i].tx_flags), le32_to_cpu(tp[i].tx_addr),
148 le32_to_cpu(tp[i + 1].tx_flags), le32_to_cpu(tp[i + 1].tx_addr),
149 le32_to_cpu(tp[i + 2].tx_flags), le32_to_cpu(tp[i + 2].tx_addr),
150 le32_to_cpu(tp[i + 3].tx_flags), le32_to_cpu(tp[i + 3].tx_addr));
151 }
152 }
153 #else
154 #define tx_add_log(hp, a, s) do { } while(0)
155 #define tx_dump_log() do { } while(0)
156 #define tx_dump_ring(hp) do { } while(0)
157 #endif
158
159 #ifdef HMEDEBUG
160 #define HMD(x) printk x
161 #else
162 #define HMD(x)
163 #endif
164
165 /* #define AUTO_SWITCH_DEBUG */
166
167 #ifdef AUTO_SWITCH_DEBUG
168 #define ASD(x) printk x
169 #else
170 #define ASD(x)
171 #endif
172
173 #define DEFAULT_IPG0 16 /* For lance-mode only */
174 #define DEFAULT_IPG1 8 /* For all modes */
175 #define DEFAULT_IPG2 4 /* For all modes */
176 #define DEFAULT_JAMSIZE 4 /* Toe jam */
177
178 #if defined(CONFIG_PCI) && defined(MODULE)
179 /* This happy_pci_ids is declared __initdata because it is only used
180 as an advisory to depmod. If this is ported to the new PCI interface
181 where it could be referenced at any time due to hot plugging,
182 the __initdata reference should be removed. */
183
184 static struct pci_device_id happymeal_pci_ids[] = {
185 {
186 .vendor = PCI_VENDOR_ID_SUN,
187 .device = PCI_DEVICE_ID_SUN_HAPPYMEAL,
188 .subvendor = PCI_ANY_ID,
189 .subdevice = PCI_ANY_ID,
190 },
191 { } /* Terminating entry */
192 };
193
194 MODULE_DEVICE_TABLE(pci, happymeal_pci_ids);
195
196 #endif
197
198 /* NOTE: In the descriptor writes one _must_ write the address
199 * member _first_. The card must not be allowed to see
200 * the updated descriptor flags until the address is
201 * correct. I've added a write memory barrier between
202 * the two stores so that I can sleep well at night... -DaveM
203 */
204
205 #if defined(CONFIG_SBUS) && defined(CONFIG_PCI)
206 static void sbus_hme_write32(void __iomem *reg, u32 val)
207 {
208 sbus_writel(val, reg);
209 }
210
211 static u32 sbus_hme_read32(void __iomem *reg)
212 {
213 return sbus_readl(reg);
214 }
215
216 static void sbus_hme_write_rxd(struct happy_meal_rxd *rxd, u32 flags, u32 addr)
217 {
218 rxd->rx_addr = addr;
219 wmb();
220 rxd->rx_flags = flags;
221 }
222
223 static void sbus_hme_write_txd(struct happy_meal_txd *txd, u32 flags, u32 addr)
224 {
225 txd->tx_addr = addr;
226 wmb();
227 txd->tx_flags = flags;
228 }
229
230 static u32 sbus_hme_read_desc32(u32 *p)
231 {
232 return *p;
233 }
234
235 static void pci_hme_write32(void __iomem *reg, u32 val)
236 {
237 writel(val, reg);
238 }
239
240 static u32 pci_hme_read32(void __iomem *reg)
241 {
242 return readl(reg);
243 }
244
245 static void pci_hme_write_rxd(struct happy_meal_rxd *rxd, u32 flags, u32 addr)
246 {
247 rxd->rx_addr = cpu_to_le32(addr);
248 wmb();
249 rxd->rx_flags = cpu_to_le32(flags);
250 }
251
252 static void pci_hme_write_txd(struct happy_meal_txd *txd, u32 flags, u32 addr)
253 {
254 txd->tx_addr = cpu_to_le32(addr);
255 wmb();
256 txd->tx_flags = cpu_to_le32(flags);
257 }
258
259 static u32 pci_hme_read_desc32(u32 *p)
260 {
261 return cpu_to_le32p(p);
262 }
263
264 #define hme_write32(__hp, __reg, __val) \
265 ((__hp)->write32((__reg), (__val)))
266 #define hme_read32(__hp, __reg) \
267 ((__hp)->read32(__reg))
268 #define hme_write_rxd(__hp, __rxd, __flags, __addr) \
269 ((__hp)->write_rxd((__rxd), (__flags), (__addr)))
270 #define hme_write_txd(__hp, __txd, __flags, __addr) \
271 ((__hp)->write_txd((__txd), (__flags), (__addr)))
272 #define hme_read_desc32(__hp, __p) \
273 ((__hp)->read_desc32(__p))
274 #define hme_dma_map(__hp, __ptr, __size, __dir) \
275 ((__hp)->dma_map((__hp)->happy_dev, (__ptr), (__size), (__dir)))
276 #define hme_dma_unmap(__hp, __addr, __size, __dir) \
277 ((__hp)->dma_unmap((__hp)->happy_dev, (__addr), (__size), (__dir)))
278 #define hme_dma_sync_for_cpu(__hp, __addr, __size, __dir) \
279 ((__hp)->dma_sync_for_cpu((__hp)->happy_dev, (__addr), (__size), (__dir)))
280 #define hme_dma_sync_for_device(__hp, __addr, __size, __dir) \
281 ((__hp)->dma_sync_for_device((__hp)->happy_dev, (__addr), (__size), (__dir)))
282 #else
283 #ifdef CONFIG_SBUS
284 /* SBUS only compilation */
285 #define hme_write32(__hp, __reg, __val) \
286 sbus_writel((__val), (__reg))
287 #define hme_read32(__hp, __reg) \
288 sbus_readl(__reg)
289 #define hme_write_rxd(__hp, __rxd, __flags, __addr) \
290 do { (__rxd)->rx_addr = (__addr); \
291 wmb(); \
292 (__rxd)->rx_flags = (__flags); \
293 } while(0)
294 #define hme_write_txd(__hp, __txd, __flags, __addr) \
295 do { (__txd)->tx_addr = (__addr); \
296 wmb(); \
297 (__txd)->tx_flags = (__flags); \
298 } while(0)
299 #define hme_read_desc32(__hp, __p) (*(__p))
300 #define hme_dma_map(__hp, __ptr, __size, __dir) \
301 sbus_map_single((__hp)->happy_dev, (__ptr), (__size), (__dir))
302 #define hme_dma_unmap(__hp, __addr, __size, __dir) \
303 sbus_unmap_single((__hp)->happy_dev, (__addr), (__size), (__dir))
304 #define hme_dma_sync_for_cpu(__hp, __addr, __size, __dir) \
305 sbus_dma_sync_single_for_cpu((__hp)->happy_dev, (__addr), (__size), (__dir))
306 #define hme_dma_sync_for_device(__hp, __addr, __size, __dir) \
307 sbus_dma_sync_single_for_device((__hp)->happy_dev, (__addr), (__size), (__dir))
308 #else
309 /* PCI only compilation */
310 #define hme_write32(__hp, __reg, __val) \
311 writel((__val), (__reg))
312 #define hme_read32(__hp, __reg) \
313 readl(__reg)
314 #define hme_write_rxd(__hp, __rxd, __flags, __addr) \
315 do { (__rxd)->rx_addr = cpu_to_le32(__addr); \
316 wmb(); \
317 (__rxd)->rx_flags = cpu_to_le32(__flags); \
318 } while(0)
319 #define hme_write_txd(__hp, __txd, __flags, __addr) \
320 do { (__txd)->tx_addr = cpu_to_le32(__addr); \
321 wmb(); \
322 (__txd)->tx_flags = cpu_to_le32(__flags); \
323 } while(0)
324 #define hme_read_desc32(__hp, __p) cpu_to_le32p(__p)
325 #define hme_dma_map(__hp, __ptr, __size, __dir) \
326 pci_map_single((__hp)->happy_dev, (__ptr), (__size), (__dir))
327 #define hme_dma_unmap(__hp, __addr, __size, __dir) \
328 pci_unmap_single((__hp)->happy_dev, (__addr), (__size), (__dir))
329 #define hme_dma_sync_for_cpu(__hp, __addr, __size, __dir) \
330 pci_dma_sync_single_for_cpu((__hp)->happy_dev, (__addr), (__size), (__dir))
331 #define hme_dma_sync_for_device(__hp, __addr, __size, __dir) \
332 pci_dma_sync_single_for_device((__hp)->happy_dev, (__addr), (__size), (__dir))
333 #endif
334 #endif
335
336
337 #ifdef SBUS_DMA_BIDIRECTIONAL
338 # define DMA_BIDIRECTIONAL SBUS_DMA_BIDIRECTIONAL
339 #else
340 # define DMA_BIDIRECTIONAL 0
341 #endif
342
343 #ifdef SBUS_DMA_FROMDEVICE
344 # define DMA_FROMDEVICE SBUS_DMA_FROMDEVICE
345 #else
346 # define DMA_TODEVICE 1
347 #endif
348
349 #ifdef SBUS_DMA_TODEVICE
350 # define DMA_TODEVICE SBUS_DMA_TODEVICE
351 #else
352 # define DMA_FROMDEVICE 2
353 #endif
354
355
356 /* Oh yes, the MIF BitBang is mighty fun to program. BitBucket is more like it. */
357 static void BB_PUT_BIT(struct happy_meal *hp, void __iomem *tregs, int bit)
358 {
359 hme_write32(hp, tregs + TCVR_BBDATA, bit);
360 hme_write32(hp, tregs + TCVR_BBCLOCK, 0);
361 hme_write32(hp, tregs + TCVR_BBCLOCK, 1);
362 }
363
364 #if 0
365 static u32 BB_GET_BIT(struct happy_meal *hp, void __iomem *tregs, int internal)
366 {
367 u32 ret;
368
369 hme_write32(hp, tregs + TCVR_BBCLOCK, 0);
370 hme_write32(hp, tregs + TCVR_BBCLOCK, 1);
371 ret = hme_read32(hp, tregs + TCVR_CFG);
372 if (internal)
373 ret &= TCV_CFG_MDIO0;
374 else
375 ret &= TCV_CFG_MDIO1;
376
377 return ret;
378 }
379 #endif
380
381 static u32 BB_GET_BIT2(struct happy_meal *hp, void __iomem *tregs, int internal)
382 {
383 u32 retval;
384
385 hme_write32(hp, tregs + TCVR_BBCLOCK, 0);
386 udelay(1);
387 retval = hme_read32(hp, tregs + TCVR_CFG);
388 if (internal)
389 retval &= TCV_CFG_MDIO0;
390 else
391 retval &= TCV_CFG_MDIO1;
392 hme_write32(hp, tregs + TCVR_BBCLOCK, 1);
393
394 return retval;
395 }
396
397 #define TCVR_FAILURE 0x80000000 /* Impossible MIF read value */
398
399 static int happy_meal_bb_read(struct happy_meal *hp,
400 void __iomem *tregs, int reg)
401 {
402 u32 tmp;
403 int retval = 0;
404 int i;
405
406 ASD(("happy_meal_bb_read: reg=%d ", reg));
407
408 /* Enable the MIF BitBang outputs. */
409 hme_write32(hp, tregs + TCVR_BBOENAB, 1);
410
411 /* Force BitBang into the idle state. */
412 for (i = 0; i < 32; i++)
413 BB_PUT_BIT(hp, tregs, 1);
414
415 /* Give it the read sequence. */
416 BB_PUT_BIT(hp, tregs, 0);
417 BB_PUT_BIT(hp, tregs, 1);
418 BB_PUT_BIT(hp, tregs, 1);
419 BB_PUT_BIT(hp, tregs, 0);
420
421 /* Give it the PHY address. */
422 tmp = hp->paddr & 0xff;
423 for (i = 4; i >= 0; i--)
424 BB_PUT_BIT(hp, tregs, ((tmp >> i) & 1));
425
426 /* Tell it what register we want to read. */
427 tmp = (reg & 0xff);
428 for (i = 4; i >= 0; i--)
429 BB_PUT_BIT(hp, tregs, ((tmp >> i) & 1));
430
431 /* Close down the MIF BitBang outputs. */
432 hme_write32(hp, tregs + TCVR_BBOENAB, 0);
433
434 /* Now read in the value. */
435 (void) BB_GET_BIT2(hp, tregs, (hp->tcvr_type == internal));
436 for (i = 15; i >= 0; i--)
437 retval |= BB_GET_BIT2(hp, tregs, (hp->tcvr_type == internal));
438 (void) BB_GET_BIT2(hp, tregs, (hp->tcvr_type == internal));
439 (void) BB_GET_BIT2(hp, tregs, (hp->tcvr_type == internal));
440 (void) BB_GET_BIT2(hp, tregs, (hp->tcvr_type == internal));
441 ASD(("value=%x\n", retval));
442 return retval;
443 }
444
445 static void happy_meal_bb_write(struct happy_meal *hp,
446 void __iomem *tregs, int reg,
447 unsigned short value)
448 {
449 u32 tmp;
450 int i;
451
452 ASD(("happy_meal_bb_write: reg=%d value=%x\n", reg, value));
453
454 /* Enable the MIF BitBang outputs. */
455 hme_write32(hp, tregs + TCVR_BBOENAB, 1);
456
457 /* Force BitBang into the idle state. */
458 for (i = 0; i < 32; i++)
459 BB_PUT_BIT(hp, tregs, 1);
460
461 /* Give it write sequence. */
462 BB_PUT_BIT(hp, tregs, 0);
463 BB_PUT_BIT(hp, tregs, 1);
464 BB_PUT_BIT(hp, tregs, 0);
465 BB_PUT_BIT(hp, tregs, 1);
466
467 /* Give it the PHY address. */
468 tmp = (hp->paddr & 0xff);
469 for (i = 4; i >= 0; i--)
470 BB_PUT_BIT(hp, tregs, ((tmp >> i) & 1));
471
472 /* Tell it what register we will be writing. */
473 tmp = (reg & 0xff);
474 for (i = 4; i >= 0; i--)
475 BB_PUT_BIT(hp, tregs, ((tmp >> i) & 1));
476
477 /* Tell it to become ready for the bits. */
478 BB_PUT_BIT(hp, tregs, 1);
479 BB_PUT_BIT(hp, tregs, 0);
480
481 for (i = 15; i >= 0; i--)
482 BB_PUT_BIT(hp, tregs, ((value >> i) & 1));
483
484 /* Close down the MIF BitBang outputs. */
485 hme_write32(hp, tregs + TCVR_BBOENAB, 0);
486 }
487
488 #define TCVR_READ_TRIES 16
489
490 static int happy_meal_tcvr_read(struct happy_meal *hp,
491 void __iomem *tregs, int reg)
492 {
493 int tries = TCVR_READ_TRIES;
494 int retval;
495
496 ASD(("happy_meal_tcvr_read: reg=0x%02x ", reg));
497 if (hp->tcvr_type == none) {
498 ASD(("no transceiver, value=TCVR_FAILURE\n"));
499 return TCVR_FAILURE;
500 }
501
502 if (!(hp->happy_flags & HFLAG_FENABLE)) {
503 ASD(("doing bit bang\n"));
504 return happy_meal_bb_read(hp, tregs, reg);
505 }
506
507 hme_write32(hp, tregs + TCVR_FRAME,
508 (FRAME_READ | (hp->paddr << 23) | ((reg & 0xff) << 18)));
509 while (!(hme_read32(hp, tregs + TCVR_FRAME) & 0x10000) && --tries)
510 udelay(20);
511 if (!tries) {
512 printk(KERN_ERR "happy meal: Aieee, transceiver MIF read bolixed\n");
513 return TCVR_FAILURE;
514 }
515 retval = hme_read32(hp, tregs + TCVR_FRAME) & 0xffff;
516 ASD(("value=%04x\n", retval));
517 return retval;
518 }
519
520 #define TCVR_WRITE_TRIES 16
521
522 static void happy_meal_tcvr_write(struct happy_meal *hp,
523 void __iomem *tregs, int reg,
524 unsigned short value)
525 {
526 int tries = TCVR_WRITE_TRIES;
527
528 ASD(("happy_meal_tcvr_write: reg=0x%02x value=%04x\n", reg, value));
529
530 /* Welcome to Sun Microsystems, can I take your order please? */
531 if (!(hp->happy_flags & HFLAG_FENABLE)) {
532 happy_meal_bb_write(hp, tregs, reg, value);
533 return;
534 }
535
536 /* Would you like fries with that? */
537 hme_write32(hp, tregs + TCVR_FRAME,
538 (FRAME_WRITE | (hp->paddr << 23) |
539 ((reg & 0xff) << 18) | (value & 0xffff)));
540 while (!(hme_read32(hp, tregs + TCVR_FRAME) & 0x10000) && --tries)
541 udelay(20);
542
543 /* Anything else? */
544 if (!tries)
545 printk(KERN_ERR "happy meal: Aieee, transceiver MIF write bolixed\n");
546
547 /* Fifty-two cents is your change, have a nice day. */
548 }
549
550 /* Auto negotiation. The scheme is very simple. We have a timer routine
551 * that keeps watching the auto negotiation process as it progresses.
552 * The DP83840 is first told to start doing it's thing, we set up the time
553 * and place the timer state machine in it's initial state.
554 *
555 * Here the timer peeks at the DP83840 status registers at each click to see
556 * if the auto negotiation has completed, we assume here that the DP83840 PHY
557 * will time out at some point and just tell us what (didn't) happen. For
558 * complete coverage we only allow so many of the ticks at this level to run,
559 * when this has expired we print a warning message and try another strategy.
560 * This "other" strategy is to force the interface into various speed/duplex
561 * configurations and we stop when we see a link-up condition before the
562 * maximum number of "peek" ticks have occurred.
563 *
564 * Once a valid link status has been detected we configure the BigMAC and
565 * the rest of the Happy Meal to speak the most efficient protocol we could
566 * get a clean link for. The priority for link configurations, highest first
567 * is:
568 * 100 Base-T Full Duplex
569 * 100 Base-T Half Duplex
570 * 10 Base-T Full Duplex
571 * 10 Base-T Half Duplex
572 *
573 * We start a new timer now, after a successful auto negotiation status has
574 * been detected. This timer just waits for the link-up bit to get set in
575 * the BMCR of the DP83840. When this occurs we print a kernel log message
576 * describing the link type in use and the fact that it is up.
577 *
578 * If a fatal error of some sort is signalled and detected in the interrupt
579 * service routine, and the chip is reset, or the link is ifconfig'd down
580 * and then back up, this entire process repeats itself all over again.
581 */
582 static int try_next_permutation(struct happy_meal *hp, void __iomem *tregs)
583 {
584 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
585
586 /* Downgrade from full to half duplex. Only possible
587 * via ethtool.
588 */
589 if (hp->sw_bmcr & BMCR_FULLDPLX) {
590 hp->sw_bmcr &= ~(BMCR_FULLDPLX);
591 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
592 return 0;
593 }
594
595 /* Downgrade from 100 to 10. */
596 if (hp->sw_bmcr & BMCR_SPEED100) {
597 hp->sw_bmcr &= ~(BMCR_SPEED100);
598 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
599 return 0;
600 }
601
602 /* We've tried everything. */
603 return -1;
604 }
605
606 static void display_link_mode(struct happy_meal *hp, void __iomem *tregs)
607 {
608 printk(KERN_INFO "%s: Link is up using ", hp->dev->name);
609 if (hp->tcvr_type == external)
610 printk("external ");
611 else
612 printk("internal ");
613 printk("transceiver at ");
614 hp->sw_lpa = happy_meal_tcvr_read(hp, tregs, MII_LPA);
615 if (hp->sw_lpa & (LPA_100HALF | LPA_100FULL)) {
616 if (hp->sw_lpa & LPA_100FULL)
617 printk("100Mb/s, Full Duplex.\n");
618 else
619 printk("100Mb/s, Half Duplex.\n");
620 } else {
621 if (hp->sw_lpa & LPA_10FULL)
622 printk("10Mb/s, Full Duplex.\n");
623 else
624 printk("10Mb/s, Half Duplex.\n");
625 }
626 }
627
628 static void display_forced_link_mode(struct happy_meal *hp, void __iomem *tregs)
629 {
630 printk(KERN_INFO "%s: Link has been forced up using ", hp->dev->name);
631 if (hp->tcvr_type == external)
632 printk("external ");
633 else
634 printk("internal ");
635 printk("transceiver at ");
636 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
637 if (hp->sw_bmcr & BMCR_SPEED100)
638 printk("100Mb/s, ");
639 else
640 printk("10Mb/s, ");
641 if (hp->sw_bmcr & BMCR_FULLDPLX)
642 printk("Full Duplex.\n");
643 else
644 printk("Half Duplex.\n");
645 }
646
647 static int set_happy_link_modes(struct happy_meal *hp, void __iomem *tregs)
648 {
649 int full;
650
651 /* All we care about is making sure the bigmac tx_cfg has a
652 * proper duplex setting.
653 */
654 if (hp->timer_state == arbwait) {
655 hp->sw_lpa = happy_meal_tcvr_read(hp, tregs, MII_LPA);
656 if (!(hp->sw_lpa & (LPA_10HALF | LPA_10FULL | LPA_100HALF | LPA_100FULL)))
657 goto no_response;
658 if (hp->sw_lpa & LPA_100FULL)
659 full = 1;
660 else if (hp->sw_lpa & LPA_100HALF)
661 full = 0;
662 else if (hp->sw_lpa & LPA_10FULL)
663 full = 1;
664 else
665 full = 0;
666 } else {
667 /* Forcing a link mode. */
668 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
669 if (hp->sw_bmcr & BMCR_FULLDPLX)
670 full = 1;
671 else
672 full = 0;
673 }
674
675 /* Before changing other bits in the tx_cfg register, and in
676 * general any of other the TX config registers too, you
677 * must:
678 * 1) Clear Enable
679 * 2) Poll with reads until that bit reads back as zero
680 * 3) Make TX configuration changes
681 * 4) Set Enable once more
682 */
683 hme_write32(hp, hp->bigmacregs + BMAC_TXCFG,
684 hme_read32(hp, hp->bigmacregs + BMAC_TXCFG) &
685 ~(BIGMAC_TXCFG_ENABLE));
686 while (hme_read32(hp, hp->bigmacregs + BMAC_TXCFG) & BIGMAC_TXCFG_ENABLE)
687 barrier();
688 if (full) {
689 hp->happy_flags |= HFLAG_FULL;
690 hme_write32(hp, hp->bigmacregs + BMAC_TXCFG,
691 hme_read32(hp, hp->bigmacregs + BMAC_TXCFG) |
692 BIGMAC_TXCFG_FULLDPLX);
693 } else {
694 hp->happy_flags &= ~(HFLAG_FULL);
695 hme_write32(hp, hp->bigmacregs + BMAC_TXCFG,
696 hme_read32(hp, hp->bigmacregs + BMAC_TXCFG) &
697 ~(BIGMAC_TXCFG_FULLDPLX));
698 }
699 hme_write32(hp, hp->bigmacregs + BMAC_TXCFG,
700 hme_read32(hp, hp->bigmacregs + BMAC_TXCFG) |
701 BIGMAC_TXCFG_ENABLE);
702 return 0;
703 no_response:
704 return 1;
705 }
706
707 static int happy_meal_init(struct happy_meal *hp);
708
709 static int is_lucent_phy(struct happy_meal *hp)
710 {
711 void __iomem *tregs = hp->tcvregs;
712 unsigned short mr2, mr3;
713 int ret = 0;
714
715 mr2 = happy_meal_tcvr_read(hp, tregs, 2);
716 mr3 = happy_meal_tcvr_read(hp, tregs, 3);
717 if ((mr2 & 0xffff) == 0x0180 &&
718 ((mr3 & 0xffff) >> 10) == 0x1d)
719 ret = 1;
720
721 return ret;
722 }
723
724 static void happy_meal_timer(unsigned long data)
725 {
726 struct happy_meal *hp = (struct happy_meal *) data;
727 void __iomem *tregs = hp->tcvregs;
728 int restart_timer = 0;
729
730 spin_lock_irq(&hp->happy_lock);
731
732 hp->timer_ticks++;
733 switch(hp->timer_state) {
734 case arbwait:
735 /* Only allow for 5 ticks, thats 10 seconds and much too
736 * long to wait for arbitration to complete.
737 */
738 if (hp->timer_ticks >= 10) {
739 /* Enter force mode. */
740 do_force_mode:
741 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
742 printk(KERN_NOTICE "%s: Auto-Negotiation unsuccessful, trying force link mode\n",
743 hp->dev->name);
744 hp->sw_bmcr = BMCR_SPEED100;
745 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
746
747 if (!is_lucent_phy(hp)) {
748 /* OK, seems we need do disable the transceiver for the first
749 * tick to make sure we get an accurate link state at the
750 * second tick.
751 */
752 hp->sw_csconfig = happy_meal_tcvr_read(hp, tregs, DP83840_CSCONFIG);
753 hp->sw_csconfig &= ~(CSCONFIG_TCVDISAB);
754 happy_meal_tcvr_write(hp, tregs, DP83840_CSCONFIG, hp->sw_csconfig);
755 }
756 hp->timer_state = ltrywait;
757 hp->timer_ticks = 0;
758 restart_timer = 1;
759 } else {
760 /* Anything interesting happen? */
761 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR);
762 if (hp->sw_bmsr & BMSR_ANEGCOMPLETE) {
763 int ret;
764
765 /* Just what we've been waiting for... */
766 ret = set_happy_link_modes(hp, tregs);
767 if (ret) {
768 /* Ooops, something bad happened, go to force
769 * mode.
770 *
771 * XXX Broken hubs which don't support 802.3u
772 * XXX auto-negotiation make this happen as well.
773 */
774 goto do_force_mode;
775 }
776
777 /* Success, at least so far, advance our state engine. */
778 hp->timer_state = lupwait;
779 restart_timer = 1;
780 } else {
781 restart_timer = 1;
782 }
783 }
784 break;
785
786 case lupwait:
787 /* Auto negotiation was successful and we are awaiting a
788 * link up status. I have decided to let this timer run
789 * forever until some sort of error is signalled, reporting
790 * a message to the user at 10 second intervals.
791 */
792 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR);
793 if (hp->sw_bmsr & BMSR_LSTATUS) {
794 /* Wheee, it's up, display the link mode in use and put
795 * the timer to sleep.
796 */
797 display_link_mode(hp, tregs);
798 hp->timer_state = asleep;
799 restart_timer = 0;
800 } else {
801 if (hp->timer_ticks >= 10) {
802 printk(KERN_NOTICE "%s: Auto negotiation successful, link still "
803 "not completely up.\n", hp->dev->name);
804 hp->timer_ticks = 0;
805 restart_timer = 1;
806 } else {
807 restart_timer = 1;
808 }
809 }
810 break;
811
812 case ltrywait:
813 /* Making the timeout here too long can make it take
814 * annoyingly long to attempt all of the link mode
815 * permutations, but then again this is essentially
816 * error recovery code for the most part.
817 */
818 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR);
819 hp->sw_csconfig = happy_meal_tcvr_read(hp, tregs, DP83840_CSCONFIG);
820 if (hp->timer_ticks == 1) {
821 if (!is_lucent_phy(hp)) {
822 /* Re-enable transceiver, we'll re-enable the transceiver next
823 * tick, then check link state on the following tick.
824 */
825 hp->sw_csconfig |= CSCONFIG_TCVDISAB;
826 happy_meal_tcvr_write(hp, tregs,
827 DP83840_CSCONFIG, hp->sw_csconfig);
828 }
829 restart_timer = 1;
830 break;
831 }
832 if (hp->timer_ticks == 2) {
833 if (!is_lucent_phy(hp)) {
834 hp->sw_csconfig &= ~(CSCONFIG_TCVDISAB);
835 happy_meal_tcvr_write(hp, tregs,
836 DP83840_CSCONFIG, hp->sw_csconfig);
837 }
838 restart_timer = 1;
839 break;
840 }
841 if (hp->sw_bmsr & BMSR_LSTATUS) {
842 /* Force mode selection success. */
843 display_forced_link_mode(hp, tregs);
844 set_happy_link_modes(hp, tregs); /* XXX error? then what? */
845 hp->timer_state = asleep;
846 restart_timer = 0;
847 } else {
848 if (hp->timer_ticks >= 4) { /* 6 seconds or so... */
849 int ret;
850
851 ret = try_next_permutation(hp, tregs);
852 if (ret == -1) {
853 /* Aieee, tried them all, reset the
854 * chip and try all over again.
855 */
856
857 /* Let the user know... */
858 printk(KERN_NOTICE "%s: Link down, cable problem?\n",
859 hp->dev->name);
860
861 ret = happy_meal_init(hp);
862 if (ret) {
863 /* ho hum... */
864 printk(KERN_ERR "%s: Error, cannot re-init the "
865 "Happy Meal.\n", hp->dev->name);
866 }
867 goto out;
868 }
869 if (!is_lucent_phy(hp)) {
870 hp->sw_csconfig = happy_meal_tcvr_read(hp, tregs,
871 DP83840_CSCONFIG);
872 hp->sw_csconfig |= CSCONFIG_TCVDISAB;
873 happy_meal_tcvr_write(hp, tregs,
874 DP83840_CSCONFIG, hp->sw_csconfig);
875 }
876 hp->timer_ticks = 0;
877 restart_timer = 1;
878 } else {
879 restart_timer = 1;
880 }
881 }
882 break;
883
884 case asleep:
885 default:
886 /* Can't happens.... */
887 printk(KERN_ERR "%s: Aieee, link timer is asleep but we got one anyways!\n",
888 hp->dev->name);
889 restart_timer = 0;
890 hp->timer_ticks = 0;
891 hp->timer_state = asleep; /* foo on you */
892 break;
893 };
894
895 if (restart_timer) {
896 hp->happy_timer.expires = jiffies + ((12 * HZ)/10); /* 1.2 sec. */
897 add_timer(&hp->happy_timer);
898 }
899
900 out:
901 spin_unlock_irq(&hp->happy_lock);
902 }
903
904 #define TX_RESET_TRIES 32
905 #define RX_RESET_TRIES 32
906
907 /* hp->happy_lock must be held */
908 static void happy_meal_tx_reset(struct happy_meal *hp, void __iomem *bregs)
909 {
910 int tries = TX_RESET_TRIES;
911
912 HMD(("happy_meal_tx_reset: reset, "));
913
914 /* Would you like to try our SMCC Delux? */
915 hme_write32(hp, bregs + BMAC_TXSWRESET, 0);
916 while ((hme_read32(hp, bregs + BMAC_TXSWRESET) & 1) && --tries)
917 udelay(20);
918
919 /* Lettuce, tomato, buggy hardware (no extra charge)? */
920 if (!tries)
921 printk(KERN_ERR "happy meal: Transceiver BigMac ATTACK!");
922
923 /* Take care. */
924 HMD(("done\n"));
925 }
926
927 /* hp->happy_lock must be held */
928 static void happy_meal_rx_reset(struct happy_meal *hp, void __iomem *bregs)
929 {
930 int tries = RX_RESET_TRIES;
931
932 HMD(("happy_meal_rx_reset: reset, "));
933
934 /* We have a special on GNU/Viking hardware bugs today. */
935 hme_write32(hp, bregs + BMAC_RXSWRESET, 0);
936 while ((hme_read32(hp, bregs + BMAC_RXSWRESET) & 1) && --tries)
937 udelay(20);
938
939 /* Will that be all? */
940 if (!tries)
941 printk(KERN_ERR "happy meal: Receiver BigMac ATTACK!");
942
943 /* Don't forget your vik_1137125_wa. Have a nice day. */
944 HMD(("done\n"));
945 }
946
947 #define STOP_TRIES 16
948
949 /* hp->happy_lock must be held */
950 static void happy_meal_stop(struct happy_meal *hp, void __iomem *gregs)
951 {
952 int tries = STOP_TRIES;
953
954 HMD(("happy_meal_stop: reset, "));
955
956 /* We're consolidating our STB products, it's your lucky day. */
957 hme_write32(hp, gregs + GREG_SWRESET, GREG_RESET_ALL);
958 while (hme_read32(hp, gregs + GREG_SWRESET) && --tries)
959 udelay(20);
960
961 /* Come back next week when we are "Sun Microelectronics". */
962 if (!tries)
963 printk(KERN_ERR "happy meal: Fry guys.");
964
965 /* Remember: "Different name, same old buggy as shit hardware." */
966 HMD(("done\n"));
967 }
968
969 /* hp->happy_lock must be held */
970 static void happy_meal_get_counters(struct happy_meal *hp, void __iomem *bregs)
971 {
972 struct net_device_stats *stats = &hp->net_stats;
973
974 stats->rx_crc_errors += hme_read32(hp, bregs + BMAC_RCRCECTR);
975 hme_write32(hp, bregs + BMAC_RCRCECTR, 0);
976
977 stats->rx_frame_errors += hme_read32(hp, bregs + BMAC_UNALECTR);
978 hme_write32(hp, bregs + BMAC_UNALECTR, 0);
979
980 stats->rx_length_errors += hme_read32(hp, bregs + BMAC_GLECTR);
981 hme_write32(hp, bregs + BMAC_GLECTR, 0);
982
983 stats->tx_aborted_errors += hme_read32(hp, bregs + BMAC_EXCTR);
984
985 stats->collisions +=
986 (hme_read32(hp, bregs + BMAC_EXCTR) +
987 hme_read32(hp, bregs + BMAC_LTCTR));
988 hme_write32(hp, bregs + BMAC_EXCTR, 0);
989 hme_write32(hp, bregs + BMAC_LTCTR, 0);
990 }
991
992 /* hp->happy_lock must be held */
993 static void happy_meal_poll_stop(struct happy_meal *hp, void __iomem *tregs)
994 {
995 ASD(("happy_meal_poll_stop: "));
996
997 /* If polling disabled or not polling already, nothing to do. */
998 if ((hp->happy_flags & (HFLAG_POLLENABLE | HFLAG_POLL)) !=
999 (HFLAG_POLLENABLE | HFLAG_POLL)) {
1000 HMD(("not polling, return\n"));
1001 return;
1002 }
1003
1004 /* Shut up the MIF. */
1005 ASD(("were polling, mif ints off, "));
1006 hme_write32(hp, tregs + TCVR_IMASK, 0xffff);
1007
1008 /* Turn off polling. */
1009 ASD(("polling off, "));
1010 hme_write32(hp, tregs + TCVR_CFG,
1011 hme_read32(hp, tregs + TCVR_CFG) & ~(TCV_CFG_PENABLE));
1012
1013 /* We are no longer polling. */
1014 hp->happy_flags &= ~(HFLAG_POLL);
1015
1016 /* Let the bits set. */
1017 udelay(200);
1018 ASD(("done\n"));
1019 }
1020
1021 /* Only Sun can take such nice parts and fuck up the programming interface
1022 * like this. Good job guys...
1023 */
1024 #define TCVR_RESET_TRIES 16 /* It should reset quickly */
1025 #define TCVR_UNISOLATE_TRIES 32 /* Dis-isolation can take longer. */
1026
1027 /* hp->happy_lock must be held */
1028 static int happy_meal_tcvr_reset(struct happy_meal *hp, void __iomem *tregs)
1029 {
1030 u32 tconfig;
1031 int result, tries = TCVR_RESET_TRIES;
1032
1033 tconfig = hme_read32(hp, tregs + TCVR_CFG);
1034 ASD(("happy_meal_tcvr_reset: tcfg<%08lx> ", tconfig));
1035 if (hp->tcvr_type == external) {
1036 ASD(("external<"));
1037 hme_write32(hp, tregs + TCVR_CFG, tconfig & ~(TCV_CFG_PSELECT));
1038 hp->tcvr_type = internal;
1039 hp->paddr = TCV_PADDR_ITX;
1040 ASD(("ISOLATE,"));
1041 happy_meal_tcvr_write(hp, tregs, MII_BMCR,
1042 (BMCR_LOOPBACK|BMCR_PDOWN|BMCR_ISOLATE));
1043 result = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
1044 if (result == TCVR_FAILURE) {
1045 ASD(("phyread_fail>\n"));
1046 return -1;
1047 }
1048 ASD(("phyread_ok,PSELECT>"));
1049 hme_write32(hp, tregs + TCVR_CFG, tconfig | TCV_CFG_PSELECT);
1050 hp->tcvr_type = external;
1051 hp->paddr = TCV_PADDR_ETX;
1052 } else {
1053 if (tconfig & TCV_CFG_MDIO1) {
1054 ASD(("internal<PSELECT,"));
1055 hme_write32(hp, tregs + TCVR_CFG, (tconfig | TCV_CFG_PSELECT));
1056 ASD(("ISOLATE,"));
1057 happy_meal_tcvr_write(hp, tregs, MII_BMCR,
1058 (BMCR_LOOPBACK|BMCR_PDOWN|BMCR_ISOLATE));
1059 result = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
1060 if (result == TCVR_FAILURE) {
1061 ASD(("phyread_fail>\n"));
1062 return -1;
1063 }
1064 ASD(("phyread_ok,~PSELECT>"));
1065 hme_write32(hp, tregs + TCVR_CFG, (tconfig & ~(TCV_CFG_PSELECT)));
1066 hp->tcvr_type = internal;
1067 hp->paddr = TCV_PADDR_ITX;
1068 }
1069 }
1070
1071 ASD(("BMCR_RESET "));
1072 happy_meal_tcvr_write(hp, tregs, MII_BMCR, BMCR_RESET);
1073
1074 while (--tries) {
1075 result = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
1076 if (result == TCVR_FAILURE)
1077 return -1;
1078 hp->sw_bmcr = result;
1079 if (!(result & BMCR_RESET))
1080 break;
1081 udelay(20);
1082 }
1083 if (!tries) {
1084 ASD(("BMCR RESET FAILED!\n"));
1085 return -1;
1086 }
1087 ASD(("RESET_OK\n"));
1088
1089 /* Get fresh copies of the PHY registers. */
1090 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR);
1091 hp->sw_physid1 = happy_meal_tcvr_read(hp, tregs, MII_PHYSID1);
1092 hp->sw_physid2 = happy_meal_tcvr_read(hp, tregs, MII_PHYSID2);
1093 hp->sw_advertise = happy_meal_tcvr_read(hp, tregs, MII_ADVERTISE);
1094
1095 ASD(("UNISOLATE"));
1096 hp->sw_bmcr &= ~(BMCR_ISOLATE);
1097 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
1098
1099 tries = TCVR_UNISOLATE_TRIES;
1100 while (--tries) {
1101 result = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
1102 if (result == TCVR_FAILURE)
1103 return -1;
1104 if (!(result & BMCR_ISOLATE))
1105 break;
1106 udelay(20);
1107 }
1108 if (!tries) {
1109 ASD((" FAILED!\n"));
1110 return -1;
1111 }
1112 ASD((" SUCCESS and CSCONFIG_DFBYPASS\n"));
1113 if (!is_lucent_phy(hp)) {
1114 result = happy_meal_tcvr_read(hp, tregs,
1115 DP83840_CSCONFIG);
1116 happy_meal_tcvr_write(hp, tregs,
1117 DP83840_CSCONFIG, (result | CSCONFIG_DFBYPASS));
1118 }
1119 return 0;
1120 }
1121
1122 /* Figure out whether we have an internal or external transceiver.
1123 *
1124 * hp->happy_lock must be held
1125 */
1126 static void happy_meal_transceiver_check(struct happy_meal *hp, void __iomem *tregs)
1127 {
1128 unsigned long tconfig = hme_read32(hp, tregs + TCVR_CFG);
1129
1130 ASD(("happy_meal_transceiver_check: tcfg=%08lx ", tconfig));
1131 if (hp->happy_flags & HFLAG_POLL) {
1132 /* If we are polling, we must stop to get the transceiver type. */
1133 ASD(("<polling> "));
1134 if (hp->tcvr_type == internal) {
1135 if (tconfig & TCV_CFG_MDIO1) {
1136 ASD(("<internal> <poll stop> "));
1137 happy_meal_poll_stop(hp, tregs);
1138 hp->paddr = TCV_PADDR_ETX;
1139 hp->tcvr_type = external;
1140 ASD(("<external>\n"));
1141 tconfig &= ~(TCV_CFG_PENABLE);
1142 tconfig |= TCV_CFG_PSELECT;
1143 hme_write32(hp, tregs + TCVR_CFG, tconfig);
1144 }
1145 } else {
1146 if (hp->tcvr_type == external) {
1147 ASD(("<external> "));
1148 if (!(hme_read32(hp, tregs + TCVR_STATUS) >> 16)) {
1149 ASD(("<poll stop> "));
1150 happy_meal_poll_stop(hp, tregs);
1151 hp->paddr = TCV_PADDR_ITX;
1152 hp->tcvr_type = internal;
1153 ASD(("<internal>\n"));
1154 hme_write32(hp, tregs + TCVR_CFG,
1155 hme_read32(hp, tregs + TCVR_CFG) &
1156 ~(TCV_CFG_PSELECT));
1157 }
1158 ASD(("\n"));
1159 } else {
1160 ASD(("<none>\n"));
1161 }
1162 }
1163 } else {
1164 u32 reread = hme_read32(hp, tregs + TCVR_CFG);
1165
1166 /* Else we can just work off of the MDIO bits. */
1167 ASD(("<not polling> "));
1168 if (reread & TCV_CFG_MDIO1) {
1169 hme_write32(hp, tregs + TCVR_CFG, tconfig | TCV_CFG_PSELECT);
1170 hp->paddr = TCV_PADDR_ETX;
1171 hp->tcvr_type = external;
1172 ASD(("<external>\n"));
1173 } else {
1174 if (reread & TCV_CFG_MDIO0) {
1175 hme_write32(hp, tregs + TCVR_CFG,
1176 tconfig & ~(TCV_CFG_PSELECT));
1177 hp->paddr = TCV_PADDR_ITX;
1178 hp->tcvr_type = internal;
1179 ASD(("<internal>\n"));
1180 } else {
1181 printk(KERN_ERR "happy meal: Transceiver and a coke please.");
1182 hp->tcvr_type = none; /* Grrr... */
1183 ASD(("<none>\n"));
1184 }
1185 }
1186 }
1187 }
1188
1189 /* The receive ring buffers are a bit tricky to get right. Here goes...
1190 *
1191 * The buffers we dma into must be 64 byte aligned. So we use a special
1192 * alloc_skb() routine for the happy meal to allocate 64 bytes more than
1193 * we really need.
1194 *
1195 * We use skb_reserve() to align the data block we get in the skb. We
1196 * also program the etxregs->cfg register to use an offset of 2. This
1197 * imperical constant plus the ethernet header size will always leave
1198 * us with a nicely aligned ip header once we pass things up to the
1199 * protocol layers.
1200 *
1201 * The numbers work out to:
1202 *
1203 * Max ethernet frame size 1518
1204 * Ethernet header size 14
1205 * Happy Meal base offset 2
1206 *
1207 * Say a skb data area is at 0xf001b010, and its size alloced is
1208 * (ETH_FRAME_LEN + 64 + 2) = (1514 + 64 + 2) = 1580 bytes.
1209 *
1210 * First our alloc_skb() routine aligns the data base to a 64 byte
1211 * boundary. We now have 0xf001b040 as our skb data address. We
1212 * plug this into the receive descriptor address.
1213 *
1214 * Next, we skb_reserve() 2 bytes to account for the Happy Meal offset.
1215 * So now the data we will end up looking at starts at 0xf001b042. When
1216 * the packet arrives, we will check out the size received and subtract
1217 * this from the skb->length. Then we just pass the packet up to the
1218 * protocols as is, and allocate a new skb to replace this slot we have
1219 * just received from.
1220 *
1221 * The ethernet layer will strip the ether header from the front of the
1222 * skb we just sent to it, this leaves us with the ip header sitting
1223 * nicely aligned at 0xf001b050. Also, for tcp and udp packets the
1224 * Happy Meal has even checksummed the tcp/udp data for us. The 16
1225 * bit checksum is obtained from the low bits of the receive descriptor
1226 * flags, thus:
1227 *
1228 * skb->csum = rxd->rx_flags & 0xffff;
1229 * skb->ip_summed = CHECKSUM_HW;
1230 *
1231 * before sending off the skb to the protocols, and we are good as gold.
1232 */
1233 static void happy_meal_clean_rings(struct happy_meal *hp)
1234 {
1235 int i;
1236
1237 for (i = 0; i < RX_RING_SIZE; i++) {
1238 if (hp->rx_skbs[i] != NULL) {
1239 struct sk_buff *skb = hp->rx_skbs[i];
1240 struct happy_meal_rxd *rxd;
1241 u32 dma_addr;
1242
1243 rxd = &hp->happy_block->happy_meal_rxd[i];
1244 dma_addr = hme_read_desc32(hp, &rxd->rx_addr);
1245 hme_dma_unmap(hp, dma_addr, RX_BUF_ALLOC_SIZE, DMA_FROMDEVICE);
1246 dev_kfree_skb_any(skb);
1247 hp->rx_skbs[i] = NULL;
1248 }
1249 }
1250
1251 for (i = 0; i < TX_RING_SIZE; i++) {
1252 if (hp->tx_skbs[i] != NULL) {
1253 struct sk_buff *skb = hp->tx_skbs[i];
1254 struct happy_meal_txd *txd;
1255 u32 dma_addr;
1256 int frag;
1257
1258 hp->tx_skbs[i] = NULL;
1259
1260 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
1261 txd = &hp->happy_block->happy_meal_txd[i];
1262 dma_addr = hme_read_desc32(hp, &txd->tx_addr);
1263 hme_dma_unmap(hp, dma_addr,
1264 (hme_read_desc32(hp, &txd->tx_flags)
1265 & TXFLAG_SIZE),
1266 DMA_TODEVICE);
1267
1268 if (frag != skb_shinfo(skb)->nr_frags)
1269 i++;
1270 }
1271
1272 dev_kfree_skb_any(skb);
1273 }
1274 }
1275 }
1276
1277 /* hp->happy_lock must be held */
1278 static void happy_meal_init_rings(struct happy_meal *hp)
1279 {
1280 struct hmeal_init_block *hb = hp->happy_block;
1281 struct net_device *dev = hp->dev;
1282 int i;
1283
1284 HMD(("happy_meal_init_rings: counters to zero, "));
1285 hp->rx_new = hp->rx_old = hp->tx_new = hp->tx_old = 0;
1286
1287 /* Free any skippy bufs left around in the rings. */
1288 HMD(("clean, "));
1289 happy_meal_clean_rings(hp);
1290
1291 /* Now get new skippy bufs for the receive ring. */
1292 HMD(("init rxring, "));
1293 for (i = 0; i < RX_RING_SIZE; i++) {
1294 struct sk_buff *skb;
1295
1296 skb = happy_meal_alloc_skb(RX_BUF_ALLOC_SIZE, GFP_ATOMIC);
1297 if (!skb) {
1298 hme_write_rxd(hp, &hb->happy_meal_rxd[i], 0, 0);
1299 continue;
1300 }
1301 hp->rx_skbs[i] = skb;
1302 skb->dev = dev;
1303
1304 /* Because we reserve afterwards. */
1305 skb_put(skb, (ETH_FRAME_LEN + RX_OFFSET));
1306 hme_write_rxd(hp, &hb->happy_meal_rxd[i],
1307 (RXFLAG_OWN | ((RX_BUF_ALLOC_SIZE - RX_OFFSET) << 16)),
1308 hme_dma_map(hp, skb->data, RX_BUF_ALLOC_SIZE, DMA_FROMDEVICE));
1309 skb_reserve(skb, RX_OFFSET);
1310 }
1311
1312 HMD(("init txring, "));
1313 for (i = 0; i < TX_RING_SIZE; i++)
1314 hme_write_txd(hp, &hb->happy_meal_txd[i], 0, 0);
1315
1316 HMD(("done\n"));
1317 }
1318
1319 /* hp->happy_lock must be held */
1320 static void happy_meal_begin_auto_negotiation(struct happy_meal *hp,
1321 void __iomem *tregs,
1322 struct ethtool_cmd *ep)
1323 {
1324 int timeout;
1325
1326 /* Read all of the registers we are interested in now. */
1327 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR);
1328 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
1329 hp->sw_physid1 = happy_meal_tcvr_read(hp, tregs, MII_PHYSID1);
1330 hp->sw_physid2 = happy_meal_tcvr_read(hp, tregs, MII_PHYSID2);
1331
1332 /* XXX Check BMSR_ANEGCAPABLE, should not be necessary though. */
1333
1334 hp->sw_advertise = happy_meal_tcvr_read(hp, tregs, MII_ADVERTISE);
1335 if (ep == NULL || ep->autoneg == AUTONEG_ENABLE) {
1336 /* Advertise everything we can support. */
1337 if (hp->sw_bmsr & BMSR_10HALF)
1338 hp->sw_advertise |= (ADVERTISE_10HALF);
1339 else
1340 hp->sw_advertise &= ~(ADVERTISE_10HALF);
1341
1342 if (hp->sw_bmsr & BMSR_10FULL)
1343 hp->sw_advertise |= (ADVERTISE_10FULL);
1344 else
1345 hp->sw_advertise &= ~(ADVERTISE_10FULL);
1346 if (hp->sw_bmsr & BMSR_100HALF)
1347 hp->sw_advertise |= (ADVERTISE_100HALF);
1348 else
1349 hp->sw_advertise &= ~(ADVERTISE_100HALF);
1350 if (hp->sw_bmsr & BMSR_100FULL)
1351 hp->sw_advertise |= (ADVERTISE_100FULL);
1352 else
1353 hp->sw_advertise &= ~(ADVERTISE_100FULL);
1354 happy_meal_tcvr_write(hp, tregs, MII_ADVERTISE, hp->sw_advertise);
1355
1356 /* XXX Currently no Happy Meal cards I know off support 100BaseT4,
1357 * XXX and this is because the DP83840 does not support it, changes
1358 * XXX would need to be made to the tx/rx logic in the driver as well
1359 * XXX so I completely skip checking for it in the BMSR for now.
1360 */
1361
1362 #ifdef AUTO_SWITCH_DEBUG
1363 ASD(("%s: Advertising [ ", hp->dev->name));
1364 if (hp->sw_advertise & ADVERTISE_10HALF)
1365 ASD(("10H "));
1366 if (hp->sw_advertise & ADVERTISE_10FULL)
1367 ASD(("10F "));
1368 if (hp->sw_advertise & ADVERTISE_100HALF)
1369 ASD(("100H "));
1370 if (hp->sw_advertise & ADVERTISE_100FULL)
1371 ASD(("100F "));
1372 #endif
1373
1374 /* Enable Auto-Negotiation, this is usually on already... */
1375 hp->sw_bmcr |= BMCR_ANENABLE;
1376 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
1377
1378 /* Restart it to make sure it is going. */
1379 hp->sw_bmcr |= BMCR_ANRESTART;
1380 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
1381
1382 /* BMCR_ANRESTART self clears when the process has begun. */
1383
1384 timeout = 64; /* More than enough. */
1385 while (--timeout) {
1386 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
1387 if (!(hp->sw_bmcr & BMCR_ANRESTART))
1388 break; /* got it. */
1389 udelay(10);
1390 }
1391 if (!timeout) {
1392 printk(KERN_ERR "%s: Happy Meal would not start auto negotiation "
1393 "BMCR=0x%04x\n", hp->dev->name, hp->sw_bmcr);
1394 printk(KERN_NOTICE "%s: Performing force link detection.\n",
1395 hp->dev->name);
1396 goto force_link;
1397 } else {
1398 hp->timer_state = arbwait;
1399 }
1400 } else {
1401 force_link:
1402 /* Force the link up, trying first a particular mode.
1403 * Either we are here at the request of ethtool or
1404 * because the Happy Meal would not start to autoneg.
1405 */
1406
1407 /* Disable auto-negotiation in BMCR, enable the duplex and
1408 * speed setting, init the timer state machine, and fire it off.
1409 */
1410 if (ep == NULL || ep->autoneg == AUTONEG_ENABLE) {
1411 hp->sw_bmcr = BMCR_SPEED100;
1412 } else {
1413 if (ep->speed == SPEED_100)
1414 hp->sw_bmcr = BMCR_SPEED100;
1415 else
1416 hp->sw_bmcr = 0;
1417 if (ep->duplex == DUPLEX_FULL)
1418 hp->sw_bmcr |= BMCR_FULLDPLX;
1419 }
1420 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
1421
1422 if (!is_lucent_phy(hp)) {
1423 /* OK, seems we need do disable the transceiver for the first
1424 * tick to make sure we get an accurate link state at the
1425 * second tick.
1426 */
1427 hp->sw_csconfig = happy_meal_tcvr_read(hp, tregs,
1428 DP83840_CSCONFIG);
1429 hp->sw_csconfig &= ~(CSCONFIG_TCVDISAB);
1430 happy_meal_tcvr_write(hp, tregs, DP83840_CSCONFIG,
1431 hp->sw_csconfig);
1432 }
1433 hp->timer_state = ltrywait;
1434 }
1435
1436 hp->timer_ticks = 0;
1437 hp->happy_timer.expires = jiffies + (12 * HZ)/10; /* 1.2 sec. */
1438 hp->happy_timer.data = (unsigned long) hp;
1439 hp->happy_timer.function = &happy_meal_timer;
1440 add_timer(&hp->happy_timer);
1441 }
1442
1443 /* hp->happy_lock must be held */
1444 static int happy_meal_init(struct happy_meal *hp)
1445 {
1446 void __iomem *gregs = hp->gregs;
1447 void __iomem *etxregs = hp->etxregs;
1448 void __iomem *erxregs = hp->erxregs;
1449 void __iomem *bregs = hp->bigmacregs;
1450 void __iomem *tregs = hp->tcvregs;
1451 u32 regtmp, rxcfg;
1452 unsigned char *e = &hp->dev->dev_addr[0];
1453
1454 /* If auto-negotiation timer is running, kill it. */
1455 del_timer(&hp->happy_timer);
1456
1457 HMD(("happy_meal_init: happy_flags[%08x] ",
1458 hp->happy_flags));
1459 if (!(hp->happy_flags & HFLAG_INIT)) {
1460 HMD(("set HFLAG_INIT, "));
1461 hp->happy_flags |= HFLAG_INIT;
1462 happy_meal_get_counters(hp, bregs);
1463 }
1464
1465 /* Stop polling. */
1466 HMD(("to happy_meal_poll_stop\n"));
1467 happy_meal_poll_stop(hp, tregs);
1468
1469 /* Stop transmitter and receiver. */
1470 HMD(("happy_meal_init: to happy_meal_stop\n"));
1471 happy_meal_stop(hp, gregs);
1472
1473 /* Alloc and reset the tx/rx descriptor chains. */
1474 HMD(("happy_meal_init: to happy_meal_init_rings\n"));
1475 happy_meal_init_rings(hp);
1476
1477 /* Shut up the MIF. */
1478 HMD(("happy_meal_init: Disable all MIF irqs (old[%08x]), ",
1479 hme_read32(hp, tregs + TCVR_IMASK)));
1480 hme_write32(hp, tregs + TCVR_IMASK, 0xffff);
1481
1482 /* See if we can enable the MIF frame on this card to speak to the DP83840. */
1483 if (hp->happy_flags & HFLAG_FENABLE) {
1484 HMD(("use frame old[%08x], ",
1485 hme_read32(hp, tregs + TCVR_CFG)));
1486 hme_write32(hp, tregs + TCVR_CFG,
1487 hme_read32(hp, tregs + TCVR_CFG) & ~(TCV_CFG_BENABLE));
1488 } else {
1489 HMD(("use bitbang old[%08x], ",
1490 hme_read32(hp, tregs + TCVR_CFG)));
1491 hme_write32(hp, tregs + TCVR_CFG,
1492 hme_read32(hp, tregs + TCVR_CFG) | TCV_CFG_BENABLE);
1493 }
1494
1495 /* Check the state of the transceiver. */
1496 HMD(("to happy_meal_transceiver_check\n"));
1497 happy_meal_transceiver_check(hp, tregs);
1498
1499 /* Put the Big Mac into a sane state. */
1500 HMD(("happy_meal_init: "));
1501 switch(hp->tcvr_type) {
1502 case none:
1503 /* Cannot operate if we don't know the transceiver type! */
1504 HMD(("AAIEEE no transceiver type, EAGAIN"));
1505 return -EAGAIN;
1506
1507 case internal:
1508 /* Using the MII buffers. */
1509 HMD(("internal, using MII, "));
1510 hme_write32(hp, bregs + BMAC_XIFCFG, 0);
1511 break;
1512
1513 case external:
1514 /* Not using the MII, disable it. */
1515 HMD(("external, disable MII, "));
1516 hme_write32(hp, bregs + BMAC_XIFCFG, BIGMAC_XCFG_MIIDISAB);
1517 break;
1518 };
1519
1520 if (happy_meal_tcvr_reset(hp, tregs))
1521 return -EAGAIN;
1522
1523 /* Reset the Happy Meal Big Mac transceiver and the receiver. */
1524 HMD(("tx/rx reset, "));
1525 happy_meal_tx_reset(hp, bregs);
1526 happy_meal_rx_reset(hp, bregs);
1527
1528 /* Set jam size and inter-packet gaps to reasonable defaults. */
1529 HMD(("jsize/ipg1/ipg2, "));
1530 hme_write32(hp, bregs + BMAC_JSIZE, DEFAULT_JAMSIZE);
1531 hme_write32(hp, bregs + BMAC_IGAP1, DEFAULT_IPG1);
1532 hme_write32(hp, bregs + BMAC_IGAP2, DEFAULT_IPG2);
1533
1534 /* Load up the MAC address and random seed. */
1535 HMD(("rseed/macaddr, "));
1536
1537 /* The docs recommend to use the 10LSB of our MAC here. */
1538 hme_write32(hp, bregs + BMAC_RSEED, ((e[5] | e[4]<<8)&0x3ff));
1539
1540 hme_write32(hp, bregs + BMAC_MACADDR2, ((e[4] << 8) | e[5]));
1541 hme_write32(hp, bregs + BMAC_MACADDR1, ((e[2] << 8) | e[3]));
1542 hme_write32(hp, bregs + BMAC_MACADDR0, ((e[0] << 8) | e[1]));
1543
1544 HMD(("htable, "));
1545 if ((hp->dev->flags & IFF_ALLMULTI) ||
1546 (hp->dev->mc_count > 64)) {
1547 hme_write32(hp, bregs + BMAC_HTABLE0, 0xffff);
1548 hme_write32(hp, bregs + BMAC_HTABLE1, 0xffff);
1549 hme_write32(hp, bregs + BMAC_HTABLE2, 0xffff);
1550 hme_write32(hp, bregs + BMAC_HTABLE3, 0xffff);
1551 } else if ((hp->dev->flags & IFF_PROMISC) == 0) {
1552 u16 hash_table[4];
1553 struct dev_mc_list *dmi = hp->dev->mc_list;
1554 char *addrs;
1555 int i;
1556 u32 crc;
1557
1558 for (i = 0; i < 4; i++)
1559 hash_table[i] = 0;
1560
1561 for (i = 0; i < hp->dev->mc_count; i++) {
1562 addrs = dmi->dmi_addr;
1563 dmi = dmi->next;
1564
1565 if (!(*addrs & 1))
1566 continue;
1567
1568 crc = ether_crc_le(6, addrs);
1569 crc >>= 26;
1570 hash_table[crc >> 4] |= 1 << (crc & 0xf);
1571 }
1572 hme_write32(hp, bregs + BMAC_HTABLE0, hash_table[0]);
1573 hme_write32(hp, bregs + BMAC_HTABLE1, hash_table[1]);
1574 hme_write32(hp, bregs + BMAC_HTABLE2, hash_table[2]);
1575 hme_write32(hp, bregs + BMAC_HTABLE3, hash_table[3]);
1576 } else {
1577 hme_write32(hp, bregs + BMAC_HTABLE3, 0);
1578 hme_write32(hp, bregs + BMAC_HTABLE2, 0);
1579 hme_write32(hp, bregs + BMAC_HTABLE1, 0);
1580 hme_write32(hp, bregs + BMAC_HTABLE0, 0);
1581 }
1582
1583 /* Set the RX and TX ring ptrs. */
1584 HMD(("ring ptrs rxr[%08x] txr[%08x]\n",
1585 ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_rxd, 0)),
1586 ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_txd, 0))));
1587 hme_write32(hp, erxregs + ERX_RING,
1588 ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_rxd, 0)));
1589 hme_write32(hp, etxregs + ETX_RING,
1590 ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_txd, 0)));
1591
1592 /* Parity issues in the ERX unit of some HME revisions can cause some
1593 * registers to not be written unless their parity is even. Detect such
1594 * lost writes and simply rewrite with a low bit set (which will be ignored
1595 * since the rxring needs to be 2K aligned).
1596 */
1597 if (hme_read32(hp, erxregs + ERX_RING) !=
1598 ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_rxd, 0)))
1599 hme_write32(hp, erxregs + ERX_RING,
1600 ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_rxd, 0))
1601 | 0x4);
1602
1603 /* Set the supported burst sizes. */
1604 HMD(("happy_meal_init: old[%08x] bursts<",
1605 hme_read32(hp, gregs + GREG_CFG)));
1606
1607 #ifndef __sparc__
1608 /* It is always PCI and can handle 64byte bursts. */
1609 hme_write32(hp, gregs + GREG_CFG, GREG_CFG_BURST64);
1610 #else
1611 if ((hp->happy_bursts & DMA_BURST64) &&
1612 ((hp->happy_flags & HFLAG_PCI) != 0
1613 #ifdef CONFIG_SBUS
1614 || sbus_can_burst64(hp->happy_dev)
1615 #endif
1616 || 0)) {
1617 u32 gcfg = GREG_CFG_BURST64;
1618
1619 /* I have no idea if I should set the extended
1620 * transfer mode bit for Cheerio, so for now I
1621 * do not. -DaveM
1622 */
1623 #ifdef CONFIG_SBUS
1624 if ((hp->happy_flags & HFLAG_PCI) == 0 &&
1625 sbus_can_dma_64bit(hp->happy_dev)) {
1626 sbus_set_sbus64(hp->happy_dev,
1627 hp->happy_bursts);
1628 gcfg |= GREG_CFG_64BIT;
1629 }
1630 #endif
1631
1632 HMD(("64>"));
1633 hme_write32(hp, gregs + GREG_CFG, gcfg);
1634 } else if (hp->happy_bursts & DMA_BURST32) {
1635 HMD(("32>"));
1636 hme_write32(hp, gregs + GREG_CFG, GREG_CFG_BURST32);
1637 } else if (hp->happy_bursts & DMA_BURST16) {
1638 HMD(("16>"));
1639 hme_write32(hp, gregs + GREG_CFG, GREG_CFG_BURST16);
1640 } else {
1641 HMD(("XXX>"));
1642 hme_write32(hp, gregs + GREG_CFG, 0);
1643 }
1644 #endif /* __sparc__ */
1645
1646 /* Turn off interrupts we do not want to hear. */
1647 HMD((", enable global interrupts, "));
1648 hme_write32(hp, gregs + GREG_IMASK,
1649 (GREG_IMASK_GOTFRAME | GREG_IMASK_RCNTEXP |
1650 GREG_IMASK_SENTFRAME | GREG_IMASK_TXPERR));
1651
1652 /* Set the transmit ring buffer size. */
1653 HMD(("tx rsize=%d oreg[%08x], ", (int)TX_RING_SIZE,
1654 hme_read32(hp, etxregs + ETX_RSIZE)));
1655 hme_write32(hp, etxregs + ETX_RSIZE, (TX_RING_SIZE >> ETX_RSIZE_SHIFT) - 1);
1656
1657 /* Enable transmitter DVMA. */
1658 HMD(("tx dma enable old[%08x], ",
1659 hme_read32(hp, etxregs + ETX_CFG)));
1660 hme_write32(hp, etxregs + ETX_CFG,
1661 hme_read32(hp, etxregs + ETX_CFG) | ETX_CFG_DMAENABLE);
1662
1663 /* This chip really rots, for the receiver sometimes when you
1664 * write to its control registers not all the bits get there
1665 * properly. I cannot think of a sane way to provide complete
1666 * coverage for this hardware bug yet.
1667 */
1668 HMD(("erx regs bug old[%08x]\n",
1669 hme_read32(hp, erxregs + ERX_CFG)));
1670 hme_write32(hp, erxregs + ERX_CFG, ERX_CFG_DEFAULT(RX_OFFSET));
1671 regtmp = hme_read32(hp, erxregs + ERX_CFG);
1672 hme_write32(hp, erxregs + ERX_CFG, ERX_CFG_DEFAULT(RX_OFFSET));
1673 if (hme_read32(hp, erxregs + ERX_CFG) != ERX_CFG_DEFAULT(RX_OFFSET)) {
1674 printk(KERN_ERR "happy meal: Eieee, rx config register gets greasy fries.\n");
1675 printk(KERN_ERR "happy meal: Trying to set %08x, reread gives %08x\n",
1676 ERX_CFG_DEFAULT(RX_OFFSET), regtmp);
1677 /* XXX Should return failure here... */
1678 }
1679
1680 /* Enable Big Mac hash table filter. */
1681 HMD(("happy_meal_init: enable hash rx_cfg_old[%08x], ",
1682 hme_read32(hp, bregs + BMAC_RXCFG)));
1683 rxcfg = BIGMAC_RXCFG_HENABLE | BIGMAC_RXCFG_REJME;
1684 if (hp->dev->flags & IFF_PROMISC)
1685 rxcfg |= BIGMAC_RXCFG_PMISC;
1686 hme_write32(hp, bregs + BMAC_RXCFG, rxcfg);
1687
1688 /* Let the bits settle in the chip. */
1689 udelay(10);
1690
1691 /* Ok, configure the Big Mac transmitter. */
1692 HMD(("BIGMAC init, "));
1693 regtmp = 0;
1694 if (hp->happy_flags & HFLAG_FULL)
1695 regtmp |= BIGMAC_TXCFG_FULLDPLX;
1696
1697 /* Don't turn on the "don't give up" bit for now. It could cause hme
1698 * to deadlock with the PHY if a Jabber occurs.
1699 */
1700 hme_write32(hp, bregs + BMAC_TXCFG, regtmp /*| BIGMAC_TXCFG_DGIVEUP*/);
1701
1702 /* Give up after 16 TX attempts. */
1703 hme_write32(hp, bregs + BMAC_ALIMIT, 16);
1704
1705 /* Enable the output drivers no matter what. */
1706 regtmp = BIGMAC_XCFG_ODENABLE;
1707
1708 /* If card can do lance mode, enable it. */
1709 if (hp->happy_flags & HFLAG_LANCE)
1710 regtmp |= (DEFAULT_IPG0 << 5) | BIGMAC_XCFG_LANCE;
1711
1712 /* Disable the MII buffers if using external transceiver. */
1713 if (hp->tcvr_type == external)
1714 regtmp |= BIGMAC_XCFG_MIIDISAB;
1715
1716 HMD(("XIF config old[%08x], ",
1717 hme_read32(hp, bregs + BMAC_XIFCFG)));
1718 hme_write32(hp, bregs + BMAC_XIFCFG, regtmp);
1719
1720 /* Start things up. */
1721 HMD(("tx old[%08x] and rx [%08x] ON!\n",
1722 hme_read32(hp, bregs + BMAC_TXCFG),
1723 hme_read32(hp, bregs + BMAC_RXCFG)));
1724 hme_write32(hp, bregs + BMAC_TXCFG,
1725 hme_read32(hp, bregs + BMAC_TXCFG) | BIGMAC_TXCFG_ENABLE);
1726 hme_write32(hp, bregs + BMAC_RXCFG,
1727 hme_read32(hp, bregs + BMAC_RXCFG) | BIGMAC_RXCFG_ENABLE);
1728
1729 /* Get the autonegotiation started, and the watch timer ticking. */
1730 happy_meal_begin_auto_negotiation(hp, tregs, NULL);
1731
1732 /* Success. */
1733 return 0;
1734 }
1735
1736 /* hp->happy_lock must be held */
1737 static void happy_meal_set_initial_advertisement(struct happy_meal *hp)
1738 {
1739 void __iomem *tregs = hp->tcvregs;
1740 void __iomem *bregs = hp->bigmacregs;
1741 void __iomem *gregs = hp->gregs;
1742
1743 happy_meal_stop(hp, gregs);
1744 hme_write32(hp, tregs + TCVR_IMASK, 0xffff);
1745 if (hp->happy_flags & HFLAG_FENABLE)
1746 hme_write32(hp, tregs + TCVR_CFG,
1747 hme_read32(hp, tregs + TCVR_CFG) & ~(TCV_CFG_BENABLE));
1748 else
1749 hme_write32(hp, tregs + TCVR_CFG,
1750 hme_read32(hp, tregs + TCVR_CFG) | TCV_CFG_BENABLE);
1751 happy_meal_transceiver_check(hp, tregs);
1752 switch(hp->tcvr_type) {
1753 case none:
1754 return;
1755 case internal:
1756 hme_write32(hp, bregs + BMAC_XIFCFG, 0);
1757 break;
1758 case external:
1759 hme_write32(hp, bregs + BMAC_XIFCFG, BIGMAC_XCFG_MIIDISAB);
1760 break;
1761 };
1762 if (happy_meal_tcvr_reset(hp, tregs))
1763 return;
1764
1765 /* Latch PHY registers as of now. */
1766 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR);
1767 hp->sw_advertise = happy_meal_tcvr_read(hp, tregs, MII_ADVERTISE);
1768
1769 /* Advertise everything we can support. */
1770 if (hp->sw_bmsr & BMSR_10HALF)
1771 hp->sw_advertise |= (ADVERTISE_10HALF);
1772 else
1773 hp->sw_advertise &= ~(ADVERTISE_10HALF);
1774
1775 if (hp->sw_bmsr & BMSR_10FULL)
1776 hp->sw_advertise |= (ADVERTISE_10FULL);
1777 else
1778 hp->sw_advertise &= ~(ADVERTISE_10FULL);
1779 if (hp->sw_bmsr & BMSR_100HALF)
1780 hp->sw_advertise |= (ADVERTISE_100HALF);
1781 else
1782 hp->sw_advertise &= ~(ADVERTISE_100HALF);
1783 if (hp->sw_bmsr & BMSR_100FULL)
1784 hp->sw_advertise |= (ADVERTISE_100FULL);
1785 else
1786 hp->sw_advertise &= ~(ADVERTISE_100FULL);
1787
1788 /* Update the PHY advertisement register. */
1789 happy_meal_tcvr_write(hp, tregs, MII_ADVERTISE, hp->sw_advertise);
1790 }
1791
1792 /* Once status is latched (by happy_meal_interrupt) it is cleared by
1793 * the hardware, so we cannot re-read it and get a correct value.
1794 *
1795 * hp->happy_lock must be held
1796 */
1797 static int happy_meal_is_not_so_happy(struct happy_meal *hp, u32 status)
1798 {
1799 int reset = 0;
1800
1801 /* Only print messages for non-counter related interrupts. */
1802 if (status & (GREG_STAT_STSTERR | GREG_STAT_TFIFO_UND |
1803 GREG_STAT_MAXPKTERR | GREG_STAT_RXERR |
1804 GREG_STAT_RXPERR | GREG_STAT_RXTERR | GREG_STAT_EOPERR |
1805 GREG_STAT_MIFIRQ | GREG_STAT_TXEACK | GREG_STAT_TXLERR |
1806 GREG_STAT_TXPERR | GREG_STAT_TXTERR | GREG_STAT_SLVERR |
1807 GREG_STAT_SLVPERR))
1808 printk(KERN_ERR "%s: Error interrupt for happy meal, status = %08x\n",
1809 hp->dev->name, status);
1810
1811 if (status & GREG_STAT_RFIFOVF) {
1812 /* Receive FIFO overflow is harmless and the hardware will take
1813 care of it, just some packets are lost. Who cares. */
1814 printk(KERN_DEBUG "%s: Happy Meal receive FIFO overflow.\n", hp->dev->name);
1815 }
1816
1817 if (status & GREG_STAT_STSTERR) {
1818 /* BigMAC SQE link test failed. */
1819 printk(KERN_ERR "%s: Happy Meal BigMAC SQE test failed.\n", hp->dev->name);
1820 reset = 1;
1821 }
1822
1823 if (status & GREG_STAT_TFIFO_UND) {
1824 /* Transmit FIFO underrun, again DMA error likely. */
1825 printk(KERN_ERR "%s: Happy Meal transmitter FIFO underrun, DMA error.\n",
1826 hp->dev->name);
1827 reset = 1;
1828 }
1829
1830 if (status & GREG_STAT_MAXPKTERR) {
1831 /* Driver error, tried to transmit something larger
1832 * than ethernet max mtu.
1833 */
1834 printk(KERN_ERR "%s: Happy Meal MAX Packet size error.\n", hp->dev->name);
1835 reset = 1;
1836 }
1837
1838 if (status & GREG_STAT_NORXD) {
1839 /* This is harmless, it just means the system is
1840 * quite loaded and the incoming packet rate was
1841 * faster than the interrupt handler could keep up
1842 * with.
1843 */
1844 printk(KERN_INFO "%s: Happy Meal out of receive "
1845 "descriptors, packet dropped.\n",
1846 hp->dev->name);
1847 }
1848
1849 if (status & (GREG_STAT_RXERR|GREG_STAT_RXPERR|GREG_STAT_RXTERR)) {
1850 /* All sorts of DMA receive errors. */
1851 printk(KERN_ERR "%s: Happy Meal rx DMA errors [ ", hp->dev->name);
1852 if (status & GREG_STAT_RXERR)
1853 printk("GenericError ");
1854 if (status & GREG_STAT_RXPERR)
1855 printk("ParityError ");
1856 if (status & GREG_STAT_RXTERR)
1857 printk("RxTagBotch ");
1858 printk("]\n");
1859 reset = 1;
1860 }
1861
1862 if (status & GREG_STAT_EOPERR) {
1863 /* Driver bug, didn't set EOP bit in tx descriptor given
1864 * to the happy meal.
1865 */
1866 printk(KERN_ERR "%s: EOP not set in happy meal transmit descriptor!\n",
1867 hp->dev->name);
1868 reset = 1;
1869 }
1870
1871 if (status & GREG_STAT_MIFIRQ) {
1872 /* MIF signalled an interrupt, were we polling it? */
1873 printk(KERN_ERR "%s: Happy Meal MIF interrupt.\n", hp->dev->name);
1874 }
1875
1876 if (status &
1877 (GREG_STAT_TXEACK|GREG_STAT_TXLERR|GREG_STAT_TXPERR|GREG_STAT_TXTERR)) {
1878 /* All sorts of transmit DMA errors. */
1879 printk(KERN_ERR "%s: Happy Meal tx DMA errors [ ", hp->dev->name);
1880 if (status & GREG_STAT_TXEACK)
1881 printk("GenericError ");
1882 if (status & GREG_STAT_TXLERR)
1883 printk("LateError ");
1884 if (status & GREG_STAT_TXPERR)
1885 printk("ParityErro ");
1886 if (status & GREG_STAT_TXTERR)
1887 printk("TagBotch ");
1888 printk("]\n");
1889 reset = 1;
1890 }
1891
1892 if (status & (GREG_STAT_SLVERR|GREG_STAT_SLVPERR)) {
1893 /* Bus or parity error when cpu accessed happy meal registers
1894 * or it's internal FIFO's. Should never see this.
1895 */
1896 printk(KERN_ERR "%s: Happy Meal register access SBUS slave (%s) error.\n",
1897 hp->dev->name,
1898 (status & GREG_STAT_SLVPERR) ? "parity" : "generic");
1899 reset = 1;
1900 }
1901
1902 if (reset) {
1903 printk(KERN_NOTICE "%s: Resetting...\n", hp->dev->name);
1904 happy_meal_init(hp);
1905 return 1;
1906 }
1907 return 0;
1908 }
1909
1910 /* hp->happy_lock must be held */
1911 static void happy_meal_mif_interrupt(struct happy_meal *hp)
1912 {
1913 void __iomem *tregs = hp->tcvregs;
1914
1915 printk(KERN_INFO "%s: Link status change.\n", hp->dev->name);
1916 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
1917 hp->sw_lpa = happy_meal_tcvr_read(hp, tregs, MII_LPA);
1918
1919 /* Use the fastest transmission protocol possible. */
1920 if (hp->sw_lpa & LPA_100FULL) {
1921 printk(KERN_INFO "%s: Switching to 100Mbps at full duplex.", hp->dev->name);
1922 hp->sw_bmcr |= (BMCR_FULLDPLX | BMCR_SPEED100);
1923 } else if (hp->sw_lpa & LPA_100HALF) {
1924 printk(KERN_INFO "%s: Switching to 100MBps at half duplex.", hp->dev->name);
1925 hp->sw_bmcr |= BMCR_SPEED100;
1926 } else if (hp->sw_lpa & LPA_10FULL) {
1927 printk(KERN_INFO "%s: Switching to 10MBps at full duplex.", hp->dev->name);
1928 hp->sw_bmcr |= BMCR_FULLDPLX;
1929 } else {
1930 printk(KERN_INFO "%s: Using 10Mbps at half duplex.", hp->dev->name);
1931 }
1932 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
1933
1934 /* Finally stop polling and shut up the MIF. */
1935 happy_meal_poll_stop(hp, tregs);
1936 }
1937
1938 #ifdef TXDEBUG
1939 #define TXD(x) printk x
1940 #else
1941 #define TXD(x)
1942 #endif
1943
1944 /* hp->happy_lock must be held */
1945 static void happy_meal_tx(struct happy_meal *hp)
1946 {
1947 struct happy_meal_txd *txbase = &hp->happy_block->happy_meal_txd[0];
1948 struct happy_meal_txd *this;
1949 struct net_device *dev = hp->dev;
1950 int elem;
1951
1952 elem = hp->tx_old;
1953 TXD(("TX<"));
1954 while (elem != hp->tx_new) {
1955 struct sk_buff *skb;
1956 u32 flags, dma_addr, dma_len;
1957 int frag;
1958
1959 TXD(("[%d]", elem));
1960 this = &txbase[elem];
1961 flags = hme_read_desc32(hp, &this->tx_flags);
1962 if (flags & TXFLAG_OWN)
1963 break;
1964 skb = hp->tx_skbs[elem];
1965 if (skb_shinfo(skb)->nr_frags) {
1966 int last;
1967
1968 last = elem + skb_shinfo(skb)->nr_frags;
1969 last &= (TX_RING_SIZE - 1);
1970 flags = hme_read_desc32(hp, &txbase[last].tx_flags);
1971 if (flags & TXFLAG_OWN)
1972 break;
1973 }
1974 hp->tx_skbs[elem] = NULL;
1975 hp->net_stats.tx_bytes += skb->len;
1976
1977 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
1978 dma_addr = hme_read_desc32(hp, &this->tx_addr);
1979 dma_len = hme_read_desc32(hp, &this->tx_flags);
1980
1981 dma_len &= TXFLAG_SIZE;
1982 hme_dma_unmap(hp, dma_addr, dma_len, DMA_TODEVICE);
1983
1984 elem = NEXT_TX(elem);
1985 this = &txbase[elem];
1986 }
1987
1988 dev_kfree_skb_irq(skb);
1989 hp->net_stats.tx_packets++;
1990 }
1991 hp->tx_old = elem;
1992 TXD((">"));
1993
1994 if (netif_queue_stopped(dev) &&
1995 TX_BUFFS_AVAIL(hp) > (MAX_SKB_FRAGS + 1))
1996 netif_wake_queue(dev);
1997 }
1998
1999 #ifdef RXDEBUG
2000 #define RXD(x) printk x
2001 #else
2002 #define RXD(x)
2003 #endif
2004
2005 /* Originally I used to handle the allocation failure by just giving back just
2006 * that one ring buffer to the happy meal. Problem is that usually when that
2007 * condition is triggered, the happy meal expects you to do something reasonable
2008 * with all of the packets it has DMA'd in. So now I just drop the entire
2009 * ring when we cannot get a new skb and give them all back to the happy meal,
2010 * maybe things will be "happier" now.
2011 *
2012 * hp->happy_lock must be held
2013 */
2014 static void happy_meal_rx(struct happy_meal *hp, struct net_device *dev)
2015 {
2016 struct happy_meal_rxd *rxbase = &hp->happy_block->happy_meal_rxd[0];
2017 struct happy_meal_rxd *this;
2018 int elem = hp->rx_new, drops = 0;
2019 u32 flags;
2020
2021 RXD(("RX<"));
2022 this = &rxbase[elem];
2023 while (!((flags = hme_read_desc32(hp, &this->rx_flags)) & RXFLAG_OWN)) {
2024 struct sk_buff *skb;
2025 int len = flags >> 16;
2026 u16 csum = flags & RXFLAG_CSUM;
2027 u32 dma_addr = hme_read_desc32(hp, &this->rx_addr);
2028
2029 RXD(("[%d ", elem));
2030
2031 /* Check for errors. */
2032 if ((len < ETH_ZLEN) || (flags & RXFLAG_OVERFLOW)) {
2033 RXD(("ERR(%08x)]", flags));
2034 hp->net_stats.rx_errors++;
2035 if (len < ETH_ZLEN)
2036 hp->net_stats.rx_length_errors++;
2037 if (len & (RXFLAG_OVERFLOW >> 16)) {
2038 hp->net_stats.rx_over_errors++;
2039 hp->net_stats.rx_fifo_errors++;
2040 }
2041
2042 /* Return it to the Happy meal. */
2043 drop_it:
2044 hp->net_stats.rx_dropped++;
2045 hme_write_rxd(hp, this,
2046 (RXFLAG_OWN|((RX_BUF_ALLOC_SIZE-RX_OFFSET)<<16)),
2047 dma_addr);
2048 goto next;
2049 }
2050 skb = hp->rx_skbs[elem];
2051 if (len > RX_COPY_THRESHOLD) {
2052 struct sk_buff *new_skb;
2053
2054 /* Now refill the entry, if we can. */
2055 new_skb = happy_meal_alloc_skb(RX_BUF_ALLOC_SIZE, GFP_ATOMIC);
2056 if (new_skb == NULL) {
2057 drops++;
2058 goto drop_it;
2059 }
2060 hme_dma_unmap(hp, dma_addr, RX_BUF_ALLOC_SIZE, DMA_FROMDEVICE);
2061 hp->rx_skbs[elem] = new_skb;
2062 new_skb->dev = dev;
2063 skb_put(new_skb, (ETH_FRAME_LEN + RX_OFFSET));
2064 hme_write_rxd(hp, this,
2065 (RXFLAG_OWN|((RX_BUF_ALLOC_SIZE-RX_OFFSET)<<16)),
2066 hme_dma_map(hp, new_skb->data, RX_BUF_ALLOC_SIZE, DMA_FROMDEVICE));
2067 skb_reserve(new_skb, RX_OFFSET);
2068
2069 /* Trim the original skb for the netif. */
2070 skb_trim(skb, len);
2071 } else {
2072 struct sk_buff *copy_skb = dev_alloc_skb(len + 2);
2073
2074 if (copy_skb == NULL) {
2075 drops++;
2076 goto drop_it;
2077 }
2078
2079 copy_skb->dev = dev;
2080 skb_reserve(copy_skb, 2);
2081 skb_put(copy_skb, len);
2082 hme_dma_sync_for_cpu(hp, dma_addr, len, DMA_FROMDEVICE);
2083 memcpy(copy_skb->data, skb->data, len);
2084 hme_dma_sync_for_device(hp, dma_addr, len, DMA_FROMDEVICE);
2085
2086 /* Reuse original ring buffer. */
2087 hme_write_rxd(hp, this,
2088 (RXFLAG_OWN|((RX_BUF_ALLOC_SIZE-RX_OFFSET)<<16)),
2089 dma_addr);
2090
2091 skb = copy_skb;
2092 }
2093
2094 /* This card is _fucking_ hot... */
2095 skb->csum = ntohs(csum ^ 0xffff);
2096 skb->ip_summed = CHECKSUM_HW;
2097
2098 RXD(("len=%d csum=%4x]", len, csum));
2099 skb->protocol = eth_type_trans(skb, dev);
2100 netif_rx(skb);
2101
2102 dev->last_rx = jiffies;
2103 hp->net_stats.rx_packets++;
2104 hp->net_stats.rx_bytes += len;
2105 next:
2106 elem = NEXT_RX(elem);
2107 this = &rxbase[elem];
2108 }
2109 hp->rx_new = elem;
2110 if (drops)
2111 printk(KERN_INFO "%s: Memory squeeze, deferring packet.\n", hp->dev->name);
2112 RXD((">"));
2113 }
2114
2115 static irqreturn_t happy_meal_interrupt(int irq, void *dev_id, struct pt_regs *regs)
2116 {
2117 struct net_device *dev = (struct net_device *) dev_id;
2118 struct happy_meal *hp = dev->priv;
2119 u32 happy_status = hme_read32(hp, hp->gregs + GREG_STAT);
2120
2121 HMD(("happy_meal_interrupt: status=%08x ", happy_status));
2122
2123 spin_lock(&hp->happy_lock);
2124
2125 if (happy_status & GREG_STAT_ERRORS) {
2126 HMD(("ERRORS "));
2127 if (happy_meal_is_not_so_happy(hp, /* un- */ happy_status))
2128 goto out;
2129 }
2130
2131 if (happy_status & GREG_STAT_MIFIRQ) {
2132 HMD(("MIFIRQ "));
2133 happy_meal_mif_interrupt(hp);
2134 }
2135
2136 if (happy_status & GREG_STAT_TXALL) {
2137 HMD(("TXALL "));
2138 happy_meal_tx(hp);
2139 }
2140
2141 if (happy_status & GREG_STAT_RXTOHOST) {
2142 HMD(("RXTOHOST "));
2143 happy_meal_rx(hp, dev);
2144 }
2145
2146 HMD(("done\n"));
2147 out:
2148 spin_unlock(&hp->happy_lock);
2149
2150 return IRQ_HANDLED;
2151 }
2152
2153 #ifdef CONFIG_SBUS
2154 static irqreturn_t quattro_sbus_interrupt(int irq, void *cookie, struct pt_regs *ptregs)
2155 {
2156 struct quattro *qp = (struct quattro *) cookie;
2157 int i;
2158
2159 for (i = 0; i < 4; i++) {
2160 struct net_device *dev = qp->happy_meals[i];
2161 struct happy_meal *hp = dev->priv;
2162 u32 happy_status = hme_read32(hp, hp->gregs + GREG_STAT);
2163
2164 HMD(("quattro_interrupt: status=%08x ", happy_status));
2165
2166 if (!(happy_status & (GREG_STAT_ERRORS |
2167 GREG_STAT_MIFIRQ |
2168 GREG_STAT_TXALL |
2169 GREG_STAT_RXTOHOST)))
2170 continue;
2171
2172 spin_lock(&hp->happy_lock);
2173
2174 if (happy_status & GREG_STAT_ERRORS) {
2175 HMD(("ERRORS "));
2176 if (happy_meal_is_not_so_happy(hp, happy_status))
2177 goto next;
2178 }
2179
2180 if (happy_status & GREG_STAT_MIFIRQ) {
2181 HMD(("MIFIRQ "));
2182 happy_meal_mif_interrupt(hp);
2183 }
2184
2185 if (happy_status & GREG_STAT_TXALL) {
2186 HMD(("TXALL "));
2187 happy_meal_tx(hp);
2188 }
2189
2190 if (happy_status & GREG_STAT_RXTOHOST) {
2191 HMD(("RXTOHOST "));
2192 happy_meal_rx(hp, dev);
2193 }
2194
2195 next:
2196 spin_unlock(&hp->happy_lock);
2197 }
2198 HMD(("done\n"));
2199
2200 return IRQ_HANDLED;
2201 }
2202 #endif
2203
2204 static int happy_meal_open(struct net_device *dev)
2205 {
2206 struct happy_meal *hp = dev->priv;
2207 int res;
2208
2209 HMD(("happy_meal_open: "));
2210
2211 /* On SBUS Quattro QFE cards, all hme interrupts are concentrated
2212 * into a single source which we register handling at probe time.
2213 */
2214 if ((hp->happy_flags & (HFLAG_QUATTRO|HFLAG_PCI)) != HFLAG_QUATTRO) {
2215 if (request_irq(dev->irq, &happy_meal_interrupt,
2216 SA_SHIRQ, dev->name, (void *)dev)) {
2217 HMD(("EAGAIN\n"));
2218 #ifdef __sparc__
2219 printk(KERN_ERR "happy_meal(SBUS): Can't order irq %s to go.\n",
2220 __irq_itoa(dev->irq));
2221 #else
2222 printk(KERN_ERR "happy_meal(SBUS): Can't order irq %d to go.\n",
2223 dev->irq);
2224 #endif
2225
2226 return -EAGAIN;
2227 }
2228 }
2229
2230 HMD(("to happy_meal_init\n"));
2231
2232 spin_lock_irq(&hp->happy_lock);
2233 res = happy_meal_init(hp);
2234 spin_unlock_irq(&hp->happy_lock);
2235
2236 if (res && ((hp->happy_flags & (HFLAG_QUATTRO|HFLAG_PCI)) != HFLAG_QUATTRO))
2237 free_irq(dev->irq, dev);
2238 return res;
2239 }
2240
2241 static int happy_meal_close(struct net_device *dev)
2242 {
2243 struct happy_meal *hp = dev->priv;
2244
2245 spin_lock_irq(&hp->happy_lock);
2246 happy_meal_stop(hp, hp->gregs);
2247 happy_meal_clean_rings(hp);
2248
2249 /* If auto-negotiation timer is running, kill it. */
2250 del_timer(&hp->happy_timer);
2251
2252 spin_unlock_irq(&hp->happy_lock);
2253
2254 /* On Quattro QFE cards, all hme interrupts are concentrated
2255 * into a single source which we register handling at probe
2256 * time and never unregister.
2257 */
2258 if ((hp->happy_flags & (HFLAG_QUATTRO|HFLAG_PCI)) != HFLAG_QUATTRO)
2259 free_irq(dev->irq, dev);
2260
2261 return 0;
2262 }
2263
2264 #ifdef SXDEBUG
2265 #define SXD(x) printk x
2266 #else
2267 #define SXD(x)
2268 #endif
2269
2270 static void happy_meal_tx_timeout(struct net_device *dev)
2271 {
2272 struct happy_meal *hp = dev->priv;
2273
2274 printk (KERN_ERR "%s: transmit timed out, resetting\n", dev->name);
2275 tx_dump_log();
2276 printk (KERN_ERR "%s: Happy Status %08x TX[%08x:%08x]\n", dev->name,
2277 hme_read32(hp, hp->gregs + GREG_STAT),
2278 hme_read32(hp, hp->etxregs + ETX_CFG),
2279 hme_read32(hp, hp->bigmacregs + BMAC_TXCFG));
2280
2281 spin_lock_irq(&hp->happy_lock);
2282 happy_meal_init(hp);
2283 spin_unlock_irq(&hp->happy_lock);
2284
2285 netif_wake_queue(dev);
2286 }
2287
2288 static int happy_meal_start_xmit(struct sk_buff *skb, struct net_device *dev)
2289 {
2290 struct happy_meal *hp = dev->priv;
2291 int entry;
2292 u32 tx_flags;
2293
2294 tx_flags = TXFLAG_OWN;
2295 if (skb->ip_summed == CHECKSUM_HW) {
2296 u32 csum_start_off, csum_stuff_off;
2297
2298 csum_start_off = (u32) (skb->h.raw - skb->data);
2299 csum_stuff_off = (u32) ((skb->h.raw + skb->csum) - skb->data);
2300
2301 tx_flags = (TXFLAG_OWN | TXFLAG_CSENABLE |
2302 ((csum_start_off << 14) & TXFLAG_CSBUFBEGIN) |
2303 ((csum_stuff_off << 20) & TXFLAG_CSLOCATION));
2304 }
2305
2306 spin_lock_irq(&hp->happy_lock);
2307
2308 if (TX_BUFFS_AVAIL(hp) <= (skb_shinfo(skb)->nr_frags + 1)) {
2309 netif_stop_queue(dev);
2310 spin_unlock_irq(&hp->happy_lock);
2311 printk(KERN_ERR "%s: BUG! Tx Ring full when queue awake!\n",
2312 dev->name);
2313 return 1;
2314 }
2315
2316 entry = hp->tx_new;
2317 SXD(("SX<l[%d]e[%d]>", len, entry));
2318 hp->tx_skbs[entry] = skb;
2319
2320 if (skb_shinfo(skb)->nr_frags == 0) {
2321 u32 mapping, len;
2322
2323 len = skb->len;
2324 mapping = hme_dma_map(hp, skb->data, len, DMA_TODEVICE);
2325 tx_flags |= (TXFLAG_SOP | TXFLAG_EOP);
2326 hme_write_txd(hp, &hp->happy_block->happy_meal_txd[entry],
2327 (tx_flags | (len & TXFLAG_SIZE)),
2328 mapping);
2329 entry = NEXT_TX(entry);
2330 } else {
2331 u32 first_len, first_mapping;
2332 int frag, first_entry = entry;
2333
2334 /* We must give this initial chunk to the device last.
2335 * Otherwise we could race with the device.
2336 */
2337 first_len = skb_headlen(skb);
2338 first_mapping = hme_dma_map(hp, skb->data, first_len, DMA_TODEVICE);
2339 entry = NEXT_TX(entry);
2340
2341 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
2342 skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
2343 u32 len, mapping, this_txflags;
2344
2345 len = this_frag->size;
2346 mapping = hme_dma_map(hp,
2347 ((void *) page_address(this_frag->page) +
2348 this_frag->page_offset),
2349 len, DMA_TODEVICE);
2350 this_txflags = tx_flags;
2351 if (frag == skb_shinfo(skb)->nr_frags - 1)
2352 this_txflags |= TXFLAG_EOP;
2353 hme_write_txd(hp, &hp->happy_block->happy_meal_txd[entry],
2354 (this_txflags | (len & TXFLAG_SIZE)),
2355 mapping);
2356 entry = NEXT_TX(entry);
2357 }
2358 hme_write_txd(hp, &hp->happy_block->happy_meal_txd[first_entry],
2359 (tx_flags | TXFLAG_SOP | (first_len & TXFLAG_SIZE)),
2360 first_mapping);
2361 }
2362
2363 hp->tx_new = entry;
2364
2365 if (TX_BUFFS_AVAIL(hp) <= (MAX_SKB_FRAGS + 1))
2366 netif_stop_queue(dev);
2367
2368 /* Get it going. */
2369 hme_write32(hp, hp->etxregs + ETX_PENDING, ETX_TP_DMAWAKEUP);
2370
2371 spin_unlock_irq(&hp->happy_lock);
2372
2373 dev->trans_start = jiffies;
2374
2375 tx_add_log(hp, TXLOG_ACTION_TXMIT, 0);
2376 return 0;
2377 }
2378
2379 static struct net_device_stats *happy_meal_get_stats(struct net_device *dev)
2380 {
2381 struct happy_meal *hp = dev->priv;
2382
2383 spin_lock_irq(&hp->happy_lock);
2384 happy_meal_get_counters(hp, hp->bigmacregs);
2385 spin_unlock_irq(&hp->happy_lock);
2386
2387 return &hp->net_stats;
2388 }
2389
2390 static void happy_meal_set_multicast(struct net_device *dev)
2391 {
2392 struct happy_meal *hp = dev->priv;
2393 void __iomem *bregs = hp->bigmacregs;
2394 struct dev_mc_list *dmi = dev->mc_list;
2395 char *addrs;
2396 int i;
2397 u32 crc;
2398
2399 spin_lock_irq(&hp->happy_lock);
2400
2401 netif_stop_queue(dev);
2402
2403 if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 64)) {
2404 hme_write32(hp, bregs + BMAC_HTABLE0, 0xffff);
2405 hme_write32(hp, bregs + BMAC_HTABLE1, 0xffff);
2406 hme_write32(hp, bregs + BMAC_HTABLE2, 0xffff);
2407 hme_write32(hp, bregs + BMAC_HTABLE3, 0xffff);
2408 } else if (dev->flags & IFF_PROMISC) {
2409 hme_write32(hp, bregs + BMAC_RXCFG,
2410 hme_read32(hp, bregs + BMAC_RXCFG) | BIGMAC_RXCFG_PMISC);
2411 } else {
2412 u16 hash_table[4];
2413
2414 for (i = 0; i < 4; i++)
2415 hash_table[i] = 0;
2416
2417 for (i = 0; i < dev->mc_count; i++) {
2418 addrs = dmi->dmi_addr;
2419 dmi = dmi->next;
2420
2421 if (!(*addrs & 1))
2422 continue;
2423
2424 crc = ether_crc_le(6, addrs);
2425 crc >>= 26;
2426 hash_table[crc >> 4] |= 1 << (crc & 0xf);
2427 }
2428 hme_write32(hp, bregs + BMAC_HTABLE0, hash_table[0]);
2429 hme_write32(hp, bregs + BMAC_HTABLE1, hash_table[1]);
2430 hme_write32(hp, bregs + BMAC_HTABLE2, hash_table[2]);
2431 hme_write32(hp, bregs + BMAC_HTABLE3, hash_table[3]);
2432 }
2433
2434 netif_wake_queue(dev);
2435
2436 spin_unlock_irq(&hp->happy_lock);
2437 }
2438
2439 /* Ethtool support... */
2440 static int hme_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2441 {
2442 struct happy_meal *hp = dev->priv;
2443
2444 cmd->supported =
2445 (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
2446 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
2447 SUPPORTED_Autoneg | SUPPORTED_TP | SUPPORTED_MII);
2448
2449 /* XXX hardcoded stuff for now */
2450 cmd->port = PORT_TP; /* XXX no MII support */
2451 cmd->transceiver = XCVR_INTERNAL; /* XXX no external xcvr support */
2452 cmd->phy_address = 0; /* XXX fixed PHYAD */
2453
2454 /* Record PHY settings. */
2455 spin_lock_irq(&hp->happy_lock);
2456 hp->sw_bmcr = happy_meal_tcvr_read(hp, hp->tcvregs, MII_BMCR);
2457 hp->sw_lpa = happy_meal_tcvr_read(hp, hp->tcvregs, MII_LPA);
2458 spin_unlock_irq(&hp->happy_lock);
2459
2460 if (hp->sw_bmcr & BMCR_ANENABLE) {
2461 cmd->autoneg = AUTONEG_ENABLE;
2462 cmd->speed =
2463 (hp->sw_lpa & (LPA_100HALF | LPA_100FULL)) ?
2464 SPEED_100 : SPEED_10;
2465 if (cmd->speed == SPEED_100)
2466 cmd->duplex =
2467 (hp->sw_lpa & (LPA_100FULL)) ?
2468 DUPLEX_FULL : DUPLEX_HALF;
2469 else
2470 cmd->duplex =
2471 (hp->sw_lpa & (LPA_10FULL)) ?
2472 DUPLEX_FULL : DUPLEX_HALF;
2473 } else {
2474 cmd->autoneg = AUTONEG_DISABLE;
2475 cmd->speed =
2476 (hp->sw_bmcr & BMCR_SPEED100) ?
2477 SPEED_100 : SPEED_10;
2478 cmd->duplex =
2479 (hp->sw_bmcr & BMCR_FULLDPLX) ?
2480 DUPLEX_FULL : DUPLEX_HALF;
2481 }
2482 return 0;
2483 }
2484
2485 static int hme_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2486 {
2487 struct happy_meal *hp = dev->priv;
2488
2489 /* Verify the settings we care about. */
2490 if (cmd->autoneg != AUTONEG_ENABLE &&
2491 cmd->autoneg != AUTONEG_DISABLE)
2492 return -EINVAL;
2493 if (cmd->autoneg == AUTONEG_DISABLE &&
2494 ((cmd->speed != SPEED_100 &&
2495 cmd->speed != SPEED_10) ||
2496 (cmd->duplex != DUPLEX_HALF &&
2497 cmd->duplex != DUPLEX_FULL)))
2498 return -EINVAL;
2499
2500 /* Ok, do it to it. */
2501 spin_lock_irq(&hp->happy_lock);
2502 del_timer(&hp->happy_timer);
2503 happy_meal_begin_auto_negotiation(hp, hp->tcvregs, cmd);
2504 spin_unlock_irq(&hp->happy_lock);
2505
2506 return 0;
2507 }
2508
2509 static void hme_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2510 {
2511 struct happy_meal *hp = dev->priv;
2512
2513 strcpy(info->driver, "sunhme");
2514 strcpy(info->version, "2.02");
2515 if (hp->happy_flags & HFLAG_PCI) {
2516 struct pci_dev *pdev = hp->happy_dev;
2517 strcpy(info->bus_info, pci_name(pdev));
2518 }
2519 #ifdef CONFIG_SBUS
2520 else {
2521 struct sbus_dev *sdev = hp->happy_dev;
2522 sprintf(info->bus_info, "SBUS:%d",
2523 sdev->slot);
2524 }
2525 #endif
2526 }
2527
2528 static u32 hme_get_link(struct net_device *dev)
2529 {
2530 struct happy_meal *hp = dev->priv;
2531
2532 spin_lock_irq(&hp->happy_lock);
2533 hp->sw_bmcr = happy_meal_tcvr_read(hp, hp->tcvregs, MII_BMCR);
2534 spin_unlock_irq(&hp->happy_lock);
2535
2536 return (hp->sw_bmsr & BMSR_LSTATUS);
2537 }
2538
2539 static struct ethtool_ops hme_ethtool_ops = {
2540 .get_settings = hme_get_settings,
2541 .set_settings = hme_set_settings,
2542 .get_drvinfo = hme_get_drvinfo,
2543 .get_link = hme_get_link,
2544 };
2545
2546 static int hme_version_printed;
2547
2548 #ifdef CONFIG_SBUS
2549 void __init quattro_get_ranges(struct quattro *qp)
2550 {
2551 struct sbus_dev *sdev = qp->quattro_dev;
2552 int err;
2553
2554 err = prom_getproperty(sdev->prom_node,
2555 "ranges",
2556 (char *)&qp->ranges[0],
2557 sizeof(qp->ranges));
2558 if (err == 0 || err == -1) {
2559 qp->nranges = 0;
2560 return;
2561 }
2562 qp->nranges = (err / sizeof(struct linux_prom_ranges));
2563 }
2564
2565 static void __init quattro_apply_ranges(struct quattro *qp, struct happy_meal *hp)
2566 {
2567 struct sbus_dev *sdev = hp->happy_dev;
2568 int rng;
2569
2570 for (rng = 0; rng < qp->nranges; rng++) {
2571 struct linux_prom_ranges *rngp = &qp->ranges[rng];
2572 int reg;
2573
2574 for (reg = 0; reg < 5; reg++) {
2575 if (sdev->reg_addrs[reg].which_io ==
2576 rngp->ot_child_space)
2577 break;
2578 }
2579 if (reg == 5)
2580 continue;
2581
2582 sdev->reg_addrs[reg].which_io = rngp->ot_parent_space;
2583 sdev->reg_addrs[reg].phys_addr += rngp->ot_parent_base;
2584 }
2585 }
2586
2587 /* Given a happy meal sbus device, find it's quattro parent.
2588 * If none exist, allocate and return a new one.
2589 *
2590 * Return NULL on failure.
2591 */
2592 static struct quattro * __init quattro_sbus_find(struct sbus_dev *goal_sdev)
2593 {
2594 struct sbus_bus *sbus;
2595 struct sbus_dev *sdev;
2596 struct quattro *qp;
2597 int i;
2598
2599 if (qfe_sbus_list == NULL)
2600 goto found;
2601
2602 for (qp = qfe_sbus_list; qp != NULL; qp = qp->next) {
2603 for (i = 0, sdev = qp->quattro_dev;
2604 (sdev != NULL) && (i < 4);
2605 sdev = sdev->next, i++) {
2606 if (sdev == goal_sdev)
2607 return qp;
2608 }
2609 }
2610 for_each_sbus(sbus) {
2611 for_each_sbusdev(sdev, sbus) {
2612 if (sdev == goal_sdev)
2613 goto found;
2614 }
2615 }
2616
2617 /* Cannot find quattro parent, fail. */
2618 return NULL;
2619
2620 found:
2621 qp = kmalloc(sizeof(struct quattro), GFP_KERNEL);
2622 if (qp != NULL) {
2623 int i;
2624
2625 for (i = 0; i < 4; i++)
2626 qp->happy_meals[i] = NULL;
2627
2628 qp->quattro_dev = goal_sdev;
2629 qp->next = qfe_sbus_list;
2630 qfe_sbus_list = qp;
2631 quattro_get_ranges(qp);
2632 }
2633 return qp;
2634 }
2635
2636 /* After all quattro cards have been probed, we call these functions
2637 * to register the IRQ handlers.
2638 */
2639 static void __init quattro_sbus_register_irqs(void)
2640 {
2641 struct quattro *qp;
2642
2643 for (qp = qfe_sbus_list; qp != NULL; qp = qp->next) {
2644 struct sbus_dev *sdev = qp->quattro_dev;
2645 int err;
2646
2647 err = request_irq(sdev->irqs[0],
2648 quattro_sbus_interrupt,
2649 SA_SHIRQ, "Quattro",
2650 qp);
2651 if (err != 0) {
2652 printk(KERN_ERR "Quattro: Fatal IRQ registery error %d.\n", err);
2653 panic("QFE request irq");
2654 }
2655 }
2656 }
2657 #endif /* CONFIG_SBUS */
2658
2659 #ifdef CONFIG_PCI
2660 static struct quattro * __init quattro_pci_find(struct pci_dev *pdev)
2661 {
2662 struct pci_dev *bdev = pdev->bus->self;
2663 struct quattro *qp;
2664
2665 if (!bdev) return NULL;
2666 for (qp = qfe_pci_list; qp != NULL; qp = qp->next) {
2667 struct pci_dev *qpdev = qp->quattro_dev;
2668
2669 if (qpdev == bdev)
2670 return qp;
2671 }
2672 qp = kmalloc(sizeof(struct quattro), GFP_KERNEL);
2673 if (qp != NULL) {
2674 int i;
2675
2676 for (i = 0; i < 4; i++)
2677 qp->happy_meals[i] = NULL;
2678
2679 qp->quattro_dev = bdev;
2680 qp->next = qfe_pci_list;
2681 qfe_pci_list = qp;
2682
2683 /* No range tricks necessary on PCI. */
2684 qp->nranges = 0;
2685 }
2686 return qp;
2687 }
2688 #endif /* CONFIG_PCI */
2689
2690 #ifdef CONFIG_SBUS
2691 static int __init happy_meal_sbus_init(struct sbus_dev *sdev, int is_qfe)
2692 {
2693 struct quattro *qp = NULL;
2694 struct happy_meal *hp;
2695 struct net_device *dev;
2696 int i, qfe_slot = -1;
2697 int err = -ENODEV;
2698
2699 if (is_qfe) {
2700 qp = quattro_sbus_find(sdev);
2701 if (qp == NULL)
2702 goto err_out;
2703 for (qfe_slot = 0; qfe_slot < 4; qfe_slot++)
2704 if (qp->happy_meals[qfe_slot] == NULL)
2705 break;
2706 if (qfe_slot == 4)
2707 goto err_out;
2708 }
2709
2710 err = -ENOMEM;
2711 dev = alloc_etherdev(sizeof(struct happy_meal));
2712 if (!dev)
2713 goto err_out;
2714 SET_MODULE_OWNER(dev);
2715
2716 if (hme_version_printed++ == 0)
2717 printk(KERN_INFO "%s", version);
2718
2719 /* If user did not specify a MAC address specifically, use
2720 * the Quattro local-mac-address property...
2721 */
2722 for (i = 0; i < 6; i++) {
2723 if (macaddr[i] != 0)
2724 break;
2725 }
2726 if (i < 6) { /* a mac address was given */
2727 for (i = 0; i < 6; i++)
2728 dev->dev_addr[i] = macaddr[i];
2729 macaddr[5]++;
2730 } else if (qfe_slot != -1 &&
2731 prom_getproplen(sdev->prom_node,
2732 "local-mac-address") == 6) {
2733 prom_getproperty(sdev->prom_node, "local-mac-address",
2734 dev->dev_addr, 6);
2735 } else {
2736 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
2737 }
2738
2739 hp = dev->priv;
2740
2741 hp->happy_dev = sdev;
2742
2743 spin_lock_init(&hp->happy_lock);
2744
2745 err = -ENODEV;
2746 if (sdev->num_registers != 5) {
2747 printk(KERN_ERR "happymeal: Device does not have 5 regs, it has %d.\n",
2748 sdev->num_registers);
2749 printk(KERN_ERR "happymeal: Would you like that for here or to go?\n");
2750 goto err_out_free_netdev;
2751 }
2752
2753 if (qp != NULL) {
2754 hp->qfe_parent = qp;
2755 hp->qfe_ent = qfe_slot;
2756 qp->happy_meals[qfe_slot] = dev;
2757 quattro_apply_ranges(qp, hp);
2758 }
2759
2760 hp->gregs = sbus_ioremap(&sdev->resource[0], 0,
2761 GREG_REG_SIZE, "HME Global Regs");
2762 if (!hp->gregs) {
2763 printk(KERN_ERR "happymeal: Cannot map Happy Meal global registers.\n");
2764 goto err_out_free_netdev;
2765 }
2766
2767 hp->etxregs = sbus_ioremap(&sdev->resource[1], 0,
2768 ETX_REG_SIZE, "HME TX Regs");
2769 if (!hp->etxregs) {
2770 printk(KERN_ERR "happymeal: Cannot map Happy Meal MAC Transmit registers.\n");
2771 goto err_out_iounmap;
2772 }
2773
2774 hp->erxregs = sbus_ioremap(&sdev->resource[2], 0,
2775 ERX_REG_SIZE, "HME RX Regs");
2776 if (!hp->erxregs) {
2777 printk(KERN_ERR "happymeal: Cannot map Happy Meal MAC Receive registers.\n");
2778 goto err_out_iounmap;
2779 }
2780
2781 hp->bigmacregs = sbus_ioremap(&sdev->resource[3], 0,
2782 BMAC_REG_SIZE, "HME BIGMAC Regs");
2783 if (!hp->bigmacregs) {
2784 printk(KERN_ERR "happymeal: Cannot map Happy Meal BIGMAC registers.\n");
2785 goto err_out_iounmap;
2786 }
2787
2788 hp->tcvregs = sbus_ioremap(&sdev->resource[4], 0,
2789 TCVR_REG_SIZE, "HME Tranceiver Regs");
2790 if (!hp->tcvregs) {
2791 printk(KERN_ERR "happymeal: Cannot map Happy Meal Tranceiver registers.\n");
2792 goto err_out_iounmap;
2793 }
2794
2795 hp->hm_revision = prom_getintdefault(sdev->prom_node, "hm-rev", 0xff);
2796 if (hp->hm_revision == 0xff)
2797 hp->hm_revision = 0xa0;
2798
2799 /* Now enable the feature flags we can. */
2800 if (hp->hm_revision == 0x20 || hp->hm_revision == 0x21)
2801 hp->happy_flags = HFLAG_20_21;
2802 else if (hp->hm_revision != 0xa0)
2803 hp->happy_flags = HFLAG_NOT_A0;
2804
2805 if (qp != NULL)
2806 hp->happy_flags |= HFLAG_QUATTRO;
2807
2808 /* Get the supported DVMA burst sizes from our Happy SBUS. */
2809 hp->happy_bursts = prom_getintdefault(sdev->bus->prom_node,
2810 "burst-sizes", 0x00);
2811
2812 hp->happy_block = sbus_alloc_consistent(hp->happy_dev,
2813 PAGE_SIZE,
2814 &hp->hblock_dvma);
2815 err = -ENOMEM;
2816 if (!hp->happy_block) {
2817 printk(KERN_ERR "happymeal: Cannot allocate descriptors.\n");
2818 goto err_out_iounmap;
2819 }
2820
2821 /* Force check of the link first time we are brought up. */
2822 hp->linkcheck = 0;
2823
2824 /* Force timer state to 'asleep' with count of zero. */
2825 hp->timer_state = asleep;
2826 hp->timer_ticks = 0;
2827
2828 init_timer(&hp->happy_timer);
2829
2830 hp->dev = dev;
2831 dev->open = &happy_meal_open;
2832 dev->stop = &happy_meal_close;
2833 dev->hard_start_xmit = &happy_meal_start_xmit;
2834 dev->get_stats = &happy_meal_get_stats;
2835 dev->set_multicast_list = &happy_meal_set_multicast;
2836 dev->tx_timeout = &happy_meal_tx_timeout;
2837 dev->watchdog_timeo = 5*HZ;
2838 dev->ethtool_ops = &hme_ethtool_ops;
2839
2840 /* Happy Meal can do it all... except VLAN. */
2841 dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_VLAN_CHALLENGED;
2842
2843 dev->irq = sdev->irqs[0];
2844
2845 #if defined(CONFIG_SBUS) && defined(CONFIG_PCI)
2846 /* Hook up PCI register/dma accessors. */
2847 hp->read_desc32 = sbus_hme_read_desc32;
2848 hp->write_txd = sbus_hme_write_txd;
2849 hp->write_rxd = sbus_hme_write_rxd;
2850 hp->dma_map = (u32 (*)(void *, void *, long, int))sbus_map_single;
2851 hp->dma_unmap = (void (*)(void *, u32, long, int))sbus_unmap_single;
2852 hp->dma_sync_for_cpu = (void (*)(void *, u32, long, int))
2853 sbus_dma_sync_single_for_cpu;
2854 hp->dma_sync_for_device = (void (*)(void *, u32, long, int))
2855 sbus_dma_sync_single_for_device;
2856 hp->read32 = sbus_hme_read32;
2857 hp->write32 = sbus_hme_write32;
2858 #endif
2859
2860 /* Grrr, Happy Meal comes up by default not advertising
2861 * full duplex 100baseT capabilities, fix this.
2862 */
2863 spin_lock_irq(&hp->happy_lock);
2864 happy_meal_set_initial_advertisement(hp);
2865 spin_unlock_irq(&hp->happy_lock);
2866
2867 if (register_netdev(hp->dev)) {
2868 printk(KERN_ERR "happymeal: Cannot register net device, "
2869 "aborting.\n");
2870 goto err_out_free_consistent;
2871 }
2872
2873 if (qfe_slot != -1)
2874 printk(KERN_INFO "%s: Quattro HME slot %d (SBUS) 10/100baseT Ethernet ",
2875 dev->name, qfe_slot);
2876 else
2877 printk(KERN_INFO "%s: HAPPY MEAL (SBUS) 10/100baseT Ethernet ",
2878 dev->name);
2879
2880 for (i = 0; i < 6; i++)
2881 printk("%2.2x%c",
2882 dev->dev_addr[i], i == 5 ? ' ' : ':');
2883 printk("\n");
2884
2885 /* We are home free at this point, link us in to the happy
2886 * device list.
2887 */
2888 hp->next_module = root_happy_dev;
2889 root_happy_dev = hp;
2890
2891 return 0;
2892
2893 err_out_free_consistent:
2894 sbus_free_consistent(hp->happy_dev,
2895 PAGE_SIZE,
2896 hp->happy_block,
2897 hp->hblock_dvma);
2898
2899 err_out_iounmap:
2900 if (hp->gregs)
2901 sbus_iounmap(hp->gregs, GREG_REG_SIZE);
2902 if (hp->etxregs)
2903 sbus_iounmap(hp->etxregs, ETX_REG_SIZE);
2904 if (hp->erxregs)
2905 sbus_iounmap(hp->erxregs, ERX_REG_SIZE);
2906 if (hp->bigmacregs)
2907 sbus_iounmap(hp->bigmacregs, BMAC_REG_SIZE);
2908 if (hp->tcvregs)
2909 sbus_iounmap(hp->tcvregs, TCVR_REG_SIZE);
2910
2911 err_out_free_netdev:
2912 free_netdev(dev);
2913
2914 err_out:
2915 return err;
2916 }
2917 #endif
2918
2919 #ifdef CONFIG_PCI
2920 #ifndef __sparc__
2921 static int is_quattro_p(struct pci_dev *pdev)
2922 {
2923 struct pci_dev *busdev = pdev->bus->self;
2924 struct list_head *tmp;
2925 int n_hmes;
2926
2927 if (busdev == NULL ||
2928 busdev->vendor != PCI_VENDOR_ID_DEC ||
2929 busdev->device != PCI_DEVICE_ID_DEC_21153)
2930 return 0;
2931
2932 n_hmes = 0;
2933 tmp = pdev->bus->devices.next;
2934 while (tmp != &pdev->bus->devices) {
2935 struct pci_dev *this_pdev = pci_dev_b(tmp);
2936
2937 if (this_pdev->vendor == PCI_VENDOR_ID_SUN &&
2938 this_pdev->device == PCI_DEVICE_ID_SUN_HAPPYMEAL)
2939 n_hmes++;
2940
2941 tmp = tmp->next;
2942 }
2943
2944 if (n_hmes != 4)
2945 return 0;
2946
2947 return 1;
2948 }
2949
2950 /* Fetch MAC address from vital product data of PCI ROM. */
2951 static void find_eth_addr_in_vpd(void __iomem *rom_base, int len, int index, unsigned char *dev_addr)
2952 {
2953 int this_offset;
2954
2955 for (this_offset = 0x20; this_offset < len; this_offset++) {
2956 void __iomem *p = rom_base + this_offset;
2957
2958 if (readb(p + 0) != 0x90 ||
2959 readb(p + 1) != 0x00 ||
2960 readb(p + 2) != 0x09 ||
2961 readb(p + 3) != 0x4e ||
2962 readb(p + 4) != 0x41 ||
2963 readb(p + 5) != 0x06)
2964 continue;
2965
2966 this_offset += 6;
2967 p += 6;
2968
2969 if (index == 0) {
2970 int i;
2971
2972 for (i = 0; i < 6; i++)
2973 dev_addr[i] = readb(p + i);
2974 break;
2975 }
2976 index--;
2977 }
2978 }
2979
2980 static void get_hme_mac_nonsparc(struct pci_dev *pdev, unsigned char *dev_addr)
2981 {
2982 u32 rom_reg_orig;
2983 void __iomem *p;
2984 int index;
2985
2986 index = 0;
2987 if (is_quattro_p(pdev))
2988 index = PCI_SLOT(pdev->devfn);
2989
2990 if (pdev->resource[PCI_ROM_RESOURCE].parent == NULL) {
2991 if (pci_assign_resource(pdev, PCI_ROM_RESOURCE) < 0)
2992 goto use_random;
2993 }
2994
2995 pci_read_config_dword(pdev, pdev->rom_base_reg, &rom_reg_orig);
2996 pci_write_config_dword(pdev, pdev->rom_base_reg,
2997 rom_reg_orig | PCI_ROM_ADDRESS_ENABLE);
2998
2999 p = ioremap(pci_resource_start(pdev, PCI_ROM_RESOURCE), (64 * 1024));
3000 if (p != NULL && readb(p) == 0x55 && readb(p + 1) == 0xaa)
3001 find_eth_addr_in_vpd(p, (64 * 1024), index, dev_addr);
3002
3003 if (p != NULL)
3004 iounmap(p);
3005
3006 pci_write_config_dword(pdev, pdev->rom_base_reg, rom_reg_orig);
3007 return;
3008
3009 use_random:
3010 /* Sun MAC prefix then 3 random bytes. */
3011 dev_addr[0] = 0x08;
3012 dev_addr[1] = 0x00;
3013 dev_addr[2] = 0x20;
3014 get_random_bytes(&dev_addr[3], 3);
3015 return;
3016 }
3017 #endif /* !(__sparc__) */
3018
3019 static int __init happy_meal_pci_init(struct pci_dev *pdev)
3020 {
3021 struct quattro *qp = NULL;
3022 #ifdef __sparc__
3023 struct pcidev_cookie *pcp;
3024 int node;
3025 #endif
3026 struct happy_meal *hp;
3027 struct net_device *dev;
3028 void __iomem *hpreg_base;
3029 unsigned long hpreg_res;
3030 int i, qfe_slot = -1;
3031 char prom_name[64];
3032 int err;
3033
3034 /* Now make sure pci_dev cookie is there. */
3035 #ifdef __sparc__
3036 pcp = pdev->sysdata;
3037 if (pcp == NULL || pcp->prom_node == -1) {
3038 printk(KERN_ERR "happymeal(PCI): Some PCI device info missing\n");
3039 return -ENODEV;
3040 }
3041 node = pcp->prom_node;
3042
3043 prom_getstring(node, "name", prom_name, sizeof(prom_name));
3044 #else
3045 if (is_quattro_p(pdev))
3046 strcpy(prom_name, "SUNW,qfe");
3047 else
3048 strcpy(prom_name, "SUNW,hme");
3049 #endif
3050
3051 err = -ENODEV;
3052 if (!strcmp(prom_name, "SUNW,qfe") || !strcmp(prom_name, "qfe")) {
3053 qp = quattro_pci_find(pdev);
3054 if (qp == NULL)
3055 goto err_out;
3056 for (qfe_slot = 0; qfe_slot < 4; qfe_slot++)
3057 if (qp->happy_meals[qfe_slot] == NULL)
3058 break;
3059 if (qfe_slot == 4)
3060 goto err_out;
3061 }
3062
3063 dev = alloc_etherdev(sizeof(struct happy_meal));
3064 err = -ENOMEM;
3065 if (!dev)
3066 goto err_out;
3067 SET_MODULE_OWNER(dev);
3068 SET_NETDEV_DEV(dev, &pdev->dev);
3069
3070 if (hme_version_printed++ == 0)
3071 printk(KERN_INFO "%s", version);
3072
3073 dev->base_addr = (long) pdev;
3074
3075 hp = (struct happy_meal *)dev->priv;
3076 memset(hp, 0, sizeof(*hp));
3077
3078 hp->happy_dev = pdev;
3079
3080 spin_lock_init(&hp->happy_lock);
3081
3082 if (qp != NULL) {
3083 hp->qfe_parent = qp;
3084 hp->qfe_ent = qfe_slot;
3085 qp->happy_meals[qfe_slot] = dev;
3086 }
3087
3088 hpreg_res = pci_resource_start(pdev, 0);
3089 err = -ENODEV;
3090 if ((pci_resource_flags(pdev, 0) & IORESOURCE_IO) != 0) {
3091 printk(KERN_ERR "happymeal(PCI): Cannot find proper PCI device base address.\n");
3092 goto err_out_clear_quattro;
3093 }
3094 if (pci_request_regions(pdev, DRV_NAME)) {
3095 printk(KERN_ERR "happymeal(PCI): Cannot obtain PCI resources, "
3096 "aborting.\n");
3097 goto err_out_clear_quattro;
3098 }
3099
3100 if ((hpreg_base = ioremap(hpreg_res, 0x8000)) == 0) {
3101 printk(KERN_ERR "happymeal(PCI): Unable to remap card memory.\n");
3102 goto err_out_free_res;
3103 }
3104
3105 for (i = 0; i < 6; i++) {
3106 if (macaddr[i] != 0)
3107 break;
3108 }
3109 if (i < 6) { /* a mac address was given */
3110 for (i = 0; i < 6; i++)
3111 dev->dev_addr[i] = macaddr[i];
3112 macaddr[5]++;
3113 } else {
3114 #ifdef __sparc__
3115 if (qfe_slot != -1 &&
3116 prom_getproplen(node, "local-mac-address") == 6) {
3117 prom_getproperty(node, "local-mac-address",
3118 dev->dev_addr, 6);
3119 } else {
3120 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
3121 }
3122 #else
3123 get_hme_mac_nonsparc(pdev, &dev->dev_addr[0]);
3124 #endif
3125 }
3126
3127 /* Layout registers. */
3128 hp->gregs = (hpreg_base + 0x0000UL);
3129 hp->etxregs = (hpreg_base + 0x2000UL);
3130 hp->erxregs = (hpreg_base + 0x4000UL);
3131 hp->bigmacregs = (hpreg_base + 0x6000UL);
3132 hp->tcvregs = (hpreg_base + 0x7000UL);
3133
3134 #ifdef __sparc__
3135 hp->hm_revision = prom_getintdefault(node, "hm-rev", 0xff);
3136 if (hp->hm_revision == 0xff) {
3137 unsigned char prev;
3138
3139 pci_read_config_byte(pdev, PCI_REVISION_ID, &prev);
3140 hp->hm_revision = 0xc0 | (prev & 0x0f);
3141 }
3142 #else
3143 /* works with this on non-sparc hosts */
3144 hp->hm_revision = 0x20;
3145 #endif
3146
3147 /* Now enable the feature flags we can. */
3148 if (hp->hm_revision == 0x20 || hp->hm_revision == 0x21)
3149 hp->happy_flags = HFLAG_20_21;
3150 else if (hp->hm_revision != 0xa0 && hp->hm_revision != 0xc0)
3151 hp->happy_flags = HFLAG_NOT_A0;
3152
3153 if (qp != NULL)
3154 hp->happy_flags |= HFLAG_QUATTRO;
3155
3156 /* And of course, indicate this is PCI. */
3157 hp->happy_flags |= HFLAG_PCI;
3158
3159 #ifdef __sparc__
3160 /* Assume PCI happy meals can handle all burst sizes. */
3161 hp->happy_bursts = DMA_BURSTBITS;
3162 #endif
3163
3164 hp->happy_block = (struct hmeal_init_block *)
3165 pci_alloc_consistent(pdev, PAGE_SIZE, &hp->hblock_dvma);
3166
3167 err = -ENODEV;
3168 if (!hp->happy_block) {
3169 printk(KERN_ERR "happymeal(PCI): Cannot get hme init block.\n");
3170 goto err_out_iounmap;
3171 }
3172
3173 hp->linkcheck = 0;
3174 hp->timer_state = asleep;
3175 hp->timer_ticks = 0;
3176
3177 init_timer(&hp->happy_timer);
3178
3179 hp->dev = dev;
3180 dev->open = &happy_meal_open;
3181 dev->stop = &happy_meal_close;
3182 dev->hard_start_xmit = &happy_meal_start_xmit;
3183 dev->get_stats = &happy_meal_get_stats;
3184 dev->set_multicast_list = &happy_meal_set_multicast;
3185 dev->tx_timeout = &happy_meal_tx_timeout;
3186 dev->watchdog_timeo = 5*HZ;
3187 dev->ethtool_ops = &hme_ethtool_ops;
3188 dev->irq = pdev->irq;
3189 dev->dma = 0;
3190
3191 /* Happy Meal can do it all... */
3192 dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM;
3193
3194 #if defined(CONFIG_SBUS) && defined(CONFIG_PCI)
3195 /* Hook up PCI register/dma accessors. */
3196 hp->read_desc32 = pci_hme_read_desc32;
3197 hp->write_txd = pci_hme_write_txd;
3198 hp->write_rxd = pci_hme_write_rxd;
3199 hp->dma_map = (u32 (*)(void *, void *, long, int))pci_map_single;
3200 hp->dma_unmap = (void (*)(void *, u32, long, int))pci_unmap_single;
3201 hp->dma_sync_for_cpu = (void (*)(void *, u32, long, int))
3202 pci_dma_sync_single_for_cpu;
3203 hp->dma_sync_for_device = (void (*)(void *, u32, long, int))
3204 pci_dma_sync_single_for_device;
3205 hp->read32 = pci_hme_read32;
3206 hp->write32 = pci_hme_write32;
3207 #endif
3208
3209 /* Grrr, Happy Meal comes up by default not advertising
3210 * full duplex 100baseT capabilities, fix this.
3211 */
3212 spin_lock_irq(&hp->happy_lock);
3213 happy_meal_set_initial_advertisement(hp);
3214 spin_unlock_irq(&hp->happy_lock);
3215
3216 if (register_netdev(hp->dev)) {
3217 printk(KERN_ERR "happymeal(PCI): Cannot register net device, "
3218 "aborting.\n");
3219 goto err_out_iounmap;
3220 }
3221
3222 if (!qfe_slot) {
3223 struct pci_dev *qpdev = qp->quattro_dev;
3224
3225 prom_name[0] = 0;
3226 if (!strncmp(dev->name, "eth", 3)) {
3227 int i = simple_strtoul(dev->name + 3, NULL, 10);
3228 sprintf(prom_name, "-%d", i + 3);
3229 }
3230 printk(KERN_INFO "%s%s: Quattro HME (PCI/CheerIO) 10/100baseT Ethernet ", dev->name, prom_name);
3231 if (qpdev->vendor == PCI_VENDOR_ID_DEC &&
3232 qpdev->device == PCI_DEVICE_ID_DEC_21153)
3233 printk("DEC 21153 PCI Bridge\n");
3234 else
3235 printk("unknown bridge %04x.%04x\n",
3236 qpdev->vendor, qpdev->device);
3237 }
3238
3239 if (qfe_slot != -1)
3240 printk(KERN_INFO "%s: Quattro HME slot %d (PCI/CheerIO) 10/100baseT Ethernet ",
3241 dev->name, qfe_slot);
3242 else
3243 printk(KERN_INFO "%s: HAPPY MEAL (PCI/CheerIO) 10/100BaseT Ethernet ",
3244 dev->name);
3245
3246 for (i = 0; i < 6; i++)
3247 printk("%2.2x%c", dev->dev_addr[i], i == 5 ? ' ' : ':');
3248
3249 printk("\n");
3250
3251 /* We are home free at this point, link us in to the happy
3252 * device list.
3253 */
3254 hp->next_module = root_happy_dev;
3255 root_happy_dev = hp;
3256
3257 return 0;
3258
3259 err_out_iounmap:
3260 iounmap(hp->gregs);
3261
3262 err_out_free_res:
3263 pci_release_regions(pdev);
3264
3265 err_out_clear_quattro:
3266 if (qp != NULL)
3267 qp->happy_meals[qfe_slot] = NULL;
3268
3269 free_netdev(dev);
3270
3271 err_out:
3272 return err;
3273 }
3274 #endif
3275
3276 #ifdef CONFIG_SBUS
3277 static int __init happy_meal_sbus_probe(void)
3278 {
3279 struct sbus_bus *sbus;
3280 struct sbus_dev *sdev;
3281 int cards = 0;
3282 char model[128];
3283
3284 for_each_sbus(sbus) {
3285 for_each_sbusdev(sdev, sbus) {
3286 char *name = sdev->prom_name;
3287
3288 if (!strcmp(name, "SUNW,hme")) {
3289 cards++;
3290 prom_getstring(sdev->prom_node, "model",
3291 model, sizeof(model));
3292 if (!strcmp(model, "SUNW,sbus-qfe"))
3293 happy_meal_sbus_init(sdev, 1);
3294 else
3295 happy_meal_sbus_init(sdev, 0);
3296 } else if (!strcmp(name, "qfe") ||
3297 !strcmp(name, "SUNW,qfe")) {
3298 cards++;
3299 happy_meal_sbus_init(sdev, 1);
3300 }
3301 }
3302 }
3303 if (cards != 0)
3304 quattro_sbus_register_irqs();
3305 return cards;
3306 }
3307 #endif
3308
3309 #ifdef CONFIG_PCI
3310 static int __init happy_meal_pci_probe(void)
3311 {
3312 struct pci_dev *pdev = NULL;
3313 int cards = 0;
3314
3315 while ((pdev = pci_find_device(PCI_VENDOR_ID_SUN,
3316 PCI_DEVICE_ID_SUN_HAPPYMEAL, pdev)) != NULL) {
3317 if (pci_enable_device(pdev))
3318 continue;
3319 pci_set_master(pdev);
3320 cards++;
3321 happy_meal_pci_init(pdev);
3322 }
3323 return cards;
3324 }
3325 #endif
3326
3327 static int __init happy_meal_probe(void)
3328 {
3329 static int called = 0;
3330 int cards;
3331
3332 root_happy_dev = NULL;
3333
3334 if (called)
3335 return -ENODEV;
3336 called++;
3337
3338 cards = 0;
3339 #ifdef CONFIG_SBUS
3340 cards += happy_meal_sbus_probe();
3341 #endif
3342 #ifdef CONFIG_PCI
3343 cards += happy_meal_pci_probe();
3344 #endif
3345 if (!cards)
3346 return -ENODEV;
3347 return 0;
3348 }
3349
3350
3351 static void __exit happy_meal_cleanup_module(void)
3352 {
3353 #ifdef CONFIG_SBUS
3354 struct quattro *last_seen_qfe = NULL;
3355 #endif
3356
3357 while (root_happy_dev) {
3358 struct happy_meal *hp = root_happy_dev;
3359 struct happy_meal *next = root_happy_dev->next_module;
3360 struct net_device *dev = hp->dev;
3361
3362 /* Unregister netdev before unmapping registers as this
3363 * call can end up trying to access those registers.
3364 */
3365 unregister_netdev(dev);
3366
3367 #ifdef CONFIG_SBUS
3368 if (!(hp->happy_flags & HFLAG_PCI)) {
3369 if (hp->happy_flags & HFLAG_QUATTRO) {
3370 if (hp->qfe_parent != last_seen_qfe) {
3371 free_irq(dev->irq, hp->qfe_parent);
3372 last_seen_qfe = hp->qfe_parent;
3373 }
3374 }
3375
3376 sbus_iounmap(hp->gregs, GREG_REG_SIZE);
3377 sbus_iounmap(hp->etxregs, ETX_REG_SIZE);
3378 sbus_iounmap(hp->erxregs, ERX_REG_SIZE);
3379 sbus_iounmap(hp->bigmacregs, BMAC_REG_SIZE);
3380 sbus_iounmap(hp->tcvregs, TCVR_REG_SIZE);
3381 sbus_free_consistent(hp->happy_dev,
3382 PAGE_SIZE,
3383 hp->happy_block,
3384 hp->hblock_dvma);
3385 }
3386 #endif
3387 #ifdef CONFIG_PCI
3388 if ((hp->happy_flags & HFLAG_PCI)) {
3389 pci_free_consistent(hp->happy_dev,
3390 PAGE_SIZE,
3391 hp->happy_block,
3392 hp->hblock_dvma);
3393 iounmap(hp->gregs);
3394 pci_release_regions(hp->happy_dev);
3395 }
3396 #endif
3397 free_netdev(dev);
3398
3399 root_happy_dev = next;
3400 }
3401
3402 /* Now cleanup the quattro lists. */
3403 #ifdef CONFIG_SBUS
3404 while (qfe_sbus_list) {
3405 struct quattro *qfe = qfe_sbus_list;
3406 struct quattro *next = qfe->next;
3407
3408 kfree(qfe);
3409
3410 qfe_sbus_list = next;
3411 }
3412 #endif
3413 #ifdef CONFIG_PCI
3414 while (qfe_pci_list) {
3415 struct quattro *qfe = qfe_pci_list;
3416 struct quattro *next = qfe->next;
3417
3418 kfree(qfe);
3419
3420 qfe_pci_list = next;
3421 }
3422 #endif
3423 }
3424
3425 module_init(happy_meal_probe);
3426 module_exit(happy_meal_cleanup_module);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree