drivers/net/irda/vlsi_ir.h

   1
   2 /*********************************************************************
   3  *
   4  *      vlsi_ir.h:      VLSI82C147 PCI IrDA controller driver for Linux
   5  *
   6  *      Version:        0.5
   7  *
   8  *      Copyright (c) 2001-2003 Martin Diehl
   9  *
  10  *      This program is free software; you can redistribute it and/or
  11  *      modify it under the terms of the GNU General Public License as
  12  *      published by the Free Software Foundation; either version 2 of
  13  *      the License, or (at your option) any later version.
  14  *
  15  *      This program is distributed in the hope that it will be useful,
  16  *      but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  *      MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18  *      GNU General Public License for more details.
  19  *
  20  *      You should have received a copy of the GNU General Public License
  21  *      along with this program; if not, write to the Free Software
  22  *      Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  *      MA 02111-1307 USA
  24  *
  25  ********************************************************************/
  26
  27 #ifndef IRDA_VLSI_FIR_H
  28 #define IRDA_VLSI_FIR_H
  29
  30 /* ================================================================
  31  * compatibility stuff
  32  */
  33
  34 /* definitions not present in pci_ids.h */
  35
  36 #ifndef PCI_CLASS_WIRELESS_IRDA
  37 #define PCI_CLASS_WIRELESS_IRDA         0x0d00
  38 #endif
  39
  40 #ifndef PCI_CLASS_SUBCLASS_MASK
  41 #define PCI_CLASS_SUBCLASS_MASK         0xffff
  42 #endif
  43
  44 /* in recent 2.5 interrupt handlers have non-void return value */
  45 #ifndef IRQ_RETVAL
  46 typedef void irqreturn_t;
  47 #define IRQ_NONE
  48 #define IRQ_HANDLED
  49 #define IRQ_RETVAL(x)
  50 #endif
  51
  52 /* some stuff need to check kernelversion. Not all 2.5 stuff was present
  53  * in early 2.5.x - the test is merely to separate 2.4 from 2.5
  54  */
  55 #include <linux/version.h>
  56
  57 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
  58
  59 /* PDE() introduced in 2.5.4 */
  60 #ifdef CONFIG_PROC_FS
  61 #define PDE(inode) ((inode)->u.generic_ip)
  62 #endif
  63
  64 /* irda crc16 calculation exported in 2.5.42 */
  65 #define irda_calc_crc16(fcs,buf,len)    (GOOD_FCS)
  66
  67 /* we use this for unified pci device name access */
  68 #define PCIDEV_NAME(pdev)       ((pdev)->name)
  69
  70 #else /* 2.5 or later */
  71
  72 /* recent 2.5/2.6 stores pci device names at varying places ;-) */
  73 #ifdef CONFIG_PCI_NAMES
  74 /* human readable name */
  75 #define PCIDEV_NAME(pdev)       ((pdev)->pretty_name)
  76 #else
  77 /* whatever we get from the associated struct device - bus:slot:dev.fn id */
  78 #define PCIDEV_NAME(pdev)       (pci_name(pdev))
  79 #endif
  80
  81 #endif
  82
  83 /* ================================================================ */
  84
  85 /* non-standard PCI registers */
  86
  87 enum vlsi_pci_regs {
  88         VLSI_PCI_CLKCTL         = 0x40,         /* chip clock input control */
  89         VLSI_PCI_MSTRPAGE       = 0x41,         /* addr [31:24] for all busmaster cycles */
  90         VLSI_PCI_IRMISC         = 0x42          /* mainly legacy UART related */
  91 };
  92
  93 /* ------------------------------------------ */
  94
  95 /* VLSI_PCI_CLKCTL: Clock Control Register (u8, rw) */
  96
  97 /* Three possible clock sources: either on-chip 48MHz PLL or
  98  * external clock applied to EXTCLK pin. External clock may
  99  * be either 48MHz or 40MHz, which is indicated by XCKSEL.
 100  * CLKSTP controls whether the selected clock source gets
 101  * connected to the IrDA block.
 102  *
 103  * On my HP OB-800 the BIOS sets external 40MHz clock as source
 104  * when IrDA enabled and I've never detected any PLL lock success.
 105  * Apparently the 14.3...MHz OSC input required for the PLL to work
 106  * is not connected and the 40MHz EXTCLK is provided externally.
 107  * At least this is what makes the driver working for me.
 108  */
 109
 110 enum vlsi_pci_clkctl {
 111
 112         /* PLL control */
 113
 114         CLKCTL_PD_INV           = 0x04,         /* PD#: inverted power down signal,
 115                                                  * i.e. PLL is powered, if PD_INV set */
 116         CLKCTL_LOCK             = 0x40,         /* (ro) set, if PLL is locked */
 117
 118         /* clock source selection */
 119
 120         CLKCTL_EXTCLK           = 0x20,         /* set to select external clock input, not PLL */
 121         CLKCTL_XCKSEL           = 0x10,         /* set to indicate EXTCLK is 40MHz, not 48MHz */
 122
 123         /* IrDA block control */
 124
 125         CLKCTL_CLKSTP           = 0x80,         /* set to disconnect from selected clock source */
 126         CLKCTL_WAKE             = 0x08          /* set to enable wakeup feature: whenever IR activity
 127                                                  * is detected, PD_INV gets set(?) and CLKSTP cleared */
 128 };
 129
 130 /* ------------------------------------------ */
 131
 132 /* VLSI_PCI_MSTRPAGE: Master Page Register (u8, rw) and busmastering stuff */
 133
 134 #define DMA_MASK_USED_BY_HW     0xffffffff
 135 #define DMA_MASK_MSTRPAGE       0x00ffffff
 136 #define MSTRPAGE_VALUE          (DMA_MASK_MSTRPAGE >> 24)
 137
 138         /* PCI busmastering is somewhat special for this guy - in short:
 139          *
 140          * We select to operate using fixed MSTRPAGE=0, use ISA DMA
 141          * address restrictions to make the PCI BM api aware of this,
 142          * but ensure the hardware is dealing with real 32bit access.
 143          *
 144          * In detail:
 145          * The chip executes normal 32bit busmaster cycles, i.e.
 146          * drives all 32 address lines. These addresses however are
 147          * composed of [0:23] taken from various busaddr-pointers
 148          * and [24:31] taken from the MSTRPAGE register in the VLSI82C147
 149          * config space. Therefore _all_ busmastering must be
 150          * targeted to/from one single 16MB (busaddr-) superpage!
 151          * The point is to make sure all the allocations for memory
 152          * locations with busmaster access (ring descriptors, buffers)
 153          * are indeed bus-mappable to the same 16MB range (for x86 this
 154          * means they must reside in the same 16MB physical memory address
 155          * range). The only constraint we have which supports "several objects
 156          * mappable to common 16MB range" paradigma, is the old ISA DMA
 157          * restriction to the first 16MB of physical address range.
 158          * Hence the approach here is to enable PCI busmaster support using
 159          * the correct 32bit dma-mask used by the chip. Afterwards the device's
 160          * dma-mask gets restricted to 24bit, which must be honoured somehow by
 161          * all allocations for memory areas to be exposed to the chip ...
 162          *
 163          * Note:
 164          * Don't be surprised to get "Setting latency timer..." messages every
 165          * time when PCI busmastering is enabled for the chip.
 166          * The chip has its PCI latency timer RO fixed at 0 - which is not a
 167          * problem here, because it is never requesting _burst_ transactions.
 168          */
 169
 170 /* ------------------------------------------ */
 171
 172 /* VLSI_PCIIRMISC: IR Miscellaneous Register (u8, rw) */
 173
 174 /* legacy UART emulation - not used by this driver - would require:
 175  * (see below for some register-value definitions)
 176  *
 177  *      - IRMISC_UARTEN must be set to enable UART address decoding
 178  *      - IRMISC_UARTSEL configured
 179  *      - IRCFG_MASTER must be cleared
 180  *      - IRCFG_SIR must be set
 181  *      - IRENABLE_PHYANDCLOCK must be asserted 0->1 (and hence IRENABLE_SIR_ON)
 182  */
 183
 184 enum vlsi_pci_irmisc {
 185
 186         /* IR transceiver control */
 187
 188         IRMISC_IRRAIL           = 0x40,         /* (ro?) IR rail power indication (and control?)
 189                                                  * 0=3.3V / 1=5V. Probably set during power-on?
 190                                                  * unclear - not touched by driver */
 191         IRMISC_IRPD             = 0x08,         /* transceiver power down, if set */
 192
 193         /* legacy UART control */
 194
 195         IRMISC_UARTTST          = 0x80,         /* UART test mode - "always write 0" */
 196         IRMISC_UARTEN           = 0x04,         /* enable UART address decoding */
 197
 198         /* bits [1:0] IRMISC_UARTSEL to select legacy UART address */
 199
 200         IRMISC_UARTSEL_3f8      = 0x00,
 201         IRMISC_UARTSEL_2f8      = 0x01,
 202         IRMISC_UARTSEL_3e8      = 0x02,
 203         IRMISC_UARTSEL_2e8      = 0x03
 204 };
 205
 206 /* ================================================================ */
 207
 208 /* registers mapped to 32 byte PCI IO space */
 209
 210 /* note: better access all registers at the indicated u8/u16 size
 211  *       although some of them contain only 1 byte of information.
 212  *       some of them (particaluarly PROMPT and IRCFG) ignore
 213  *       access when using the wrong addressing mode!
 214  */
 215
 216 enum vlsi_pio_regs {
 217         VLSI_PIO_IRINTR         = 0x00,         /* interrupt enable/request (u8, rw) */
 218         VLSI_PIO_RINGPTR        = 0x02,         /* rx/tx ring pointer (u16, ro) */
 219         VLSI_PIO_RINGBASE       = 0x04,         /* [23:10] of ring address (u16, rw) */
 220         VLSI_PIO_RINGSIZE       = 0x06,         /* rx/tx ring size (u16, rw) */
 221         VLSI_PIO_PROMPT         = 0x08,         /* triggers ring processing (u16, wo) */
 222         /* 0x0a-0x0f: reserved / duplicated UART regs */
 223         VLSI_PIO_IRCFG          = 0x10,         /* configuration select (u16, rw) */
 224         VLSI_PIO_SIRFLAG        = 0x12,         /* BOF/EOF for filtered SIR (u16, ro) */
 225         VLSI_PIO_IRENABLE       = 0x14,         /* enable and status register (u16, rw/ro) */
 226         VLSI_PIO_PHYCTL         = 0x16,         /* physical layer current status (u16, ro) */
 227         VLSI_PIO_NPHYCTL        = 0x18,         /* next physical layer select (u16, rw) */
 228         VLSI_PIO_MAXPKT         = 0x1a,         /* [11:0] max len for packet receive (u16, rw) */
 229         VLSI_PIO_RCVBCNT        = 0x1c          /* current receive-FIFO byte count (u16, ro) */
 230         /* 0x1e-0x1f: reserved / duplicated UART regs */
 231 };
 232
 233 /* ------------------------------------------ */
 234
 235 /* VLSI_PIO_IRINTR: Interrupt Register (u8, rw) */
 236
 237 /* enable-bits:
 238  *              1 = enable / 0 = disable
 239  * interrupt condition bits:
 240  *              set according to corresponding interrupt source
 241  *              (regardless of the state of the enable bits)
 242  *              enable bit status indicates whether interrupt gets raised
 243  *              write-to-clear
 244  * note: RPKTINT and TPKTINT behave different in legacy UART mode (which we don't use :-)
 245  */
 246
 247 enum vlsi_pio_irintr {
 248         IRINTR_ACTEN    = 0x80, /* activity interrupt enable */
 249         IRINTR_ACTIVITY = 0x40, /* activity monitor (traffic detected) */
 250         IRINTR_RPKTEN   = 0x20, /* receive packet interrupt enable*/
 251         IRINTR_RPKTINT  = 0x10, /* rx-packet transfered from fifo to memory finished */
 252         IRINTR_TPKTEN   = 0x08, /* transmit packet interrupt enable */
 253         IRINTR_TPKTINT  = 0x04, /* last bit of tx-packet+crc shifted to ir-pulser */
 254         IRINTR_OE_EN    = 0x02, /* UART rx fifo overrun error interrupt enable */
 255         IRINTR_OE_INT   = 0x01  /* UART rx fifo overrun error (read LSR to clear) */
 256 };
 257
 258 /* we use this mask to check whether the (shared PCI) interrupt is ours */
 259
 260 #define IRINTR_INT_MASK         (IRINTR_ACTIVITY|IRINTR_RPKTINT|IRINTR_TPKTINT)
 261
 262 /* ------------------------------------------ */
 263
 264 /* VLSI_PIO_RINGPTR: Ring Pointer Read-Back Register (u16, ro) */
 265
 266 /* _both_ ring pointers are indices relative to the _entire_ rx,tx-ring!
 267  * i.e. the referenced descriptor is located
 268  * at RINGBASE + PTR * sizeof(descr) for rx and tx
 269  * therefore, the tx-pointer has offset MAX_RING_DESCR
 270  */
 271
 272 #define MAX_RING_DESCR          64      /* tx, rx rings may contain up to 64 descr each */
 273
 274 #define RINGPTR_RX_MASK         (MAX_RING_DESCR-1)
 275 #define RINGPTR_TX_MASK         ((MAX_RING_DESCR-1)<<8)
 276
 277 #define RINGPTR_GET_RX(p)       ((p)&RINGPTR_RX_MASK)
 278 #define RINGPTR_GET_TX(p)       (((p)&RINGPTR_TX_MASK)>>8)
 279
 280 /* ------------------------------------------ */
 281
 282 /* VLSI_PIO_RINGBASE: Ring Pointer Base Address Register (u16, ro) */
 283
 284 /* Contains [23:10] part of the ring base (bus-) address
 285  * which must be 1k-alinged. [31:24] is taken from
 286  * VLSI_PCI_MSTRPAGE above.
 287  * The controller initiates non-burst PCI BM cycles to
 288  * fetch and update the descriptors in the ring.
 289  * Once fetched, the descriptor remains cached onchip
 290  * until it gets closed and updated due to the ring
 291  * processing state machine.
 292  * The entire ring area is split in rx and tx areas with each
 293  * area consisting of 64 descriptors of 8 bytes each.
 294  * The rx(tx) ring is located at ringbase+0 (ringbase+64*8).
 295  */
 296
 297 #define BUS_TO_RINGBASE(p)      (((p)>>10)&0x3fff)
 298
 299 /* ------------------------------------------ */
 300
 301 /* VLSI_PIO_RINGSIZE: Ring Size Register (u16, rw) */
 302
 303 /* bit mask to indicate the ring size to be used for rx and tx.
 304  *      possible values         encoded bits
 305  *               4                 0000
 306  *               8                 0001
 307  *              16                 0011
 308  *              32                 0111
 309  *              64                 1111
 310  * located at [15:12] for tx and [11:8] for rx ([7:0] unused)
 311  *
 312  * note: probably a good idea to have IRCFG_MSTR cleared when writing
 313  *       this so the state machines are stopped and the RINGPTR is reset!
 314  */
 315
 316 #define SIZE_TO_BITS(num)               ((((num)-1)>>2)&0x0f)
 317 #define TX_RX_TO_RINGSIZE(tx,rx)        ((SIZE_TO_BITS(tx)<<12)|(SIZE_TO_BITS(rx)<<8))
 318 #define RINGSIZE_TO_RXSIZE(rs)          ((((rs)&0x0f00)>>6)+4)
 319 #define RINGSIZE_TO_TXSIZE(rs)          ((((rs)&0xf000)>>10)+4)
 320
 321
 322 /* ------------------------------------------ */
 323
 324 /* VLSI_PIO_PROMPT: Ring Prompting Register (u16, write-to-start) */
 325
 326 /* writing any value kicks the ring processing state machines
 327  * for both tx, rx rings as follows:
 328  *      - active rings (currently owning an active descriptor)
 329  *        ignore the prompt and continue
 330  *      - idle rings fetch the next descr from the ring and start
 331  *        their processing
 332  */
 333
 334 /* ------------------------------------------ */
 335
 336 /* VLSI_PIO_IRCFG: IR Config Register (u16, rw) */
 337
 338 /* notes:
 339  *      - not more than one SIR/MIR/FIR bit must be set at any time
 340  *      - SIR, MIR, FIR and CRC16 select the configuration which will
 341  *        be applied on next 0->1 transition of IRENABLE_PHYANDCLOCK (see below).
 342  *      - besides allowing the PCI interface to execute busmaster cycles
 343  *        and therefore the ring SM to operate, the MSTR bit has side-effects:
 344  *        when MSTR is cleared, the RINGPTR's get reset and the legacy UART mode
 345  *        (in contrast to busmaster access mode) gets enabled.
 346  *      - clearing ENRX or setting ENTX while data is received may stall the
 347  *        receive fifo until ENRX reenabled _and_ another packet arrives
 348  *      - SIRFILT means the chip performs the required unwrapping of hardware
 349  *        headers (XBOF's, BOF/EOF) and un-escaping in the _receive_ direction.
 350  *        Only the resulting IrLAP payload is copied to the receive buffers -
 351  *        but with the 16bit FCS still encluded. Question remains, whether it
 352  *        was already checked or we should do it before passing the packet to IrLAP?
 353  */
 354
 355 enum vlsi_pio_ircfg {
 356         IRCFG_LOOP      = 0x4000,       /* enable loopback test mode */
 357         IRCFG_ENTX      = 0x1000,       /* transmit enable */
 358         IRCFG_ENRX      = 0x0800,       /* receive enable */
 359         IRCFG_MSTR      = 0x0400,       /* master enable */
 360         IRCFG_RXANY     = 0x0200,       /* receive any packet */
 361         IRCFG_CRC16     = 0x0080,       /* 16bit (not 32bit) CRC select for MIR/FIR */
 362         IRCFG_FIR       = 0x0040,       /* FIR 4PPM encoding mode enable */
 363         IRCFG_MIR       = 0x0020,       /* MIR HDLC encoding mode enable */
 364         IRCFG_SIR       = 0x0010,       /* SIR encoding mode enable */
 365         IRCFG_SIRFILT   = 0x0008,       /* enable SIR decode filter (receiver unwrapping) */
 366         IRCFG_SIRTEST   = 0x0004,       /* allow SIR decode filter when not in SIR mode */
 367         IRCFG_TXPOL     = 0x0002,       /* invert tx polarity when set */
 368         IRCFG_RXPOL     = 0x0001        /* invert rx polarity when set */
 369 };
 370
 371 /* ------------------------------------------ */
 372
 373 /* VLSI_PIO_SIRFLAG: SIR Flag Register (u16, ro) */
 374
 375 /* register contains hardcoded BOF=0xc0 at [7:0] and EOF=0xc1 at [15:8]
 376  * which is used for unwrapping received frames in SIR decode-filter mode
 377  */
 378
 379 /* ------------------------------------------ */
 380
 381 /* VLSI_PIO_IRENABLE: IR Enable Register (u16, rw/ro) */
 382
 383 /* notes:
 384  *      - IREN acts as gate for latching the configured IR mode information
 385  *        from IRCFG and IRPHYCTL when IREN=reset and applying them when
 386  *        IREN gets set afterwards.
 387  *      - ENTXST reflects IRCFG_ENTX
 388  *      - ENRXST = IRCFG_ENRX && (!IRCFG_ENTX || IRCFG_LOOP)
 389  */
 390
 391 enum vlsi_pio_irenable {
 392         IRENABLE_PHYANDCLOCK    = 0x8000,  /* enable IR phy and gate the mode config (rw) */
 393         IRENABLE_CFGER          = 0x4000,  /* mode configuration error (ro) */
 394         IRENABLE_FIR_ON         = 0x2000,  /* FIR on status (ro) */
 395         IRENABLE_MIR_ON         = 0x1000,  /* MIR on status (ro) */
 396         IRENABLE_SIR_ON         = 0x0800,  /* SIR on status (ro) */
 397         IRENABLE_ENTXST         = 0x0400,  /* transmit enable status (ro) */
 398         IRENABLE_ENRXST         = 0x0200,  /* Receive enable status (ro) */
 399         IRENABLE_CRC16_ON       = 0x0100   /* 16bit (not 32bit) CRC enabled status (ro) */
 400 };
 401
 402 #define   IRENABLE_MASK     0xff00  /* Read mask */
 403
 404 /* ------------------------------------------ */
 405
 406 /* VLSI_PIO_PHYCTL: IR Physical Layer Current Control Register (u16, ro) */
 407
 408 /* read-back of the currently applied physical layer status.
 409  * applied from VLSI_PIO_NPHYCTL at rising edge of IRENABLE_PHYANDCLOCK
 410  * contents identical to VLSI_PIO_NPHYCTL (see below)
 411  */
 412
 413 /* ------------------------------------------ */
 414
 415 /* VLSI_PIO_NPHYCTL: IR Physical Layer Next Control Register (u16, rw) */
 416
 417 /* latched during IRENABLE_PHYANDCLOCK=0 and applied at 0-1 transition
 418  *
 419  * consists of BAUD[15:10], PLSWID[9:5] and PREAMB[4:0] bits defined as follows:
 420  *
 421  * SIR-mode:    BAUD = (115.2kHz / baudrate) - 1
 422  *              PLSWID = (pulsetime * freq / (BAUD+1)) - 1
 423  *                      where pulsetime is the requested IrPHY pulse width
 424  *                      and freq is 8(16)MHz for 40(48)MHz primary input clock
 425  *              PREAMB: don't care for SIR
 426  *
 427  *              The nominal SIR pulse width is 3/16 bit time so we have PLSWID=12
 428  *              fixed for all SIR speeds at 40MHz input clock (PLSWID=24 at 48MHz).
 429  *              IrPHY also allows shorter pulses down to the nominal pulse duration
 430  *              at 115.2kbaud (minus some tolerance) which is 1.41 usec.
 431  *              Using the expression PLSWID = 12/(BAUD+1)-1 (multiplied by two for 48MHz)
 432  *              we get the minimum acceptable PLSWID values according to the VLSI
 433  *              specification, which provides 1.5 usec pulse width for all speeds (except
 434  *              for 2.4kbaud getting 6usec). This is fine with IrPHY v1.3 specs and
 435  *              reduces the transceiver power which drains the battery. At 9.6kbaud for
 436  *              example this amounts to more than 90% battery power saving!
 437  *
 438  * MIR-mode:    BAUD = 0
 439  *              PLSWID = 9(10) for 40(48) MHz input clock
 440  *                      to get nominal MIR pulse width
 441  *              PREAMB = 1
 442  *
 443  * FIR-mode:    BAUD = 0
 444  *              PLSWID: don't care
 445  *              PREAMB = 15
 446  */
 447
 448 #define PHYCTL_BAUD_SHIFT       10
 449 #define PHYCTL_BAUD_MASK        0xfc00
 450 #define PHYCTL_PLSWID_SHIFT     5
 451 #define PHYCTL_PLSWID_MASK      0x03e0
 452 #define PHYCTL_PREAMB_SHIFT     0
 453 #define PHYCTL_PREAMB_MASK      0x001f
 454
 455 #define PHYCTL_TO_BAUD(bwp)     (((bwp)&PHYCTL_BAUD_MASK)>>PHYCTL_BAUD_SHIFT)
 456 #define PHYCTL_TO_PLSWID(bwp)   (((bwp)&PHYCTL_PLSWID_MASK)>>PHYCTL_PLSWID_SHIFT)
 457 #define PHYCTL_TO_PREAMB(bwp)   (((bwp)&PHYCTL_PREAMB_MASK)>>PHYCTL_PREAMB_SHIFT)
 458
 459 #define BWP_TO_PHYCTL(b,w,p)    ((((b)<<PHYCTL_BAUD_SHIFT)&PHYCTL_BAUD_MASK) \
 460                                  | (((w)<<PHYCTL_PLSWID_SHIFT)&PHYCTL_PLSWID_MASK) \
 461                                  | (((p)<<PHYCTL_PREAMB_SHIFT)&PHYCTL_PREAMB_MASK))
 462
 463 #define BAUD_BITS(br)           ((115200/(br))-1)
 464
 465 static inline unsigned
 466 calc_width_bits(unsigned baudrate, unsigned widthselect, unsigned clockselect)
 467 {
 468         unsigned        tmp;
 469
 470         if (widthselect)        /* nominal 3/16 puls width */
 471                 return (clockselect) ? 12 : 24;
 472
 473         tmp = ((clockselect) ? 12 : 24) / (BAUD_BITS(baudrate)+1);
 474
 475         /* intermediate result of integer division needed here */
 476
 477         return (tmp>0) ? (tmp-1) : 0;
 478 }
 479
 480 #define PHYCTL_SIR(br,ws,cs)    BWP_TO_PHYCTL(BAUD_BITS(br),calc_width_bits((br),(ws),(cs)),0)
 481 #define PHYCTL_MIR(cs)          BWP_TO_PHYCTL(0,((cs)?9:10),1)
 482 #define PHYCTL_FIR              BWP_TO_PHYCTL(0,0,15)
 483
 484 /* quite ugly, I know. But implementing these calculations here avoids
 485  * having magic numbers in the code and allows some playing with pulsewidths
 486  * without risk to violate the standards.
 487  * FWIW, here is the table for reference:
 488  *
 489  * baudrate     BAUD    min-PLSWID      nom-PLSWID      PREAMB
 490  *     2400       47       0(0)            12(24)          0
 491  *     9600       11       0(0)            12(24)          0
 492  *    19200        5       1(2)            12(24)          0
 493  *    38400        2       3(6)            12(24)          0
 494  *    57600        1       5(10)           12(24)          0
 495  *   115200        0      11(22)           12(24)          0
 496  *      MIR        0        -               9(10)          1
 497  *      FIR        0        -               0             15
 498  *
 499  * note: x(y) means x-value for 40MHz / y-value for 48MHz primary input clock
 500  */
 501
 502 /* ------------------------------------------ */
 503
 504
 505 /* VLSI_PIO_MAXPKT: Maximum Packet Length register (u16, rw) */
 506
 507 /* maximum acceptable length for received packets */
 508
 509 /* hw imposed limitation - register uses only [11:0] */
 510 #define MAX_PACKET_LENGTH       0x0fff
 511
 512 /* IrLAP I-field (apparently not defined elsewhere) */
 513 #define IRDA_MTU                2048
 514
 515 /* complete packet consists of A(1)+C(1)+I(<=IRDA_MTU) */
 516 #define IRLAP_SKB_ALLOCSIZE     (1+1+IRDA_MTU)
 517
 518 /* the buffers we use to exchange frames with the hardware need to be
 519  * larger than IRLAP_SKB_ALLOCSIZE because we may have up to 4 bytes FCS
 520  * appended and, in SIR mode, a lot of frame wrapping bytes. The worst
 521  * case appears to be a SIR packet with I-size==IRDA_MTU and all bytes
 522  * requiring to be escaped to provide transparency. Furthermore, the peer
 523  * might ask for quite a number of additional XBOFs:
 524  *      up to 115+48 XBOFS               163
 525  *      regular BOF                        1
 526  *      A-field                            1
 527  *      C-field                            1
 528  *      I-field, IRDA_MTU, all escaped  4096
 529  *      FCS (16 bit at SIR, escaped)       4
 530  *      EOF                                1
 531  * AFAICS nothing in IrLAP guarantees A/C field not to need escaping
 532  * (f.e. 0xc0/0xc1 - i.e. BOF/EOF - are legal values there) so in the
 533  * worst case we have 4269 bytes total frame size.
 534  * However, the VLSI uses 12 bits only for all buffer length values,
 535  * which limits the maximum useable buffer size <= 4095.
 536  * Note this is not a limitation in the receive case because we use
 537  * the SIR filtering mode where the hw unwraps the frame and only the
 538  * bare packet+fcs is stored into the buffer - in contrast to the SIR
 539  * tx case where we have to pass frame-wrapped packets to the hw.
 540  * If this would ever become an issue in real life, the only workaround
 541  * I see would be using the legacy UART emulation in SIR mode.
 542  */
 543
 544 #define XFER_BUF_SIZE           MAX_PACKET_LENGTH
 545
 546 /* ------------------------------------------ */
 547
 548 /* VLSI_PIO_RCVBCNT: Receive Byte Count Register (u16, ro) */
 549
 550 /* receive packet counter gets incremented on every non-filtered
 551  * byte which was put in the receive fifo and reset for each
 552  * new packet. Used to decide whether we are just in the middle
 553  * of receiving
 554  */
 555
 556 /* better apply the [11:0] mask when reading, as some docs say the
 557  * reserved [15:12] would return 1 when reading - which is wrong AFAICS
 558  */
 559 #define RCVBCNT_MASK    0x0fff
 560
 561 /******************************************************************/
 562
 563 /* descriptors for rx/tx ring
 564  *
 565  * accessed by hardware - don't change!
 566  *
 567  * the descriptor is owned by hardware, when the ACTIVE status bit
 568  * is set and nothing (besides reading status to test the bit)
 569  * shall be done. The bit gets cleared by hw, when the descriptor
 570  * gets closed. Premature reaping of descriptors owned be the chip
 571  * can be achieved by disabling IRCFG_MSTR
 572  *
 573  * Attention: Writing addr overwrites status!
 574  *
 575  * ### FIXME: depends on endianess (but there ain't no non-i586 ob800 ;-)
 576  */
 577
 578 struct ring_descr_hw {
 579         volatile u16    rd_count;       /* tx/rx count [11:0] */
 580         u16             reserved;
 581         union {
 582                 u32     addr;           /* [23:0] of the buffer's busaddress */
 583                 struct {
 584                         u8              addr_res[3];
 585                         volatile u8     status;         /* descriptor status */
 586                 } rd_s __attribute__((packed));
 587         } rd_u __attribute((packed));
 588 } __attribute__ ((packed));
 589
 590 #define rd_addr         rd_u.addr
 591 #define rd_status       rd_u.rd_s.status
 592
 593 /* ring descriptor status bits */
 594
 595 #define RD_ACTIVE               0x80    /* descriptor owned by hw (both TX,RX) */
 596
 597 /* TX ring descriptor status */
 598
 599 #define RD_TX_DISCRC            0x40    /* do not send CRC (for SIR) */
 600 #define RD_TX_BADCRC            0x20    /* force a bad CRC */
 601 #define RD_TX_PULSE             0x10    /* send indication pulse after this frame (MIR/FIR) */
 602 #define RD_TX_FRCEUND           0x08    /* force underrun */
 603 #define RD_TX_CLRENTX           0x04    /* clear ENTX after this frame */
 604 #define RD_TX_UNDRN             0x01    /* TX fifo underrun (probably PCI problem) */
 605
 606 /* RX ring descriptor status */
 607
 608 #define RD_RX_PHYERR            0x40    /* physical encoding error */
 609 #define RD_RX_CRCERR            0x20    /* CRC error (MIR/FIR) */
 610 #define RD_RX_LENGTH            0x10    /* frame exceeds buffer length */
 611 #define RD_RX_OVER              0x08    /* RX fifo overrun (probably PCI problem) */
 612 #define RD_RX_SIRBAD            0x04    /* EOF missing: BOF follows BOF (SIR, filtered) */
 613
 614 #define RD_RX_ERROR             0x7c    /* any error in received frame */
 615
 616 /* the memory required to hold the 2 descriptor rings */
 617 #define HW_RING_AREA_SIZE       (2 * MAX_RING_DESCR * sizeof(struct ring_descr_hw))
 618
 619 /******************************************************************/
 620
 621 /* sw-ring descriptors consists of a bus-mapped transfer buffer with
 622  * associated skb and a pointer to the hw entry descriptor
 623  */
 624
 625 struct ring_descr {
 626         struct ring_descr_hw    *hw;
 627         struct sk_buff          *skb;
 628         void                    *buf;
 629 };
 630
 631 /* wrappers for operations on hw-exposed ring descriptors
 632  * access to the hw-part of the descriptors must use these.
 633  */
 634
 635 static inline int rd_is_active(struct ring_descr *rd)
 636 {
 637         return ((rd->hw->rd_status & RD_ACTIVE) != 0);
 638 }
 639
 640 static inline void rd_activate(struct ring_descr *rd)
 641 {
 642         rd->hw->rd_status |= RD_ACTIVE;
 643 }
 644
 645 static inline void rd_set_status(struct ring_descr *rd, u8 s)
 646 {
 647         rd->hw->rd_status = s;   /* may pass ownership to the hardware */
 648 }
 649
 650 static inline void rd_set_addr_status(struct ring_descr *rd, dma_addr_t a, u8 s)
 651 {
 652         /* order is important for two reasons:
 653          *  - overlayed: writing addr overwrites status
 654          *  - we want to write status last so we have valid address in
 655          *    case status has RD_ACTIVE set
 656          */
 657
 658         if ((a & ~DMA_MASK_MSTRPAGE)>>24 != MSTRPAGE_VALUE) {
 659                 IRDA_ERROR("%s: pci busaddr inconsistency!\n", __FUNCTION__);
 660                 dump_stack();
 661                 return;
 662         }
 663
 664         a &= DMA_MASK_MSTRPAGE;  /* clear highbyte to make sure we won't write
 665                                   * to status - just in case MSTRPAGE_VALUE!=0
 666                                   */
 667         rd->hw->rd_addr = cpu_to_le32(a);
 668         wmb();
 669         rd_set_status(rd, s);    /* may pass ownership to the hardware */
 670 }
 671
 672 static inline void rd_set_count(struct ring_descr *rd, u16 c)
 673 {
 674         rd->hw->rd_count = cpu_to_le16(c);
 675 }
 676
 677 static inline u8 rd_get_status(struct ring_descr *rd)
 678 {
 679         return rd->hw->rd_status;
 680 }
 681
 682 static inline dma_addr_t rd_get_addr(struct ring_descr *rd)
 683 {
 684         dma_addr_t      a;
 685
 686         a = le32_to_cpu(rd->hw->rd_addr);
 687         return (a & DMA_MASK_MSTRPAGE) | (MSTRPAGE_VALUE << 24);
 688 }
 689
 690 static inline u16 rd_get_count(struct ring_descr *rd)
 691 {
 692         return le16_to_cpu(rd->hw->rd_count);
 693 }
 694
 695 /******************************************************************/
 696
 697 /* sw descriptor rings for rx, tx:
 698  *
 699  * operations follow producer-consumer paradigm, with the hw
 700  * in the middle doing the processing.
 701  * ring size must be power of two.
 702  *
 703  * producer advances r->tail after inserting for processing
 704  * consumer advances r->head after removing processed rd
 705  * ring is empty if head==tail / full if (tail+1)==head
 706  */
 707
 708 struct vlsi_ring {
 709         struct pci_dev          *pdev;
 710         int                     dir;
 711         unsigned                len;
 712         unsigned                size;
 713         unsigned                mask;
 714         atomic_t                head, tail;
 715         struct ring_descr       *rd;
 716 };
 717
 718 /* ring processing helpers */
 719
 720 static inline struct ring_descr *ring_last(struct vlsi_ring *r)
 721 {
 722         int t;
 723
 724         t = atomic_read(&r->tail) & r->mask;
 725         return (((t+1) & r->mask) == (atomic_read(&r->head) & r->mask)) ? NULL : &r->rd[t];
 726 }
 727
 728 static inline struct ring_descr *ring_put(struct vlsi_ring *r)
 729 {
 730         atomic_inc(&r->tail);
 731         return ring_last(r);
 732 }
 733
 734 static inline struct ring_descr *ring_first(struct vlsi_ring *r)
 735 {
 736         int h;
 737
 738         h = atomic_read(&r->head) & r->mask;
 739         return (h == (atomic_read(&r->tail) & r->mask)) ? NULL : &r->rd[h];
 740 }
 741
 742 static inline struct ring_descr *ring_get(struct vlsi_ring *r)
 743 {
 744         atomic_inc(&r->head);
 745         return ring_first(r);
 746 }
 747
 748 /******************************************************************/
 749
 750 /* our private compound VLSI-PCI-IRDA device information */
 751
 752 typedef struct vlsi_irda_dev {
 753         struct pci_dev          *pdev;
 754         struct net_device_stats stats;
 755
 756         struct irlap_cb         *irlap;
 757
 758         struct qos_info         qos;
 759
 760         unsigned                mode;
 761         int                     baud, new_baud;
 762
 763         dma_addr_t              busaddr;
 764         void                    *virtaddr;
 765         struct vlsi_ring        *tx_ring, *rx_ring;
 766
 767         struct timeval          last_rx;
 768
 769         spinlock_t              lock;
 770         struct semaphore        sem;
 771
 772         u8                      resume_ok;
 773         struct proc_dir_entry   *proc_entry;
 774
 775 } vlsi_irda_dev_t;
 776
 777 /********************************************************/
 778
 779 /* the remapped error flags we use for returning from frame
 780  * post-processing in vlsi_process_tx/rx() after it was completed
 781  * by the hardware. These functions either return the >=0 number
 782  * of transfered bytes in case of success or the negative (-)
 783  * of the or'ed error flags.
 784  */
 785
 786 #define VLSI_TX_DROP            0x0001
 787 #define VLSI_TX_FIFO            0x0002
 788
 789 #define VLSI_RX_DROP            0x0100
 790 #define VLSI_RX_OVER            0x0200
 791 #define VLSI_RX_LENGTH          0x0400
 792 #define VLSI_RX_FRAME           0x0800
 793 #define VLSI_RX_CRC             0x1000
 794
 795 /********************************************************/
 796
 797 #endif /* IRDA_VLSI_FIR_H */
 798