arch/x86_64/kernel/smpboot.c

   1 /*
   2  *      x86 SMP booting functions
   3  *
   4  *      (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
   5  *      (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com>
   6  *      Copyright 2001 Andi Kleen, SuSE Labs.
   7  *
   8  *      Much of the core SMP work is based on previous work by Thomas Radke, to
   9  *      whom a great many thanks are extended.
  10  *
  11  *      Thanks to Intel for making available several different Pentium,
  12  *      Pentium Pro and Pentium-II/Xeon MP machines.
  13  *      Original development of Linux SMP code supported by Caldera.
  14  *
  15  *      This code is released under the GNU General Public License version 2 or
  16  *      later.
  17  *
  18  *      Fixes
  19  *              Felix Koop      :       NR_CPUS used properly
  20  *              Jose Renau      :       Handle single CPU case.
  21  *              Alan Cox        :       By repeated request 8) - Total BogoMIP report.
  22  *              Greg Wright     :       Fix for kernel stacks panic.
  23  *              Erich Boleyn    :       MP v1.4 and additional changes.
  24  *      Matthias Sattler        :       Changes for 2.1 kernel map.
  25  *      Michel Lespinasse       :       Changes for 2.1 kernel map.
  26  *      Michael Chastain        :       Change trampoline.S to gnu as.
  27  *              Alan Cox        :       Dumb bug: 'B' step PPro's are fine
  28  *              Ingo Molnar     :       Added APIC timers, based on code
  29  *                                      from Jose Renau
  30  *              Ingo Molnar     :       various cleanups and rewrites
  31  *              Tigran Aivazian :       fixed "0.00 in /proc/uptime on SMP" bug.
  32  *      Maciej W. Rozycki       :       Bits for genuine 82489DX APICs
  33  *      Andi Kleen              :       Changed for SMP boot into long mode.
  34  *              Rusty Russell   :       Hacked into shape for new "hotplug" boot process.
  35  */
  36
  37 #include <linux/config.h>
  38 #include <linux/init.h>
  39
  40 #include <linux/mm.h>
  41 #include <linux/kernel_stat.h>
  42 #include <linux/smp_lock.h>
  43 #include <linux/irq.h>
  44 #include <linux/bootmem.h>
  45 #include <linux/thread_info.h>
  46 #include <linux/module.h>
  47
  48 #include <linux/delay.h>
  49 #include <linux/mc146818rtc.h>
  50 #include <asm/mtrr.h>
  51 #include <asm/pgalloc.h>
  52 #include <asm/desc.h>
  53 #include <asm/kdebug.h>
  54 #include <asm/tlbflush.h>
  55 #include <asm/proto.h>
  56
  57 /* Number of siblings per CPU package */
  58 int smp_num_siblings = 1;
  59 /* Package ID of each logical CPU */
  60 u8 phys_proc_id[NR_CPUS] = { [0 ... NR_CPUS-1] = BAD_APICID };
  61 EXPORT_SYMBOL(phys_proc_id);
  62
  63 /* Bitmask of currently online CPUs */
  64 cpumask_t cpu_online_map;
  65
  66 cpumask_t cpu_callin_map;
  67 cpumask_t cpu_callout_map;
  68 static cpumask_t smp_commenced_mask;
  69
  70 /* Per CPU bogomips and other parameters */
  71 struct cpuinfo_x86 cpu_data[NR_CPUS] __cacheline_aligned;
  72
  73 cpumask_t cpu_sibling_map[NR_CPUS] __cacheline_aligned;
  74
  75 /*
  76  * Trampoline 80x86 program as an array.
  77  */
  78
  79 extern unsigned char trampoline_data [];
  80 extern unsigned char trampoline_end  [];
  81
  82 /*
  83  * Currently trivial. Write the real->protected mode
  84  * bootstrap into the page concerned. The caller
  85  * has made sure it's suitably aligned.
  86  */
  87
  88 static unsigned long __init setup_trampoline(void)
  89 {
  90         void *tramp = __va(SMP_TRAMPOLINE_BASE);
  91         memcpy(tramp, trampoline_data, trampoline_end - trampoline_data);
  92         return virt_to_phys(tramp);
  93 }
  94
  95 /*
  96  * The bootstrap kernel entry code has set these up. Save them for
  97  * a given CPU
  98  */
  99
 100 static void __init smp_store_cpu_info(int id)
 101 {
 102         struct cpuinfo_x86 *c = cpu_data + id;
 103
 104         *c = boot_cpu_data;
 105         identify_cpu(c);
 106 }
 107
 108 /*
 109  * TSC synchronization.
 110  *
 111  * We first check whether all CPUs have their TSC's synchronized,
 112  * then we print a warning if not, and always resync.
 113  */
 114
 115 static atomic_t tsc_start_flag = ATOMIC_INIT(0);
 116 static atomic_t tsc_count_start = ATOMIC_INIT(0);
 117 static atomic_t tsc_count_stop = ATOMIC_INIT(0);
 118 static unsigned long long tsc_values[NR_CPUS];
 119
 120 #define NR_LOOPS 5
 121
 122 extern unsigned int fast_gettimeoffset_quotient;
 123
 124 static void __init synchronize_tsc_bp (void)
 125 {
 126         int i;
 127         unsigned long long t0;
 128         unsigned long long sum, avg;
 129         long long delta;
 130         long one_usec;
 131         int buggy = 0;
 132
 133         printk(KERN_INFO "checking TSC synchronization across %u CPUs: ",num_booting_cpus());
 134
 135         one_usec = cpu_khz;
 136
 137         atomic_set(&tsc_start_flag, 1);
 138         wmb();
 139
 140         /*
 141          * We loop a few times to get a primed instruction cache,
 142          * then the last pass is more or less synchronized and
 143          * the BP and APs set their cycle counters to zero all at
 144          * once. This reduces the chance of having random offsets
 145          * between the processors, and guarantees that the maximum
 146          * delay between the cycle counters is never bigger than
 147          * the latency of information-passing (cachelines) between
 148          * two CPUs.
 149          */
 150         for (i = 0; i < NR_LOOPS; i++) {
 151                 /*
 152                  * all APs synchronize but they loop on '== num_cpus'
 153                  */
 154                 while (atomic_read(&tsc_count_start) != num_booting_cpus()-1) mb();
 155                 atomic_set(&tsc_count_stop, 0);
 156                 wmb();
 157                 /*
 158                  * this lets the APs save their current TSC:
 159                  */
 160                 atomic_inc(&tsc_count_start);
 161
 162                 sync_core();
 163                 rdtscll(tsc_values[smp_processor_id()]);
 164                 /*
 165                  * We clear the TSC in the last loop:
 166                  */
 167                 if (i == NR_LOOPS-1)
 168                         write_tsc(0, 0);
 169
 170                 /*
 171                  * Wait for all APs to leave the synchronization point:
 172                  */
 173                 while (atomic_read(&tsc_count_stop) != num_booting_cpus()-1) mb();
 174                 atomic_set(&tsc_count_start, 0);
 175                 wmb();
 176                 atomic_inc(&tsc_count_stop);
 177         }
 178
 179         sum = 0;
 180         for (i = 0; i < NR_CPUS; i++) {
 181                 if (cpu_isset(i, cpu_callout_map)) {
 182                 t0 = tsc_values[i];
 183                 sum += t0;
 184         }
 185         }
 186         avg = sum / num_booting_cpus();
 187
 188         sum = 0;
 189         for (i = 0; i < NR_CPUS; i++) {
 190                 if (!cpu_isset(i, cpu_callout_map))
 191                         continue;
 192
 193                 delta = tsc_values[i] - avg;
 194                 if (delta < 0)
 195                         delta = -delta;
 196                 /*
 197                  * We report bigger than 2 microseconds clock differences.
 198                  */
 199                 if (delta > 2*one_usec) {
 200                         long realdelta;
 201                         if (!buggy) {
 202                                 buggy = 1;
 203                                 printk("\n");
 204                         }
 205                         realdelta = delta / one_usec;
 206                         if (tsc_values[i] < avg)
 207                                 realdelta = -realdelta;
 208
 209                         printk("BIOS BUG: CPU#%d improperly initialized, has %ld usecs TSC skew! FIXED.\n",
 210                                 i, realdelta);
 211                 }
 212
 213                 sum += delta;
 214         }
 215         if (!buggy)
 216                 printk("passed.\n");
 217 }
 218
 219 static void __init synchronize_tsc_ap (void)
 220 {
 221         int i;
 222
 223         /*
 224          * Not every cpu is online at the time
 225          * this gets called, so we first wait for the BP to
 226          * finish SMP initialization:
 227          */
 228         while (!atomic_read(&tsc_start_flag)) mb();
 229
 230         for (i = 0; i < NR_LOOPS; i++) {
 231                 atomic_inc(&tsc_count_start);
 232                 while (atomic_read(&tsc_count_start) != num_booting_cpus()) mb();
 233
 234                 sync_core();
 235                 rdtscll(tsc_values[smp_processor_id()]);
 236                 if (i == NR_LOOPS-1)
 237                         write_tsc(0, 0);
 238
 239                 atomic_inc(&tsc_count_stop);
 240                 while (atomic_read(&tsc_count_stop) != num_booting_cpus()) mb();
 241         }
 242 }
 243 #undef NR_LOOPS
 244
 245 static atomic_t init_deasserted;
 246
 247 static void __init smp_callin(void)
 248 {
 249         int cpuid, phys_id;
 250         unsigned long timeout;
 251
 252         /*
 253          * If waken up by an INIT in an 82489DX configuration
 254          * we may get here before an INIT-deassert IPI reaches
 255          * our local APIC.  We have to wait for the IPI or we'll
 256          * lock up on an APIC access.
 257          */
 258         while (!atomic_read(&init_deasserted));
 259
 260         /*
 261          * (This works even if the APIC is not enabled.)
 262          */
 263         phys_id = GET_APIC_ID(apic_read(APIC_ID));
 264         cpuid = smp_processor_id();
 265         if (cpu_isset(cpuid, cpu_callin_map)) {
 266                 panic("smp_callin: phys CPU#%d, CPU#%d already present??\n",
 267                                         phys_id, cpuid);
 268         }
 269         Dprintk("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id);
 270
 271         /*
 272          * STARTUP IPIs are fragile beasts as they might sometimes
 273          * trigger some glue motherboard logic. Complete APIC bus
 274          * silence for 1 second, this overestimates the time the
 275          * boot CPU is spending to send the up to 2 STARTUP IPIs
 276          * by a factor of two. This should be enough.
 277          */
 278
 279         /*
 280          * Waiting 2s total for startup (udelay is not yet working)
 281          */
 282         timeout = jiffies + 2*HZ;
 283         while (time_before(jiffies, timeout)) {
 284                 /*
 285                  * Has the boot CPU finished it's STARTUP sequence?
 286                  */
 287                 if (cpu_isset(cpuid, cpu_callout_map))
 288                         break;
 289                 rep_nop();
 290         }
 291
 292         if (!time_before(jiffies, timeout)) {
 293                 panic("smp_callin: CPU%d started up but did not get a callout!\n",
 294                         cpuid);
 295         }
 296
 297         /*
 298          * the boot CPU has finished the init stage and is spinning
 299          * on callin_map until we finish. We are free to set up this
 300          * CPU, first the APIC. (this is probably redundant on most
 301          * boards)
 302          */
 303
 304         Dprintk("CALLIN, before setup_local_APIC().\n");
 305         setup_local_APIC();
 306
 307         local_irq_enable();
 308
 309         /*
 310          * Get our bogomips.
 311          */
 312         calibrate_delay();
 313         Dprintk("Stack at about %p\n",&cpuid);
 314
 315         disable_APIC_timer();
 316
 317         /*
 318          * Save our processor parameters
 319          */
 320         smp_store_cpu_info(cpuid);
 321
 322         local_irq_disable();
 323
 324         /*
 325          * Allow the master to continue.
 326          */
 327         cpu_set(cpuid, cpu_callin_map);
 328
 329         /*
 330          *      Synchronize the TSC with the BP
 331          */
 332         if (cpu_has_tsc)
 333                 synchronize_tsc_ap();
 334 }
 335
 336 static int cpucount;
 337
 338 /*
 339  * Activate a secondary processor.
 340  */
 341 void __init start_secondary(void)
 342 {
 343         /*
 344          * Dont put anything before smp_callin(), SMP
 345          * booting is too fragile that we want to limit the
 346          * things done here to the most necessary things.
 347          */
 348         cpu_init();
 349         smp_callin();
 350
 351         /* otherwise gcc will move up the smp_processor_id before the cpu_init */
 352         barrier();
 353
 354         Dprintk("cpu %d: waiting for commence\n", smp_processor_id());
 355         while (!cpu_isset(smp_processor_id(), smp_commenced_mask))
 356                 rep_nop();
 357
 358         Dprintk("cpu %d: setting up apic clock\n", smp_processor_id());
 359         setup_secondary_APIC_clock();
 360
 361         Dprintk("cpu %d: enabling apic timer\n", smp_processor_id());
 362
 363         if (nmi_watchdog == NMI_IO_APIC) {
 364                 disable_8259A_irq(0);
 365                 enable_NMI_through_LVT0(NULL);
 366                 enable_8259A_irq(0);
 367         }
 368
 369
 370         enable_APIC_timer();
 371
 372         /*
 373          * low-memory mappings have been cleared, flush them from
 374          * the local TLBs too.
 375          */
 376         local_flush_tlb();
 377
 378         Dprintk("cpu %d eSetting cpu_online_map\n", smp_processor_id());
 379         cpu_set(smp_processor_id(), cpu_online_map);
 380         wmb();
 381
 382         cpu_idle();
 383 }
 384
 385 extern volatile unsigned long init_rsp;
 386 extern void (*initial_code)(void);
 387
 388 #if APIC_DEBUG
 389 static inline void inquire_remote_apic(int apicid)
 390 {
 391         unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 };
 392         char *names[] = { "ID", "VERSION", "SPIV" };
 393         int timeout, status;
 394
 395         printk(KERN_INFO "Inquiring remote APIC #%d...\n", apicid);
 396
 397         for (i = 0; i < sizeof(regs) / sizeof(*regs); i++) {
 398                 printk("... APIC #%d %s: ", apicid, names[i]);
 399
 400                 /*
 401                  * Wait for idle.
 402                  */
 403                 apic_wait_icr_idle();
 404
 405                 apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
 406                 apic_write_around(APIC_ICR, APIC_DM_REMRD | regs[i]);
 407
 408                 timeout = 0;
 409                 do {
 410                         udelay(100);
 411                         status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK;
 412                 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000);
 413
 414                 switch (status) {
 415                 case APIC_ICR_RR_VALID:
 416                         status = apic_read(APIC_RRR);
 417                         printk("%08x\n", status);
 418                         break;
 419                 default:
 420                         printk("failed\n");
 421                 }
 422         }
 423 }
 424 #endif
 425
 426 static int __init wakeup_secondary_via_INIT(int phys_apicid, unsigned int start_rip)
 427 {
 428         unsigned long send_status = 0, accept_status = 0;
 429         int maxlvt, timeout, num_starts, j;
 430
 431         Dprintk("Asserting INIT.\n");
 432
 433         /*
 434          * Turn INIT on target chip
 435          */
 436         apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid));
 437
 438         /*
 439          * Send IPI
 440          */
 441         apic_write_around(APIC_ICR, APIC_INT_LEVELTRIG | APIC_INT_ASSERT
 442                                 | APIC_DM_INIT);
 443
 444         Dprintk("Waiting for send to finish...\n");
 445         timeout = 0;
 446         do {
 447                 Dprintk("+");
 448                 udelay(100);
 449                 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
 450         } while (send_status && (timeout++ < 1000));
 451
 452         mdelay(10);
 453
 454         Dprintk("Deasserting INIT.\n");
 455
 456         /* Target chip */
 457         apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid));
 458
 459         /* Send IPI */
 460         apic_write_around(APIC_ICR, APIC_INT_LEVELTRIG | APIC_DM_INIT);
 461
 462         Dprintk("Waiting for send to finish...\n");
 463         timeout = 0;
 464         do {
 465                 Dprintk("+");
 466                 udelay(100);
 467                 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
 468         } while (send_status && (timeout++ < 1000));
 469
 470         atomic_set(&init_deasserted, 1);
 471
 472         /*
 473          * Should we send STARTUP IPIs ?
 474          *
 475          * Determine this based on the APIC version.
 476          * If we don't have an integrated APIC, don't send the STARTUP IPIs.
 477          */
 478         if (APIC_INTEGRATED(apic_version[phys_apicid]))
 479                 num_starts = 2;
 480         else
 481                 num_starts = 0;
 482
 483         /*
 484          * Run STARTUP IPI loop.
 485          */
 486         Dprintk("#startup loops: %d.\n", num_starts);
 487
 488         maxlvt = get_maxlvt();
 489
 490         for (j = 1; j <= num_starts; j++) {
 491                 Dprintk("Sending STARTUP #%d.\n",j);
 492                 apic_read_around(APIC_SPIV);
 493                 apic_write(APIC_ESR, 0);
 494                 apic_read(APIC_ESR);
 495                 Dprintk("After apic_write.\n");
 496
 497                 /*
 498                  * STARTUP IPI
 499                  */
 500
 501                 /* Target chip */
 502                 apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid));
 503
 504                 /* Boot on the stack */
 505                 /* Kick the second */
 506                 apic_write_around(APIC_ICR, APIC_DM_STARTUP
 507                                         | (start_rip >> 12));
 508
 509                 /*
 510                  * Give the other CPU some time to accept the IPI.
 511                  */
 512                 udelay(300);
 513
 514                 Dprintk("Startup point 1.\n");
 515
 516                 Dprintk("Waiting for send to finish...\n");
 517                 timeout = 0;
 518                 do {
 519                         Dprintk("+");
 520                         udelay(100);
 521                         send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
 522                 } while (send_status && (timeout++ < 1000));
 523
 524                 /*
 525                  * Give the other CPU some time to accept the IPI.
 526                  */
 527                 udelay(200);
 528                 /*
 529                  * Due to the Pentium erratum 3AP.
 530                  */
 531                 if (maxlvt > 3) {
 532                         apic_read_around(APIC_SPIV);
 533                         apic_write(APIC_ESR, 0);
 534                 }
 535                 accept_status = (apic_read(APIC_ESR) & 0xEF);
 536                 if (send_status || accept_status)
 537                         break;
 538         }
 539         Dprintk("After Startup.\n");
 540
 541         if (send_status)
 542                 printk(KERN_ERR "APIC never delivered???\n");
 543         if (accept_status)
 544                 printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status);
 545
 546         return (send_status | accept_status);
 547 }
 548
 549 static void __init do_boot_cpu (int apicid)
 550 {
 551         struct task_struct *idle;
 552         unsigned long boot_error;
 553         int timeout, cpu;
 554         unsigned long start_rip;
 555
 556         cpu = ++cpucount;
 557         /*
 558          * We can't use kernel_thread since we must avoid to
 559          * reschedule the child.
 560          */
 561         idle = fork_idle(cpu);
 562         if (IS_ERR(idle))
 563                 panic("failed fork for CPU %d", cpu);
 564         x86_cpu_to_apicid[cpu] = apicid;
 565
 566         cpu_pda[cpu].pcurrent = idle;
 567
 568         start_rip = setup_trampoline();
 569
 570         init_rsp = idle->thread.rsp;
 571         per_cpu(init_tss,cpu).rsp0 = init_rsp;
 572         initial_code = start_secondary;
 573         clear_ti_thread_flag(idle->thread_info, TIF_FORK);
 574
 575         printk(KERN_INFO "Booting processor %d/%d rip %lx rsp %lx\n", cpu, apicid,
 576                start_rip, init_rsp);
 577
 578         /*
 579          * This grunge runs the startup process for
 580          * the targeted processor.
 581          */
 582
 583         atomic_set(&init_deasserted, 0);
 584
 585         Dprintk("Setting warm reset code and vector.\n");
 586
 587         CMOS_WRITE(0xa, 0xf);
 588         local_flush_tlb();
 589         Dprintk("1.\n");
 590         *((volatile unsigned short *) phys_to_virt(0x469)) = start_rip >> 4;
 591         Dprintk("2.\n");
 592         *((volatile unsigned short *) phys_to_virt(0x467)) = start_rip & 0xf;
 593         Dprintk("3.\n");
 594
 595         /*
 596          * Be paranoid about clearing APIC errors.
 597          */
 598         if (APIC_INTEGRATED(apic_version[apicid])) {
 599                 apic_read_around(APIC_SPIV);
 600                 apic_write(APIC_ESR, 0);
 601                 apic_read(APIC_ESR);
 602         }
 603
 604         /*
 605          * Status is now clean
 606          */
 607         boot_error = 0;
 608
 609         /*
 610          * Starting actual IPI sequence...
 611          */
 612         boot_error = wakeup_secondary_via_INIT(apicid, start_rip);
 613
 614         if (!boot_error) {
 615                 /*
 616                  * allow APs to start initializing.
 617                  */
 618                 Dprintk("Before Callout %d.\n", cpu);
 619                 cpu_set(cpu, cpu_callout_map);
 620                 Dprintk("After Callout %d.\n", cpu);
 621
 622                 /*
 623                  * Wait 5s total for a response
 624                  */
 625                 for (timeout = 0; timeout < 50000; timeout++) {
 626                         if (cpu_isset(cpu, cpu_callin_map))
 627                                 break;  /* It has booted */
 628                         udelay(100);
 629                 }
 630
 631                 if (cpu_isset(cpu, cpu_callin_map)) {
 632                         /* number CPUs logically, starting from 1 (BSP is 0) */
 633                         Dprintk("OK.\n");
 634                         print_cpu_info(&cpu_data[cpu]);
 635                         Dprintk("CPU has booted.\n");
 636                 } else {
 637                         boot_error = 1;
 638                         if (*((volatile unsigned char *)phys_to_virt(SMP_TRAMPOLINE_BASE))
 639                                         == 0xA5)
 640                                 /* trampoline started but...? */
 641                                 printk("Stuck ??\n");
 642                         else
 643                                 /* trampoline code not run */
 644                                 printk("Not responding.\n");
 645 #if APIC_DEBUG
 646                         inquire_remote_apic(apicid);
 647 #endif
 648                 }
 649         }
 650         if (boot_error) {
 651                 cpu_clear(cpu, cpu_callout_map); /* was set here (do_boot_cpu()) */
 652                 clear_bit(cpu, &cpu_initialized); /* was set by cpu_init() */
 653                 cpucount--;
 654                 x86_cpu_to_apicid[cpu] = BAD_APICID;
 655                 x86_cpu_to_log_apicid[cpu] = BAD_APICID;
 656         }
 657 }
 658
 659 static void smp_tune_scheduling (void)
 660 {
 661         int cachesize;       /* kB   */
 662         unsigned long bandwidth = 1000; /* MB/s */
 663         /*
 664          * Rough estimation for SMP scheduling, this is the number of
 665          * cycles it takes for a fully memory-limited process to flush
 666          * the SMP-local cache.
 667          *
 668          * (For a P5 this pretty much means we will choose another idle
 669          *  CPU almost always at wakeup time (this is due to the small
 670          *  L1 cache), on PIIs it's around 50-100 usecs, depending on
 671          *  the cache size)
 672          */
 673
 674         if (!cpu_khz) {
 675                 return;
 676         } else {
 677                 cachesize = boot_cpu_data.x86_cache_size;
 678                 if (cachesize == -1) {
 679                         cachesize = 16; /* Pentiums, 2x8kB cache */
 680                         bandwidth = 100;
 681                 }
 682         }
 683 }
 684
 685 /*
 686  * Cycle through the processors sending APIC IPIs to boot each.
 687  */
 688
 689 static void __init smp_boot_cpus(unsigned int max_cpus)
 690 {
 691         unsigned apicid, cpu, bit, kicked;
 692
 693         nmi_watchdog_default();
 694
 695         /*
 696          * Setup boot CPU information
 697          */
 698         smp_store_cpu_info(0); /* Final full version of the data */
 699         printk(KERN_INFO "CPU%d: ", 0);
 700         print_cpu_info(&cpu_data[0]);
 701
 702         current_thread_info()->cpu = 0;
 703         smp_tune_scheduling();
 704
 705         if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) {
 706                 printk("weird, boot CPU (#%d) not listed by the BIOS.\n",
 707                        hard_smp_processor_id());
 708                 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
 709         }
 710
 711         /*
 712          * If we couldn't find an SMP configuration at boot time,
 713          * get out of here now!
 714          */
 715         if (!smp_found_config) {
 716                 printk(KERN_NOTICE "SMP motherboard not detected.\n");
 717                 io_apic_irqs = 0;
 718                 cpu_online_map = cpumask_of_cpu(0);
 719                 cpu_set(0, cpu_sibling_map[0]);
 720                 phys_cpu_present_map = physid_mask_of_physid(0);
 721                 if (APIC_init_uniprocessor())
 722                         printk(KERN_NOTICE "Local APIC not detected."
 723                                            " Using dummy APIC emulation.\n");
 724                 goto smp_done;
 725         }
 726
 727         /*
 728          * Should not be necessary because the MP table should list the boot
 729          * CPU too, but we do it for the sake of robustness anyway.
 730          */
 731         if (!physid_isset(boot_cpu_id, phys_cpu_present_map)) {
 732                 printk(KERN_NOTICE "weird, boot CPU (#%d) not listed by the BIOS.\n",
 733                                                                  boot_cpu_id);
 734                 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
 735         }
 736
 737         /*
 738          * If we couldn't find a local APIC, then get out of here now!
 739          */
 740         if (APIC_INTEGRATED(apic_version[boot_cpu_id]) && !cpu_has_apic) {
 741                 printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n",
 742                         boot_cpu_id);
 743                 printk(KERN_ERR "... forcing use of dummy APIC emulation. (tell your hw vendor)\n");
 744                 io_apic_irqs = 0;
 745                 cpu_online_map = cpumask_of_cpu(0);
 746                 cpu_set(0, cpu_sibling_map[0]);
 747                 phys_cpu_present_map = physid_mask_of_physid(0);
 748                 disable_apic = 1;
 749                 goto smp_done;
 750         }
 751
 752         verify_local_APIC();
 753
 754         /*
 755          * If SMP should be disabled, then really disable it!
 756          */
 757         if (!max_cpus) {
 758                 smp_found_config = 0;
 759                 printk(KERN_INFO "SMP mode deactivated, forcing use of dummy APIC emulation.\n");
 760                 io_apic_irqs = 0;
 761                 cpu_online_map = cpumask_of_cpu(0);
 762                 cpu_set(0, cpu_sibling_map[0]);
 763                 phys_cpu_present_map = physid_mask_of_physid(0);
 764                 disable_apic = 1;
 765                 goto smp_done;
 766         }
 767
 768         connect_bsp_APIC();
 769         setup_local_APIC();
 770
 771         if (GET_APIC_ID(apic_read(APIC_ID)) != boot_cpu_id)
 772                 BUG();
 773
 774         x86_cpu_to_apicid[0] = boot_cpu_id;
 775
 776         /*
 777          * Now scan the CPU present map and fire up the other CPUs.
 778          */
 779         Dprintk("CPU present map: %lx\n", physids_coerce(phys_cpu_present_map));
 780
 781         kicked = 1;
 782         for (bit = 0; kicked < NR_CPUS && bit < MAX_APICS; bit++) {
 783                 apicid = cpu_present_to_apicid(bit);
 784                 /*
 785                  * Don't even attempt to start the boot CPU!
 786                  */
 787                 if (apicid == boot_cpu_id || (apicid == BAD_APICID))
 788                         continue;
 789
 790                 if (!physid_isset(apicid, phys_cpu_present_map))
 791                         continue;
 792                 if ((max_cpus >= 0) && (max_cpus <= cpucount+1))
 793                         continue;
 794
 795                 do_boot_cpu(apicid);
 796                 ++kicked;
 797         }
 798
 799         /*
 800          * Cleanup possible dangling ends...
 801          */
 802         {
 803                 /*
 804                  * Install writable page 0 entry to set BIOS data area.
 805                  */
 806                 local_flush_tlb();
 807
 808                 /*
 809                  * Paranoid:  Set warm reset code and vector here back
 810                  * to default values.
 811                  */
 812                 CMOS_WRITE(0, 0xf);
 813
 814                 *((volatile int *) phys_to_virt(0x467)) = 0;
 815         }
 816
 817         /*
 818          * Allow the user to impress friends.
 819          */
 820
 821         Dprintk("Before bogomips.\n");
 822         if (!cpucount) {
 823                 printk(KERN_INFO "Only one processor found.\n");
 824         } else {
 825                 unsigned long bogosum = 0;
 826                 for (cpu = 0; cpu < NR_CPUS; cpu++)
 827                         if (cpu_isset(cpu, cpu_callout_map))
 828                                 bogosum += cpu_data[cpu].loops_per_jiffy;
 829                 printk(KERN_INFO "Total of %d processors activated (%lu.%02lu BogoMIPS).\n",
 830                         cpucount+1,
 831                         bogosum/(500000/HZ),
 832                         (bogosum/(5000/HZ))%100);
 833                 Dprintk("Before bogocount - setting activated=1.\n");
 834         }
 835
 836         /*
 837          * Construct cpu_sibling_map[], so that we can tell the
 838          * sibling CPU efficiently.
 839          */
 840         for (cpu = 0; cpu < NR_CPUS; cpu++)
 841                 cpus_clear(cpu_sibling_map[cpu]);
 842
 843         for (cpu = 0; cpu < NR_CPUS; cpu++) {
 844                 int siblings = 0;
 845                 int i;
 846                 if (!cpu_isset(cpu, cpu_callout_map))
 847                         continue;
 848
 849                 if (smp_num_siblings > 1) {
 850                         for (i = 0; i < NR_CPUS; i++) {
 851                                 if (!cpu_isset(i, cpu_callout_map))
 852                                         continue;
 853                                 if (phys_proc_id[cpu] == phys_proc_id[i]) {
 854                                         siblings++;
 855                                         cpu_set(i, cpu_sibling_map[cpu]);
 856                                 }
 857                         }
 858                 } else {
 859                         siblings++;
 860                         cpu_set(cpu, cpu_sibling_map[cpu]);
 861                 }
 862
 863                 if (siblings != smp_num_siblings) {
 864                         printk(KERN_WARNING
 865                "WARNING: %d siblings found for CPU%d, should be %d\n",
 866                                siblings, cpu, smp_num_siblings);
 867                         smp_num_siblings = siblings;
 868                 }
 869         }
 870
 871         Dprintk("Boot done.\n");
 872
 873         /*
 874          * Here we can be sure that there is an IO-APIC in the system. Let's
 875          * go and set it up:
 876          */
 877         if (!skip_ioapic_setup && nr_ioapics)
 878                 setup_IO_APIC();
 879         else
 880                 nr_ioapics = 0;
 881
 882         setup_boot_APIC_clock();
 883
 884         /*
 885          * Synchronize the TSC with the AP
 886          */
 887         if (cpu_has_tsc && cpucount)
 888                 synchronize_tsc_bp();
 889
 890  smp_done:
 891         time_init_smp();
 892 }
 893
 894 /* These are wrappers to interface to the new boot process.  Someone
 895    who understands all this stuff should rewrite it properly. --RR 15/Jul/02 */
 896 void __init smp_prepare_cpus(unsigned int max_cpus)
 897 {
 898         smp_boot_cpus(max_cpus);
 899 }
 900
 901 void __devinit smp_prepare_boot_cpu(void)
 902 {
 903         cpu_set(smp_processor_id(), cpu_online_map);
 904         cpu_set(smp_processor_id(), cpu_callout_map);
 905 }
 906
 907 int __devinit __cpu_up(unsigned int cpu)
 908 {
 909         /* This only works at boot for x86.  See "rewrite" above. */
 910         if (cpu_isset(cpu, smp_commenced_mask)) {
 911                 local_irq_enable();
 912                 return -ENOSYS;
 913         }
 914
 915         /* In case one didn't come up */
 916         if (!cpu_isset(cpu, cpu_callin_map)) {
 917                 local_irq_enable();
 918                 return -EIO;
 919         }
 920         local_irq_enable();
 921
 922         /* Unleash the CPU! */
 923         Dprintk("waiting for cpu %d\n", cpu);
 924
 925         cpu_set(cpu, smp_commenced_mask);
 926         while (!cpu_isset(cpu, cpu_online_map))
 927                 mb();
 928         return 0;
 929 }
 930
 931 void __init smp_cpus_done(unsigned int max_cpus)
 932 {
 933 #ifdef CONFIG_X86_IO_APIC
 934         setup_ioapic_dest();
 935 #endif
 936         zap_low_mappings();
 937 }
 938