arch/ppc/platforms/sandpoint.h

   1 /*
   2  * arch/ppc/platforms/sandpoint.h
   3  *
   4  * Definitions for Motorola SPS Sandpoint Test Platform
   5  *
   6  * Author: Mark A. Greer
   7  *         mgreer@mvista.com
   8  *
   9  * 2000-2003 (c) MontaVista, Software, Inc.  This file is licensed under
  10  * the terms of the GNU General Public License version 2.  This program
  11  * is licensed "as is" without any warranty of any kind, whether express
  12  * or implied.
  13  */
  14
  15 /*
  16  * Sandpoint uses the CHRP map (Map B).
  17  */
  18
  19 #ifndef __PPC_PLATFORMS_SANDPOINT_H
  20 #define __PPC_PLATFORMS_SANDPOINT_H
  21
  22 #include <asm/ppcboot.h>
  23
  24 #if 0
  25 /* The Sandpoint X3 allows the IDE interrupt to be directly connected
  26  * from the Windbond (PCI INTC or INTD) to the serial EPIC.  Someday
  27  * we should try this, but it was easier to use the existing 83c553
  28  * initialization than change it to route the different interrupts :-).
  29  *      -- Dan
  30  */
  31 #define SANDPOINT_IDE_INT0              23      /* EPIC 7 */
  32 #define SANDPOINT_IDE_INT1              24      /* EPIC 8 */
  33 #else
  34 #define SANDPOINT_IDE_INT0              14      /* 8259 Test */
  35 #define SANDPOINT_IDE_INT1              15      /* 8259 Test */
  36 #endif
  37
  38 /*
  39  * The sandpoint boards have processor modules that either have an 8240 or
  40  * an MPC107 host bridge on them.  These bridges have an IDSEL line that allows
  41  * them to respond to PCI transactions as if they were a normal PCI devices.
  42  * However, the processor on the processor side of the bridge can not reach
  43  * out onto the PCI bus and then select the bridge or bad things will happen
  44  * (documented in the 8240 and 107 manuals).
  45  * Because of this, we always skip the bridge PCI device when accessing the
  46  * PCI bus.  The PCI slot that the bridge occupies is defined by the macro
  47  * below.
  48  */
  49 #define SANDPOINT_HOST_BRIDGE_IDSEL     12
  50
  51 /*
  52  * Serial defines.
  53  */
  54 #define SANDPOINT_SERIAL_0              0xfe0003f8
  55 #define SANDPOINT_SERIAL_1              0xfe0002f8
  56
  57 #define RS_TABLE_SIZE  2
  58
  59 /* Rate for the 1.8432 Mhz clock for the onboard serial chip */
  60 #define BASE_BAUD                       ( 1843200 / 16 )
  61 #define UART_CLK                        1843200
  62
  63 #ifdef CONFIG_SERIAL_DETECT_IRQ
  64 #define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF|ASYNC_AUTO_IRQ)
  65 #else
  66 #define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF)
  67 #endif
  68
  69 #define STD_SERIAL_PORT_DFNS \
  70         { 0, BASE_BAUD, SANDPOINT_SERIAL_0, 4, STD_COM_FLAGS, /* ttyS0 */ \
  71                 iomem_base: (u8 *)SANDPOINT_SERIAL_0,                     \
  72                 io_type: SERIAL_IO_MEM },                                 \
  73         { 0, BASE_BAUD, SANDPOINT_SERIAL_1, 3, STD_COM_FLAGS, /* ttyS1 */ \
  74                 iomem_base: (u8 *)SANDPOINT_SERIAL_1,                     \
  75                 io_type: SERIAL_IO_MEM },
  76
  77 #define SERIAL_PORT_DFNS \
  78         STD_SERIAL_PORT_DFNS
  79
  80 #endif /* __PPC_PLATFORMS_SANDPOINT_H */