arch/ppc/platforms/sandpoint.c

   1 /*
   2  * arch/ppc/platforms/sandpoint_setup.c
   3  *
   4  * Board setup routines for the Motorola SPS Sandpoint Test Platform.
   5  *
   6  * Author: Mark A. Greer
   7  *       mgreer@mvista.com
   8  *
   9  * 2000-2003 (c) MontaVista Software, Inc.  This file is licensed under
  10  * the terms of the GNU General Public License version 2.  This program
  11  * is licensed "as is" without any warranty of any kind, whether express
  12  * or implied.
  13  */
  14
  15 /*
  16  * This file adds support for the Motorola SPS Sandpoint Test Platform.
  17  * These boards have a PPMC slot for the processor so any combination
  18  * of cpu and host bridge can be attached.  This port is for an 8240 PPMC
  19  * module from Motorola SPS and other closely related cpu/host bridge
  20  * combinations (e.g., 750/755/7400 with MPC107 host bridge).
  21  * The sandpoint itself has a Windbond 83c553 (PCI-ISA bridge, 2 DMA ctlrs, 2
  22  * cascaded 8259 interrupt ctlrs, 8254 Timer/Counter, and an IDE ctlr), a
  23  * National 87308 (RTC, 2 UARTs, Keyboard & mouse ctlrs, and a floppy ctlr),
  24  * and 4 PCI slots (only 2 of which are usable; the other 2 are keyed for 3.3V
  25  * but are really 5V).
  26  *
  27  * The firmware on the sandpoint is called DINK (not my acronym :).  This port
  28  * depends on DINK to do some basic initialization (e.g., initialize the memory
  29  * ctlr) and to ensure that the processor is using MAP B (CHRP map).
  30  *
  31  * The switch settings for the Sandpoint board MUST be as follows:
  32  *      S3: down
  33  *      S4: up
  34  *      S5: up
  35  *      S6: down
  36  *
  37  * 'down' is in the direction from the PCI slots towards the PPMC slot;
  38  * 'up' is in the direction from the PPMC slot towards the PCI slots.
  39  * Be careful, the way the sandpoint board is installed in XT chasses will
  40  * make the directions reversed.
  41  *
  42  * Since Motorola listened to our suggestions for improvement, we now have
  43  * the Sandpoint X3 board.  All of the PCI slots are available, it uses
  44  * the serial interrupt interface (just a hardware thing we need to
  45  * configure properly).
  46  *
  47  * Use the default X3 switch settings.  The interrupts are then:
  48  *              EPIC    Source
  49  *                0     SIOINT          (8259, active low)
  50  *                1     PCI #1
  51  *                2     PCI #2
  52  *                3     PCI #3
  53  *                4     PCI #4
  54  *                7     Winbond INTC    (IDE interrupt)
  55  *                8     Winbond INTD    (IDE interrupt)
  56  *
  57  *
  58  * Motorola has finally released a version of DINK32 that correctly
  59  * (seemingly) initalizes the memory controller correctly, regardless
  60  * of the amount of memory in the system.  Once a method of determining
  61  * what version of DINK initializes the system for us, if applicable, is
  62  * found, we can hopefully stop hardcoding 32MB of RAM.
  63  */
  64
  65 #include <linux/config.h>
  66 #include <linux/stddef.h>
  67 #include <linux/kernel.h>
  68 #include <linux/init.h>
  69 #include <linux/errno.h>
  70 #include <linux/reboot.h>
  71 #include <linux/pci.h>
  72 #include <linux/kdev_t.h>
  73 #include <linux/major.h>
  74 #include <linux/initrd.h>
  75 #include <linux/console.h>
  76 #include <linux/delay.h>
  77 #include <linux/irq.h>
  78 #include <linux/ide.h>
  79 #include <linux/seq_file.h>
  80 #include <linux/root_dev.h>
  81 #include <linux/serial.h>
  82 #include <linux/tty.h>  /* for linux/serial_core.h */
  83 #include <linux/serial_core.h>
  84
  85 #include <asm/system.h>
  86 #include <asm/pgtable.h>
  87 #include <asm/page.h>
  88 #include <asm/time.h>
  89 #include <asm/dma.h>
  90 #include <asm/io.h>
  91 #include <asm/machdep.h>
  92 #include <asm/prom.h>
  93 #include <asm/smp.h>
  94 #include <asm/vga.h>
  95 #include <asm/open_pic.h>
  96 #include <asm/i8259.h>
  97 #include <asm/todc.h>
  98 #include <asm/bootinfo.h>
  99 #include <asm/mpc10x.h>
 100 #include <asm/pci-bridge.h>
 101 #include <asm/kgdb.h>
 102
 103 #include "sandpoint.h"
 104
 105 /* Set non-zero if an X2 Sandpoint detected. */
 106 static int sandpoint_is_x2;
 107
 108 unsigned char __res[sizeof(bd_t)];
 109
 110 static void sandpoint_halt(void);
 111 static void sandpoint_probe_type(void);
 112
 113 /*
 114  * Define all of the IRQ senses and polarities.  Taken from the
 115  * Sandpoint X3 User's manual.
 116  */
 117 static u_char sandpoint_openpic_initsenses[] __initdata = {
 118         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* 0: SIOINT */
 119         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* 2: PCI Slot 1 */
 120         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* 3: PCI Slot 2 */
 121         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* 4: PCI Slot 3 */
 122         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* 5: PCI Slot 4 */
 123         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* 8: IDE (INT C) */
 124         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE)       /* 9: IDE (INT D) */
 125 };
 126
 127 /*
 128  * Motorola SPS Sandpoint interrupt routing.
 129  */
 130 static inline int
 131 x3_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
 132 {
 133         static char pci_irq_table[][4] =
 134         /*
 135          *      PCI IDSEL/INTPIN->INTLINE
 136          *         A   B   C   D
 137          */
 138         {
 139                 { 16,  0,  0,  0 },     /* IDSEL 11 - i8259 on Winbond */
 140                 {  0,  0,  0,  0 },     /* IDSEL 12 - unused */
 141                 { 18, 21, 20, 19 },     /* IDSEL 13 - PCI slot 1 */
 142                 { 19, 18, 21, 20 },     /* IDSEL 14 - PCI slot 2 */
 143                 { 20, 19, 18, 21 },     /* IDSEL 15 - PCI slot 3 */
 144                 { 21, 20, 19, 18 },     /* IDSEL 16 - PCI slot 4 */
 145         };
 146
 147         const long min_idsel = 11, max_idsel = 16, irqs_per_slot = 4;
 148         return PCI_IRQ_TABLE_LOOKUP;
 149 }
 150
 151 static inline int
 152 x2_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
 153 {
 154         static char pci_irq_table[][4] =
 155         /*
 156          *      PCI IDSEL/INTPIN->INTLINE
 157          *         A   B   C   D
 158          */
 159         {
 160                 { 18,  0,  0,  0 },     /* IDSEL 11 - i8259 on Windbond */
 161                 {  0,  0,  0,  0 },     /* IDSEL 12 - unused */
 162                 { 16, 17, 18, 19 },     /* IDSEL 13 - PCI slot 1 */
 163                 { 17, 18, 19, 16 },     /* IDSEL 14 - PCI slot 2 */
 164                 { 18, 19, 16, 17 },     /* IDSEL 15 - PCI slot 3 */
 165                 { 19, 16, 17, 18 },     /* IDSEL 16 - PCI slot 4 */
 166         };
 167
 168         const long min_idsel = 11, max_idsel = 16, irqs_per_slot = 4;
 169         return PCI_IRQ_TABLE_LOOKUP;
 170 }
 171
 172 static void __init
 173 sandpoint_setup_winbond_83553(struct pci_controller *hose)
 174 {
 175         int             devfn;
 176
 177         /*
 178          * Route IDE interrupts directly to the 8259's IRQ 14 & 15.
 179          * We can't route the IDE interrupt to PCI INTC# or INTD# because those
 180          * woule interfere with the PMC's INTC# and INTD# lines.
 181          */
 182         /*
 183          * Winbond Fcn 0
 184          */
 185         devfn = PCI_DEVFN(11,0);
 186
 187         early_write_config_byte(hose,
 188                                 0,
 189                                 devfn,
 190                                 0x43, /* IDE Interrupt Routing Control */
 191                                 0xef);
 192         early_write_config_word(hose,
 193                                 0,
 194                                 devfn,
 195                                 0x44, /* PCI Interrupt Routing Control */
 196                                 0x0000);
 197
 198         /* Want ISA memory cycles to be forwarded to PCI bus */
 199         early_write_config_byte(hose,
 200                                 0,
 201                                 devfn,
 202                                 0x48, /* ISA-to-PCI Addr Decoder Control */
 203                                 0xf0);
 204
 205         /* Enable Port 92.  */
 206         early_write_config_byte(hose,
 207                                 0,
 208                                 devfn,
 209                                 0x4e,   /* AT System Control Register */
 210                                 0x06);
 211         /*
 212          * Winbond Fcn 1
 213          */
 214         devfn = PCI_DEVFN(11,1);
 215
 216         /* Put IDE controller into native mode. */
 217         early_write_config_byte(hose,
 218                                 0,
 219                                 devfn,
 220                                 0x09,   /* Programming interface Register */
 221                                 0x8f);
 222
 223         /* Init IRQ routing, enable both ports, disable fast 16 */
 224         early_write_config_dword(hose,
 225                                 0,
 226                                 devfn,
 227                                 0x40,   /* IDE Control/Status Register */
 228                                 0x00ff0011);
 229         return;
 230 }
 231
 232 /* On the sandpoint X2, we must avoid sending configuration cycles to
 233  * device #12 (IDSEL addr = AD12).
 234  */
 235 static int
 236 x2_exclude_device(u_char bus, u_char devfn)
 237 {
 238         if ((bus == 0) && (PCI_SLOT(devfn) == SANDPOINT_HOST_BRIDGE_IDSEL))
 239                 return PCIBIOS_DEVICE_NOT_FOUND;
 240         else
 241                 return PCIBIOS_SUCCESSFUL;
 242 }
 243
 244 static void __init
 245 sandpoint_find_bridges(void)
 246 {
 247         struct pci_controller   *hose;
 248
 249         hose = pcibios_alloc_controller();
 250
 251         if (!hose)
 252                 return;
 253
 254         hose->first_busno = 0;
 255         hose->last_busno = 0xff;
 256
 257         if (mpc10x_bridge_init(hose,
 258                                MPC10X_MEM_MAP_B,
 259                                MPC10X_MEM_MAP_B,
 260                                MPC10X_MAPB_EUMB_BASE) == 0) {
 261
 262                 /* Do early winbond init, then scan PCI bus */
 263                 sandpoint_setup_winbond_83553(hose);
 264                 hose->last_busno = pciauto_bus_scan(hose, hose->first_busno);
 265
 266                 ppc_md.pcibios_fixup = NULL;
 267                 ppc_md.pcibios_fixup_bus = NULL;
 268                 ppc_md.pci_swizzle = common_swizzle;
 269                 if (sandpoint_is_x2) {
 270                         ppc_md.pci_map_irq = x2_map_irq;
 271                         ppc_md.pci_exclude_device = x2_exclude_device;
 272                 } else
 273                         ppc_md.pci_map_irq = x3_map_irq;
 274         }
 275         else {
 276                 if (ppc_md.progress)
 277                         ppc_md.progress("Bridge init failed", 0x100);
 278                 printk("Host bridge init failed\n");
 279         }
 280
 281         return;
 282 }
 283
 284 static void __init
 285 sandpoint_setup_arch(void)
 286 {
 287         /* Probe for Sandpoint model */
 288         sandpoint_probe_type();
 289         if (sandpoint_is_x2)
 290                 epic_serial_mode = 0;
 291
 292         loops_per_jiffy = 100000000 / HZ;
 293
 294 #ifdef CONFIG_BLK_DEV_INITRD
 295         if (initrd_start)
 296                 ROOT_DEV = Root_RAM0;
 297         else
 298 #endif
 299 #ifdef  CONFIG_ROOT_NFS
 300                 ROOT_DEV = Root_NFS;
 301 #else
 302                 ROOT_DEV = Root_HDA1;
 303 #endif
 304
 305         /* Lookup PCI host bridges */
 306         sandpoint_find_bridges();
 307
 308         printk(KERN_INFO "Motorola SPS Sandpoint Test Platform\n");
 309         printk(KERN_INFO "Port by MontaVista Software, Inc. (source@mvista.com)\n");
 310
 311         /* DINK32 12.3 and below do not correctly enable any caches.
 312          * We will do this now with good known values.  Future versions
 313          * of DINK32 are supposed to get this correct.
 314          */
 315         if (cpu_has_feature(CPU_FTR_SPEC7450))
 316                 /* 745x is different.  We only want to pass along enable. */
 317                 _set_L2CR(L2CR_L2E);
 318         else if (cpu_has_feature(CPU_FTR_L2CR))
 319                 /* All modules have 1MB of L2.  We also assume that an
 320                  * L2 divisor of 3 will work.
 321                  */
 322                 _set_L2CR(L2CR_L2E | L2CR_L2SIZ_1MB | L2CR_L2CLK_DIV3
 323                                 | L2CR_L2RAM_PIPE | L2CR_L2OH_1_0 | L2CR_L2DF);
 324 #if 0
 325         /* Untested right now. */
 326         if (cpu_has_feature(CPU_FTR_L3CR)) {
 327                 /* Magic value. */
 328                 _set_L3CR(0x8f032000);
 329         }
 330 #endif
 331 }
 332
 333 #define SANDPOINT_87308_CFG_ADDR                0x15c
 334 #define SANDPOINT_87308_CFG_DATA                0x15d
 335
 336 #define SANDPOINT_87308_CFG_INB(addr, byte) {                           \
 337         outb((addr), SANDPOINT_87308_CFG_ADDR);                         \
 338         (byte) = inb(SANDPOINT_87308_CFG_DATA);                         \
 339 }
 340
 341 #define SANDPOINT_87308_CFG_OUTB(addr, byte) {                          \
 342         outb((addr), SANDPOINT_87308_CFG_ADDR);                         \
 343         outb((byte), SANDPOINT_87308_CFG_DATA);                         \
 344 }
 345
 346 #define SANDPOINT_87308_SELECT_DEV(dev_num) {                           \
 347         SANDPOINT_87308_CFG_OUTB(0x07, (dev_num));                      \
 348 }
 349
 350 #define SANDPOINT_87308_DEV_ENABLE(dev_num) {                           \
 351         SANDPOINT_87308_SELECT_DEV(dev_num);                            \
 352         SANDPOINT_87308_CFG_OUTB(0x30, 0x01);                           \
 353 }
 354
 355 /*
 356  * To probe the Sandpoint type, we need to check for a connection between GPIO
 357  * pins 6 and 7 on the NS87308 SuperIO.
 358  */
 359 static void __init sandpoint_probe_type(void)
 360 {
 361         u8 x;
 362         /* First, ensure that the GPIO pins are enabled. */
 363         SANDPOINT_87308_SELECT_DEV(0x07); /* Select GPIO logical device */
 364         SANDPOINT_87308_CFG_OUTB(0x60, 0x07); /* Base address 0x700 */
 365         SANDPOINT_87308_CFG_OUTB(0x61, 0x00);
 366         SANDPOINT_87308_CFG_OUTB(0x30, 0x01); /* Enable */
 367
 368         /* Now, set pin 7 to output and pin 6 to input. */
 369         outb((inb(0x701) | 0x80) & 0xbf, 0x701);
 370         /* Set push-pull output */
 371         outb(inb(0x702) | 0x80, 0x702);
 372         /* Set pull-up on input */
 373         outb(inb(0x703) | 0x40, 0x703);
 374         /* Set output high and check */
 375         x = inb(0x700);
 376         outb(x | 0x80, 0x700);
 377         x = inb(0x700);
 378         sandpoint_is_x2 = ! (x & 0x40);
 379         if (ppc_md.progress && sandpoint_is_x2)
 380                 ppc_md.progress("High output says X2", 0);
 381         /* Set output low and check */
 382         outb(x & 0x7f, 0x700);
 383         sandpoint_is_x2 |= inb(0x700) & 0x40;
 384         if (ppc_md.progress && sandpoint_is_x2)
 385                 ppc_md.progress("Low output says X2", 0);
 386         if (ppc_md.progress && ! sandpoint_is_x2)
 387                 ppc_md.progress("Sandpoint is X3", 0);
 388 }
 389
 390 /*
 391  * Fix IDE interrupts.
 392  */
 393 static int __init
 394 sandpoint_fix_winbond_83553(void)
 395 {
 396         /* Make some 8259 interrupt level sensitive */
 397         outb(0xe0, 0x4d0);
 398         outb(0xde, 0x4d1);
 399
 400         return 0;
 401 }
 402
 403 arch_initcall(sandpoint_fix_winbond_83553);
 404
 405 /*
 406  * Initialize the ISA devices on the Nat'l PC87308VUL SuperIO chip.
 407  */
 408 static int __init
 409 sandpoint_setup_natl_87308(void)
 410 {
 411         u_char  reg;
 412
 413         /*
 414          * Enable all the devices on the Super I/O chip.
 415          */
 416         SANDPOINT_87308_SELECT_DEV(0x00); /* Select kbd logical device */
 417         SANDPOINT_87308_CFG_OUTB(0xf0, 0x00); /* Set KBC clock to 8 Mhz */
 418         SANDPOINT_87308_DEV_ENABLE(0x00); /* Enable keyboard */
 419         SANDPOINT_87308_DEV_ENABLE(0x01); /* Enable mouse */
 420         SANDPOINT_87308_DEV_ENABLE(0x02); /* Enable rtc */
 421         SANDPOINT_87308_DEV_ENABLE(0x03); /* Enable fdc (floppy) */
 422         SANDPOINT_87308_DEV_ENABLE(0x04); /* Enable parallel */
 423         SANDPOINT_87308_DEV_ENABLE(0x05); /* Enable UART 2 */
 424         SANDPOINT_87308_CFG_OUTB(0xf0, 0x82); /* Enable bank select regs */
 425         SANDPOINT_87308_DEV_ENABLE(0x06); /* Enable UART 1 */
 426         SANDPOINT_87308_CFG_OUTB(0xf0, 0x82); /* Enable bank select regs */
 427
 428         /* Set up floppy in PS/2 mode */
 429         outb(0x09, SIO_CONFIG_RA);
 430         reg = inb(SIO_CONFIG_RD);
 431         reg = (reg & 0x3F) | 0x40;
 432         outb(reg, SIO_CONFIG_RD);
 433         outb(reg, SIO_CONFIG_RD);       /* Have to write twice to change! */
 434
 435         return 0;
 436 }
 437
 438 arch_initcall(sandpoint_setup_natl_87308);
 439
 440 static int __init
 441 sandpoint_request_io(void)
 442 {
 443         request_region(0x00,0x20,"dma1");
 444         request_region(0x20,0x20,"pic1");
 445         request_region(0x40,0x20,"timer");
 446         request_region(0x80,0x10,"dma page reg");
 447         request_region(0xa0,0x20,"pic2");
 448         request_region(0xc0,0x20,"dma2");
 449
 450         return 0;
 451 }
 452
 453 arch_initcall(sandpoint_request_io);
 454
 455 /*
 456  * Interrupt setup and service.  Interrrupts on the Sandpoint come
 457  * from the four PCI slots plus the 8259 in the Winbond Super I/O (SIO).
 458  * The 8259 is cascaded from EPIC IRQ0, IRQ1-4 map to PCI slots 1-4,
 459  * IDE is on EPIC 7 and 8.
 460  */
 461 static void __init
 462 sandpoint_init_IRQ(void)
 463 {
 464         int i;
 465
 466         OpenPIC_InitSenses = sandpoint_openpic_initsenses;
 467         OpenPIC_NumInitSenses = sizeof(sandpoint_openpic_initsenses);
 468
 469         mpc10x_set_openpic();
 470         openpic_hookup_cascade(sandpoint_is_x2 ? 17 : NUM_8259_INTERRUPTS, "82c59 cascade",
 471                         i8259_irq);
 472
 473         /*
 474          * openpic_init() has set up irq_desc[16-31] to be openpic
 475          * interrupts.  We need to set irq_desc[0-15] to be i8259
 476          * interrupts.
 477          */
 478         for(i=0; i < NUM_8259_INTERRUPTS; i++)
 479                 irq_desc[i].handler = &i8259_pic;
 480
 481         /*
 482          * The EPIC allows for a read in the range of 0xFEF00000 ->
 483          * 0xFEFFFFFF to generate a PCI interrupt-acknowledge transaction.
 484          */
 485         i8259_init(0xfef00000);
 486 }
 487
 488 static u32
 489 sandpoint_irq_canonicalize(u32 irq)
 490 {
 491         if (irq == 2)
 492                 return 9;
 493         else
 494                 return irq;
 495 }
 496
 497 static unsigned long __init
 498 sandpoint_find_end_of_memory(void)
 499 {
 500         bd_t *bp = (bd_t *)__res;
 501
 502         if (bp->bi_memsize)
 503                 return bp->bi_memsize;
 504
 505         /* DINK32 13.0 correctly initalizes things, so iff you use
 506          * this you _should_ be able to change this instead of a
 507          * hardcoded value. */
 508 #if 0
 509         return mpc10x_get_mem_size(MPC10X_MEM_MAP_B);
 510 #else
 511         return 32*1024*1024;
 512 #endif
 513 }
 514
 515 static void __init
 516 sandpoint_map_io(void)
 517 {
 518         io_block_mapping(0xfe000000, 0xfe000000, 0x02000000, _PAGE_IO);
 519 }
 520
 521 static void
 522 sandpoint_restart(char *cmd)
 523 {
 524         local_irq_disable();
 525
 526         /* Set exception prefix high - to the firmware */
 527         _nmask_and_or_msr(0, MSR_IP);
 528
 529         /* Reset system via Port 92 */
 530         outb(0x00, 0x92);
 531         outb(0x01, 0x92);
 532         for(;;);        /* Spin until reset happens */
 533 }
 534
 535 static void
 536 sandpoint_power_off(void)
 537 {
 538         local_irq_disable();
 539         for(;;);        /* No way to shut power off with software */
 540         /* NOTREACHED */
 541 }
 542
 543 static void
 544 sandpoint_halt(void)
 545 {
 546         sandpoint_power_off();
 547         /* NOTREACHED */
 548 }
 549
 550 static int
 551 sandpoint_show_cpuinfo(struct seq_file *m)
 552 {
 553         seq_printf(m, "vendor\t\t: Motorola SPS\n");
 554         seq_printf(m, "machine\t\t: Sandpoint\n");
 555
 556         return 0;
 557 }
 558
 559 #if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
 560 /*
 561  * IDE support.
 562  */
 563 static int              sandpoint_ide_ports_known = 0;
 564 static unsigned long    sandpoint_ide_regbase[MAX_HWIFS];
 565 static unsigned long    sandpoint_ide_ctl_regbase[MAX_HWIFS];
 566 static unsigned long    sandpoint_idedma_regbase;
 567
 568 static void
 569 sandpoint_ide_probe(void)
 570 {
 571         struct pci_dev *pdev = pci_get_device(PCI_VENDOR_ID_WINBOND,
 572                         PCI_DEVICE_ID_WINBOND_82C105, NULL);
 573
 574         if (pdev) {
 575                 sandpoint_ide_regbase[0]=pdev->resource[0].start;
 576                 sandpoint_ide_regbase[1]=pdev->resource[2].start;
 577                 sandpoint_ide_ctl_regbase[0]=pdev->resource[1].start;
 578                 sandpoint_ide_ctl_regbase[1]=pdev->resource[3].start;
 579                 sandpoint_idedma_regbase=pdev->resource[4].start;
 580                 pci_dev_put(pdev);
 581         }
 582
 583         sandpoint_ide_ports_known = 1;
 584 }
 585
 586 static int
 587 sandpoint_ide_default_irq(unsigned long base)
 588 {
 589         if (sandpoint_ide_ports_known == 0)
 590                 sandpoint_ide_probe();
 591
 592         if (base == sandpoint_ide_regbase[0])
 593                 return SANDPOINT_IDE_INT0;
 594         else if (base == sandpoint_ide_regbase[1])
 595                 return SANDPOINT_IDE_INT1;
 596         else
 597                 return 0;
 598 }
 599
 600 static unsigned long
 601 sandpoint_ide_default_io_base(int index)
 602 {
 603         if (sandpoint_ide_ports_known == 0)
 604                 sandpoint_ide_probe();
 605
 606         return sandpoint_ide_regbase[index];
 607 }
 608
 609 static void __init
 610 sandpoint_ide_init_hwif_ports(hw_regs_t *hw, unsigned long data_port,
 611                 unsigned long ctrl_port, int *irq)
 612 {
 613         unsigned long reg = data_port;
 614         uint    alt_status_base;
 615         int     i;
 616
 617         for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++) {
 618                 hw->io_ports[i] = reg++;
 619         }
 620
 621         if (data_port == sandpoint_ide_regbase[0]) {
 622                 alt_status_base = sandpoint_ide_ctl_regbase[0] + 2;
 623                 hw->irq = 14;
 624         }
 625         else if (data_port == sandpoint_ide_regbase[1]) {
 626                 alt_status_base = sandpoint_ide_ctl_regbase[1] + 2;
 627                 hw->irq = 15;
 628         }
 629         else {
 630                 alt_status_base = 0;
 631                 hw->irq = 0;
 632         }
 633
 634         if (ctrl_port) {
 635                 hw->io_ports[IDE_CONTROL_OFFSET] = ctrl_port;
 636         } else {
 637                 hw->io_ports[IDE_CONTROL_OFFSET] = alt_status_base;
 638         }
 639
 640         if (irq != NULL) {
 641                 *irq = hw->irq;
 642         }
 643 }
 644 #endif
 645
 646 /*
 647  * Set BAT 3 to map 0xf8000000 to end of physical memory space 1-to-1.
 648  */
 649 static __inline__ void
 650 sandpoint_set_bat(void)
 651 {
 652         unsigned long bat3u, bat3l;
 653
 654         __asm__ __volatile__(
 655                         " lis %0,0xf800\n       \
 656                         ori %1,%0,0x002a\n      \
 657                         ori %0,%0,0x0ffe\n      \
 658                         mtspr 0x21e,%0\n        \
 659                         mtspr 0x21f,%1\n        \
 660                         isync\n                 \
 661                         sync "
 662                         : "=r" (bat3u), "=r" (bat3l));
 663 }
 664
 665 TODC_ALLOC();
 666
 667 void __init
 668 platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
 669                 unsigned long r6, unsigned long r7)
 670 {
 671         parse_bootinfo(find_bootinfo());
 672
 673         /* ASSUMPTION:  If both r3 (bd_t pointer) and r6 (cmdline pointer)
 674          * are non-zero, then we should use the board info from the bd_t
 675          * structure and the cmdline pointed to by r6 instead of the
 676          * information from birecs, if any.  Otherwise, use the information
 677          * from birecs as discovered by the preceeding call to
 678          * parse_bootinfo().  This rule should work with both PPCBoot, which
 679          * uses a bd_t board info structure, and the kernel boot wrapper,
 680          * which uses birecs.
 681          */
 682         if (r3 && r6) {
 683                 /* copy board info structure */
 684                 memcpy( (void *)__res,(void *)(r3+KERNELBASE), sizeof(bd_t) );
 685                 /* copy command line */
 686                 *(char *)(r7+KERNELBASE) = 0;
 687                 strcpy(cmd_line, (char *)(r6+KERNELBASE));
 688         }
 689
 690 #ifdef CONFIG_BLK_DEV_INITRD
 691         /* take care of initrd if we have one */
 692         if (r4) {
 693                 initrd_start = r4 + KERNELBASE;
 694                 initrd_end = r5 + KERNELBASE;
 695         }
 696 #endif /* CONFIG_BLK_DEV_INITRD */
 697
 698         /* Map in board regs, etc. */
 699         sandpoint_set_bat();
 700
 701         isa_io_base = MPC10X_MAPB_ISA_IO_BASE;
 702         isa_mem_base = MPC10X_MAPB_ISA_MEM_BASE;
 703         pci_dram_offset = MPC10X_MAPB_DRAM_OFFSET;
 704         ISA_DMA_THRESHOLD = 0x00ffffff;
 705         DMA_MODE_READ = 0x44;
 706         DMA_MODE_WRITE = 0x48;
 707
 708         ppc_md.setup_arch = sandpoint_setup_arch;
 709         ppc_md.show_cpuinfo = sandpoint_show_cpuinfo;
 710         ppc_md.irq_canonicalize = sandpoint_irq_canonicalize;
 711         ppc_md.init_IRQ = sandpoint_init_IRQ;
 712         ppc_md.get_irq = openpic_get_irq;
 713
 714         ppc_md.restart = sandpoint_restart;
 715         ppc_md.power_off = sandpoint_power_off;
 716         ppc_md.halt = sandpoint_halt;
 717
 718         ppc_md.find_end_of_memory = sandpoint_find_end_of_memory;
 719         ppc_md.setup_io_mappings = sandpoint_map_io;
 720
 721         TODC_INIT(TODC_TYPE_PC97307, 0x70, 0x00, 0x71, 8);
 722         ppc_md.time_init = todc_time_init;
 723         ppc_md.set_rtc_time = todc_set_rtc_time;
 724         ppc_md.get_rtc_time = todc_get_rtc_time;
 725         ppc_md.calibrate_decr = todc_calibrate_decr;
 726
 727         ppc_md.nvram_read_val = todc_mc146818_read_val;
 728         ppc_md.nvram_write_val = todc_mc146818_write_val;
 729
 730 #ifdef CONFIG_KGDB
 731         ppc_md.kgdb_map_scc = gen550_kgdb_map_scc;
 732 #endif
 733 #ifdef CONFIG_SERIAL_TEXT_DEBUG
 734         ppc_md.progress = gen550_progress;
 735 #endif
 736
 737 #if defined(CONFIG_BLK_DEV_IDE) || defined(CONFIG_BLK_DEV_IDE_MODULE)
 738         ppc_ide_md.default_irq = sandpoint_ide_default_irq;
 739         ppc_ide_md.default_io_base = sandpoint_ide_default_io_base;
 740         ppc_ide_md.ide_init_hwif = sandpoint_ide_init_hwif_ports;
 741 #endif
 742 }