arch/ppc/platforms/4xx/luan.c

   1 /*
   2  * arch/ppc/platforms/4xx/luan.c
   3  *
   4  * Luan board specific routines
   5  *
   6  * Matt Porter <mporter@kernel.crashing.org>
   7  *
   8  * Copyright 2004-2005 MontaVista Software Inc.
   9  *
  10  * This program is free software; you can redistribute  it and/or modify it
  11  * under  the terms of  the GNU General  Public License as published by the
  12  * Free Software Foundation;  either version 2 of the  License, or (at your
  13  * option) any later version.
  14  */
  15
  16 #include <linux/config.h>
  17 #include <linux/stddef.h>
  18 #include <linux/kernel.h>
  19 #include <linux/init.h>
  20 #include <linux/errno.h>
  21 #include <linux/reboot.h>
  22 #include <linux/pci.h>
  23 #include <linux/kdev_t.h>
  24 #include <linux/types.h>
  25 #include <linux/major.h>
  26 #include <linux/blkdev.h>
  27 #include <linux/console.h>
  28 #include <linux/delay.h>
  29 #include <linux/ide.h>
  30 #include <linux/initrd.h>
  31 #include <linux/irq.h>
  32 #include <linux/seq_file.h>
  33 #include <linux/root_dev.h>
  34 #include <linux/tty.h>
  35 #include <linux/serial.h>
  36 #include <linux/serial_core.h>
  37
  38 #include <asm/system.h>
  39 #include <asm/pgtable.h>
  40 #include <asm/page.h>
  41 #include <asm/dma.h>
  42 #include <asm/io.h>
  43 #include <asm/machdep.h>
  44 #include <asm/ocp.h>
  45 #include <asm/pci-bridge.h>
  46 #include <asm/time.h>
  47 #include <asm/todc.h>
  48 #include <asm/bootinfo.h>
  49 #include <asm/ppc4xx_pic.h>
  50 #include <asm/ppcboot.h>
  51
  52 #include <syslib/ibm44x_common.h>
  53 #include <syslib/ibm440gx_common.h>
  54 #include <syslib/ibm440sp_common.h>
  55
  56 /*
  57  * This is a horrible kludge, we eventually need to abstract this
  58  * generic PHY stuff, so the  standard phy mode defines can be
  59  * easily used from arch code.
  60  */
  61 #include "../../../../drivers/net/ibm_emac/ibm_emac_phy.h"
  62
  63 bd_t __res;
  64
  65 static struct ibm44x_clocks clocks __initdata;
  66
  67 static void __init
  68 luan_calibrate_decr(void)
  69 {
  70         unsigned int freq;
  71
  72         if (mfspr(SPRN_CCR1) & CCR1_TCS)
  73                 freq = LUAN_TMR_CLK;
  74         else
  75                 freq = clocks.cpu;
  76
  77         ibm44x_calibrate_decr(freq);
  78 }
  79
  80 static int
  81 luan_show_cpuinfo(struct seq_file *m)
  82 {
  83         seq_printf(m, "vendor\t\t: IBM\n");
  84         seq_printf(m, "machine\t\t: PPC440SP EVB (Luan)\n");
  85
  86         return 0;
  87 }
  88
  89 static inline int
  90 luan_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
  91 {
  92         struct pci_controller *hose = pci_bus_to_hose(dev->bus->number);
  93
  94         /* PCIX0 in adapter mode, no host interrupt routing */
  95
  96         /* PCIX1 */
  97         if (hose->index == 0) {
  98                 static char pci_irq_table[][4] =
  99                 /*
 100                  *      PCI IDSEL/INTPIN->INTLINE
 101                  *        A   B   C   D
 102                  */
 103                 {
 104                         { 49, 49, 49, 49 },     /* IDSEL 1 - PCIX1 Slot 0 */
 105                         { 49, 49, 49, 49 },     /* IDSEL 2 - PCIX1 Slot 1 */
 106                         { 49, 49, 49, 49 },     /* IDSEL 3 - PCIX1 Slot 2 */
 107                         { 49, 49, 49, 49 },     /* IDSEL 4 - PCIX1 Slot 3 */
 108                 };
 109                 const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
 110                 return PCI_IRQ_TABLE_LOOKUP;
 111         /* PCIX2 */
 112         } else if (hose->index == 1) {
 113                 static char pci_irq_table[][4] =
 114                 /*
 115                  *      PCI IDSEL/INTPIN->INTLINE
 116                  *        A   B   C   D
 117                  */
 118                 {
 119                         { 50, 50, 50, 50 },     /* IDSEL 1 - PCIX2 Slot 0 */
 120                         { 50, 50, 50, 50 },     /* IDSEL 2 - PCIX2 Slot 1 */
 121                         { 50, 50, 50, 50 },     /* IDSEL 3 - PCIX2 Slot 2 */
 122                         { 50, 50, 50, 50 },     /* IDSEL 4 - PCIX2 Slot 3 */
 123                 };
 124                 const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
 125                 return PCI_IRQ_TABLE_LOOKUP;
 126         }
 127         return -1;
 128 }
 129
 130 static void __init luan_set_emacdata(void)
 131 {
 132         struct ocp_def *def;
 133         struct ocp_func_emac_data *emacdata;
 134
 135         /* Set phy_map, phy_mode, and mac_addr for the EMAC */
 136         def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, 0);
 137         emacdata = def->additions;
 138         emacdata->phy_map = 0x00000001; /* Skip 0x00 */
 139         emacdata->phy_mode = PHY_MODE_GMII;
 140         memcpy(emacdata->mac_addr, __res.bi_enetaddr, 6);
 141 }
 142
 143 #define PCIX_READW(offset) \
 144         (readw((void *)((u32)pcix_reg_base+offset)))
 145
 146 #define PCIX_WRITEW(value, offset) \
 147         (writew(value, (void *)((u32)pcix_reg_base+offset)))
 148
 149 #define PCIX_WRITEL(value, offset) \
 150         (writel(value, (void *)((u32)pcix_reg_base+offset)))
 151
 152 static void __init
 153 luan_setup_pcix(void)
 154 {
 155         int i;
 156         void *pcix_reg_base;
 157
 158         for (i=0;i<3;i++) {
 159                 pcix_reg_base = ioremap64(PCIX0_REG_BASE + i*PCIX_REG_OFFSET, PCIX_REG_SIZE);
 160
 161                 /* Enable PCIX0 I/O, Mem, and Busmaster cycles */
 162                 PCIX_WRITEW(PCIX_READW(PCIX0_COMMAND) | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER, PCIX0_COMMAND);
 163
 164                 /* Disable all windows */
 165                 PCIX_WRITEL(0, PCIX0_POM0SA);
 166                 PCIX_WRITEL(0, PCIX0_POM1SA);
 167                 PCIX_WRITEL(0, PCIX0_POM2SA);
 168                 PCIX_WRITEL(0, PCIX0_PIM0SA);
 169                 PCIX_WRITEL(0, PCIX0_PIM0SAH);
 170                 PCIX_WRITEL(0, PCIX0_PIM1SA);
 171                 PCIX_WRITEL(0, PCIX0_PIM2SA);
 172                 PCIX_WRITEL(0, PCIX0_PIM2SAH);
 173
 174                 /*
 175                  * Setup 512MB PLB->PCI outbound mem window
 176                  * (a_n000_0000->0_n000_0000)
 177                  * */
 178                 PCIX_WRITEL(0x0000000a, PCIX0_POM0LAH);
 179                 PCIX_WRITEL(0x80000000 | i*LUAN_PCIX_MEM_SIZE, PCIX0_POM0LAL);
 180                 PCIX_WRITEL(0x00000000, PCIX0_POM0PCIAH);
 181                 PCIX_WRITEL(0x80000000 | i*LUAN_PCIX_MEM_SIZE, PCIX0_POM0PCIAL);
 182                 PCIX_WRITEL(0xe0000001, PCIX0_POM0SA);
 183
 184                 /* Setup 2GB PCI->PLB inbound memory window at 0, enable MSIs */
 185                 PCIX_WRITEL(0x00000000, PCIX0_PIM0LAH);
 186                 PCIX_WRITEL(0x00000000, PCIX0_PIM0LAL);
 187                 PCIX_WRITEL(0xe0000007, PCIX0_PIM0SA);
 188                 PCIX_WRITEL(0xffffffff, PCIX0_PIM0SAH);
 189
 190                 iounmap(pcix_reg_base);
 191         }
 192
 193         eieio();
 194 }
 195
 196 static void __init
 197 luan_setup_hose(struct pci_controller *hose,
 198                 int lower_mem,
 199                 int upper_mem,
 200                 int cfga,
 201                 int cfgd,
 202                 u64 pcix_io_base)
 203 {
 204         char name[20];
 205
 206         sprintf(name, "PCIX%d host bridge", hose->index);
 207
 208         hose->pci_mem_offset = LUAN_PCIX_MEM_OFFSET;
 209
 210         pci_init_resource(&hose->io_resource,
 211                         LUAN_PCIX_LOWER_IO,
 212                         LUAN_PCIX_UPPER_IO,
 213                         IORESOURCE_IO,
 214                         name);
 215
 216         pci_init_resource(&hose->mem_resources[0],
 217                         lower_mem,
 218                         upper_mem,
 219                         IORESOURCE_MEM,
 220                         name);
 221
 222         hose->io_space.start = LUAN_PCIX_LOWER_IO;
 223         hose->io_space.end = LUAN_PCIX_UPPER_IO;
 224         hose->mem_space.start = lower_mem;
 225         hose->mem_space.end = upper_mem;
 226         isa_io_base =
 227                 (unsigned long)ioremap64(pcix_io_base, PCIX_IO_SIZE);
 228         hose->io_base_virt = (void *)isa_io_base;
 229
 230         setup_indirect_pci(hose, cfga, cfgd);
 231         hose->set_cfg_type = 1;
 232 }
 233
 234 static void __init
 235 luan_setup_hoses(void)
 236 {
 237         struct pci_controller *hose1, *hose2;
 238
 239         /* Configure windows on the PCI-X host bridge */
 240         luan_setup_pcix();
 241
 242         /* Allocate hoses for PCIX1 and PCIX2 */
 243         hose1 = pcibios_alloc_controller();
 244         hose2 = pcibios_alloc_controller();
 245         if (!hose1 || !hose2)
 246                 return;
 247
 248         /* Setup PCIX1 */
 249         hose1->first_busno = 0;
 250         hose1->last_busno = 0xff;
 251
 252         luan_setup_hose(hose1,
 253                         LUAN_PCIX1_LOWER_MEM,
 254                         LUAN_PCIX1_UPPER_MEM,
 255                         PCIX1_CFGA,
 256                         PCIX1_CFGD,
 257                         PCIX1_IO_BASE);
 258
 259         hose1->last_busno = pciauto_bus_scan(hose1, hose1->first_busno);
 260
 261         /* Setup PCIX2 */
 262         hose2->first_busno = hose1->last_busno + 1;
 263         hose2->last_busno = 0xff;
 264
 265         luan_setup_hose(hose2,
 266                         LUAN_PCIX2_LOWER_MEM,
 267                         LUAN_PCIX2_UPPER_MEM,
 268                         PCIX2_CFGA,
 269                         PCIX2_CFGD,
 270                         PCIX2_IO_BASE);
 271
 272         hose2->last_busno = pciauto_bus_scan(hose2, hose2->first_busno);
 273
 274         ppc_md.pci_swizzle = common_swizzle;
 275         ppc_md.pci_map_irq = luan_map_irq;
 276 }
 277
 278 TODC_ALLOC();
 279
 280 static void __init
 281 luan_early_serial_map(void)
 282 {
 283         struct uart_port port;
 284
 285         /* Setup ioremapped serial port access */
 286         memset(&port, 0, sizeof(port));
 287         port.membase = ioremap64(PPC440SP_UART0_ADDR, 8);
 288         port.irq = UART0_INT;
 289         port.uartclk = clocks.uart0;
 290         port.regshift = 0;
 291         port.iotype = SERIAL_IO_MEM;
 292         port.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST;
 293         port.line = 0;
 294
 295         if (early_serial_setup(&port) != 0) {
 296                 printk("Early serial init of port 0 failed\n");
 297         }
 298
 299         port.membase = ioremap64(PPC440SP_UART1_ADDR, 8);
 300         port.irq = UART1_INT;
 301         port.uartclk = clocks.uart1;
 302         port.line = 1;
 303
 304         if (early_serial_setup(&port) != 0) {
 305                 printk("Early serial init of port 1 failed\n");
 306         }
 307
 308         port.membase = ioremap64(PPC440SP_UART2_ADDR, 8);
 309         port.irq = UART2_INT;
 310         port.uartclk = BASE_BAUD;
 311         port.line = 2;
 312
 313         if (early_serial_setup(&port) != 0) {
 314                 printk("Early serial init of port 2 failed\n");
 315         }
 316 }
 317
 318 static void __init
 319 luan_setup_arch(void)
 320 {
 321         luan_set_emacdata();
 322
 323 #if !defined(CONFIG_BDI_SWITCH)
 324         /*
 325          * The Abatron BDI JTAG debugger does not tolerate others
 326          * mucking with the debug registers.
 327          */
 328         mtspr(SPRN_DBCR0, (DBCR0_TDE | DBCR0_IDM));
 329 #endif
 330
 331         /*
 332          * Determine various clocks.
 333          * To be completely correct we should get SysClk
 334          * from FPGA, because it can be changed by on-board switches
 335          * --ebs
 336          */
 337         /* 440GX and 440SP clocking is the same -mdp */
 338         ibm440gx_get_clocks(&clocks, 33333333, 6 * 1843200);
 339         ocp_sys_info.opb_bus_freq = clocks.opb;
 340
 341         /* init to some ~sane value until calibrate_delay() runs */
 342         loops_per_jiffy = 50000000/HZ;
 343
 344         /* Setup PCIXn host bridges */
 345         luan_setup_hoses();
 346
 347 #ifdef CONFIG_BLK_DEV_INITRD
 348         if (initrd_start)
 349                 ROOT_DEV = Root_RAM0;
 350         else
 351 #endif
 352 #ifdef CONFIG_ROOT_NFS
 353                 ROOT_DEV = Root_NFS;
 354 #else
 355                 ROOT_DEV = Root_HDA1;
 356 #endif
 357
 358         luan_early_serial_map();
 359
 360         /* Identify the system */
 361         printk("Luan port (MontaVista Software, Inc. <source@mvista.com>)\n");
 362 }
 363
 364 void __init platform_init(unsigned long r3, unsigned long r4,
 365                 unsigned long r5, unsigned long r6, unsigned long r7)
 366 {
 367         parse_bootinfo(find_bootinfo());
 368
 369         /*
 370          * If we were passed in a board information, copy it into the
 371          * residual data area.
 372          */
 373         if (r3)
 374                 __res = *(bd_t *)(r3 + KERNELBASE);
 375
 376         ibm44x_platform_init();
 377
 378         ppc_md.setup_arch = luan_setup_arch;
 379         ppc_md.show_cpuinfo = luan_show_cpuinfo;
 380         ppc_md.find_end_of_memory = ibm440sp_find_end_of_memory;
 381         ppc_md.get_irq = NULL;          /* Set in ppc4xx_pic_init() */
 382
 383         ppc_md.calibrate_decr = luan_calibrate_decr;
 384 #ifdef CONFIG_KGDB
 385         ppc_md.early_serial_map = luan_early_serial_map;
 386 #endif
 387 }