arch/ppc/platforms/4xx/ibmnp405h.h

   1 /*
   2  * arch/ppc/platforms/4xx/ibmnp405h.h
   3  *
   4  * Author: Armin Kuster <akuster@mvista.com>
   5  *
   6  * 2002 (c) MontaVista, Software, Inc.  This file is licensed under
   7  * the terms of the GNU General Public License version 2.  This program
   8  * is licensed "as is" without any warranty of any kind, whether express
   9  * or implied.
  10  */
  11
  12 #ifdef __KERNEL__
  13 #ifndef __ASM_IBMNP405H_H__
  14 #define __ASM_IBMNP405H_H__
  15
  16 #include <linux/config.h>
  17
  18 /* ibm405.h at bottom of this file */
  19
  20 #define PPC405_PCI_CONFIG_ADDR  0xeec00000
  21 #define PPC405_PCI_CONFIG_DATA  0xeec00004
  22 #define PPC405_PCI_PHY_MEM_BASE 0x80000000      /* hose_a->pci_mem_offset */
  23                                                 /* setbat */
  24 #define PPC405_PCI_MEM_BASE     PPC405_PCI_PHY_MEM_BASE /* setbat */
  25 #define PPC405_PCI_PHY_IO_BASE  0xe8000000      /* setbat */
  26 #define PPC405_PCI_IO_BASE      PPC405_PCI_PHY_IO_BASE  /* setbat */
  27
  28 #define PPC405_PCI_LOWER_MEM    0x00000000      /* hose_a->mem_space.start */
  29 #define PPC405_PCI_UPPER_MEM    0xBfffffff      /* hose_a->mem_space.end */
  30 #define PPC405_PCI_LOWER_IO     0x00000000      /* hose_a->io_space.start */
  31 #define PPC405_PCI_UPPER_IO     0x0000ffff      /* hose_a->io_space.end */
  32
  33 #define PPC405_ISA_IO_BASE      PPC405_PCI_IO_BASE
  34
  35 #define PPC4xx_PCI_IO_ADDR      ((uint)PPC405_PCI_PHY_IO_BASE)
  36 #define PPC4xx_PCI_IO_SIZE      ((uint)64*1024)
  37 #define PPC4xx_PCI_CFG_ADDR     ((uint)PPC405_PCI_CONFIG_ADDR)
  38 #define PPC4xx_PCI_CFG_SIZE     ((uint)4*1024)
  39 #define PPC4xx_PCI_LCFG_ADDR    ((uint)0xef400000)
  40 #define PPC4xx_PCI_LCFG_SIZE    ((uint)4*1024)
  41 #define PPC4xx_ONB_IO_ADDR      ((uint)0xef600000)
  42 #define PPC4xx_ONB_IO_SIZE      ((uint)4*1024)
  43
  44 /* serial port defines */
  45 #define RS_TABLE_SIZE   4
  46
  47 #define UART0_INT       0
  48 #define UART1_INT       1
  49 #define PCIL0_BASE      0xEF400000
  50 #define UART0_IO_BASE   0xEF600300
  51 #define UART1_IO_BASE   0xEF600400
  52 #define OPB0_BASE       0xEF600600
  53 #define EMAC0_BASE      0xEF600800
  54
  55 #define BD_EMAC_ADDR(e,i) bi_enetaddr[e][i]
  56
  57 #define STD_UART_OP(num)                                        \
  58         { 0, BASE_BAUD, 0, UART##num##_INT,                     \
  59                 (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST),        \
  60                 iomem_base:(u8 *) UART##num##_IO_BASE,          \
  61                 io_type: SERIAL_IO_MEM},
  62
  63 #if defined(CONFIG_UART0_TTYS0)
  64 #define SERIAL_DEBUG_IO_BASE    UART0_IO_BASE
  65 #define SERIAL_PORT_DFNS        \
  66         STD_UART_OP(0)          \
  67         STD_UART_OP(1)
  68 #endif
  69
  70 #if defined(CONFIG_UART0_TTYS1)
  71 #define SERIAL_DEBUG_IO_BASE    UART0_IO_BASE
  72 #define SERIAL_PORT_DFNS        \
  73         STD_UART_OP(1)          \
  74         STD_UART_OP(0)
  75 #endif
  76
  77 /* DCR defines */
  78 /* ------------------------------------------------------------------------- */
  79
  80 #define DCRN_CHCR_BASE  0x0F1
  81 #define DCRN_CHPSR_BASE 0x0B4
  82 #define DCRN_CPMSR_BASE 0x0BA
  83 #define DCRN_CPMFR_BASE 0x0B9
  84 #define DCRN_CPMER_BASE 0x0B8
  85
  86 /* CPM Clocking & Power Mangement defines */
  87 #define IBM_CPM_PCI             0x40000000      /* PCI */
  88 #define IBM_CPM_EMAC2   0x20000000      /* EMAC 2 MII */
  89 #define IBM_CPM_EMAC3   0x04000000      /* EMAC 3 MII */
  90 #define IBM_CPM_EMAC0   0x00800000      /* EMAC 0 MII */
  91 #define IBM_CPM_EMAC1   0x00100000      /* EMAC 1 MII */
  92 #define IBM_CPM_EMMII   0       /* Shift value for MII */
  93 #define IBM_CPM_EMRX    1       /* Shift value for recv */
  94 #define IBM_CPM_EMTX    2       /* Shift value for MAC */
  95 #define IBM_CPM_UIC1    0x00020000      /* Universal Interrupt Controller */
  96 #define IBM_CPM_UIC0    0x00010000      /* Universal Interrupt Controller */
  97 #define IBM_CPM_CPU     0x00008000      /* processor core */
  98 #define IBM_CPM_EBC     0x00004000      /* ROM/SRAM peripheral controller */
  99 #define IBM_CPM_SDRAM0  0x00002000      /* SDRAM memory controller */
 100 #define IBM_CPM_GPIO0   0x00001000      /* General Purpose IO (??) */
 101 #define IBM_CPM_HDLC    0x00000800      /* HDCL */
 102 #define IBM_CPM_TMRCLK  0x00000400      /* CPU timers */
 103 #define IBM_CPM_PLB     0x00000100      /* PLB bus arbiter */
 104 #define IBM_CPM_OPB     0x00000080      /* PLB to OPB bridge */
 105 #define IBM_CPM_DMA     0x00000040      /* DMA controller */
 106 #define IBM_CPM_IIC0    0x00000010      /* IIC interface */
 107 #define IBM_CPM_UART0   0x00000002      /* serial port 0 */
 108 #define IBM_CPM_UART1   0x00000001      /* serial port 1 */
 109 /* this is the default setting for devices put to sleep when booting */
 110
 111 #define DFLT_IBM4xx_PM  ~(IBM_CPM_UIC0 | IBM_CPM_UIC1 | IBM_CPM_CPU     \
 112                         | IBM_CPM_EBC | IBM_CPM_SDRAM0 | IBM_CPM_PLB    \
 113                         | IBM_CPM_OPB | IBM_CPM_TMRCLK | IBM_CPM_DMA    \
 114                         | IBM_CPM_EMAC0 | IBM_CPM_EMAC1 | IBM_CPM_EMAC2 \
 115                         | IBM_CPM_EMAC3 | IBM_CPM_PCI)
 116
 117 #define DCRN_DMA0_BASE  0x100
 118 #define DCRN_DMA1_BASE  0x108
 119 #define DCRN_DMA2_BASE  0x110
 120 #define DCRN_DMA3_BASE  0x118
 121 #define DCRNCAP_DMA_SG  1       /* have DMA scatter/gather capability */
 122 #define DCRN_DMASR_BASE 0x120
 123 #define DCRN_EBC_BASE   0x012
 124 #define DCRN_DCP0_BASE  0x014
 125 #define DCRN_MAL_BASE   0x180
 126 #define DCRN_OCM0_BASE  0x018
 127 #define DCRN_PLB0_BASE  0x084
 128 #define DCRN_PLLMR_BASE 0x0B0
 129 #define DCRN_POB0_BASE  0x0A0
 130 #define DCRN_SDRAM0_BASE 0x010
 131 #define DCRN_UIC0_BASE  0x0C0
 132 #define DCRN_UIC1_BASE  0x0D0
 133 #define DCRN_CPC0_EPRCSR 0x0F3
 134
 135 #define UIC0_UIC1NC     0x00000002
 136
 137 #define CHR1_CETE       0x00000004      /* CPU external timer enable */
 138 #define UIC0    DCRN_UIC0_BASE
 139 #define UIC1    DCRN_UIC1_BASE
 140
 141 #undef NR_UICS
 142 #define NR_UICS 2
 143
 144 /* EMAC DCRN's FIXME: armin */
 145 #define DCRN_MALRXCTP2R(base)   ((base) + 0x42) /* Channel Rx 2 Channel Table Pointer */
 146 #define DCRN_MALRXCTP3R(base)   ((base) + 0x43) /* Channel Rx 3 Channel Table Pointer */
 147 #define DCRN_MALTXCTP4R(base)   ((base) + 0x24) /* Channel Tx 4 Channel Table Pointer */
 148 #define DCRN_MALTXCTP5R(base)   ((base) + 0x25) /* Channel Tx 5 Channel Table Pointer */
 149 #define DCRN_MALTXCTP6R(base)   ((base) + 0x26) /* Channel Tx 6 Channel Table Pointer */
 150 #define DCRN_MALTXCTP7R(base)   ((base) + 0x27) /* Channel Tx 7 Channel Table Pointer */
 151 #define DCRN_MALRCBS2(base)     ((base) + 0x62) /* Channel Rx 2 Channel Buffer Size */
 152 #define DCRN_MALRCBS3(base)     ((base) + 0x63) /* Channel Rx 3 Channel Buffer Size */
 153
 154 #include <asm/ibm405.h>
 155
 156 #endif                          /* __ASM_IBMNP405H_H__ */
 157 #endif                          /* __KERNEL__ */