arch/ppc/platforms/4xx/bubinga.h

   1 /*
   2  * Support for IBM PPC 405EP evaluation board (Bubinga).
   3  *
   4  * Author: SAW (IBM), derived from walnut.h.
   5  *         Maintained by MontaVista Software <source@mvista.com>
   6  *
   7  * 2003 (c) MontaVista Softare Inc.  This file is licensed under the
   8  * terms of the GNU General Public License version 2. This program is
   9  * licensed "as is" without any warranty of any kind, whether express
  10  * or implied.
  11  */
  12
  13 #ifdef __KERNEL__
  14 #ifndef __BUBINGA_H__
  15 #define __BUBINGA_H__
  16
  17 /* 405EP */
  18 #include <platforms/4xx/ibm405ep.h>
  19
  20 #ifndef __ASSEMBLY__
  21 /*
  22  * Data structure defining board information maintained by the boot
  23  * ROM on IBM's evaluation board. An effort has been made to
  24  * keep the field names consistent with the 8xx 'bd_t' board info
  25  * structures.
  26  */
  27
  28 typedef struct board_info {
  29         unsigned char    bi_s_version[4];       /* Version of this structure */
  30         unsigned char    bi_r_version[30];      /* Version of the IBM ROM */
  31         unsigned int     bi_memsize;            /* DRAM installed, in bytes */
  32         unsigned char    bi_enetaddr[2][6];     /* Local Ethernet MAC address */        unsigned char    bi_pci_enetaddr[6];    /* PCI Ethernet MAC address */
  33         unsigned int     bi_intfreq;            /* Processor speed, in Hz */
  34         unsigned int     bi_busfreq;            /* PLB Bus speed, in Hz */
  35         unsigned int     bi_pci_busfreq;        /* PCI Bus speed, in Hz */
  36         unsigned int     bi_opb_busfreq;        /* OPB Bus speed, in Hz */
  37         unsigned int     bi_pllouta_freq;       /* PLL OUTA speed, in Hz */
  38 } bd_t;
  39
  40 /* Some 4xx parts use a different timebase frequency from the internal clock.
  41 */
  42 #define bi_tbfreq bi_intfreq
  43
  44
  45 /* Memory map for the Bubinga board.
  46  * Generic 4xx plus RTC.
  47  */
  48
  49 extern void *bubinga_rtc_base;
  50 #define BUBINGA_RTC_PADDR       ((uint)0xf0000000)
  51 #define BUBINGA_RTC_VADDR       BUBINGA_RTC_PADDR
  52 #define BUBINGA_RTC_SIZE        ((uint)8*1024)
  53
  54 /* The UART clock is based off an internal clock -
  55  * define BASE_BAUD based on the internal clock and divider(s).
  56  * Since BASE_BAUD must be a constant, we will initialize it
  57  * using clock/divider values which OpenBIOS initializes
  58  * for typical configurations at various CPU speeds.
  59  * The base baud is calculated as (FWDA / EXT UART DIV / 16)
  60  */
  61 #define BASE_BAUD       0
  62
  63 #define BUBINGA_FPGA_BASE      0xF0300000
  64
  65 #define PPC4xx_MACHINE_NAME     "IBM Bubinga"
  66
  67 #endif /* !__ASSEMBLY__ */
  68 #endif /* __BUBINGA_H__ */
  69 #endif /* __KERNEL__ */