arch/ppc/boot/simple/rw4/ppc_40x.h

   1 /*----------------------------------------------------------------------------+
   2 |       This source code has been made available to you by IBM on an AS-IS
   3 |       basis.  Anyone receiving this source is licensed under IBM
   4 |       copyrights to use it in any way he or she deems fit, including
   5 |       copying it, modifying it, compiling it, and redistributing it either
   6 |       with or without modifications.  No license under IBM patents or
   7 |       patent applications is to be implied by the copyright license.
   8 |
   9 |       Any user of this software should understand that IBM cannot provide
  10 |       technical support for this software and will not be responsible for
  11 |       any consequences resulting from the use of this software.
  12 |
  13 |       Any person who transfers this source code or any derivative work
  14 |       must include the IBM copyright notice, this paragraph, and the
  15 |       preceding two paragraphs in the transferred software.
  16 |
  17 |       COPYRIGHT   I B M   CORPORATION 1997
  18 |       LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
  19 +----------------------------------------------------------------------------*/
  20 /*----------------------------------------------------------------------------+
  21 | Author:    Tony J. Cerreto
  22 | Component: Assembler include file.
  23 | File:      ppc_40x.h
  24 | Purpose:   Include file containing PPC DCR defines.
  25 |
  26 | Changes:
  27 | Date       Author  Comment
  28 | ---------  ------  --------------------------------------------------------
  29 | 01-Mar-00  tjc     Created
  30 +----------------------------------------------------------------------------*/
  31 /* added by linguohui*/
  32 #define MW
  33 /*----------------------------------------------------------------------------+
  34 | PPC Special purpose registers Numbers
  35 +----------------------------------------------------------------------------*/
  36 #define ccr0            0x3b3               /* core configuration reg        */
  37 #define ctr             0x009               /* count register                */
  38 #define ctrreg          0x009               /* count register                */
  39 #define dbcr0           0x3f2               /* debug control register 0      */
  40 #define dbcr1           0x3bd               /* debug control register 1      */
  41 #define dbsr            0x3f0               /* debug status register         */
  42 #define dccr            0x3fa               /* data cache control reg.       */
  43 #define dcwr            0x3ba               /* data cache write-thru reg     */
  44 #define dear            0x3d5               /* data exception address reg    */
  45 #define esr             0x3d4               /* exception syndrome register   */
  46 #define evpr            0x3d6               /* exception vector prefix reg   */
  47 #define iccr            0x3fb               /* instruction cache cntrl re    */
  48 #define icdbdr          0x3d3               /* instr cache dbug data reg     */
  49 #define lrreg           0x008               /* link register                 */
  50 #define pid             0x3b1               /* process id reg                */
  51 #define pit             0x3db               /* programmable interval time    */
  52 #define pvr             0x11f               /* processor version register    */
  53 #define sgr             0x3b9               /* storage guarded reg           */
  54 #define sler            0x3bb               /* storage little endian reg     */
  55 #define sprg0           0x110               /* special general purpose 0     */
  56 #define sprg1           0x111               /* special general purpose 1     */
  57 #define sprg2           0x112               /* special general purpose 2     */
  58 #define sprg3           0x113               /* special general purpose 3     */
  59 #define sprg4           0x114               /* special general purpose 4     */
  60 #define sprg5           0x115               /* special general purpose 5     */
  61 #define sprg6           0x116               /* special general purpose 6     */
  62 #define sprg7           0x117               /* special general purpose 7     */
  63 #define srr0            0x01a               /* save/restore register 0       */
  64 #define srr1            0x01b               /* save/restore register 1       */
  65 #define srr2            0x3de               /* save/restore register 2       */
  66 #define srr3            0x3df               /* save/restore register 3       */
  67 #define tbhi            0x11D
  68 #define tblo            0x11C
  69 #define tcr             0x3da               /* timer control register        */
  70 #define tsr             0x3d8               /* timer status register         */
  71 #define xerreg          0x001               /* fixed point exception         */
  72 #define xer             0x001               /* fixed point exception         */
  73 #define zpr             0x3b0               /* zone protection reg           */
  74
  75 /*----------------------------------------------------------------------------+
  76 | Decompression Controller
  77 +----------------------------------------------------------------------------*/
  78 #define kiar            0x014               /* Decompression cntl addr reg   */
  79 #define kidr            0x015               /* Decompression cntl data reg   */
  80 #define kitor0          0x00                /* index table origin Reg 0      */
  81 #define kitor1          0x01                /* index table origin Reg 1      */
  82 #define kitor2          0x02                /* index table origin Reg 2      */
  83 #define kitor3          0x03                /* index table origin Reg 3      */
  84 #define kaddr0          0x04                /* addr decode Definition Reg 0  */
  85 #define kaddr1          0x05                /* addr decode Definition Reg 1  */
  86 #define kconf           0x40                /* Decompression cntl config reg */
  87 #define kid             0x41                /* Decompression cntl id reg     */
  88 #define kver            0x42                /* Decompression cntl ver number */
  89 #define kpear           0x50                /* bus error addr reg (PLB)      */
  90 #define kbear           0x51                /* bus error addr reg (DCP-EBC)  */
  91 #define kesr0           0x52                /* bus error status reg 0        */
  92
  93 /*----------------------------------------------------------------------------+
  94 | Romeo Specific Device Control Register Numbers.
  95 +----------------------------------------------------------------------------*/
  96 #ifndef VESTA
  97 #define cdbcr           0x3d7                   /* cache debug cntrl reg     */
  98
  99 #define a_latcnt        0x1a9                   /* PLB Latency count         */
 100 #define a_tgval         0x1ac                   /* tone generation value     */
 101 #define a_plb_pr        0x1bf                   /* PLB priority              */
 102
 103 #define cic_sel1        0x031                   /* select register 1         */
 104 #define cic_sel2        0x032                   /* select register 2         */
 105
 106 #define clkgcrst        0x122                   /* chip reset register */
 107
 108 #define cp_cpmsr        0x100                   /*rstatus register           */
 109 #define cp_cpmer        0x101                   /* enable register           */
 110
 111 #define dcp_kiar        0x190                   /* indirect address register */
 112 #define dcp_kidr        0x191                   /* indirect data register    */
 113
 114 #define hsmc_mcgr       0x1c0                   /* HSMC global register      */
 115 #define hsmc_mcbesr     0x1c1                   /* bus error status register */
 116 #define hsmc_mcbear     0x1c2                   /* bus error address register*/
 117 #define hsmc_mcbr0      0x1c4                   /* SDRAM sub-ctrl bank reg 0 */
 118 #define hsmc_mccr0      0x1c5                   /* SDRAM sub-ctrl ctrl reg 0 */
 119 #define hsmc_mcbr1      0x1c7                   /* SDRAM sub-ctrl bank reg 1 */
 120 #define hsmc_mccr1      0x1c8                   /* SDRAM sub-ctrl ctrl reg 1 */
 121 #define hsmc_sysr       0x1d1                   /* system register           */
 122 #define hsmc_data       0x1d2                   /* data register             */
 123 #define hsmc_mccrr      0x1d3                   /* refresh register          */
 124
 125 #define ocm_pbar        0x1E0                   /* base address register     */
 126
 127 #define plb0_pacr0      0x057                   /* PLB arbiter control reg   */
 128 #define plb1_pacr1      0x067                   /* PLB arbiter control reg   */
 129
 130 #define v_displb        0x157                   /* set left border of display*/
 131 #define v_disptb        0x158                   /* top border of display     */
 132 #define v_osd_la        0x159                   /* first link address for OSD*/
 133 #define v_ptsdlta       0x15E                   /* PTS delta register        */
 134 #define v_v0base        0x16C                   /* base mem add for VBI-0    */
 135 #define v_v1base        0x16D                   /* base mem add for VBI-1    */
 136 #define v_osbase        0x16E                   /* base mem add for OSD data */
 137 #endif
 138
 139 /*----------------------------------------------------------------------------+
 140 | Vesta Device Control Register Numbers.
 141 +----------------------------------------------------------------------------*/
 142 /*----------------------------------------------------------------------------+
 143 | Cross bar switch.
 144 +----------------------------------------------------------------------------*/
 145 #define cbs0_cr         0x010               /* CBS configuration register    */
 146
 147 /*----------------------------------------------------------------------------+
 148 | DCR external master (DCRX).
 149 +----------------------------------------------------------------------------*/
 150 #define dcrx0_icr       0x020               /* internal control register     */
 151 #define dcrx0_isr       0x021               /* internal status register      */
 152 #define dcrx0_ecr       0x022               /* external control register     */
 153 #define dcrx0_esr       0x023               /* external status register      */
 154 #define dcrx0_tar       0x024               /* target address register       */
 155 #define dcrx0_tdr       0x025               /* target data register          */
 156 #define dcrx0_igr       0x026               /* interrupt generation register */
 157 #define dcrx0_bcr       0x027               /* buffer control register       */
 158
 159 /*----------------------------------------------------------------------------+
 160 | Chip interconnect configuration.
 161 +----------------------------------------------------------------------------*/
 162 #define cic0_cr         0x030               /* CIC control register          */
 163 #define cic0_vcr        0x033               /* video macro control reg       */
 164 #define cic0_sel3       0x035               /* select register 3             */
 165
 166 /*----------------------------------------------------------------------------+
 167 | Chip interconnect configuration.
 168 +----------------------------------------------------------------------------*/
 169 #define sgpo0_sgpO      0x036               /* simplified GPIO output        */
 170 #define sgpo0_gpod      0x037               /* simplified GPIO open drain    */
 171 #define sgpo0_gptc      0x038               /* simplified GPIO tristate cntl */
 172 #define sgpo0_gpi       0x039               /* simplified GPIO input         */
 173
 174 /*----------------------------------------------------------------------------+
 175 | Universal interrupt controller.
 176 +----------------------------------------------------------------------------*/
 177 #define uic0_sr         0x040               /* status register               */
 178 #define uic0_srs        0x041               /* status register set           */
 179 #define uic0_er         0x042               /* enable register               */
 180 #define uic0_cr         0x043               /* critical register             */
 181 #define uic0_pr         0x044               /* parity register               */
 182 #define uic0_tr         0x045               /* triggering register           */
 183 #define uic0_msr        0x046               /* masked status register        */
 184 #define uic0_vr         0x047               /* vector register               */
 185 #define uic0_vcr        0x048               /* enable config register        */
 186
 187 /*----------------------------------------------------------------------------+
 188 | PLB 0 and 1.
 189 +----------------------------------------------------------------------------*/
 190 #define pb0_pesr        0x054               /* PLB error status reg 0        */
 191 #define pb0_pesrs       0x055               /* PLB error status reg 0 set    */
 192 #define pb0_pear        0x056               /* PLB error address reg         */
 193
 194 #define pb1_pesr        0x064               /* PLB error status reg 1        */
 195 #define pb1_pesrs       0x065               /* PLB error status reg 1 set    */
 196 #define pb1_pear        0x066               /* PLB error address reg         */
 197
 198 /*----------------------------------------------------------------------------+
 199 | EBIU DCR registers.
 200 +----------------------------------------------------------------------------*/
 201 #define ebiu0_brcrh0    0x070               /* bus region register 0 high    */
 202 #define ebiu0_brcrh1    0x071               /* bus region register 1 high    */
 203 #define ebiu0_brcrh2    0x072               /* bus region register 2 high    */
 204 #define ebiu0_brcrh3    0x073               /* bus region register 3 high    */
 205 #define ebiu0_brcrh4    0x074               /* bus region register 4 high    */
 206 #define ebiu0_brcrh5    0x075               /* bus region register 5 high    */
 207 #define ebiu0_brcrh6    0x076               /* bus region register 6 high    */
 208 #define ebiu0_brcrh7    0x077               /* bus region register 7 high    */
 209 #define ebiu0_brcr0     0x080               /* bus region register 0         */
 210 #define ebiu0_brcr1     0x081               /* bus region register 1         */
 211 #define ebiu0_brcr2     0x082               /* bus region register 2         */
 212 #define ebiu0_brcr3     0x083               /* bus region register 3         */
 213 #define ebiu0_brcr4     0x084               /* bus region register 4         */
 214 #define ebiu0_brcr5     0x085               /* bus region register 5         */
 215 #define ebiu0_brcr6     0x086               /* bus region register 6         */
 216 #define ebiu0_brcr7     0x087               /* bus region register 7         */
 217 #define ebiu0_bear      0x090               /* bus error address register    */
 218 #define ebiu0_besr      0x091               /* bus error syndrome reg        */
 219 #define ebiu0_besr0s    0x093               /* bus error syndrome reg        */
 220 #define ebiu0_biucr     0x09a               /* bus interface control reg     */
 221
 222 /*----------------------------------------------------------------------------+
 223 | OPB bridge.
 224 +----------------------------------------------------------------------------*/
 225 #define opbw0_gesr      0x0b0               /* error status reg              */
 226 #define opbw0_gesrs     0x0b1               /* error status reg              */
 227 #define opbw0_gear      0x0b2               /* error address reg             */
 228
 229 /*----------------------------------------------------------------------------+
 230 | DMA.
 231 +----------------------------------------------------------------------------*/
 232 #define dma0_cr0        0x0c0               /* DMA channel control reg 0     */
 233 #define dma0_ct0        0x0c1               /* DMA count register 0          */
 234 #define dma0_da0        0x0c2               /* DMA destination addr reg 0    */
 235 #define dma0_sa0        0x0c3               /* DMA source addr register 0    */
 236 #define dma0_cc0        0x0c4               /* DMA chained count 0           */
 237 #define dma0_cr1        0x0c8               /* DMA channel control reg 1     */
 238 #define dma0_ct1        0x0c9               /* DMA count register 1          */
 239 #define dma0_da1        0x0ca               /* DMA destination addr reg 1    */
 240 #define dma0_sa1        0x0cb               /* DMA source addr register 1    */
 241 #define dma0_cc1        0x0cc               /* DMA chained count 1           */
 242 #define dma0_cr2        0x0d0               /* DMA channel control reg 2     */
 243 #define dma0_ct2        0x0d1               /* DMA count register 2          */
 244 #define dma0_da2        0x0d2               /* DMA destination addr reg 2    */
 245 #define dma0_sa2        0x0d3               /* DMA source addr register 2    */
 246 #define dma0_cc2        0x0d4               /* DMA chained count 2           */
 247 #define dma0_cr3        0x0d8               /* DMA channel control reg 3     */
 248 #define dma0_ct3        0x0d9               /* DMA count register 3          */
 249 #define dma0_da3        0x0da               /* DMA destination addr reg 3    */
 250 #define dma0_sa3        0x0db               /* DMA source addr register 3    */
 251 #define dma0_cc3        0x0dc               /* DMA chained count 3           */
 252 #define dma0_sr         0x0e0               /* DMA status register           */
 253 #define dma0_srs        0x0e1               /* DMA status register           */
 254 #define dma0_s1         0x031               /* DMA select1 register          */
 255 #define dma0_s2         0x032               /* DMA select2 register          */
 256
 257 /*---------------------------------------------------------------------------+
 258 | Clock and power management.
 259 +----------------------------------------------------------------------------*/
 260 #define cpm0_fr         0x102               /* force register                */
 261
 262 /*----------------------------------------------------------------------------+
 263 | Serial Clock Control.
 264 +----------------------------------------------------------------------------*/
 265 #define ser0_ccr        0x120               /* serial clock control register */
 266
 267 /*----------------------------------------------------------------------------+
 268 | Audio Clock Control.
 269 +----------------------------------------------------------------------------*/
 270 #define aud0_apcr       0x121               /* audio clock ctrl register     */
 271
 272 /*----------------------------------------------------------------------------+
 273 | DENC.
 274 +----------------------------------------------------------------------------*/
 275 #define denc0_idr       0x130               /* DENC ID register              */
 276 #define denc0_cr1       0x131               /* control register 1            */
 277 #define denc0_rr1       0x132               /* microvision 1 (reserved 1)    */
 278 #define denc0_cr2       0x133               /* control register 2            */
 279 #define denc0_rr2       0x134               /* microvision 2 (reserved 2)    */
 280 #define denc0_rr3       0x135               /* microvision 3 (reserved 3)    */
 281 #define denc0_rr4       0x136               /* microvision 4 (reserved 4)    */
 282 #define denc0_rr5       0x137               /* microvision 5 (reserved 5)    */
 283 #define denc0_ccdr      0x138               /* closed caption data           */
 284 #define denc0_cccr      0x139               /* closed caption control        */
 285 #define denc0_trr       0x13A               /* teletext request register     */
 286 #define denc0_tosr      0x13B               /* teletext odd field line se    */
 287 #define denc0_tesr      0x13C               /* teletext even field line s    */
 288 #define denc0_rlsr      0x13D               /* RGB rhift left register       */
 289 #define denc0_vlsr      0x13E               /* video level shift register    */
 290 #define denc0_vsr       0x13F               /* video scaling register        */
 291
 292 /*----------------------------------------------------------------------------+
 293 | Video decoder.  Suspect 0x179, 0x169, 0x16a, 0x152 (rc).
 294 +----------------------------------------------------------------------------*/
 295 #define vid0_ccntl      0x140               /* control decoder operation     */
 296 #define vid0_cmode      0x141               /* video operational mode        */
 297 #define vid0_sstc0      0x142               /* STC high order bits 31:0      */
 298 #define vid0_sstc1      0x143               /* STC low order bit 32          */
 299 #define vid0_spts0      0x144               /* PTS high order bits 31:0      */
 300 #define vid0_spts1      0x145               /* PTS low order bit 32          */
 301 #define vid0_fifo       0x146               /* FIFO data port                */
 302 #define vid0_fifos      0x147               /* FIFO status                   */
 303 #define vid0_cmd        0x148               /* send command to decoder       */
 304 #define vid0_cmdd       0x149               /* port for command params       */
 305 #define vid0_cmdst      0x14A               /* command status                */
 306 #define vid0_cmdad      0x14B               /* command address               */
 307 #define vid0_procia     0x14C               /* instruction store             */
 308 #define vid0_procid     0x14D               /* data port for I_Store         */
 309 #define vid0_osdm       0x151               /* OSD mode control              */
 310 #define vid0_hosti      0x152               /* base interrupt register       */
 311 #define vid0_mask       0x153               /* interrupt mask register       */
 312 #define vid0_dispm      0x154               /* operational mode for Disp     */
 313 #define vid0_dispd      0x155               /* setting for 'Sync' delay      */
 314 #define vid0_vbctl      0x156               /* VBI                           */
 315 #define vid0_ttxctl     0x157               /* teletext control              */
 316 #define vid0_disptb     0x158               /* display left/top border       */
 317 #define vid0_osdgla     0x159               /* Graphics plane link addr      */
 318 #define vid0_osdila     0x15A               /* Image plane link addr         */
 319 #define vid0_rbthr      0x15B               /* rate buffer threshold         */
 320 #define vid0_osdcla     0x15C               /* Cursor link addr              */
 321 #define vid0_stcca      0x15D               /* STC common address            */
 322 #define vid0_ptsctl     0x15F               /* PTS Control                   */
 323 #define vid0_wprot      0x165               /* write protect for I_Store     */
 324 #define vid0_vcqa       0x167               /* video clip queued block Ad    */
 325 #define vid0_vcql       0x168               /* video clip queued block Le    */
 326 #define vid0_blksz      0x169               /* block size bytes for copy op  */
 327 #define vid0_srcad      0x16a               /* copy source address bits 6-31 */
 328 #define vid0_udbas      0x16B               /* base mem add for user data    */
 329 #define vid0_vbibas     0x16C               /* base mem add for VBI 0/1      */
 330 #define vid0_osdibas    0x16D               /* Image plane base address      */
 331 #define vid0_osdgbas    0x16E               /* Graphic plane base address    */
 332 #define vid0_rbbase     0x16F               /* base mem add for video buf    */
 333 #define vid0_dramad     0x170               /* DRAM address                  */
 334 #define vid0_dramdt     0x171               /* data port for DRAM access     */
 335 #define vid0_dramcs     0x172               /* DRAM command and statusa      */
 336 #define vid0_vcwa       0x173               /* v clip work address           */
 337 #define vid0_vcwl       0x174               /* v clip work length            */
 338 #define vid0_mseg0      0x175               /* segment address 0             */
 339 #define vid0_mseg1      0x176               /* segment address 1             */
 340 #define vid0_mseg2      0x177               /* segment address 2             */
 341 #define vid0_mseg3      0x178               /* segment address 3             */
 342 #define vid0_fbbase     0x179               /* frame buffer base memory      */
 343 #define vid0_osdcbas    0x17A               /* Cursor base addr              */
 344 #define vid0_lboxtb     0x17B               /* top left border               */
 345 #define vid0_trdly      0x17C               /* transparency gate delay       */
 346 #define vid0_sbord      0x17D               /* left/top small pict. bord.    */
 347 #define vid0_zoffs      0x17E               /* hor/ver zoom window           */
 348 #define vid0_rbsz       0x17F               /* rate buffer size read         */
 349
 350 /*----------------------------------------------------------------------------+
 351 | Transport demultiplexer.
 352 +----------------------------------------------------------------------------*/
 353 #define xpt0_lr         0x180               /* demux location register       */
 354 #define xpt0_data       0x181               /* demux data register           */
 355 #define xpt0_ir         0x182               /* demux interrupt register      */
 356
 357 #define xpt0_config1    0x0000              /* configuration 1               */
 358 #define xpt0_control1   0x0001              /* control 1                     */
 359 #define xpt0_festat     0x0002              /* Front-end status              */
 360 #define xpt0_feimask    0x0003              /* Front_end interrupt Mask      */
 361 #define xpt0_ocmcnfg    0x0004              /* OCM Address                   */
 362 #define xpt0_settapi    0x0005              /* Set TAP Interrupt             */
 363
 364 #define xpt0_pcrhi      0x0010              /* PCR High                      */
 365 #define xpt0_pcrlow     0x0011              /* PCR Low                       */
 366 #define xpt0_lstchi     0x0012              /* Latched STC High              */
 367 #define xpt0_lstclow    0x0013              /* Latched STC Low               */
 368 #define xpt0_stchi      0x0014              /* STC High                      */
 369 #define xpt0_stclow     0x0015              /* STC Low                       */
 370 #define xpt0_pwm        0x0016              /* PWM                           */
 371 #define xpt0_pcrstct    0x0017              /* PCR-STC Threshold             */
 372 #define xpt0_pcrstcd    0x0018              /* PCR-STC Delta                 */
 373 #define xpt0_stccomp    0x0019              /* STC Compare                   */
 374 #define xpt0_stccmpd    0x001a              /* STC Compare Disarm            */
 375
 376 #define xpt0_dsstat     0x0048              /* Descrambler Status            */
 377 #define xpt0_dsimask    0x0049              /* Descrambler Interrupt Mask    */
 378
 379 #define xpt0_vcchng     0x01f0              /* Video Channel Change          */
 380 #define xpt0_acchng     0x01f1              /* Audio Channel Change          */
 381 #define xpt0_axenable   0x01fe              /* Aux PID Enables               */
 382 #define xpt0_pcrpid     0x01ff              /* PCR PID                       */
 383
 384 #define xpt0_config2    0x1000              /* Configuration 2               */
 385 #define xpt0_pbuflvl    0x1002              /* Packet Buffer Level           */
 386 #define xpt0_intmask    0x1003              /* Interrupt Mask                */
 387 #define xpt0_plbcnfg    0x1004              /* PLB Configuration             */
 388
 389 #define xpt0_qint       0x1010              /* Queues Interrupts             */
 390 #define xpt0_qintmsk    0x1011              /* Queues Interrupts Mask        */
 391 #define xpt0_astatus    0x1012              /* Audio Status                  */
 392 #define xpt0_aintmask   0x1013              /* Audio Interrupt Mask          */
 393 #define xpt0_vstatus    0x1014              /* Video Status                  */
 394 #define xpt0_vintmask   0x1015              /* Video Interrupt Mask          */
 395
 396 #define xpt0_qbase      0x1020              /* Queue Base                    */
 397 #define xpt0_bucketq    0x1021              /* Bucket Queue                  */
 398 #define xpt0_qstops     0x1024              /* Queue Stops                   */
 399 #define xpt0_qresets    0x1025              /* Queue Resets                  */
 400 #define xpt0_sfchng     0x1026              /* Section Filter Change         */
 401
 402 /*----------------------------------------------------------------------------+
 403 | Audio decoder. Suspect 0x1ad, 0x1b4, 0x1a3, 0x1a5 (read/write status)
 404 +----------------------------------------------------------------------------*/
 405 #define aud0_ctrl0      0x1a0               /* control 0                     */
 406 #define aud0_ctrl1      0x1a1               /* control 1                     */
 407 #define aud0_ctrl2      0x1a2               /* control 2                     */
 408 #define aud0_cmd        0x1a3               /* command register              */
 409 #define aud0_isr        0x1a4               /* interrupt status register     */
 410 #define aud0_imr        0x1a5               /* interrupt mask register       */
 411 #define aud0_dsr        0x1a6               /* decoder status register       */
 412 #define aud0_stc        0x1a7               /* system time clock             */
 413 #define aud0_csr        0x1a8               /* channel status register       */
 414 #define aud0_lcnt       0x1a9               /* queued address register 2     */
 415 #define aud0_pts        0x1aa               /* presentation time stamp       */
 416 #define aud0_tgctrl     0x1ab               /* tone generation control       */
 417 #define aud0_qlr2       0x1ac               /* queued length register 2      */
 418 #define aud0_auxd       0x1ad               /* aux data                      */
 419 #define aud0_strmid     0x1ae               /* stream ID                     */
 420 #define aud0_qar        0x1af               /* queued address register       */
 421 #define aud0_dsps       0x1b0               /* DSP status                    */
 422 #define aud0_qlr        0x1b1               /* queued len address            */
 423 #define aud0_dspc       0x1b2               /* DSP control                   */
 424 #define aud0_wlr2       0x1b3               /* working length register 2     */
 425 #define aud0_instd      0x1b4               /* instruction download          */
 426 #define aud0_war        0x1b5               /* working address register      */
 427 #define aud0_seg1       0x1b6               /* segment 1 base register       */
 428 #define aud0_seg2       0x1b7               /* segment 2 base register       */
 429 #define aud0_avf        0x1b9               /* audio att value front         */
 430 #define aud0_avr        0x1ba               /* audio att value rear          */
 431 #define aud0_avc        0x1bb               /* audio att value center        */
 432 #define aud0_seg3       0x1bc               /* segment 3 base register       */
 433 #define aud0_offset     0x1bd               /* offset address                */
 434 #define aud0_wrl        0x1be               /* working length register       */
 435 #define aud0_war2       0x1bf               /* working address register 2    */
 436
 437 /*----------------------------------------------------------------------------+
 438 | High speed memory controller 0 and 1.
 439 +----------------------------------------------------------------------------*/
 440 #define hsmc0_gr        0x1e0               /* HSMC global register          */
 441 #define hsmc0_besr      0x1e1               /* bus error status register     */
 442 #define hsmc0_bear      0x1e2               /* bus error address register    */
 443 #define hsmc0_br0       0x1e4               /* SDRAM sub-ctrl bank reg 0     */
 444 #define hsmc0_cr0       0x1e5               /* SDRAM sub-ctrl ctrl reg 0     */
 445 #define hsmc0_br1       0x1e7               /* SDRAM sub-ctrl bank reg 1     */
 446 #define hsmc0_cr1       0x1e8               /* SDRAM sub-ctrl ctrl reg 1     */
 447 #define hsmc0_sysr      0x1f1               /* system register               */
 448 #define hsmc0_data      0x1f2               /* data register                 */
 449 #define hsmc0_crr       0x1f3               /* refresh register              */
 450
 451 #define hsmc1_gr        0x1c0               /* HSMC global register          */
 452 #define hsmc1_besr      0x1c1               /* bus error status register     */
 453 #define hsmc1_bear      0x1c2               /* bus error address register    */
 454 #define hsmc1_br0       0x1c4               /* SDRAM sub-ctrl bank reg 0     */
 455 #define hsmc1_cr0       0x1c5               /* SDRAM sub-ctrl ctrl reg 0     */
 456 #define hsmc1_br1       0x1c7               /* SDRAM sub-ctrl bank reg 1     */
 457 #define hsmc1_cr1       0x1c8               /* SDRAM sub-ctrl ctrl reg 1     */
 458 #define hsmc1_sysr      0x1d1               /* system register               */
 459 #define hsmc1_data      0x1d2               /* data register                 */
 460 #define hsmc1_crr       0x1d3               /* refresh register              */
 461
 462 /*----------------------------------------------------------------------------+
 463 | Machine State Register bit definitions.
 464 +----------------------------------------------------------------------------*/
 465 #define msr_ape         0x00100000
 466 #define msr_apa         0x00080000
 467 #define msr_we          0x00040000
 468 #define msr_ce          0x00020000
 469 #define msr_ile         0x00010000
 470 #define msr_ee          0x00008000
 471 #define msr_pr          0x00004000
 472 #define msr_me          0x00001000
 473 #define msr_de          0x00000200
 474 #define msr_ir          0x00000020
 475 #define msr_dr          0x00000010
 476 #define msr_le          0x00000001
 477
 478 /*----------------------------------------------------------------------------+
 479 | Used during interrupt processing.
 480 +----------------------------------------------------------------------------*/
 481 #define stack_reg_image_size            160
 482
 483 /*----------------------------------------------------------------------------+
 484 | Function prolog definition and other Metaware (EABI) defines.
 485 +----------------------------------------------------------------------------*/
 486 #ifdef MW
 487
 488 #define r0              0
 489 #define r1              1
 490 #define r2              2
 491 #define r3              3
 492 #define r4              4
 493 #define r5              5
 494 #define r6              6
 495 #define r7              7
 496 #define r8              8
 497 #define r9              9
 498 #define r10             10
 499 #define r11             11
 500 #define r12             12
 501 #define r13             13
 502 #define r14             14
 503 #define r15             15
 504 #define r16             16
 505 #define r17             17
 506 #define r18             18
 507 #define r19             19
 508 #define r20             20
 509 #define r21             21
 510 #define r22             22
 511 #define r23             23
 512 #define r24             24
 513 #define r25             25
 514 #define r26             26
 515 #define r27             27
 516 #define r28             28
 517 #define r29             29
 518 #define r30             30
 519 #define r31             31
 520
 521 #define cr0             0
 522 #define cr1             1
 523 #define cr2             2
 524 #define cr3             3
 525 #define cr4             4
 526 #define cr5             5
 527 #define cr6             6
 528 #define cr7             7
 529
 530 #define function_prolog(func_name)      .text; \
 531                                         .align  2; \
 532                                         .globl  func_name; \
 533                                         func_name:
 534 #define function_epilog(func_name)      .type func_name,@function; \
 535                                         .size func_name,.-func_name
 536
 537 #define function_call(func_name)        bl func_name
 538
 539 #define stack_frame_min                 8
 540 #define stack_frame_bc                  0
 541 #define stack_frame_lr                  4
 542 #define stack_neg_off                   0
 543
 544 #endif
 545
 546 /*----------------------------------------------------------------------------+
 547 | Function prolog definition and other DIAB (Elf) defines.
 548 +----------------------------------------------------------------------------*/
 549 #ifdef ELF_DIAB
 550
 551 fprolog:        macro   f_name
 552                 .text
 553                 .align  2
 554                 .globl  f_name
 555 f_name:
 556                 endm
 557
 558 fepilog:        macro   f_name
 559                 .type   f_name,@function
 560                 .size   f_name,.-f_name
 561                 endm
 562
 563 #define function_prolog(func_name)      fprolog func_name
 564 #define function_epilog(func_name)      fepilog func_name
 565 #define function_call(func_name)        bl func_name
 566
 567 #define stack_frame_min                 8
 568 #define stack_frame_bc                  0
 569 #define stack_frame_lr                  4
 570 #define stack_neg_off                   0
 571
 572 #endif
 573
 574 /*----------------------------------------------------------------------------+
 575 | Function prolog definition and other Xlc (XCOFF) defines.
 576 +----------------------------------------------------------------------------*/
 577 #ifdef XCOFF
 578
 579 .machine "403ga"
 580
 581 #define r0              0
 582 #define r1              1
 583 #define r2              2
 584 #define r3              3
 585 #define r4              4
 586 #define r5              5
 587 #define r6              6
 588 #define r7              7
 589 #define r8              8
 590 #define r9              9
 591 #define r10             10
 592 #define r11             11
 593 #define r12             12
 594 #define r13             13
 595 #define r14             14
 596 #define r15             15
 597 #define r16             16
 598 #define r17             17
 599 #define r18             18
 600 #define r19             19
 601 #define r20             20
 602 #define r21             21
 603 #define r22             22
 604 #define r23             23
 605 #define r24             24
 606 #define r25             25
 607 #define r26             26
 608 #define r27             27
 609 #define r28             28
 610 #define r29             29
 611 #define r30             30
 612 #define r31             31
 613
 614 #define cr0             0
 615 #define cr1             1
 616 #define cr2             2
 617 #define cr3             3
 618 #define cr4             4
 619 #define cr5             5
 620 #define cr6             6
 621 #define cr7             7
 622
 623 #define function_prolog(func_name)      .csect .func_name[PR]; \
 624                                         .globl .func_name[PR]; \
 625                                         func_name:
 626
 627 #define function_epilog(func_name)      .toc; \
 628                                         .csect  func_name[DS]; \
 629                                         .globl  func_name[DS]; \
 630                                         .long   .func_name[PR]; \
 631                                         .long   TOC[tc0]
 632
 633 #define function_call(func_name)        .extern .func_name[PR]; \
 634                                         stw     r2,stack_frame_toc(r1); \
 635                                         mfspr   r2,sprg0; \
 636                                         bl      .func_name[PR]; \
 637                                         lwz     r2,stack_frame_toc(r1)
 638
 639 #define stack_frame_min                 56
 640 #define stack_frame_bc                  0
 641 #define stack_frame_lr                  8
 642 #define stack_frame_toc                 20
 643 #define stack_neg_off                   276
 644
 645 #endif
 646 #define function_prolog(func_name)      .text; \
 647                                         .align  2; \
 648                                         .globl  func_name; \
 649                                         func_name:
 650 #define function_epilog(func_name)      .type func_name,@function; \
 651                                         .size func_name,.-func_name
 652
 653 #define function_call(func_name)        bl func_name
 654
 655 /*----------------------------------------------------------------------------+
 656 | Function prolog definition for GNU
 657 +----------------------------------------------------------------------------*/
 658 #ifdef _GNU_TOOL
 659
 660 #define function_prolog(func_name)      .globl  func_name; \
 661                                         func_name:
 662 #define function_epilog(func_name)
 663
 664 #endif