arch/mips/sgi-ip32/ip32-irq.c

   1 /*
   2  * Code to handle IP32 IRQs
   3  *
   4  * This file is subject to the terms and conditions of the GNU General Public
   5  * License.  See the file "COPYING" in the main directory of this archive
   6  * for more details.
   7  *
   8  * Copyright (C) 2000 Harald Koerfgen
   9  * Copyright (C) 2001 Keith M Wesolowski
  10  */
  11 #include <linux/init.h>
  12 #include <linux/kernel_stat.h>
  13 #include <linux/types.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/irq.h>
  16 #include <linux/bitops.h>
  17 #include <linux/kernel.h>
  18 #include <linux/slab.h>
  19 #include <linux/mm.h>
  20 #include <linux/random.h>
  21 #include <linux/sched.h>
  22
  23 #include <asm/mipsregs.h>
  24 #include <asm/signal.h>
  25 #include <asm/system.h>
  26 #include <asm/time.h>
  27 #include <asm/ip32/crime.h>
  28 #include <asm/ip32/mace.h>
  29 #include <asm/ip32/ip32_ints.h>
  30
  31 /* issue a PIO read to make sure no PIO writes are pending */
  32 static void inline flush_crime_bus(void)
  33 {
  34         volatile unsigned long junk = crime->control;
  35 }
  36
  37 static void inline flush_mace_bus(void)
  38 {
  39         volatile unsigned long junk = mace->perif.ctrl.misc;
  40 }
  41
  42 #undef DEBUG_IRQ
  43 #ifdef DEBUG_IRQ
  44 #define DBG(x...) printk(x)
  45 #else
  46 #define DBG(x...)
  47 #endif
  48
  49 /* O2 irq map
  50  *
  51  * IP0 -> software (ignored)
  52  * IP1 -> software (ignored)
  53  * IP2 -> (irq0) C crime 1.1 all interrupts; crime 1.5 ???
  54  * IP3 -> (irq1) X unknown
  55  * IP4 -> (irq2) X unknown
  56  * IP5 -> (irq3) X unknown
  57  * IP6 -> (irq4) X unknown
  58  * IP7 -> (irq5) 0 CPU count/compare timer (system timer)
  59  *
  60  * crime: (C)
  61  *
  62  * CRIME_INT_STAT 31:0:
  63  *
  64  * 0  -> 1  Video in 1
  65  * 1  -> 2  Video in 2
  66  * 2  -> 3  Video out
  67  * 3  -> 4  Mace ethernet
  68  * 4  -> S  SuperIO sub-interrupt
  69  * 5  -> M  Miscellaneous sub-interrupt
  70  * 6  -> A  Audio sub-interrupt
  71  * 7  -> 8  PCI bridge errors
  72  * 8  -> 9  PCI SCSI aic7xxx 0
  73  * 9  -> 10 PCI SCSI aic7xxx 1
  74  * 10 -> 11 PCI slot 0
  75  * 11 -> 12 unused (PCI slot 1)
  76  * 12 -> 13 unused (PCI slot 2)
  77  * 13 -> 14 unused (PCI shared 0)
  78  * 14 -> 15 unused (PCI shared 1)
  79  * 15 -> 16 unused (PCI shared 2)
  80  * 16 -> 17 GBE0 (E)
  81  * 17 -> 18 GBE1 (E)
  82  * 18 -> 19 GBE2 (E)
  83  * 19 -> 20 GBE3 (E)
  84  * 20 -> 21 CPU errors
  85  * 21 -> 22 Memory errors
  86  * 22 -> 23 RE empty edge (E)
  87  * 23 -> 24 RE full edge (E)
  88  * 24 -> 25 RE idle edge (E)
  89  * 25 -> 26 RE empty level
  90  * 26 -> 27 RE full level
  91  * 27 -> 28 RE idle level
  92  * 28 -> 29 unused (software 0) (E)
  93  * 29 -> 30 unused (software 1) (E)
  94  * 30 -> 31 unused (software 2) - crime 1.5 CPU SysCorError (E)
  95  * 31 -> 32 VICE
  96  *
  97  * S, M, A: Use the MACE ISA interrupt register
  98  * MACE_ISA_INT_STAT 31:0
  99  *
 100  * 0-7 -> 33-40 Audio
 101  * 8 -> 41 RTC
 102  * 9 -> 42 Keyboard
 103  * 10 -> X Keyboard polled
 104  * 11 -> 44 Mouse
 105  * 12 -> X Mouse polled
 106  * 13-15 -> 46-48 Count/compare timers
 107  * 16-19 -> 49-52 Parallel (16 E)
 108  * 20-25 -> 53-58 Serial 1 (22 E)
 109  * 26-31 -> 59-64 Serial 2 (28 E)
 110  *
 111  * Note that this means IRQs 5-7, 43, and 45 do not exist.  This is a
 112  * different IRQ map than IRIX uses, but that's OK as Linux irq handling
 113  * is quite different anyway.
 114  */
 115
 116 /*
 117  * IRQ spinlock - Ralf says not to disable CPU interrupts,
 118  * and I think he knows better.
 119  */
 120 static DEFINE_SPINLOCK(ip32_irq_lock);
 121
 122 /* Some initial interrupts to set up */
 123 extern irqreturn_t crime_memerr_intr (int irq, void *dev_id,
 124                                       struct pt_regs *regs);
 125 extern irqreturn_t crime_cpuerr_intr (int irq, void *dev_id,
 126                                       struct pt_regs *regs);
 127
 128 struct irqaction memerr_irq = { crime_memerr_intr, SA_INTERRUPT,
 129                         CPU_MASK_NONE, "CRIME memory error", NULL, NULL };
 130 struct irqaction cpuerr_irq = { crime_cpuerr_intr, SA_INTERRUPT,
 131                         CPU_MASK_NONE, "CRIME CPU error", NULL, NULL };
 132
 133 extern void ip32_handle_int(void);
 134
 135 /*
 136  * For interrupts wired from a single device to the CPU.  Only the clock
 137  * uses this it seems, which is IRQ 0 and IP7.
 138  */
 139
 140 static void enable_cpu_irq(unsigned int irq)
 141 {
 142         set_c0_status(STATUSF_IP7);
 143 }
 144
 145 static unsigned int startup_cpu_irq(unsigned int irq)
 146 {
 147         enable_cpu_irq(irq);
 148         return 0;
 149 }
 150
 151 static void disable_cpu_irq(unsigned int irq)
 152 {
 153         clear_c0_status(STATUSF_IP7);
 154 }
 155
 156 static void end_cpu_irq(unsigned int irq)
 157 {
 158         if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
 159                 enable_cpu_irq (irq);
 160 }
 161
 162 #define shutdown_cpu_irq disable_cpu_irq
 163 #define mask_and_ack_cpu_irq disable_cpu_irq
 164
 165 static struct hw_interrupt_type ip32_cpu_interrupt = {
 166         "IP32 CPU",
 167         startup_cpu_irq,
 168         shutdown_cpu_irq,
 169         enable_cpu_irq,
 170         disable_cpu_irq,
 171         mask_and_ack_cpu_irq,
 172         end_cpu_irq,
 173         NULL
 174 };
 175
 176 /*
 177  * This is for pure CRIME interrupts - ie not MACE.  The advantage?
 178  * We get to split the register in half and do faster lookups.
 179  */
 180
 181 static uint64_t crime_mask;
 182
 183 static void enable_crime_irq(unsigned int irq)
 184 {
 185         unsigned long flags;
 186
 187         spin_lock_irqsave(&ip32_irq_lock, flags);
 188         crime_mask |= 1 << (irq - 1);
 189         crime->imask = crime_mask;
 190         spin_unlock_irqrestore(&ip32_irq_lock, flags);
 191 }
 192
 193 static unsigned int startup_crime_irq(unsigned int irq)
 194 {
 195         enable_crime_irq(irq);
 196         return 0; /* This is probably not right; we could have pending irqs */
 197 }
 198
 199 static void disable_crime_irq(unsigned int irq)
 200 {
 201         unsigned long flags;
 202
 203         spin_lock_irqsave(&ip32_irq_lock, flags);
 204         crime_mask &= ~(1 << (irq - 1));
 205         crime->imask = crime_mask;
 206         flush_crime_bus();
 207         spin_unlock_irqrestore(&ip32_irq_lock, flags);
 208 }
 209
 210 static void mask_and_ack_crime_irq(unsigned int irq)
 211 {
 212         unsigned long flags;
 213
 214         /* Edge triggered interrupts must be cleared. */
 215         if ((irq >= CRIME_GBE0_IRQ && irq <= CRIME_GBE3_IRQ)
 216             || (irq >= CRIME_RE_EMPTY_E_IRQ && irq <= CRIME_RE_IDLE_E_IRQ)
 217             || (irq >= CRIME_SOFT0_IRQ && irq <= CRIME_SOFT2_IRQ)) {
 218                 uint64_t crime_int;
 219                 spin_lock_irqsave(&ip32_irq_lock, flags);
 220                 crime_int = crime->hard_int;
 221                 crime_int &= ~(1 << (irq - 1));
 222                 crime->hard_int = crime_int;
 223                 spin_unlock_irqrestore(&ip32_irq_lock, flags);
 224         }
 225         disable_crime_irq(irq);
 226 }
 227
 228 static void end_crime_irq(unsigned int irq)
 229 {
 230         if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
 231                 enable_crime_irq(irq);
 232 }
 233
 234 #define shutdown_crime_irq disable_crime_irq
 235
 236 static struct hw_interrupt_type ip32_crime_interrupt = {
 237         "IP32 CRIME",
 238         startup_crime_irq,
 239         shutdown_crime_irq,
 240         enable_crime_irq,
 241         disable_crime_irq,
 242         mask_and_ack_crime_irq,
 243         end_crime_irq,
 244         NULL
 245 };
 246
 247 /*
 248  * This is for MACE PCI interrupts.  We can decrease bus traffic by masking
 249  * as close to the source as possible.  This also means we can take the
 250  * next chunk of the CRIME register in one piece.
 251  */
 252
 253 static unsigned long macepci_mask;
 254
 255 static void enable_macepci_irq(unsigned int irq)
 256 {
 257         unsigned long flags;
 258
 259         spin_lock_irqsave(&ip32_irq_lock, flags);
 260         macepci_mask |= MACEPCI_CONTROL_INT(irq - 9);
 261         mace->pci.control = macepci_mask;
 262         crime_mask |= 1 << (irq - 1);
 263         crime->imask = crime_mask;
 264         spin_unlock_irqrestore(&ip32_irq_lock, flags);
 265 }
 266
 267 static unsigned int startup_macepci_irq(unsigned int irq)
 268 {
 269         enable_macepci_irq (irq);
 270         return 0;
 271 }
 272
 273 static void disable_macepci_irq(unsigned int irq)
 274 {
 275         unsigned long flags;
 276
 277         spin_lock_irqsave(&ip32_irq_lock, flags);
 278         crime_mask &= ~(1 << (irq - 1));
 279         crime->imask = crime_mask;
 280         flush_crime_bus();
 281         macepci_mask &= ~MACEPCI_CONTROL_INT(irq - 9);
 282         mace->pci.control = macepci_mask;
 283         flush_mace_bus();
 284         spin_unlock_irqrestore(&ip32_irq_lock, flags);
 285 }
 286
 287 static void end_macepci_irq(unsigned int irq)
 288 {
 289         if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
 290                 enable_macepci_irq(irq);
 291 }
 292
 293 #define shutdown_macepci_irq disable_macepci_irq
 294 #define mask_and_ack_macepci_irq disable_macepci_irq
 295
 296 static struct hw_interrupt_type ip32_macepci_interrupt = {
 297         "IP32 MACE PCI",
 298         startup_macepci_irq,
 299         shutdown_macepci_irq,
 300         enable_macepci_irq,
 301         disable_macepci_irq,
 302         mask_and_ack_macepci_irq,
 303         end_macepci_irq,
 304         NULL
 305 };
 306
 307 /* This is used for MACE ISA interrupts.  That means bits 4-6 in the
 308  * CRIME register.
 309  */
 310
 311 #define MACEISA_AUDIO_INT       (MACEISA_AUDIO_SW_INT |         \
 312                                  MACEISA_AUDIO_SC_INT |         \
 313                                  MACEISA_AUDIO1_DMAT_INT |      \
 314                                  MACEISA_AUDIO1_OF_INT |        \
 315                                  MACEISA_AUDIO2_DMAT_INT |      \
 316                                  MACEISA_AUDIO2_MERR_INT |      \
 317                                  MACEISA_AUDIO3_DMAT_INT |      \
 318                                  MACEISA_AUDIO3_MERR_INT)
 319 #define MACEISA_MISC_INT        (MACEISA_RTC_INT |              \
 320                                  MACEISA_KEYB_INT |             \
 321                                  MACEISA_KEYB_POLL_INT |        \
 322                                  MACEISA_MOUSE_INT |            \
 323                                  MACEISA_MOUSE_POLL_INT |       \
 324                                  MACEISA_TIMER0_INT |           \
 325                                  MACEISA_TIMER1_INT |           \
 326                                  MACEISA_TIMER2_INT)
 327 #define MACEISA_SUPERIO_INT     (MACEISA_PARALLEL_INT |         \
 328                                  MACEISA_PAR_CTXA_INT |         \
 329                                  MACEISA_PAR_CTXB_INT |         \
 330                                  MACEISA_PAR_MERR_INT |         \
 331                                  MACEISA_SERIAL1_INT |          \
 332                                  MACEISA_SERIAL1_TDMAT_INT |    \
 333                                  MACEISA_SERIAL1_TDMAPR_INT |   \
 334                                  MACEISA_SERIAL1_TDMAME_INT |   \
 335                                  MACEISA_SERIAL1_RDMAT_INT |    \
 336                                  MACEISA_SERIAL1_RDMAOR_INT |   \
 337                                  MACEISA_SERIAL2_INT |          \
 338                                  MACEISA_SERIAL2_TDMAT_INT |    \
 339                                  MACEISA_SERIAL2_TDMAPR_INT |   \
 340                                  MACEISA_SERIAL2_TDMAME_INT |   \
 341                                  MACEISA_SERIAL2_RDMAT_INT |    \
 342                                  MACEISA_SERIAL2_RDMAOR_INT)
 343
 344 static unsigned long maceisa_mask;
 345
 346 static void enable_maceisa_irq (unsigned int irq)
 347 {
 348         unsigned int crime_int = 0;
 349         unsigned long flags;
 350
 351         DBG ("maceisa enable: %u\n", irq);
 352
 353         switch (irq) {
 354         case MACEISA_AUDIO_SW_IRQ ... MACEISA_AUDIO3_MERR_IRQ:
 355                 crime_int = MACE_AUDIO_INT;
 356                 break;
 357         case MACEISA_RTC_IRQ ... MACEISA_TIMER2_IRQ:
 358                 crime_int = MACE_MISC_INT;
 359                 break;
 360         case MACEISA_PARALLEL_IRQ ... MACEISA_SERIAL2_RDMAOR_IRQ:
 361                 crime_int = MACE_SUPERIO_INT;
 362                 break;
 363         }
 364         DBG ("crime_int %08x enabled\n", crime_int);
 365         spin_lock_irqsave(&ip32_irq_lock, flags);
 366         crime_mask |= crime_int;
 367         crime->imask = crime_mask;
 368         maceisa_mask |= 1 << (irq - 33);
 369         mace->perif.ctrl.imask = maceisa_mask;
 370         spin_unlock_irqrestore(&ip32_irq_lock, flags);
 371 }
 372
 373 static unsigned int startup_maceisa_irq(unsigned int irq)
 374 {
 375         enable_maceisa_irq(irq);
 376         return 0;
 377 }
 378
 379 static void disable_maceisa_irq(unsigned int irq)
 380 {
 381         unsigned int crime_int = 0;
 382         unsigned long flags;
 383
 384         spin_lock_irqsave(&ip32_irq_lock, flags);
 385         maceisa_mask &= ~(1 << (irq - 33));
 386         if(!(maceisa_mask & MACEISA_AUDIO_INT))
 387                 crime_int |= MACE_AUDIO_INT;
 388         if(!(maceisa_mask & MACEISA_MISC_INT))
 389                 crime_int |= MACE_MISC_INT;
 390         if(!(maceisa_mask & MACEISA_SUPERIO_INT))
 391                 crime_int |= MACE_SUPERIO_INT;
 392         crime_mask &= ~crime_int;
 393         crime->imask = crime_mask;
 394         flush_crime_bus();
 395         mace->perif.ctrl.imask = maceisa_mask;
 396         flush_mace_bus();
 397         spin_unlock_irqrestore(&ip32_irq_lock, flags);
 398 }
 399
 400 static void mask_and_ack_maceisa_irq(unsigned int irq)
 401 {
 402         unsigned long mace_int, flags;
 403
 404         switch (irq) {
 405         case MACEISA_PARALLEL_IRQ:
 406         case MACEISA_SERIAL1_TDMAPR_IRQ:
 407         case MACEISA_SERIAL2_TDMAPR_IRQ:
 408                 /* edge triggered */
 409                 spin_lock_irqsave(&ip32_irq_lock, flags);
 410                 mace_int = mace->perif.ctrl.istat;
 411                 mace_int &= ~(1 << (irq - 33));
 412                 mace->perif.ctrl.istat = mace_int;
 413                 spin_unlock_irqrestore(&ip32_irq_lock, flags);
 414                 break;
 415         }
 416         disable_maceisa_irq(irq);
 417 }
 418
 419 static void end_maceisa_irq(unsigned irq)
 420 {
 421         if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
 422                 enable_maceisa_irq(irq);
 423 }
 424
 425 #define shutdown_maceisa_irq disable_maceisa_irq
 426
 427 static struct hw_interrupt_type ip32_maceisa_interrupt = {
 428         "IP32 MACE ISA",
 429         startup_maceisa_irq,
 430         shutdown_maceisa_irq,
 431         enable_maceisa_irq,
 432         disable_maceisa_irq,
 433         mask_and_ack_maceisa_irq,
 434         end_maceisa_irq,
 435         NULL
 436 };
 437
 438 /* This is used for regular non-ISA, non-PCI MACE interrupts.  That means
 439  * bits 0-3 and 7 in the CRIME register.
 440  */
 441
 442 static void enable_mace_irq(unsigned int irq)
 443 {
 444         unsigned long flags;
 445
 446         spin_lock_irqsave(&ip32_irq_lock, flags);
 447         crime_mask |= 1 << (irq - 1);
 448         crime->imask = crime_mask;
 449         spin_unlock_irqrestore(&ip32_irq_lock, flags);
 450 }
 451
 452 static unsigned int startup_mace_irq(unsigned int irq)
 453 {
 454         enable_mace_irq(irq);
 455         return 0;
 456 }
 457
 458 static void disable_mace_irq(unsigned int irq)
 459 {
 460         unsigned long flags;
 461
 462         spin_lock_irqsave(&ip32_irq_lock, flags);
 463         crime_mask &= ~(1 << (irq - 1));
 464         crime->imask = crime_mask;
 465         flush_crime_bus();
 466         spin_unlock_irqrestore(&ip32_irq_lock, flags);
 467 }
 468
 469 static void end_mace_irq(unsigned int irq)
 470 {
 471         if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
 472                 enable_mace_irq(irq);
 473 }
 474
 475 #define shutdown_mace_irq disable_mace_irq
 476 #define mask_and_ack_mace_irq disable_mace_irq
 477
 478 static struct hw_interrupt_type ip32_mace_interrupt = {
 479         "IP32 MACE",
 480         startup_mace_irq,
 481         shutdown_mace_irq,
 482         enable_mace_irq,
 483         disable_mace_irq,
 484         mask_and_ack_mace_irq,
 485         end_mace_irq,
 486         NULL
 487 };
 488
 489 static void ip32_unknown_interrupt(struct pt_regs *regs)
 490 {
 491         printk ("Unknown interrupt occurred!\n");
 492         printk ("cp0_status: %08x\n", read_c0_status());
 493         printk ("cp0_cause: %08x\n", read_c0_cause());
 494         printk ("CRIME intr mask: %016lx\n", crime->imask);
 495         printk ("CRIME intr status: %016lx\n", crime->istat);
 496         printk ("CRIME hardware intr register: %016lx\n", crime->hard_int);
 497         printk ("MACE ISA intr mask: %08lx\n", mace->perif.ctrl.imask);
 498         printk ("MACE ISA intr status: %08lx\n", mace->perif.ctrl.istat);
 499         printk ("MACE PCI control register: %08x\n", mace->pci.control);
 500
 501         printk("Register dump:\n");
 502         show_regs(regs);
 503
 504         printk("Please mail this report to linux-mips@linux-mips.org\n");
 505         printk("Spinning...");
 506         while(1) ;
 507 }
 508
 509 /* CRIME 1.1 appears to deliver all interrupts to this one pin. */
 510 /* change this to loop over all edge-triggered irqs, exception masked out ones */
 511 void ip32_irq0(struct pt_regs *regs)
 512 {
 513         uint64_t crime_int;
 514         int irq = 0;
 515
 516         crime_int = crime->istat & crime_mask;
 517         irq = ffs(crime_int);
 518         crime_int = 1 << (irq - 1);
 519
 520         if (crime_int & CRIME_MACEISA_INT_MASK) {
 521                 unsigned long mace_int = mace->perif.ctrl.istat;
 522                 irq = ffs(mace_int & maceisa_mask) + 32;
 523         }
 524         DBG("*irq %u*\n", irq);
 525         do_IRQ(irq, regs);
 526 }
 527
 528 void ip32_irq1(struct pt_regs *regs)
 529 {
 530         ip32_unknown_interrupt(regs);
 531 }
 532
 533 void ip32_irq2(struct pt_regs *regs)
 534 {
 535         ip32_unknown_interrupt(regs);
 536 }
 537
 538 void ip32_irq3(struct pt_regs *regs)
 539 {
 540         ip32_unknown_interrupt(regs);
 541 }
 542
 543 void ip32_irq4(struct pt_regs *regs)
 544 {
 545         ip32_unknown_interrupt(regs);
 546 }
 547
 548 void ip32_irq5(struct pt_regs *regs)
 549 {
 550         ll_timer_interrupt(IP32_R4K_TIMER_IRQ, regs);
 551 }
 552
 553 void __init arch_init_irq(void)
 554 {
 555         unsigned int irq;
 556
 557         /* Install our interrupt handler, then clear and disable all
 558          * CRIME and MACE interrupts. */
 559         crime->imask = 0;
 560         crime->hard_int = 0;
 561         crime->soft_int = 0;
 562         mace->perif.ctrl.istat = 0;
 563         mace->perif.ctrl.imask = 0;
 564         set_except_vector(0, ip32_handle_int);
 565
 566         for (irq = 0; irq <= IP32_IRQ_MAX; irq++) {
 567                 hw_irq_controller *controller;
 568
 569                 if (irq == IP32_R4K_TIMER_IRQ)
 570                         controller = &ip32_cpu_interrupt;
 571                 else if (irq <= MACE_PCI_BRIDGE_IRQ && irq >= MACE_VID_IN1_IRQ)
 572                         controller = &ip32_mace_interrupt;
 573                 else if (irq <= MACEPCI_SHARED2_IRQ && irq >= MACEPCI_SCSI0_IRQ)
 574                         controller = &ip32_macepci_interrupt;
 575                 else if (irq <= CRIME_VICE_IRQ && irq >= CRIME_GBE0_IRQ)
 576                         controller = &ip32_crime_interrupt;
 577                 else
 578                         controller = &ip32_maceisa_interrupt;
 579
 580                 irq_desc[irq].status = IRQ_DISABLED;
 581                 irq_desc[irq].action = 0;
 582                 irq_desc[irq].depth = 0;
 583                 irq_desc[irq].handler = controller;
 584         }
 585         setup_irq(CRIME_MEMERR_IRQ, &memerr_irq);
 586         setup_irq(CRIME_CPUERR_IRQ, &cpuerr_irq);
 587
 588 #define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
 589         change_c0_status(ST0_IM, ALLINTS);
 590 }