arch/mips/pci/pci-vr41xx.h

   1 /*
   2  *  pci-vr41xx.h, Include file for PCI Control Unit of the NEC VR4100 series.
   3  *
   4  *  Copyright (C) 2002  MontaVista Software Inc.
   5  *    Author: Yoichi Yuasa <yyuasa@mvista.com or source@mvista.com>
   6  *  Copyright (C) 2004  Yoichi Yuasa <yuasa@hh.iij4u.or.jp>
   7  *
   8  *  This program is free software; you can redistribute it and/or modify
   9  *  it under the terms of the GNU General Public License as published by
  10  *  the Free Software Foundation; either version 2 of the License, or
  11  *  (at your option) any later version.
  12  *
  13  *  This program is distributed in the hope that it will be useful,
  14  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  *  GNU General Public License for more details.
  17  *
  18  *  You should have received a copy of the GNU General Public License
  19  *  along with this program; if not, write to the Free Software
  20  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  21  */
  22 #ifndef __PCI_VR41XX_H
  23 #define __PCI_VR41XX_H
  24
  25 #define PCIMMAW1REG             KSEG1ADDR(0x0f000c00)
  26 #define PCIMMAW2REG             KSEG1ADDR(0x0f000c04)
  27 #define PCITAW1REG              KSEG1ADDR(0x0f000c08)
  28 #define PCITAW2REG              KSEG1ADDR(0x0f000c0c)
  29 #define PCIMIOAWREG             KSEG1ADDR(0x0f000c10)
  30  #define IBA(addr)              ((addr) & 0xff000000U)
  31  #define MASTER_MSK(mask)       (((mask) >> 11) & 0x000fe000U)
  32  #define PCIA(addr)             (((addr) >> 24) & 0x000000ffU)
  33  #define TARGET_MSK(mask)       (((mask) >> 8) & 0x000fe000U)
  34  #define ITA(addr)              (((addr) >> 24) & 0x000000ffU)
  35  #define PCIIA(addr)            (((addr) >> 24) & 0x000000ffU)
  36  #define WINEN                  0x1000U
  37 #define PCICONFDREG             KSEG1ADDR(0x0f000c14)
  38 #define PCICONFAREG             KSEG1ADDR(0x0f000c18)
  39 #define PCIMAILREG              KSEG1ADDR(0x0f000c1c)
  40 #define BUSERRADREG             KSEG1ADDR(0x0f000c24)
  41  #define EA(reg)                ((reg) &0xfffffffc)
  42
  43 #define INTCNTSTAREG            KSEG1ADDR(0x0f000c28)
  44  #define MABTCLR                0x80000000U
  45  #define TRDYCLR                0x40000000U
  46  #define PARCLR                 0x20000000U
  47  #define MBCLR                  0x10000000U
  48  #define SERRCLR                0x08000000U
  49  #define RTYCLR                 0x04000000U
  50  #define MABCLR                 0x02000000U
  51  #define TABCLR                 0x01000000U
  52  /* RFU */
  53  #define MABTMSK                0x00008000U
  54  #define TRDYMSK                0x00004000U
  55  #define PARMSK                 0x00002000U
  56  #define MBMSK                  0x00001000U
  57  #define SERRMSK                0x00000800U
  58  #define RTYMSK                 0x00000400U
  59  #define MABMSK                 0x00000200U
  60  #define TABMSK                 0x00000100U
  61  #define IBAMABT                0x00000080U
  62  #define TRDYRCH                0x00000040U
  63  #define PAR                    0x00000020U
  64  #define MB                     0x00000010U
  65  #define PCISERR                0x00000008U
  66  #define RTYRCH                 0x00000004U
  67  #define MABORT                 0x00000002U
  68  #define TABORT                 0x00000001U
  69
  70 #define PCIEXACCREG             KSEG1ADDR(0x0f000c2c)
  71  #define UNLOCK                 0x2U
  72  #define EAREQ                  0x1U
  73 #define PCIRECONTREG            KSEG1ADDR(0x0f000c30)
  74  #define RTRYCNT(reg)           ((reg) & 0x000000ffU)
  75 #define PCIENREG                KSEG1ADDR(0x0f000c34)
  76  #define BLOODY_CONFIG_DONE     0x4U
  77 #define PCICLKSELREG            KSEG1ADDR(0x0f000c38)
  78  #define EQUAL_VTCLOCK          0x2U
  79  #define HALF_VTCLOCK           0x0U
  80  #define ONE_THIRD_VTCLOCK      0x3U
  81  #define QUARTER_VTCLOCK        0x1U
  82 #define PCITRDYVREG             KSEG1ADDR(0x0f000c3c)
  83  #define TRDYV(val)             ((uint32_t)(val) & 0xffU)
  84 #define PCICLKRUNREG            KSEG1ADDR(0x0f000c60)
  85
  86 #define VENDORIDREG             KSEG1ADDR(0x0f000d00)
  87 #define DEVICEIDREG             KSEG1ADDR(0x0f000d00)
  88 #define COMMANDREG              KSEG1ADDR(0x0f000d04)
  89 #define STATUSREG               KSEG1ADDR(0x0f000d04)
  90 #define REVIDREG                KSEG1ADDR(0x0f000d08)
  91 #define CLASSREG                KSEG1ADDR(0x0f000d08)
  92 #define CACHELSREG              KSEG1ADDR(0x0f000d0c)
  93 #define LATTIMEREG              KSEG1ADDR(0x0f000d0c)
  94  #define MLTIM(val)             (((uint32_t)(val) << 7) & 0xff00U)
  95 #define MAILBAREG               KSEG1ADDR(0x0f000d10)
  96 #define PCIMBA1REG              KSEG1ADDR(0x0f000d14)
  97 #define PCIMBA2REG              KSEG1ADDR(0x0f000d18)
  98  #define MBADD(base)            ((base) & 0xfffff800U)
  99  #define PMBA(base)             ((base) & 0xffe00000U)
 100  #define PREF                   0x8U
 101  #define PREF_APPROVAL          0x8U
 102  #define PREF_DISAPPROVAL       0x0U
 103  #define TYPE                   0x6U
 104  #define TYPE_32BITSPACE        0x0U
 105  #define MSI                    0x1U
 106  #define MSI_MEMORY             0x0U
 107 #define INTLINEREG              KSEG1ADDR(0x0f000d3c)
 108 #define INTPINREG               KSEG1ADDR(0x0f000d3c)
 109 #define RETVALREG               KSEG1ADDR(0x0f000d40)
 110 #define PCIAPCNTREG             KSEG1ADDR(0x0f000d40)
 111  #define TKYGNT                 0x04000000U
 112  #define TKYGNT_ENABLE          0x04000000U
 113  #define TKYGNT_DISABLE         0x00000000U
 114  #define PAPC                   0x03000000U
 115  #define PAPC_ALTERNATE_B       0x02000000U
 116  #define PAPC_ALTERNATE_0       0x01000000U
 117  #define PAPC_FAIR              0x00000000U
 118  #define RTYVAL(val)            (((uint32_t)(val) << 7) & 0xff00U)
 119  #define RTYVAL_MASK            0xff00U
 120
 121 #define PCI_CLOCK_MAX           33333333U
 122
 123 /*
 124  * Default setup
 125  */
 126 #define PCI_MASTER_MEM1_BUS_BASE_ADDRESS        0x10000000U
 127 #define PCI_MASTER_MEM1_ADDRESS_MASK            0x7c000000U
 128 #define PCI_MASTER_MEM1_PCI_BASE_ADDRESS        0x10000000U
 129
 130 #define PCI_TARGET_MEM1_ADDRESS_MASK            0x08000000U
 131 #define PCI_TARGET_MEM1_BUS_BASE_ADDRESS        0x00000000U
 132
 133 #define PCI_MASTER_IO_BUS_BASE_ADDRESS          0x16000000U
 134 #define PCI_MASTER_IO_ADDRESS_MASK              0x7e000000U
 135 #define PCI_MASTER_IO_PCI_BASE_ADDRESS          0x00000000U
 136
 137 #define PCI_MAILBOX_BASE_ADDRESS                0x00000000U
 138
 139 #define PCI_TARGET_WINDOW1_BASE_ADDRESS         0x00000000U
 140
 141 #define IO_PORT_BASE            KSEG1ADDR(PCI_MASTER_IO_BUS_BASE_ADDRESS)
 142 #define IO_PORT_RESOURCE_START  PCI_MASTER_IO_PCI_BASE_ADDRESS
 143 #define IO_PORT_RESOURCE_END    (~PCI_MASTER_IO_ADDRESS_MASK & PCI_MASTER_ADDRESS_MASK)
 144
 145 #define PCI_IO_RESOURCE_START   0x01000000UL
 146 #define PCI_IO_RESOURCE_END     0x01ffffffUL
 147
 148 #define PCI_MEM_RESOURCE_START  0x11000000UL
 149 #define PCI_MEM_RESOURCE_END    0x13ffffffUL
 150
 151 #endif /* __PCI_VR41XX_H */